[LLVMdev] [LLVMDev] [Modeling] About the structure of my allocator

[Jeff Kunkel]

Would I be correct in assuming that the alias set is defined as the
registers which may reside in the same space as the register? In other words
the register is either a super or sub register which holds the same physical
location in the register set?

Could someone please explain what the Alias set is if it is not what I
described above?

TargetRegisterInfo::getAliasSet( unsigned reg )

Thanks
Jeff Kunkel

On Thu, Sep 2, 2010 at 1:56 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:

> I need to model my registers for my allocator. I need to identify the
> super-register and the sub-register conflicts. Something like:
>
> For each set of registers R in the set of aligned registers defined by the
> input request virtual register alpha. Now each register block r in R can
> have zero, one, or more registers defined in the block started at the
> aligned size and ending at the aligned size plus the request register
> alpha's size. The final step is to weigh and choose a block to put alpha
> into.
>
> How do I model the registers R and register blocks r to obtain my desired
> information?
>
> - Thanks
> - Jeff Kunkel
>
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