[LLVMdev] [LLVMDev] [Modeling] About the structure of my allocator

[Jeff Kunkel]

I need to model my registers for my allocator. I need to identify the
super-register and the sub-register conflicts. Something like:

For each set of registers R in the set of aligned registers defined by the
input request virtual register alpha. Now each register block r in R can
have zero, one, or more registers defined in the block started at the
aligned size and ending at the aligned size plus the request register
alpha's size. The final step is to weigh and choose a block to put alpha
into.

How do I model the registers R and register blocks r to obtain my desired
information?

- Thanks
- Jeff Kunkel
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