[LLVMdev] Instruction with variable number of outputs

[Jakob Stoklund Olesen]

On Mar 22, 2010, at 4:28 PM, Chris Lattner wrote:

>>>> 
>>>> def reglist : Operand<i32> {
>>>> let PrintMethod = "printRegisterList";
>>>> let MIOperandInfo = (ops variable_ops);
>>>> }
>>>> 
>>>> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts),
>> 
>> This syntax is not ideal, because reglist:$dsts is a variable list of output operands. But at least there is no extra input operand.
>> 
>> I need a way of describing the LDM instruction with:
>> 
>> Fixed outputs: none
>> Fixed inputs: addr and pred
>> Variable ops: list of output registers
> 
> I would prefer to spell this as:
> 
> def LDM : AXI4ld<(outs reglist:$dsts), (ins addrmode4:$addr, pred:$p),
> 
> Would this work?  You could change 'reglist' to have one fixed operand and the rest variable?  There is no reason to support the 'no output' form of reglist.

That spelling is better, but you probably want to keep all the reglist operands optional. We don't need to support an empty reglist, but since fixed outputs go first on the machine instruction, the reglist would be broken up:

reglist[0], addr[0], addr[1], pred[0], pred[1], reglist[1], reglist[2], ...

We don't want that. We want this:

addr[0], addr[1], pred[0], pred[1], reglist[0], reglist[1], reglist[2], ...

So we need to change tablegen to support variable_ops in MIOperandInfo on the last element of either outs or ins.

I'll look into it when I get the time.

/jakob