[LLVMdev] Instruction with variable number of outputs

[Chris Lattner]

On Mar 19, 2010, at 7:46 AM, Jakob Stoklund Olesen wrote:

> Hi,
> 
> After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like:
> 
> // A list of registers separated by comma. Used by load/store multiple.
> def reglist : Operand<i32> {
>  let PrintMethod = "printRegisterList";
> }
> 
> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
>                          reglist:$dsts, variable_ops),
>                 IndexModeNone, LdStMulFrm, IIC_iLoadm,
>                 "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
> 
> Tablegen produces an instruction description

Ok, you mean TargetInstrDesc, right?

> with 5 input operands: 2 for $addr, 2 for $p, and 1 for $dsts. But $dsts and the following variable_ops are all outputs!

Right, variable_ops means that it takes a variable number of operands, not that an operand has a variable number of registers.

> The description should only have 4 operands + variable_ops.
> 
> How can you specify a named, variable list of output operands?

Why do you need to do this?  You currently can't do it.

-Chris

> 
> Perhaps this could be made to work:
> 
> def reglist : Operand<i32> {
>  let PrintMethod = "printRegisterList";
>  let MIOperandInfo = (ops variable_ops);
> }
> 
> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts),
> 
> 
> 
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