[LLVMdev] Disable the Module Verifier pass?

John Criswell criswell at uiuc.edu
Tue Apr 20 07:11:43 PDT 2010

Zheng Wang wrote:
> Hello,
> Is there anyway to disable the module verifier pass (in llvm-ld and llc)?
> I got an error as " Instruction does not dominate all uses!".
> Obviously, there must be something wrong. The module verifier simply
> aborts `llvm-ld` instead of generating bytecode. If somehow I can
> disable the module verifier, then I can use llc to produce LLVM
> assembly code for my program. This will help me to debug my pass.

llc assumes that its input passes verification, so disabling the 
verifier pass in the linker is probably not going to be as helpful as 
you think.

You can, however, disable the verifier in opt.  So, you can do the 

1) Run opt -std-link-opts -load <your pass.so> -<your pass name> 
-disable-verify <input.bc> -f -o <output.bc>

The -std-link-opts option runs the optimization passes used by llvm-ld.  
You can now disassemble output.bc to see what your pass is doing wrong.

If, for some reason, the bitcode writer cannot write your invalid 
bitcode to disk, then you will have to run the above command in the 
debugger.  Remove the -disable-verify option so that opt crashes in the 
verifier.  Then use the debugger to examine what is wrong.  Remember 
that many LLVM classes (such as Module, Value, Instruction, BasicBlock, 
and Function) have a dump() method that will print their contents to the 
screen.  So, if using gdb, the verifier crashes because instruction I 
doesn't dominate all of its uses, then you can use:

% call I->dump()

... to see what the instruction pointed to by I looks like.

-- John T.

> Cheers
> Zheng
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