[LLVMdev] TableGen question - how to split a 64bit operation to two 32bit

[Artur Pietrek]

Hi Jim,

On Tue, Oct 6, 2009 at 5:39 PM, Jim Grosbach <grosbach at apple.com> wrote:

> Hi Artur,
>
> The Thumb2 target (in lib/Targets/ARM/ARMInstrThumb2.td) materializes a
> 32-bit constant by a two-instruction sequence to load the low and high
> half-words. It's not pretty, but it works. The pattern is at the bottom of
> the file.
>
> Regards,
> -Jim


Wow, somehow I've missed that when I was looking in the source. Thanks a
lot.

Artur



> On Oct 6, 2009, at 5:10 AM, Artur Pietrek wrote:
>
>  Hi all,
>> I'm working on my own backend for a custom CPU. I have defined paired
>> registers for 64bit operations, however to set a 64bit paired register with
>> 64bit immediate I have to set each register in that pair separately with the
>> higher and the lower 32bits of the immediate.
>> Could anyone give me an advice how to describe it in *InstructionInfo.td
>> or point me to something similar in the LLVM source code? (I was looking for
>> it but couldn't find it)
>>
>> Thanks,
>> Artur
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>
>
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