<div class="gmail_quote">Hi Jim,</div><div class="gmail_quote"><br></div><div class="gmail_quote">On Tue, Oct 6, 2009 at 5:39 PM, Jim Grosbach <span dir="ltr"><<a href="mailto:grosbach@apple.com">grosbach@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">Hi Artur,<br>
<br>
The Thumb2 target (in lib/Targets/ARM/ARMInstrThumb2.td) materializes a 32-bit constant by a two-instruction sequence to load the low and high half-words. It's not pretty, but it works. The pattern is at the bottom of the file.<br>
<br>
Regards,<br>
-Jim</blockquote><div><br></div><div>Wow, somehow I've missed that when I was looking in the source. Thanks a lot.</div><div><br></div><div>Artur</div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
<div><div class="h5">
On Oct 6, 2009, at 5:10 AM, Artur Pietrek wrote:<br>
<br>
</div></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div></div><div class="h5">
Hi all,<br>
I'm working on my own backend for a custom CPU. I have defined paired registers for 64bit operations, however to set a 64bit paired register with 64bit immediate I have to set each register in that pair separately with the higher and the lower 32bits of the immediate.<br>
Could anyone give me an advice how to describe it in *InstructionInfo.td or point me to something similar in the LLVM source code? (I was looking for it but couldn't find it)<br>
<br>
Thanks,<br>
Artur<br></div></div>
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