[LLVMdev] Puzzled by "set" in target description file

[Heyu Zhu]

Hello everyone,

I  try to write target description by reference to existing backends.

Target description declares an instruction as below:

def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
                         "mov", " $dst, $src",
                         [(set GPR:$dst, so_imm2part:$src)]>;

I find 'set' declared in file TargetSelectDAG.td as
     def set;

But if i modify it,
     def set_try;

def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
                         "mov", " $dst, $src",
                         [(set_try GPR:$dst, so_imm2part:$src)]>;

tblgen will give a message: Unrecognized node set_try.

Why 'set ' is a node without SDNode when define?

Thanks.
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