[LLVMdev] Two Regalloc Enhancements[MESSAGE NOT SCANNED]

Mark Shannon marks at dcs.gla.ac.uk
Fri Jul 24 04:46:24 PDT 2009

Hi David,

What effect is there on compile time?

David Greene wrote:
> We have two features for register allocation we'd like to contribute if folks 
> think they are worthwhile.  We want to get a read on whether they will be 
> useful to people.
> The first features backschedules reloads during the spilling phase.  As 
> reloads are generated, we have some very simple code to try to schedule them 
> as far ahead of the use as possible.
> The second features modifies linearscan to try to spread register usage out a 
> bit.  Rather than always grabbing the first free register in the allocatable 
> list, it remembers the last few registers recently assigned and does not reuse 
> them unless there are no other registers available.  This tends to help the 
> backscheduling code by distributing register usage and providing more 
> scheduling freedom.  It also can induce spilling where none was there before 
> if the allocator has "just enough" registers.  We haven't noticed any serious 
> performance problems in practice.
> With both patches, we have seen performance improvements on some codes.
> I know there's some work on post-ra scheduling going on which would probably
> supercede the reload backscheduling code.  If that's coming soon, there's 
> probably not much point in contributing it.  The "round-robin" register 
> assignment would help and post-ra scheduler.
> What's the community's opinion on whether these two features are worth
> committing to the public repository?
>                                    -Dave
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