[LLVMdev] Two Regalloc Enhancements

[Evan Cheng]

On Jul 23, 2009, at 4:23 PM, David Greene wrote:

> On Thursday 23 July 2009 18:07, Evan Cheng wrote:
>
>> Ok. As with any heuristics change, some tests will benefit, some will
>> suffer. I am ok with both sets of changes assuming there are ways to
>> control them.
>
> Yep, we have flags.
>
>> Post-ra scheduling has been working for a while. The reason it's not
>> turned on for x86 is it's not helping much (1 or 2%) while the  
>> compile
>> time cost is too high (~9% codegen time). I assume you guys are doing
>> your experiments using AMD processors. It could be Intel's uArch is
>> just not benefiting from the load scheduling.
>
> Yes, I can imagine there would be differences here.  The memory  
> architectures
> are quite different.
>
>> Round-robin register assignment probably will help post-ra  
>> scheduling.
>> However, for small functions it may end up increase the number of
>> registers used. That can be bad for performance.
>
> Correct.  As I said, we haven't noticed any degredation.  But our  
> code base is
> very different from yours.  :)
>
>>> What's the community's opinion on whether these two features are  
>>> worth
>>> committing to the public repository?
>>
>> I welcome the features as long as we can add them as llc-beta first.
>> Once we have some more testing across all the platforms, we can then
>> decide whether they can be turned on. Is that ok?
>
> Fine with me.  How do I do this?  Just put them under some flags  
> that default
> to false?

Yep! Thanks.

Evan
>
>                                  -Dave
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