[LLVMdev] Look-ahead instruction selection

[Bill Wendling]

On Jan 5, 2009, at 5:38 PM, [Alex] wrote:

> Maybe I didn't describe the question very well.
>
> I want to match these patterns:
>
>  (and (mul node:$val0, node:$val1))
>  (and (add node:$val0, node:$val1))
>  (and (sub node:$val0, node:$val1))
>  (and (udiv node:$val0, node:$val1))
>
> into "four" different machines instructions, respectively:
>
>  MUL_AND
>  ADD_AND
>  SUB_AND
>  UDIV_AND
>
> That is, this machine is capable of doing an arithmetic operation  
> and a
> "following" AND operation by a single machine instruction. There are  
> a lot
> of arithmetic operations but they can only be combined with a  
> following AND
> operation. It's important that only the following AND can be merged/ 
> combined
> with the arithmetic operation. The pattern:
>
>   (mul node:$val0, (AND))
>
> can _not_ be matched.
>
> The problem is, it seems to me, that the instruction returned in these
> patterns is always the AND, which is the "root" of these partial DAG
> pattern, instead of the arithmetic operation. The LLVM instruction  
> selector
> is capable of doing this "look ahead" matching? What is the  
> suggested way to
> do this?
>
Have you tried using special patterns for these instructions? If you  
check in X86InstrInfo.td, there are some like this:

def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
                      (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
                  addr:$dst),
           (SHRD16mrCL addr:$dst, GR16:$src2)>;

You might have some luck with something along these lines:

def : Pat<(and (mul node:$val0, node:$val1), ...),
           (MUL_AND node:$val0, node:$val1)>;

(The pattern you have above seems incomplete because it lacks an extra  
"node:$val#" for the "and" part after the "mul" part.)

-bw