[LLVMdev] Back-end with general purpose registers

[Chris Lattner]

On Dec 8, 2009, at 7:08 AM, Robert Quill wrote:

> Hi all,
>
> I am trying to write a back-end for LLVM where any instruction may  
> take
> any type of data. I am looking for the output to be of the format:
>
> inst.type reg1,reg2

X86 has a similar issue, where operands can be either a register,  
memory, or immediate.  We handle this by splitting the instructions  
into multiple different instructions that handle each case, e.g.  
addRI, addRR, addRM, addMR, addMI, etc.

-Chris

>
> etc. Where inst is the instruction, e.g. mov and type is data-type  
> e.g.
> f32 etc. I tried creating a back-end with a register class which could
> take i32 and f32:
>
> def GPRegs
> : RegisterClass <"Test",
>                [i32,f32],  // Formats supported by this class
>                32,         // Memory alignment
>                [ R0, R1, R2, R3, R4 ]
> ....
>
> And then used this class in the patterns for the instructions.  
> However,
> I couldn't get this to work as the pattern matcher only considered the
> first type in the list.
>
> Has anyone ever tried writing a very general back-end like this  
> before?
> Does anyone have any advice?
>
> Feel free to ask for more info if I haven't been very clear.
>
> Thanks for your help,
>
> Rob
>
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