[LLVMdev] Back-end with general purpose registers

[Robert Quill]

Hi all,

I am trying to write a back-end for LLVM where any instruction may take
any type of data. I am looking for the output to be of the format:

inst.type reg1,reg2

etc. Where inst is the instruction, e.g. mov and type is data-type e.g.
f32 etc. I tried creating a back-end with a register class which could
take i32 and f32:

def GPRegs
: RegisterClass <"Test", 
                [i32,f32],  // Formats supported by this class
                32,         // Memory alignment
                [ R0, R1, R2, R3, R4 ]
....

And then used this class in the patterns for the instructions. However,
I couldn't get this to work as the pattern matcher only considered the
first type in the list.

Has anyone ever tried writing a very general back-end like this before?
Does anyone have any advice?

Feel free to ask for more info if I haven't been very clear.

Thanks for your help,

Rob

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