[LLVMdev] Hi Cache Miss and Branch Misprediction

[John Criswell]

Ketan Pundlik Umare wrote:
> Than a lot John!!!!
>
> That was great, i wanted to read the performance counter, but was always afraid how llvm would react (virtual machine)
>   
Reading the performance counters should be fine.  The tricky part is how 
fine-grained you want the information to be and whether you'll need 
kernel support to do what you want to do.  If you want to limit the 
performance counters to just events caused by the current process, 
you'll need OS support to virtualize the performance counter registers.  
The perfctr patch to Linux (listed on the resource page of the URL I 
sent you) does that for Intel/AMD processors.

> Thanx for the resource i ll go through it.
> i think i read somewhere that llvm doesnot support assembly instructions???
>   
That used to be true a long time ago, but it is no longer true.  LLVM 
supports inline assembly.  However, you may run into bugs or missing 
features with inline assembly if you use an inline assembly feature that 
isn't used often.  If that happens, please file a bug report.
> Also can you redirect me to run-time transforms for llvm, where can i find the material. I thought that the transfor pass is done on the IR only and it is static??? Please correct my thinking.
>   
AFAIK, an LLVM transform can be done anytime you have LLVM IR for a 
program.  With the JIT infrastructure in LLVM, I believe you can run an 
LLVM pass on the IR, generate native code from the IR, get performance 
numbers, transform the LLVM IR again, and re-generate the native code 
again.  IIRC, regeneration of native code is done at function 
granularity, and all callers are updated to call the new code.

I'm not very familiar with the JIT classes in LLVM, but I believe you 
want to look at the ExecutionEngine class and the source code for lli 
(the basic LLVM JIT command line tool) and the libraries it uses.

Can others more familiar with the LLVM JIT infrastructure provide more 
information?

-- John T.

> You were of great help
> Thank you
> Ketan
> ----- Original Message -----
> From: "John Criswell" <criswell at cs.uiuc.edu>
> To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>
> Sent: Tuesday, September 30, 2008 11:37:05 AM GMT -05:00 US/Canada Eastern
> Subject: Re: [LLVMdev] Hi Cache Miss and Branch Misprediction
>
> Ketan Pundlik Umare wrote:
>   
>> Thanx a lot Guys!!
>> But i have to do this online and and use it to do some kind code transformation. Its for a different project.
>>
>>     
> Another possibility is to write an LLVM transform that inserts code into
> a program to do this profiling for you.
>
> For example, consider cache misses.  You could write a function that
> reads the processor's performance counter registers for cache misses in
> native code.  You could then write an LLVM transform that instruments a
> program to call this function to calculate cache misses in various parts
> of the program.  A run-time transform used in a JIT built using LLVM
> could then use this information to transform various parts of the
> program at run-time.
>
> If you want to do fine grained profiling (for example, instrumenting
> individual LLVM load/store instructions), there may be more efficient
> ways to read the performance counters.  You may be able to, for example,
> write an inline asm statement to read the performance counter registers
> directly (LLVM supports inline assembly).
>
> If you want to instrument code that is not visible at the LLVM IR level
> (e.g., cache misses due to register spills), then you'd need to modify
> the code generator, I believe.
>
> You may want to check this resource
> (http://perfsuite.ncsa.uiuc.edu/publications/LJ135/t1.html) for
> information on software you can use to read performance counters on Linux.
>
> -- John T.
>
>   
>> But all this has given me a quite a bit of knowledge.Wow!!!
>>
>> Thank you
>> Best
>> Ketan
>> ----- Original Message -----
>> From: "OvermindDL1" <overminddl1 at gmail.com>
>> To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>
>> Sent: Monday, September 29, 2008 10:17:41 PM GMT -05:00 US/Canada Eastern
>> Subject: Re: [LLVMdev] Hi Cache Miss and Branch Misprediction
>>
>> On Mon, Sep 29, 2008 at 6:30 PM, Mike Stump <mrs at apple.com> wrote:
>>
>>     
>>> /* snip */
>>>
>>>       
>> AMD's CodeAnalyst is free and quite wonderful at this job.  Shows
>> details about just about anything the CPU reports (and on newer AMD
>> CPU's there is an even more ridiculous amount of information) about
>> every little function call, time they took, multiple profiling modes,
>> etc...
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>>     
>
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