[LLVMdev] INSERT_SUBREG node.

[sanjiv gupta]

On Mon, 2008-10-20 at 08:07 -0700, Evan Cheng wrote:
> On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote:
> 
> >>>
> >>> PR2916 filed.
> >>> Though I did not quite understand why this could be a tablegen bug?
> >>
> >>
> >> Based on your comments. :-) It should be possible to specify two FSR0
> >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
> >> workaround you described:
> >>
> >>
> >> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> >> let SubRegClassList = [FSR8, FSR8];   // HERE.
> >> }
> >>
> > It is currently possible.
> 
> I am confused. Is what you described in PR2916 an issue or not?
> 
is specifying the same subregclass two times okay? or do we need to
cleanup the implementation so that you specify a SubRegClass only once.
The other related issue is that we can not use SubIdx starting from
Zero.

- Sanjiv

> Evan
> 
> >
> >
> > - Sanjiv
> >
> >>
> >> Evan
> >>
> >>>
> >>>
> >>> - Sanjiv
> >>>
> >>>
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