[LLVMdev] INSERT_SUBREG node.

[Evan Cheng]

On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote:

>>>
>>> PR2916 filed.
>>> Though I did not quite understand why this could be a tablegen bug?
>>
>>
>> Based on your comments. :-) It should be possible to specify two FSR0
>> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
>> workaround you described:
>>
>>
>> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
>> let SubRegClassList = [FSR8, FSR8];   // HERE.
>> }
>>
> It is currently possible.

I am confused. Is what you described in PR2916 an issue or not?

Evan

>
>
> - Sanjiv
>
>>
>> Evan
>>
>>>
>>>
>>> - Sanjiv
>>>
>>>
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>>
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