[LLVMdev] Adding address registers to back-end

[Boris Boesler]

Hi!

  I'm writing a new back-end for a new architecture. First, I'll do  
some "tests" with an existing back-end (I chose the Sparc back-end).  
My architecture has special address-registers and I want to add such  
new address-registers to my Sparc back-end.

1) I defined a new register call AddrRegs
2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. ))
3) I added method addPointerRegClass() to my InstrInfo class

  The compiler generates the some code as before, but that seems to  
be ok, because I haven't used ptr_rc yet.

4) I changed the address mode MEMri:

def MEMri : Operand<iPTR> {
   let PrintMethod = "printMemOperand";
   // was: let MIOperandInfo = (ops IntRegs, i32imm);
   let MIOperandInfo = (ops ptr_rc, i32imm);
}

for the C code int c; void f(void) { c = 4711; } I get the error  
message:

Register class of operand and regclass of use don't agree!
Operand = 0
Op->Val = 0x42b08d60: i32 = SETHIi 0x42b08d00
MI = STri       %reg1026
VReg = 1026
VReg RegClass     size = 4, align = 4
Expected RegClass size = 4, align = 4

  The GlobalAddress for variable c is replaced by an ADD(HI(c), LO 
(c)) during lowering. I assume the code-generator cant place values  
in the address registers? All address-registers are elements in the  
register sets IntRegs and AddrRegs.

  Using address registers is part of the ppc code-generator and I'm  
checking that one, but I can't see the differences. Can someone guide  
me?

Thanks,
Boris