[LLVMdev] PR1350 (Vreg subregs) questions

[Chris Lattner]

On Tue, 12 Jun 2007, Christopher Lamb wrote:
>> >  What's the best way to get an SDNode through to DAG scheduling
>> >  without getting mangled during Lowering/ISel?
>> 
>>  What do you mean by "mangled"? Please clarify.
>
> My mangled I mean the nodes shouldn't be isel'ed into anything else because 
> they need to survive through to scheduling. Is there a preferred means of 
> having those nodes skipped during selection and lowering?

You'll have to teach legalize and isel about these nodes, just like they 
know about ISD::Register nodes.  subregs will be a new first-class node 
type that all of the dag stuff will have to know about (at least to pass 
them through).

>> >  When should subregs be flattened to actual registers: AsmPrinter?
>> >  Somewhere in LiveIntervals, during RegAlloc?

This should definitely be done during regalloc.

-Chris

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