[LLVMdev] PR1350 (Vreg subregs) questions

[Christopher Lamb]

On Jun 11, 2007, at 7:22 PM, Evan Cheng wrote:

>
> On Jun 11, 2007, at 6:14 PM, Christopher Lamb wrote:
>
>>
>> What's the best way to get an SDNode through to DAG scheduling
>> without getting mangled during Lowering/ISel?
>
> What do you mean by "mangled"? Please clarify.

My mangled I mean the nodes shouldn't be isel'ed into anything else  
because they need to survive through to scheduling. Is there a  
preferred means of having those nodes skipped during selection and  
lowering?

>>
>> When should subregs be flattened to actual registers: AsmPrinter?
>> Somewhere in LiveIntervals, during RegAlloc?
>
> You mean turning part of a larger physical register into a sub-
> register?

Yes.

> I would think LiveIntervals or else copy coalescing might
> not work right.

Ok. Can you give me some hints as to starting points in LiveIntervals?

--
Chris

>
> Evan
>
>>
>> Is there are common API used to turn vregs into physregs that could
>> be changed to flatten any subregs in a central location?
>> --
>> Christopher Lamb
>>
>>
>>
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--
Christopher Lamb



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