[LLVMdev] Pattern matching questions

[Chris Lattner]

On Tue, 9 Jan 2007, Evan Cheng wrote:
>> - How does one deal with multiple instruction sequences in a pattern?
>>   To load a constant is a two instruction sequence, but both
>>   instructions only take two operands (assume that r3 is a 32-bit
>>   register):
>>
>>   ilhu $3, 45             # r3 = (45 << 16)
>>   iohl $3, 5              # r3 |= 5
>>
>>   I tried:
>>
>>   def : Pat<(i32 imm:$imm),
>>             (IOHL (ILHU (HI16 imm:$imm)), (LO16 imm:$imm))>;
>
> It is possible to write multi-instruction pattern, e.g.
> X86InstrSSE.td line 1911. But how are you defining HI16 and LO16?
> Sounds like you want to define them as SDNodeXform that returns upper
> and lower 16 bits respectively. Take a look at PSxLDQ_imm in
> X86InstrSSE.td as an example.

Another good example is the PPC backend, which has the exact same issue 
for integer constants.

>> - The return instruction for Cell SPU is "bi $lr". How do I jam that
>>   into the instruction info w/o tblgen bitching up a storm about the
>>   "$" or the extra "bi" operands?
>
> I am not sure. Does "bi \$lr" works? Or "bi $$lr"? Or even something
> like
> !strconcat("bi ", !strconcat("$", "lr")).

Yep, $$ should work.

>> - Immediates in a pattern: To move one register to another involves
>>   using the 3-operand OR instruction, but how do I encode an immediate
>>   w/o a type inference contradiction?
>>
>>   def : Pat<(set R32C:$rDest, R32C:$rSrc),
>>             (ORIr32 R32C:$rSrc, 0)>;

You current cannot specify move patterns in the .td file.  You specify 
them with XXXRegisterInfo::copyRegToReg and XXXInstrInfo::isMoveInstr. 
See the PPC or Sparc backend for some simple examples.

-Chris

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