[LLVMdev] Pattern matching questions

[Scott Michel]

On Jan 9, 2007, at 1:37 PM, Evan Cheng wrote:

>> - The return instruction for Cell SPU is "bi $lr". How do I jam that
>>   into the instruction info w/o tblgen bitching up a storm about the
>>   "$" or the extra "bi" operands?
>
> I am not sure. Does "bi \$lr" works? Or "bi $$lr"? Or even something
> like
> !strconcat("bi ", !strconcat("$", "lr")).

I'll give the strconcat a try. Hadn't thought of that...

>> - Immediates in a pattern: To move one register to another involves
>>   using the 3-operand OR instruction, but how do I encode an  
>> immediate
>>   w/o a type inference contradiction?
>>
>>   def : Pat<(set R32C:$rDest, R32C:$rSrc),
>>             (ORIr32 R32C:$rSrc, 0)>;
>
> I am not sure what you mean. By 3-operand, you mean 2 source operand
> and 1 destination. I don't think the error you are seeing have
> anything to do with the immediate. For a def : Pat pattern, you don't
> need to specify the "set R32C:$rDest" portion.

The PPC "OR" instruction has three operands (ok, in llvm-speak, it's  
probably two operands and one result). The SPU's ORI has two  
operands, one result. I was just thinking that I could get a reg-to- 
reg move encoded using this instruction, but couldn't because the  
immediate, 0, causes a type inference contradiction.

Q: Why don't I need the R32C:$rDest?