[LLVMdev] Instruction pattern type inference problem
Christopher Lamb
christopher.lamb at gmail.com
Sun Apr 22 20:35:02 PDT 2007
I have a back end which has both scalar and vector registers that
alias each other. I'm having a problem generating the ISel from
tablegen that appears only when a vector register class is declared
to contain integer vectors. At that moment tablegen doesn't seem to
be able to infer integer types in patterns that it was able to
before, but I'm not clear on why that's the case.
This isn't just the results of instructions, but also immediate
values as well. It seems to affect a smattering of node types. Any
insights?
For instance:
where GPRegs contains types [i32, f32]
def BEQ : IF8<Opc.BEQ,
(ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16),
"beq $Rsrc1, $Rsrc2, $SImm16",
[(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb:
$SImm16)], s_br>;
Tablegen reports:
BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2,
SETEQ:Other), (bb:Other):$SImm16)
as soon as I add a register class that supports either [v2i32] or
[v4i32] I get the following:
BGE: (brcond:void (setcc:isInt GPRegs:i32:$Rsrc1, 0:i32,
SETGE:Other), (bb:Other):$SImm16)
build/llvm/trunk/Debug/bin/tblgen: In BGE: Could not infer all types
in pattern!
Thanks
--
Christopher Lamb
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