[LLVMdev] avoid live range overlap of "vector" registers

[Chris Lattner]

On Wed, 11 May 2005, Morten Ofstad wrote:
> Chris Lattner wrote:
>> void %test() {
>>         %A = load %f32v4* %G
>>         %B = call %f32v4 %swizzle(%f32v4 %A, %i32v4 <uint 1, uint 1, uint 
>> 1, uint 1>)   ;; splat XYZW -> YYYY
>>         store %f32v4 %B, %f32v4* %G
>>         ret void
>> }
>> 
>> ... Except using llvm.swizzle instead of 'swizzle'.
>
> I much prefer the name chosen in the SSE instruction set: 'shuffle'

Shuffle sounds fine to me :)

>> Unfortunately the code generator currently does not support packed types, 
>> so this will require some work.  However, this certainly is the closest 
>> match for your model.
>
> This work needs to be done for SSE code generation, which I think would 
> be of interest to several people (including me) -- Our front-end 
> generates code that uses packed datatypes a lot and I'm not entirely 
> happy with the current situation using the LowerPacked pass... If SSE 
> code generation was working, we would use LLVM for a lot more, at the 
> moment we have a small runtime library with SSE optimized functions for 
> things like trilinear interpolation, but the LLVM optimizer can't do 
> very much with these functions since they are just external calls.

I agree, many people are interested in it.  The only question is who will 
step up to do it (first). ;-)

-Chris

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