[LLVMdev] avoid live range overlap of "vector" registers

[Robert L. Bocchino Jr.]

Hi,

> This work needs to be done for SSE code generation, which I think 
> would be of interest to several people (including me) -- Our front-end 
> generates code that uses packed datatypes a lot and I'm not entirely 
> happy with the current situation using the LowerPacked pass... If SSE 
> code generation was working, we would use LLVM for a lot more, at the 
> moment we have a small runtime library with SSE optimized functions 
> for things like trilinear interpolation, but the LLVM optimizer can't 
> do very much with these functions since they are just external calls.

I've been working on using LLVM for compilation to vector 
architectures.  One of the things I've been working on is a vector type 
(essentially an extension of the packed type to arbitrary vector 
lengths) with vector operations.  I hope to contribute my vector-LLVM 
extensions to the LLVM source base, and integrate them with the packed 
type, by the end of the summer.

Code generation for subword-SIMD vector instructions (like SSE) is 
definitely on our radar screen, although we may be focusing on AltiVec.

Rob

Robert L. Bocchino Jr.
Ph.D. Student, Computer Science
University of Illinois, Urbana-Champaign
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