[llvm] [AMDGPU] Legalize uniform 16-bit loads to match subword load instructions (PR #225097)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 2 07:51:31 PDT 2026
https://github.com/LU-JOHN updated https://github.com/llvm/llvm-project/pull/225097
>From d2a2b3f074442a418cfe85382a591ebdd706c2b5 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Mon, 21 Sep 2026 09:30:03 -0500
Subject: [PATCH 1/7] Enable scalar subword loads for plain 16-bit loads
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/lib/Target/AMDGPU/SMInstructions.td | 21 +-
.../test/CodeGen/AMDGPU/fcanonicalize.bf16.ll | 50 +-
.../CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll | 42 +-
.../CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll | 42 +-
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 539 +++++++-----------
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll | 217 +++----
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll | 238 +++-----
llvm/test/CodeGen/AMDGPU/min.ll | 22 +-
.../AMDGPU/preload-implicit-kernargs.ll | 38 +-
9 files changed, 477 insertions(+), 732 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 19aeafe9b30ccc..0f155fd898e981 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -980,7 +980,7 @@ multiclass SMLoad_Pattern <string Instr, ValueType vt, bit immci = true> {
}
}
-multiclass ScalarLoadWithExtensionPat <string Instr, SDPatternOperator node, ValueType vt> {
+multiclass ScalarSubwordLoadPat <string Instr, SDPatternOperator node, ValueType vt> {
// 1. IMM offset
def : GCNPat <
(node (SMRDImm i64:$sbase, i32:$offset)),
@@ -1041,12 +1041,19 @@ multiclass ScalarBufferLoadIntrinsicPat <SDPatternOperator name, string Instr> {
// selector to prefer those.
let AddedComplexity = 100 in {
-defm : ScalarLoadWithExtensionPat <"S_LOAD_U8", smrd_extloadi8, i32>;
-defm : ScalarLoadWithExtensionPat <"S_LOAD_U8", smrd_zextloadi8, i32>;
-defm : ScalarLoadWithExtensionPat <"S_LOAD_I8", smrd_sextloadi8, i32>;
-defm : ScalarLoadWithExtensionPat <"S_LOAD_U16", smrd_extloadi16, i32>;
-defm : ScalarLoadWithExtensionPat <"S_LOAD_U16", smrd_zextloadi16, i32>;
-defm : ScalarLoadWithExtensionPat <"S_LOAD_I16", smrd_sextloadi16, i32>;
+// Extending subword loads
+defm : ScalarSubwordLoadPat <"S_LOAD_U8", smrd_extloadi8, i32>;
+defm : ScalarSubwordLoadPat <"S_LOAD_U8", smrd_zextloadi8, i32>;
+defm : ScalarSubwordLoadPat <"S_LOAD_I8", smrd_sextloadi8, i32>;
+defm : ScalarSubwordLoadPat <"S_LOAD_U16", smrd_extloadi16, i32>;
+defm : ScalarSubwordLoadPat <"S_LOAD_U16", smrd_zextloadi16, i32>;
+defm : ScalarSubwordLoadPat <"S_LOAD_I16", smrd_sextloadi16, i32>;
+
+// Non-extending subword loads
+foreach vt = Reg16Types.types in {
+ defm : ScalarSubwordLoadPat <"S_LOAD_U16", smrd_load, vt>;
+}
+
defm : ScalarBufferLoadIntrinsicPat <SIsbuffer_load_byte, "S_BUFFER_LOAD_I8">;
defm : ScalarBufferLoadIntrinsicPat <SIsbuffer_load_ubyte, "S_BUFFER_LOAD_U8">;
defm : ScalarBufferLoadIntrinsicPat <SIsbuffer_load_short, "S_BUFFER_LOAD_I16">;
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
index f559943070dd77..6ad79905071133 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
@@ -120,11 +120,11 @@ define amdgpu_kernel void @v_test_canonicalize_fabs_var_bf16(ptr addrspace(1) %o
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u16 v1, v0, s[0:1]
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_mul_bf16 v1, 1.0, v1 op_sel_hi:[0,1]
+; GFX1250-NEXT: s_load_u16 s2, s[0:1], 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_and_b32 s2, s2, 0x7fff
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_pk_mul_bf16 v1, 1.0, s2 op_sel_hi:[0,1]
; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
%val = load bfloat, ptr addrspace(1) %out
@@ -145,11 +145,11 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_bf16(ptr addrspace(
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u16 v1, v0, s[0:1]
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_or_b32_e32 v1, 0x8000, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_mul_bf16 v1, 1.0, v1 op_sel_hi:[0,1]
+; GFX1250-NEXT: s_load_u16 s2, s[0:1], 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_bitset1_b32 s2, 15
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_pk_mul_bf16 v1, 1.0, s2 op_sel_hi:[0,1]
; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
%val = load bfloat, ptr addrspace(1) %out
@@ -170,11 +170,11 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_var_bf16(ptr addrspace(1) %o
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u16 v1, v0, s[0:1]
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_xor_b32_e32 v1, 0x8000, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_mul_bf16 v1, 1.0, v1 op_sel_hi:[0,1]
+; GFX1250-NEXT: s_load_u16 s2, s[0:1], 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_xor_b32 s2, s2, 0x8000
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_pk_mul_bf16 v1, 1.0, s2 op_sel_hi:[0,1]
; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
%val = load bfloat, ptr addrspace(1) %out
@@ -194,11 +194,11 @@ define amdgpu_kernel void @v_test_no_denormals_canonicalize_fneg_var_bf16(ptr ad
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u16 v1, v0, s[0:1]
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_xor_b32_e32 v1, 0x8000, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_mul_bf16 v1, 1.0, v1 op_sel_hi:[0,1]
+; GFX1250-NEXT: s_load_u16 s2, s[0:1], 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_xor_b32 s2, s2, 0x8000
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_pk_mul_bf16 v1, 1.0, s2 op_sel_hi:[0,1]
; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
%val = load bfloat, ptr addrspace(1) %out
@@ -218,11 +218,11 @@ define amdgpu_kernel void @v_test_no_denormals_canonicalize_fneg_fabs_var_bf16(p
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u16 v1, v0, s[0:1]
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_or_b32_e32 v1, 0x8000, v1
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_pk_mul_bf16 v1, 1.0, v1 op_sel_hi:[0,1]
+; GFX1250-NEXT: s_load_u16 s2, s[0:1], 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_bitset1_b32 s2, 15
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_pk_mul_bf16 v1, 1.0, s2 op_sel_hi:[0,1]
; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
%val = load bfloat, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
index 73f8df5ed65153..73304ba2b319df 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
@@ -65,37 +65,31 @@ define amdgpu_kernel void @rcp_f16(
; GFX12-TRUE16-LABEL: rcp_f16:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: s_mov_b32 s6, -1
-; GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
-; GFX12-TRUE16-NEXT: s_mov_b32 s10, s6
-; GFX12-TRUE16-NEXT: s_mov_b32 s11, s7
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
-; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
-; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null
-; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
+; GFX12-TRUE16-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_s_rcp_f16 s2, s2
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: rcp_f16:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_mov_b32 s6, -1
-; GFX12-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
-; GFX12-FAKE16-NEXT: s_mov_b32 s10, s6
-; GFX12-FAKE16-NEXT: s_mov_b32 s11, s7
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_mov_b32 s8, s2
-; GFX12-FAKE16-NEXT: s_mov_b32 s9, s3
-; GFX12-FAKE16-NEXT: s_mov_b32 s4, s0
-; GFX12-FAKE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
-; GFX12-FAKE16-NEXT: s_mov_b32 s5, s1
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
-; GFX12-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
+; GFX12-FAKE16-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_s_rcp_f16 s2, s2
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX12-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
index e5979d8c99b606..fd36da8c635bf8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
@@ -70,37 +70,31 @@ define amdgpu_kernel void @rsq_f16(
; SDAG-GFX12-TRUE16-LABEL: rsq_f16:
; SDAG-GFX12-TRUE16: ; %bb.0: ; %entry
; SDAG-GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s6, -1
-; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
-; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s10, s6
-; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s11, s7
; SDAG-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
-; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
-; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
-; SDAG-GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null
-; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
-; SDAG-GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; SDAG-GFX12-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
-; SDAG-GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
+; SDAG-GFX12-TRUE16-NEXT: s_load_u16 s2, s[2:3], 0x0
+; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; SDAG-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; SDAG-GFX12-TRUE16-NEXT: v_s_rsq_f16 s2, s2
+; SDAG-GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; SDAG-GFX12-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
+; SDAG-GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s2, -1
+; SDAG-GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; SDAG-GFX12-TRUE16-NEXT: s_endpgm
;
; SDAG-GFX12-FAKE16-LABEL: rsq_f16:
; SDAG-GFX12-FAKE16: ; %bb.0: ; %entry
; SDAG-GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s6, -1
-; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
-; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s10, s6
-; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s11, s7
; SDAG-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s8, s2
-; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s9, s3
-; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s4, s0
-; SDAG-GFX12-FAKE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
-; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s5, s1
-; SDAG-GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; SDAG-GFX12-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
-; SDAG-GFX12-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
+; SDAG-GFX12-FAKE16-NEXT: s_load_u16 s2, s[2:3], 0x0
+; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; SDAG-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; SDAG-GFX12-FAKE16-NEXT: v_s_rsq_f16 s2, s2
+; SDAG-GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; SDAG-GFX12-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
+; SDAG-GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s2, -1
+; SDAG-GFX12-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; SDAG-GFX12-FAKE16-NEXT: s_endpgm
;
; GISEL-GCN-LABEL: rsq_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index 050373430cce57..633c54f06a3621 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -539,34 +539,50 @@ define amdgpu_kernel void @constant_load_v16i1(ptr addrspace(1) %out, ptr addrsp
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: constant_load_v16i1:
; GFX12-FAKE16: ; %bb.0:
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
;
-; GFX1250-LABEL: constant_load_v16i1:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u16 v1, v0, s[2:3] nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-TRUE16-LABEL: constant_load_v16i1:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-TRUE16-NEXT: v_nop
+; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: s_load_u16 s2, s[2:3], 0x0 nv
+; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1250-TRUE16-NEXT: s_endpgm
+;
+; GFX1250-FAKE16-LABEL: constant_load_v16i1:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-FAKE16-NEXT: v_nop
+; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: s_load_u16 s2, s[2:3], 0x0 nv
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX1250-FAKE16-NEXT: s_endpgm
%load = load <16 x i1>, ptr addrspace(4) %in
store <16 x i1> %load, ptr addrspace(1) %out
ret void
@@ -2218,86 +2234,44 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
; EG-NEXT: ADD_INT * T14.X, T11.X, literal.x,
; EG-NEXT: 12(1.681558e-44), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_zextload_v16i1_to_v16i32:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v16, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v16, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
-; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-TRUE16-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10003
-; GFX12-TRUE16-NEXT: s_bfe_u32 s5, s2, 0x10001
-; GFX12-TRUE16-NEXT: s_bfe_u32 s6, s2, 0x10007
-; GFX12-TRUE16-NEXT: s_bfe_u32 s7, s2, 0x10009
-; GFX12-TRUE16-NEXT: s_bfe_u32 s8, s2, 0x1000d
-; GFX12-TRUE16-NEXT: s_and_b32 s9, s2, 1
-; GFX12-TRUE16-NEXT: s_bfe_u32 s10, s2, 0x1000a
-; GFX12-TRUE16-NEXT: s_bfe_u32 s2, s2, 0x1000c
-; GFX12-TRUE16-NEXT: s_bfe_u32 s11, s3, 0x10005
-; GFX12-TRUE16-NEXT: s_bfe_u32 s12, s3, 0x1000b
-; GFX12-TRUE16-NEXT: s_lshr_b32 s13, s3, 15
-; GFX12-TRUE16-NEXT: s_bfe_u32 s14, s3, 0x10002
-; GFX12-TRUE16-NEXT: s_bfe_u32 s15, s3, 0x10006
-; GFX12-TRUE16-NEXT: s_bfe_u32 s16, s3, 0x10004
-; GFX12-TRUE16-NEXT: s_bfe_u32 s17, s3, 0x10008
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s3, 0x1000e
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s8
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v13, s5 :: v_dual_mov_b32 v2, s3
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v8, s16
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s10
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v4, s17
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v10, s15
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s9
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v14, s14
-; GFX12-TRUE16-NEXT: s_clause 0x3
-; GFX12-TRUE16-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
-; GFX12-TRUE16-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
-; GFX12-TRUE16-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
-; GFX12-TRUE16-NEXT: global_store_b128 v16, v[12:15], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_zextload_v16i1_to_v16i32:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v16, 0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v16, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-FAKE16-NEXT: s_and_b32 s6, 0xffff, s2
-; GFX12-FAKE16-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX12-FAKE16-NEXT: s_bfe_u32 s4, s2, 0x10001
-; GFX12-FAKE16-NEXT: s_bfe_u32 s5, s2, 0x10007
-; GFX12-FAKE16-NEXT: s_bfe_u32 s7, s2, 0x10009
-; GFX12-FAKE16-NEXT: s_bfe_u32 s8, s2, 0x1000d
-; GFX12-FAKE16-NEXT: s_and_b32 s9, s2, 1
-; GFX12-FAKE16-NEXT: s_bfe_u32 s10, s2, 0x1000a
-; GFX12-FAKE16-NEXT: s_bfe_u32 s2, s2, 0x1000c
-; GFX12-FAKE16-NEXT: s_bfe_u32 s11, s6, 0x10005
-; GFX12-FAKE16-NEXT: s_bfe_u32 s12, s6, 0x1000b
-; GFX12-FAKE16-NEXT: s_lshr_b32 s13, s6, 15
-; GFX12-FAKE16-NEXT: s_bfe_u32 s14, s6, 0x10002
-; GFX12-FAKE16-NEXT: s_bfe_u32 s15, s6, 0x10006
-; GFX12-FAKE16-NEXT: s_bfe_u32 s16, s6, 0x10004
-; GFX12-FAKE16-NEXT: s_bfe_u32 s17, s6, 0x10008
-; GFX12-FAKE16-NEXT: s_bfe_u32 s6, s6, 0x1000e
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s8
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v2, s6
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v8, s16
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s10
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v4, s17
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v10, s15
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, s9
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v14, s14
-; GFX12-FAKE16-NEXT: s_clause 0x3
-; GFX12-FAKE16-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
-; GFX12-FAKE16-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
-; GFX12-FAKE16-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
-; GFX12-FAKE16-NEXT: global_store_b128 v16, v[12:15], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_zextload_v16i1_to_v16i32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_and_b32 s6, 0xffff, s2
+; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10003
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10001
+; GFX12-NEXT: s_bfe_u32 s5, s2, 0x10007
+; GFX12-NEXT: s_bfe_u32 s7, s2, 0x10009
+; GFX12-NEXT: s_bfe_u32 s8, s2, 0x1000d
+; GFX12-NEXT: s_and_b32 s9, s2, 1
+; GFX12-NEXT: s_bfe_u32 s10, s2, 0x1000a
+; GFX12-NEXT: s_bfe_u32 s2, s2, 0x1000c
+; GFX12-NEXT: s_bfe_u32 s11, s6, 0x10005
+; GFX12-NEXT: s_bfe_u32 s12, s6, 0x1000b
+; GFX12-NEXT: s_lshr_b32 s13, s6, 15
+; GFX12-NEXT: s_bfe_u32 s14, s6, 0x10002
+; GFX12-NEXT: s_bfe_u32 s15, s6, 0x10006
+; GFX12-NEXT: s_bfe_u32 s16, s6, 0x10004
+; GFX12-NEXT: s_bfe_u32 s17, s6, 0x10008
+; GFX12-NEXT: s_bfe_u32 s6, s6, 0x1000e
+; GFX12-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s8
+; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s7
+; GFX12-NEXT: v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v2, s6
+; GFX12-NEXT: v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, s17
+; GFX12-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v11, s5
+; GFX12-NEXT: v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, s16
+; GFX12-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s15
+; GFX12-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v13, s4
+; GFX12-NEXT: v_mov_b32_e32 v14, s14
+; GFX12-NEXT: s_clause 0x3
+; GFX12-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
+; GFX12-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
+; GFX12-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
+; GFX12-NEXT: global_store_b128 v16, v[12:15], s[0:1]
+; GFX12-NEXT: s_endpgm
;
; GFX1250-LABEL: constant_zextload_v16i1_to_v16i32:
; GFX1250: ; %bb.0:
@@ -2306,11 +2280,9 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v16, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u16 v0, v16, s[2:3] nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-NEXT: s_load_u16 s2, s[2:3], 0x0 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_and_b32 s6, 0xffff, s2
; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x10003
; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10001
@@ -2328,14 +2300,15 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
; GFX1250-NEXT: s_bfe_u32 s16, s6, 0x10004
; GFX1250-NEXT: s_bfe_u32 s17, s6, 0x10008
; GFX1250-NEXT: s_bfe_u32 s6, s6, 0x1000e
-; GFX1250-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s8
-; GFX1250-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s13
-; GFX1250-NEXT: v_dual_mov_b32 v5, s7 :: v_dual_mov_b32 v6, s10
-; GFX1250-NEXT: v_dual_mov_b32 v4, s17 :: v_dual_mov_b32 v7, s12
-; GFX1250-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, s9
-; GFX1250-NEXT: v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s11
-; GFX1250-NEXT: v_dual_mov_b32 v10, s15 :: v_dual_mov_b32 v14, s14
-; GFX1250-NEXT: v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v15, s3
+; GFX1250-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v0, s2
+; GFX1250-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v5, s7
+; GFX1250-NEXT: v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v2, s6
+; GFX1250-NEXT: v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, s17
+; GFX1250-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v11, s5
+; GFX1250-NEXT: v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, s16
+; GFX1250-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s15
+; GFX1250-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v13, s4
+; GFX1250-NEXT: v_mov_b32_e32 v14, s14
; GFX1250-NEXT: s_clause 0x3
; GFX1250-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
; GFX1250-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
@@ -7315,235 +7288,120 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; EG-NEXT: ADD_INT * T22.X, T15.X, literal.x,
; EG-NEXT: 28(3.923636e-44), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_zextload_v16i1_to_v16i64:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v9, v3
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v3, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v0
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x1000a
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v6, 11, 1
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10009
-; GFX12-TRUE16-NEXT: v_bfe_u32 v0, v6, 8, 1
-; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x1000c
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 15, v6
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:80
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x1000d
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, s3
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10007
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[0:3], s[0:1] offset:64
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10006
-; GFX12-TRUE16-NEXT: v_bfe_u32 v0, v6, 5, 1
-; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v6, 14, 1
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:96
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, s3
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10004
-; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10002
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:48
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v0
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:32
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, s3
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10001
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, 1
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s2
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, s3
-; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[6:9], s[0:1] offset:112
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_zextload_v16i1_to_v16i64:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v9, v3
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v3, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v0
-; GFX12-FAKE16-NEXT: s_bfe_u32 s3, s2, 0x1000a
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_bfe_u32 v4, v6, 11, 1
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-FAKE16-NEXT: s_bfe_u32 s3, s2, 0x10009
-; GFX12-FAKE16-NEXT: v_bfe_u32 v0, v6, 8, 1
-; GFX12-FAKE16-NEXT: s_bfe_u32 s4, s2, 0x1000c
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 15, v6
-; GFX12-FAKE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:80
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-FAKE16-NEXT: s_bfe_u32 s3, s2, 0x1000d
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s3
-; GFX12-FAKE16-NEXT: s_bfe_u32 s3, s2, 0x10007
-; GFX12-FAKE16-NEXT: global_store_b128 v3, v[0:3], s[0:1] offset:64
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-FAKE16-NEXT: s_bfe_u32 s4, s2, 0x10006
-; GFX12-FAKE16-NEXT: v_bfe_u32 v0, v6, 5, 1
-; GFX12-FAKE16-NEXT: v_bfe_u32 v6, v6, 14, 1
-; GFX12-FAKE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:96
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s3
-; GFX12-FAKE16-NEXT: s_bfe_u32 s3, s2, 0x10004
-; GFX12-FAKE16-NEXT: s_bfe_u32 s4, s2, 0x10002
-; GFX12-FAKE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:48
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v0
-; GFX12-FAKE16-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX12-FAKE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:32
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s3
-; GFX12-FAKE16-NEXT: s_bfe_u32 s3, s2, 0x10001
-; GFX12-FAKE16-NEXT: s_and_b32 s2, s2, 1
-; GFX12-FAKE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:16
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, s2
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s3
-; GFX12-FAKE16-NEXT: s_clause 0x1
-; GFX12-FAKE16-NEXT: global_store_b128 v3, v[6:9], s[0:1] offset:112
-; GFX12-FAKE16-NEXT: global_store_b128 v3, v[2:5], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
-;
-; GFX1250-TRUE16-LABEL: constant_zextload_v16i1_to_v16i64:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-TRUE16-NEXT: v_nop
-; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v3, 0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, v3
-; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: global_load_u16 v0, v3, s[2:3] nv
-; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1250-TRUE16-NEXT: s_and_b32 s3, 0xffff, s2
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x1000a
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s5, s3, 0x1000b
-; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v2, s4
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v4, s5
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10009
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s5, s3, 0x10008
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1250-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:80
-; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v2, s5
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s5, s3, 0x1000e
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v4, s4
-; GFX1250-TRUE16-NEXT: s_lshr_b32 s4, s3, 15
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s3, s3, 0x10005
-; GFX1250-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:64
-; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v2, s5
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s5, s2, 0x1000c
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v4, s4
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x1000d
-; GFX1250-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:112
-; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v2, s5
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s5, s2, 0x10006
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v4, s4
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10007
-; GFX1250-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:96
-; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10004
-; GFX1250-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:48
-; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v4, s3
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10002
-; GFX1250-TRUE16-NEXT: s_bfe_u32 s2, s2, 0x10001
-; GFX1250-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX1250-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:32
-; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v4, s3
-; GFX1250-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:16
-; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v2, s2
-; GFX1250-TRUE16-NEXT: global_store_b128 v3, v[0:3], s[0:1]
-; GFX1250-TRUE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_zextload_v16i1_to_v16i64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000a
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s4
+; GFX12-NEXT: s_and_b32 s3, 0xffff, s2
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10009
+; GFX12-NEXT: s_bfe_u32 s5, s3, 0x1000b
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, s5
+; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10008
+; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:80
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s5
+; GFX12-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-NEXT: s_lshr_b32 s4, s3, 15
+; GFX12-NEXT: s_bfe_u32 s5, s3, 0x1000e
+; GFX12-NEXT: s_bfe_u32 s3, s3, 0x10005
+; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:64
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s5
+; GFX12-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000d
+; GFX12-NEXT: s_bfe_u32 s5, s2, 0x1000c
+; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:112
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s5
+; GFX12-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10007
+; GFX12-NEXT: s_bfe_u32 s5, s2, 0x10006
+; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:96
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s5
+; GFX12-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10004
+; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s4
+; GFX12-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10003
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10002
+; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:32
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s4
+; GFX12-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10001
+; GFX12-NEXT: s_and_b32 s2, s2, 1
+; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-NEXT: s_endpgm
;
-; GFX1250-FAKE16-LABEL: constant_zextload_v16i1_to_v16i64:
-; GFX1250-FAKE16: ; %bb.0:
-; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-FAKE16-NEXT: v_nop
-; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v5, v1
-; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v9, v1
-; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v13, v1
-; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v15, v1 :: v_dual_mov_b32 v17, v1
-; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v21, v1
-; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v23, v1 :: v_dual_mov_b32 v25, v1
-; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v27, v1 :: v_dual_mov_b32 v29, v1
-; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: global_load_u16 v12, v1, s[2:3] nv
-; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-FAKE16-NEXT: s_mov_b32 s2, 0xffff
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v31, v1 :: v_dual_bitop2_b32 v22, s2, v12 bitop3:0x40
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v0, v12, 10, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v6, v12, 9, 1
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v28, 1, v12
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v14, v12, 13, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v2, v22, 11, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v4, v22, 8, 1
-; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 15, v22
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v8, v22, 14, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v18, v12, 7, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v26, v12, 3, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v30, v12, 1, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v24, v12, 2, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v20, v12, 4, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v16, v12, 6, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v12, v12, 12, 1
-; GFX1250-FAKE16-NEXT: v_bfe_u32 v22, v22, 5, 1
-; GFX1250-FAKE16-NEXT: s_clause 0x7
-; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:80
-; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[4:7], s[0:1] offset:64
-; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[8:11], s[0:1] offset:112
-; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[12:15], s[0:1] offset:96
-; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[16:19], s[0:1] offset:48
-; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[20:23], s[0:1] offset:32
-; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[24:27], s[0:1] offset:16
-; GFX1250-FAKE16-NEXT: global_store_b128 v1, v[28:31], s[0:1]
-; GFX1250-FAKE16-NEXT: s_endpgm
+; GFX1250-LABEL: constant_zextload_v16i1_to_v16i64:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_load_u16 s2, s[2:3], 0x0 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x1000a
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s4
+; GFX1250-NEXT: s_and_b32 s3, 0xffff, s2
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10009
+; GFX1250-NEXT: s_bfe_u32 s5, s3, 0x1000b
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, s5
+; GFX1250-NEXT: s_bfe_u32 s5, s3, 0x10008
+; GFX1250-NEXT: v_mov_b32_e32 v1, v3
+; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:80
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
+; GFX1250-NEXT: s_lshr_b32 s4, s3, 15
+; GFX1250-NEXT: s_bfe_u32 s5, s3, 0x1000e
+; GFX1250-NEXT: s_bfe_u32 s3, s3, 0x10005
+; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:64
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x1000d
+; GFX1250-NEXT: s_bfe_u32 s5, s2, 0x1000c
+; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:112
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10007
+; GFX1250-NEXT: s_bfe_u32 s5, s2, 0x10006
+; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:96
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10004
+; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:48
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v4, s3
+; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x10003
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10002
+; GFX1250-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-NEXT: s_bfe_u32 s2, s2, 0x10001
+; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:32
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v4, s3
+; GFX1250-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:16
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_mov_b32_e32 v2, s2
+; GFX1250-NEXT: global_store_b128 v3, v[0:3], s[0:1]
+; GFX1250-NEXT: s_endpgm
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = zext <16 x i1> %load to <16 x i64>
store <16 x i64> %ext, ptr addrspace(1) %out
@@ -7825,7 +7683,7 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; EG-NEXT: MOV T20.W, T20.Z,
; EG-NEXT: MOV * T14.W, T14.Z,
; EG-NEXT: 28(3.923636e-44), 0(0.000000e+00)
-;
+
; GFX12-TRUE16-LABEL: constant_sextload_v16i1_to_v16i64:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@@ -7967,7 +7825,7 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-FAKE16-NEXT: global_store_b128 v32, v[24:27], s[0:1] offset:16
; GFX12-FAKE16-NEXT: global_store_b128 v32, v[28:31], s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
-;
+
; GFX1250-LABEL: constant_sextload_v16i1_to_v16i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -7975,7 +7833,6 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b32_e32 v32, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: global_load_u16 v0, v32, s[2:3] nv
; GFX1250-NEXT: s_wait_loadcnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
index 48a2db2aca1e4a..895dedfff038ec 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
@@ -84,18 +84,19 @@ define amdgpu_kernel void @constant_load_i16(ptr addrspace(1) %out, ptr addrspac
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: constant_load_i16:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
entry:
@@ -765,29 +766,31 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v8, 0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_clause 0x7
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v3, v8, s[0:1] offset:12
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v7, v8, s[0:1] offset:28
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v6, v8, s[0:1] offset:24
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v5, v8, s[0:1] offset:20
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v4, v8, s[0:1] offset:16
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v2, v8, s[0:1] offset:8
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v1, v8, s[0:1] offset:4
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v8, s[0:1]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x7
+; GFX12-TRUE16-NEXT: s_load_u16 s2, s[0:1], 0xc
+; GFX12-TRUE16-NEXT: s_load_u16 s3, s[0:1], 0x8
+; GFX12-TRUE16-NEXT: s_load_u16 s4, s[0:1], 0x4
+; GFX12-TRUE16-NEXT: s_load_u16 s5, s[0:1], 0x0
+; GFX12-TRUE16-NEXT: s_load_u16 s6, s[0:1], 0x1c
+; GFX12-TRUE16-NEXT: s_load_u16 s7, s[0:1], 0x18
+; GFX12-TRUE16-NEXT: s_load_u16 s8, s[0:1], 0x14
+; GFX12-TRUE16-NEXT: s_load_u16 s9, s[0:1], 0x10
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s5
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, s6
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, s7
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, s8
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, s9
+; GFX12-TRUE16-NEXT: s_clause 0x7
; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v3, v8, s[0:1] offset:14
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x7
; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v7, v8, s[0:1] offset:30
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x7
; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v6, v8, s[0:1] offset:26
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x7
; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v5, v8, s[0:1] offset:22
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x7
; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v4, v8, s[0:1] offset:18
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x7
; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v2, v8, s[0:1] offset:10
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x7
; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v1, v8, s[0:1] offset:6
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x7
; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v0, v8, s[0:1] offset:2
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_clause 0x1
@@ -798,32 +801,30 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GFX12-FAKE16-LABEL: constant_load_v16i16_align2:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v8, 0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_clause 0x7
-; GFX12-FAKE16-NEXT: global_load_u16 v3, v8, s[0:1] offset:12
-; GFX12-FAKE16-NEXT: global_load_u16 v7, v8, s[0:1] offset:28
-; GFX12-FAKE16-NEXT: global_load_u16 v6, v8, s[0:1] offset:24
-; GFX12-FAKE16-NEXT: global_load_u16 v5, v8, s[0:1] offset:20
-; GFX12-FAKE16-NEXT: global_load_u16 v4, v8, s[0:1] offset:16
-; GFX12-FAKE16-NEXT: global_load_u16 v2, v8, s[0:1] offset:8
-; GFX12-FAKE16-NEXT: global_load_u16 v1, v8, s[0:1] offset:4
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v8, s[0:1]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x7
+; GFX12-FAKE16-NEXT: s_load_u16 s2, s[0:1], 0xc
+; GFX12-FAKE16-NEXT: s_load_u16 s3, s[0:1], 0x8
+; GFX12-FAKE16-NEXT: s_load_u16 s4, s[0:1], 0x4
+; GFX12-FAKE16-NEXT: s_load_u16 s5, s[0:1], 0x0
+; GFX12-FAKE16-NEXT: s_load_u16 s6, s[0:1], 0x1c
+; GFX12-FAKE16-NEXT: s_load_u16 s7, s[0:1], 0x18
+; GFX12-FAKE16-NEXT: s_load_u16 s8, s[0:1], 0x14
+; GFX12-FAKE16-NEXT: s_load_u16 s9, s[0:1], 0x10
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v3, s2
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v1, s4
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v7, s6
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v6, s7 :: v_dual_mov_b32 v5, s8
+; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s9
+; GFX12-FAKE16-NEXT: s_clause 0x7
; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v3, v8, s[0:1] offset:14
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x7
; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v7, v8, s[0:1] offset:30
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x7
; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v6, v8, s[0:1] offset:26
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x7
; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v5, v8, s[0:1] offset:22
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x7
; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v4, v8, s[0:1] offset:18
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x7
; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v2, v8, s[0:1] offset:10
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x7
; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v1, v8, s[0:1] offset:6
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x7
; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v0, v8, s[0:1] offset:2
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: s_clause 0x1
@@ -5422,27 +5423,17 @@ define amdgpu_kernel void @constant_zextload_i16_to_i64(ptr addrspace(1) %out, p
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_zextload_i16_to_i64:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-TRUE16-NEXT: global_store_b64 v1, v[0:1], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_zextload_i16_to_i64:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v1, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: global_store_b64 v1, v[0:1], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_zextload_i16_to_i64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX12-NEXT: global_store_b64 v1, v[0:1], s[0:1]
+; GFX12-NEXT: s_endpgm
%a = load i16, ptr addrspace(4) %in
%ext = zext i16 %a to i64
store i64 %ext, ptr addrspace(1) %out
@@ -5524,31 +5515,19 @@ define amdgpu_kernel void @constant_sextload_i16_to_i64(ptr addrspace(1) %out, p
; EG-NEXT: ASHR * T0.Y, PV.X, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_sextload_i16_to_i64:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v2, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_sextload_i16_to_i64:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v2, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_sextload_i16_to_i64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_sext_i32_i16 s2, s2
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_ashr_i32 s3, s2, 31
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-NEXT: s_endpgm
%a = load i16, ptr addrspace(4) %in
%ext = sext i16 %a to i64
store i64 %ext, ptr addrspace(1) %out
@@ -5623,27 +5602,17 @@ define amdgpu_kernel void @constant_zextload_v1i16_to_v1i64(ptr addrspace(1) %ou
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_zextload_v1i16_to_v1i64:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-TRUE16-NEXT: global_store_b64 v1, v[0:1], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_zextload_v1i16_to_v1i64:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v1, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: global_store_b64 v1, v[0:1], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_zextload_v1i16_to_v1i64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX12-NEXT: global_store_b64 v1, v[0:1], s[0:1]
+; GFX12-NEXT: s_endpgm
%load = load <1 x i16>, ptr addrspace(4) %in
%ext = zext <1 x i16> %load to <1 x i64>
store <1 x i64> %ext, ptr addrspace(1) %out
@@ -5720,31 +5689,19 @@ define amdgpu_kernel void @constant_sextload_v1i16_to_v1i64(ptr addrspace(1) %ou
; EG-NEXT: ASHR * T0.Y, PV.X, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_sextload_v1i16_to_v1i64:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v2, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_sextload_v1i16_to_v1i64:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v2, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_sextload_v1i16_to_v1i64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_sext_i32_i16 s2, s2
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_ashr_i32 s3, s2, 31
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-NEXT: s_endpgm
%load = load <1 x i16>, ptr addrspace(4) %in
%ext = sext <1 x i16> %load to <1 x i64>
store <1 x i64> %ext, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index 57d1aba94566e0..ec1444d983dbc7 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -183,18 +183,19 @@ define amdgpu_kernel void @constant_load_v2i8(ptr addrspace(1) %out, ptr addrspa
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: constant_load_v2i8:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
entry:
@@ -944,33 +945,20 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i32(ptr addrspace(1) %out
; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,
; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45)
;
-; GFX12-TRUE16-LABEL: constant_zextload_v2i8_to_v2i32:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v2, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_zextload_v2i8_to_v2i32:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v2, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
-; GFX12-FAKE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_zextload_v2i8_to_v2i32:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_and_b32 s3, 0xffff, s2
+; GFX12-NEXT: s_and_b32 s2, s2, 0xff
+; GFX12-NEXT: s_lshr_b32 s3, s3, 8
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX12-NEXT: s_endpgm
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = zext <2 x i8> %load to <2 x i32>
store <2 x i32> %ext, ptr addrspace(1) %out
@@ -5633,37 +5621,21 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i64(ptr addrspace(1) %out
; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,
; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45)
;
-; GFX12-TRUE16-LABEL: constant_zextload_v2i8_to_v2i64:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v1
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_zextload_v2i8_to_v2i64:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v3, v1
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v1, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-FAKE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_zextload_v2i8_to_v2i64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_and_b32 s3, 0xffff, s2
+; GFX12-NEXT: s_and_b32 s2, s2, 0xff
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX12-NEXT: s_lshr_b32 s3, s3, 8
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v3, v1
+; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-NEXT: s_endpgm
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = zext <2 x i8> %load to <2 x i64>
store <2 x i64> %ext, ptr addrspace(1) %out
@@ -5763,39 +5735,25 @@ define amdgpu_kernel void @constant_sextload_v2i8_to_v2i64(ptr addrspace(1) %out
; EG-NEXT: ASHR * T4.W, PV.Z, literal.y,
; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
;
-; GFX12-TRUE16-LABEL: constant_sextload_v2i8_to_v2i64:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v4, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v1, 0, 8
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX12-TRUE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_sextload_v2i8_to_v2i64:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, 0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v4, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_bfe_i32 v2, v1, 0, 8
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX12-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_sextload_v2i8_to_v2i64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: v_mov_b32_e32 v4, 0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: s_lshr_b32 s2, s2, 8
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_mov_b32_e32 v3, s3
+; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-NEXT: v_mov_b32_e32 v2, s2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX12-NEXT: s_endpgm
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = sext <2 x i8> %load to <2 x i64>
store <2 x i64> %ext, ptr addrspace(1) %out
@@ -9513,35 +9471,20 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i16(ptr addrspace(1) %out
; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_zextload_v2i8_to_v2i16:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_zextload_v2i8_to_v2i16:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v1
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_zextload_v2i8_to_v2i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_and_b32 s3, 0xffff, s2
+; GFX12-NEXT: s_and_b32 s2, s2, 0xff
+; GFX12-NEXT: s_lshr_b32 s3, s3, 8
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: s_endpgm
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = zext <2 x i8> %load to <2 x i16>
store <2 x i16> %ext, ptr addrspace(1) %out
@@ -9643,37 +9586,20 @@ define amdgpu_kernel void @constant_sextload_v2i8_to_v2i16(ptr addrspace(1) %out
; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_sextload_v2i8_to_v2i16:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v1, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_sextload_v2i8_to_v2i16:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_bfe_i32 v2, v1, 0, 16
-; GFX12-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX12-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_sextload_v2i8_to_v2i16:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_sext_i32_i16 s3, s2
+; GFX12-NEXT: s_bfe_i32 s2, s2, 0x80000
+; GFX12-NEXT: s_lshr_b32 s3, s3, 8
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: s_endpgm
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = sext <2 x i8> %load to <2 x i16>
store <2 x i16> %ext, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll
index ac4ee03db37256..b403c6f3419b48 100644
--- a/llvm/test/CodeGen/AMDGPU/min.ll
+++ b/llvm/test/CodeGen/AMDGPU/min.ll
@@ -3324,17 +3324,17 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x0 nv
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_load_u16 v1, v0, s[14:15]
-; GFX1250-NEXT: global_load_u16 v2, v0, s[12:13]
-; GFX1250-NEXT: s_wait_loadcnt 0x1
-; GFX1250-NEXT: v_and_b32_e32 v3, 0xffff, v1
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_and_b32_e32 v4, 0xffff, v2
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, v4, v3
-; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: s_load_u16 s0, s[14:15], 0x0
+; GFX1250-NEXT: s_load_u16 s1, s[12:13], 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_and_b32 s2, 0xffff, s0
+; GFX1250-NEXT: s_and_b32 s3, 0xffff, s1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_cmp_lt_u32 s3, s2
+; GFX1250-NEXT: s_cselect_b32 s0, s1, s0
+; GFX1250-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v1, s0
+; GFX1250-NEXT: v_mov_b32_e32 v2, s1
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: global_store_b16 v0, v1, s[8:9]
; GFX1250-NEXT: global_store_b8 v0, v2, s[10:11]
diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
index 60078fde83b56b..d8ce9f1726965a 100644
--- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
@@ -298,17 +298,30 @@ define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inr
; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
-; GFX1250-LABEL: incorrect_type_i16_block_count_x:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-NEXT: global_load_u16 v1, v0, s[0:1] offset:8 nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-FAKE16-LABEL: incorrect_type_i16_block_count_x:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-FAKE16-NEXT: v_nop
+; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-FAKE16-NEXT: s_load_u16 s0, s[0:1], 0x8 nv
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-FAKE16-NEXT: global_store_b16 v0, v1, s[2:3]
+; GFX1250-FAKE16-NEXT: s_endpgm
+;
+; GFX1250-REAL16-LABEL: incorrect_type_i16_block_count_x:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-REAL16-NEXT: v_nop
+; GFX1250-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-REAL16-NEXT: s_load_u16 s0, s[0:1], 0x8 nv
+; GFX1250-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX1250-REAL16-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-REAL16-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i16, ptr addrspace(4) %imp_arg_ptr
store i16 %load, ptr addrspace(1) %out
@@ -1172,6 +1185,3 @@ define amdgpu_kernel void @preload_block_count_z_workgroup_size_z_remainder_z(pt
}
attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX1250-FAKE16: {{.*}}
-; GFX1250-REAL16: {{.*}}
>From 8e125371ae4ebca5a45a5e3aafafcb82ba226345 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Wed, 23 Sep 2026 05:19:43 -0500
Subject: [PATCH 2/7] Use legalization approach
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/include/llvm/CodeGen/TargetLowering.h | 6 +
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 +-
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 42 +
llvm/lib/Target/AMDGPU/SIISelLowering.h | 1 +
llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fcmp.f16.ll | 88 +-
llvm/test/CodeGen/AMDGPU/fmax3.ll | 48 +-
llvm/test/CodeGen/AMDGPU/fmaximum.ll | 6 +-
llvm/test/CodeGen/AMDGPU/fmin3.ll | 48 +-
llvm/test/CodeGen/AMDGPU/fminimum.ll | 6 +-
llvm/test/CodeGen/AMDGPU/frem.ll | 13632 +++++++++-------
llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 275 +-
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll | 158 +-
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll | 65 +-
llvm/test/CodeGen/AMDGPU/min.ll | 11 +-
...-to-valu-pseudo-scalar-trans-f16-true16.ll | 50 +-
.../AMDGPU/preload-implicit-kernargs.ll | 39 +-
23 files changed, 8004 insertions(+), 6490 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 46521fa8c544a6..a53b4fdd9f91f7 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4845,6 +4845,12 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
return isTypeLegal(VT);
}
+ /// Overload that provides context about the specific node being optimized.
+ /// By default, calls the version without the node parameter.
+ virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT, SDNode *N) const {
+ return isTypeDesirableForOp(Opc, VT);
+ }
+
/// Return true if it is profitable for dag combiner to transform a floating
/// point op of specified opcode to a equivalent op of an integer
/// type. e.g. f32 load -> i32 load can be profitable on ARM.
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f94c861200f206..c43f6990fb18c5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17970,7 +17970,8 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
// fold (truncate (load x)) -> (smaller load x)
// fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
- if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
+ if (!LegalTypes ||
+ TLI.isTypeDesirableForOp(N0.getOpcode(), VT, N0.getNode())) {
if (SDValue Reduced = reduceLoadWidth(N))
return Reduced;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index be0424dc379b46..3ebd668d32b421 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2505,6 +2505,24 @@ bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
return TargetLowering::isTypeDesirableForOp(Op, VT);
}
+bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT,
+ SDNode *N) const {
+ // Do not convert uniform i32 loads to 16-bit.
+ // Uniform 16-bit loads are legalized to i16 = trunc (zextload i16->i32)
+ // to match subword load patterns. Allowing conversion back to a 16-bit
+ // load would create an infinite loop.
+ if (Subtarget->hasScalarSubwordLoads() && Op == ISD::LOAD && !VT.isVector() &&
+ VT.getSizeInBits() == 16) {
+ auto *Load = dyn_cast<LoadSDNode>(N);
+ if (Load && Load->getValueType(0) == MVT::i32 && !Load->isDivergent() &&
+ AMDGPU::isUniformMMO(Load->getMemOperand())) {
+ return false;
+ }
+ }
+
+ return isTypeDesirableForOp(Op, VT);
+}
+
MachinePointerInfo
SITargetLowering::getKernargSegmentPtrInfo(MachineFunction &MF) const {
// This isn't really a constant pool but close enough.
@@ -13605,6 +13623,30 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
MachineMemOperand *MMO = Load->getMemOperand();
if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) {
+ // Legalize uniform 16-bit loads to i16 = trunc (zextload i16->i32)
+ // to match subword load patterns.
+ if (!MemVT.isVector() && MemVT.getSizeInBits() == 16 &&
+ isTypeLegal(MemVT) && Subtarget->hasScalarSubwordLoads() &&
+ !Load->isDivergent() && AMDGPU::isUniformMMO(MMO)) {
+ SDValue Chain = Load->getChain();
+ SDValue BasePtr = Load->getBasePtr();
+
+ // Load as i16 and zero-extend to i32 (matches S_LOAD_U16 behavior)
+ SDValue NewLD = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain,
+ BasePtr, MVT::i16, MMO);
+
+ // Truncate back to i16
+ SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, NewLD);
+
+ // For f16/bf16, bitcast from i16 to the original fp type
+ SDValue Result = (MemVT == MVT::i16)
+ ? Trunc
+ : DAG.getNode(ISD::BITCAST, DL, MemVT, Trunc);
+
+ SDValue Ops[] = {Result, NewLD.getValue(1)};
+ return DAG.getMergeValues(Ops, DL);
+ }
+
if (MemVT == MVT::i16 && isTypeLegal(MVT::i16))
return SDValue();
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index 7de2c529028c36..c55ecce8a28fe6 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -417,6 +417,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override;
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
+ bool isTypeDesirableForOp(unsigned Op, EVT VT, SDNode *N) const override;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
diff --git a/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll b/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
index 7fe521102be992..25a488f2b795fb 100644
--- a/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
+++ b/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
@@ -126,9 +126,9 @@ define amdgpu_kernel void @d16_two_order_group(ptr addrspace(3) %in1, ptr %in2)
; GFX12-NEXT: flat_load_d16_b16 v0, v[1:2]
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v3, s0
-; GFX12-NEXT: ds_load_u16_d16_hi v0, v3
+; GFX12-NEXT: ds_load_u16 v3, v3
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX12-NEXT: v_or_b16 v0.l, v3.l, v0.l
; GFX12-NEXT: flat_store_b16 v[1:2], v0
; GFX12-NEXT: s_endpgm
%i16a = load i16, ptr addrspace(3) %in1, align 2
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
index 1720f242fcc96d..3685fb0d5d18fb 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
@@ -131,13 +131,13 @@ define amdgpu_kernel void @fcmp_f16_lt(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -303,9 +303,9 @@ define amdgpu_kernel void @fcmp_f16_lt_abs(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
@@ -483,13 +483,13 @@ define amdgpu_kernel void @fcmp_f16_eq(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -655,13 +655,13 @@ define amdgpu_kernel void @fcmp_f16_le(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -827,13 +827,13 @@ define amdgpu_kernel void @fcmp_f16_gt(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -999,13 +999,13 @@ define amdgpu_kernel void @fcmp_f16_lg(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -1171,13 +1171,13 @@ define amdgpu_kernel void @fcmp_f16_ge(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -1343,13 +1343,13 @@ define amdgpu_kernel void @fcmp_f16_o(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -1515,13 +1515,13 @@ define amdgpu_kernel void @fcmp_f16_u(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -1687,13 +1687,13 @@ define amdgpu_kernel void @fcmp_f16_nge(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -1859,13 +1859,13 @@ define amdgpu_kernel void @fcmp_f16_nlg(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -2031,13 +2031,13 @@ define amdgpu_kernel void @fcmp_f16_ngt(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -2203,13 +2203,13 @@ define amdgpu_kernel void @fcmp_f16_nle(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -2375,13 +2375,13 @@ define amdgpu_kernel void @fcmp_f16_neq(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -2547,13 +2547,13 @@ define amdgpu_kernel void @fcmp_f16_nlt(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fmax3.ll b/llvm/test/CodeGen/AMDGPU/fmax3.ll
index f34efb4f4af2ba..6618966a8e1ce4 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax3.ll
@@ -696,15 +696,15 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5
; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6
; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v1.l, v2.l, v0.l
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
;
@@ -760,15 +760,15 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13
; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14
; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15
-; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8
; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9
-; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v1.l, v2.l, v0.l
; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-TRUE16-NEXT: s_endpgm
;
@@ -1044,24 +1044,24 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
; GFX12-TRUE16-NEXT: s_mov_b32 s15, s11
; GFX12-TRUE16-NEXT: s_mov_b32 s18, s10
; GFX12-TRUE16-NEXT: s_mov_b32 s19, s11
-; GFX12-TRUE16-NEXT: s_mov_b32 s22, s10
-; GFX12-TRUE16-NEXT: s_mov_b32 s23, s11
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s16, s4
; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5
-; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6
-; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT: s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT: s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v1.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v2.l, v1.l, v0.l
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
;
@@ -1108,24 +1108,24 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
; GFX1250-TRUE16-NEXT: s_mov_b32 s7, s3
; GFX1250-TRUE16-NEXT: s_mov_b32 s18, s2
; GFX1250-TRUE16-NEXT: s_mov_b32 s19, s3
-; GFX1250-TRUE16-NEXT: s_mov_b32 s22, s2
-; GFX1250-TRUE16-NEXT: s_mov_b32 s23, s3
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s4, s10
; GFX1250-TRUE16-NEXT: s_mov_b32 s5, s11
; GFX1250-TRUE16-NEXT: s_mov_b32 s16, s12
; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13
-; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14
-; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15
-; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: s_mov_b32 s12, s14
+; GFX1250-TRUE16-NEXT: s_mov_b32 s13, s15
+; GFX1250-TRUE16-NEXT: s_mov_b32 s14, s2
+; GFX1250-TRUE16-NEXT: s_mov_b32 s15, s3
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[12:15], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8
; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9
-; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v1.l, v0.l, v0.h
+; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v2.l, v1.l, v0.l
; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
index 213d6ffeb9f00e..dffa28a5c52fd2 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
@@ -1492,11 +1492,11 @@ define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3] scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT: global_load_u16 v2, v1, s[4:5] scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-SDAG-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3.ll b/llvm/test/CodeGen/AMDGPU/fmin3.ll
index c03e81e6b71299..bcd50ee8f47fd6 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3.ll
@@ -696,15 +696,15 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5
; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6
; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v1.l, v2.l, v0.l
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
;
@@ -760,15 +760,15 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13
; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14
; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15
-; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8
; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9
-; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
+; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v1.l, v2.l, v0.l
; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-TRUE16-NEXT: s_endpgm
;
@@ -1044,24 +1044,24 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
; GFX12-TRUE16-NEXT: s_mov_b32 s15, s11
; GFX12-TRUE16-NEXT: s_mov_b32 s18, s10
; GFX12-TRUE16-NEXT: s_mov_b32 s19, s11
-; GFX12-TRUE16-NEXT: s_mov_b32 s22, s10
-; GFX12-TRUE16-NEXT: s_mov_b32 s23, s11
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s16, s4
; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5
-; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6
-; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT: s_mov_b32 s6, s10
+; GFX12-TRUE16-NEXT: s_mov_b32 s7, s11
+; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v1.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v2.l, v1.l, v0.l
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
;
@@ -1108,24 +1108,24 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
; GFX1250-TRUE16-NEXT: s_mov_b32 s7, s3
; GFX1250-TRUE16-NEXT: s_mov_b32 s18, s2
; GFX1250-TRUE16-NEXT: s_mov_b32 s19, s3
-; GFX1250-TRUE16-NEXT: s_mov_b32 s22, s2
-; GFX1250-TRUE16-NEXT: s_mov_b32 s23, s3
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s4, s10
; GFX1250-TRUE16-NEXT: s_mov_b32 s5, s11
; GFX1250-TRUE16-NEXT: s_mov_b32 s16, s12
; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13
-; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14
-; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15
-; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: s_mov_b32 s12, s14
+; GFX1250-TRUE16-NEXT: s_mov_b32 s13, s15
+; GFX1250-TRUE16-NEXT: s_mov_b32 s14, s2
+; GFX1250-TRUE16-NEXT: s_mov_b32 s15, s3
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[12:15], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8
; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9
-; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v1.l, v0.l, v0.h
+; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v2.l, v1.l, v0.l
; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll
index 094dd76e0f945b..11acac09aa30f4 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll
@@ -1492,11 +1492,11 @@ define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3] scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT: global_load_u16 v2, v1, s[4:5] scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-SDAG-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index f26e177173bd8e..e2ea47c6b27fb0 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -28,28 +28,42 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e64 v2, |v1|
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
-; SI-NEXT: s_cbranch_vccz .LBB0_4
-; SI-NEXT: ; %bb.1: ; %frem.compute
+; SI-NEXT: v_cvt_f32_f16_e64 v4, |v1|
+; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v4
+; SI-NEXT: s_cbranch_vccz .LBB0_2
+; SI-NEXT: ; %bb.1: ; %frem.else
+; SI-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v4
+; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; SI-NEXT: s_mov_b64 s[0:1], 0
+; SI-NEXT: s_branch .LBB0_3
+; SI-NEXT: .LBB0_2:
+; SI-NEXT: s_mov_b64 s[0:1], -1
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: .LBB0_3: ; %Flow18
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s0, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s0, 1
+; SI-NEXT: s_cbranch_scc1 .LBB0_9
+; SI-NEXT: ; %bb.4: ; %frem.compute
; SI-NEXT: s_mov_b32 s3, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v3
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v4
-; SI-NEXT: v_frexp_mant_f32_e32 v4, v3
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s3
-; SI-NEXT: v_frexp_mant_f32_e32 v4, v2
-; SI-NEXT: s_cselect_b32 s2, s0, 0
-; SI-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: v_ldexp_f32_e64 v2, v4, 1
+; SI-NEXT: v_frexp_mant_f32_e32 v2, v3
+; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; SI-NEXT: v_ldexp_f32_e64 v3, v2, 11
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s3
+; SI-NEXT: v_frexp_mant_f32_e32 v2, v4
+; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; SI-NEXT: v_ldexp_f32_e64 v2, v2, 1
; SI-NEXT: v_div_scale_f32 v5, s[4:5], v2, v2, 1.0
; SI-NEXT: v_rcp_f32_e32 v6, v5
-; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
+; SI-NEXT: s_cselect_b32 s2, s0, 0
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v4
; SI-NEXT: v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT: v_fma_f32 v7, -v5, v6, 1.0
@@ -66,11 +80,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB0_5
-; SI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB0_8
+; SI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s1, s2, s3
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB0_3: ; %frem.loop_body
+; SI-NEXT: .LBB0_6: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v5, v3
; SI-NEXT: v_mul_f32_e32 v3, v5, v4
@@ -82,18 +96,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB0_3
-; SI-NEXT: s_branch .LBB0_6
-; SI-NEXT: .LBB0_4: ; %frem.else
-; SI-NEXT: v_and_b32_e32 v4, 0x8000, v0
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; SI-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc
-; SI-NEXT: s_branch .LBB0_7
-; SI-NEXT: .LBB0_5:
-; SI-NEXT: v_mov_b32_e32 v5, v3
-; SI-NEXT: .LBB0_6: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB0_6
+; SI-NEXT: ; %bb.7: ; %Flow
+; SI-NEXT: v_mov_b32_e32 v3, v5
+; SI-NEXT: .LBB0_8: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s1, s1, -10
-; SI-NEXT: v_ldexp_f32_e64 v3, v5, s1
+; SI-NEXT: v_ldexp_f32_e64 v3, v3, s1
; SI-NEXT: v_mul_f32_e32 v4, v3, v4
; SI-NEXT: v_rndne_f32_e32 v4, v4
; SI-NEXT: v_fma_f32 v3, -v4, v2, v3
@@ -105,7 +113,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_and_b32_e32 v3, 0x8000, v0
; SI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: .LBB0_7:
+; SI-NEXT: .LBB0_9: ; %Flow19
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; SI-NEXT: s_mov_b32 s0, 0x7f800000
@@ -133,64 +141,72 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; CI-NEXT: buffer_load_ushort v1, off, s[0:3], 0 offset:8
; CI-NEXT: s_waitcnt vmcnt(1)
-; CI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; CI-NEXT: v_cvt_f32_f16_e64 v4, |v0|
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |v1|
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
-; CI-NEXT: s_cbranch_vccz .LBB0_4
-; CI-NEXT: ; %bb.1: ; %frem.compute
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
-; CI-NEXT: v_frexp_mant_f32_e32 v3, v3
-; CI-NEXT: v_ldexp_f32_e64 v6, v3, 11
-; CI-NEXT: v_frexp_mant_f32_e32 v3, v2
-; CI-NEXT: v_ldexp_f32_e64 v3, v3, 1
+; CI-NEXT: v_cvt_f32_f16_e64 v3, |v1|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
+; CI-NEXT: s_cbranch_vccz .LBB0_2
+; CI-NEXT: ; %bb.1: ; %frem.else
+; CI-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
+; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; CI-NEXT: s_mov_b64 s[0:1], 0
+; CI-NEXT: s_branch .LBB0_3
+; CI-NEXT: .LBB0_2:
+; CI-NEXT: s_mov_b64 s[0:1], -1
+; CI-NEXT: ; implicit-def: $vgpr2
+; CI-NEXT: .LBB0_3: ; %Flow18
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cselect_b32 s0, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s0, 1
+; CI-NEXT: s_cbranch_scc1 .LBB0_9
+; CI-NEXT: ; %bb.4: ; %frem.compute
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
+; CI-NEXT: v_frexp_mant_f32_e32 v2, v4
+; CI-NEXT: v_frexp_mant_f32_e32 v4, v3
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
+; CI-NEXT: v_ldexp_f32_e64 v3, v4, 1
; CI-NEXT: v_div_scale_f32 v9, s[0:1], v3, v3, 1.0
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
+; CI-NEXT: v_ldexp_f32_e64 v5, v2, 11
; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8
; CI-NEXT: v_not_b32_e32 v4, v2
; CI-NEXT: v_add_i32_e32 v4, vcc, v4, v7
-; CI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
+; CI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; CI-NEXT: v_rcp_f32_e32 v10, v9
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; CI-NEXT: v_fma_f32 v10, v11, v10, v10
-; CI-NEXT: v_mul_f32_e32 v11, v5, v10
-; CI-NEXT: v_fma_f32 v12, -v9, v11, v5
+; CI-NEXT: v_mul_f32_e32 v11, v6, v10
+; CI-NEXT: v_fma_f32 v12, -v9, v11, v6
; CI-NEXT: v_fma_f32 v11, v12, v10, v11
-; CI-NEXT: v_fma_f32 v5, -v9, v11, v5
+; CI-NEXT: v_fma_f32 v6, -v9, v11, v6
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
+; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; CI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB0_5
-; CI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB0_8
+; CI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT: v_add_i32_e32 v4, vcc, 11, v4
-; CI-NEXT: .LBB0_3: ; %frem.loop_body
+; CI-NEXT: .LBB0_6: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v6
-; CI-NEXT: v_mul_f32_e32 v6, v7, v5
-; CI-NEXT: v_rndne_f32_e32 v6, v6
-; CI-NEXT: v_fma_f32 v6, -v6, v3, v7
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; CI-NEXT: v_add_f32_e32 v8, v6, v3
-; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; CI-NEXT: v_mov_b32_e32 v7, v5
+; CI-NEXT: v_mul_f32_e32 v5, v7, v6
+; CI-NEXT: v_rndne_f32_e32 v5, v5
+; CI-NEXT: v_fma_f32 v5, -v5, v3, v7
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; CI-NEXT: v_add_f32_e32 v8, v5, v3
+; CI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
-; CI-NEXT: v_ldexp_f32_e64 v6, v6, 11
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; CI-NEXT: s_cbranch_vccnz .LBB0_3
-; CI-NEXT: s_branch .LBB0_6
-; CI-NEXT: .LBB0_4: ; %frem.else
-; CI-NEXT: v_and_b32_e32 v4, 0x8000, v0
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; CI-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc
-; CI-NEXT: s_branch .LBB0_7
-; CI-NEXT: .LBB0_5:
-; CI-NEXT: v_mov_b32_e32 v7, v6
-; CI-NEXT: .LBB0_6: ; %frem.loop_exit
+; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11
+; CI-NEXT: s_cbranch_vccnz .LBB0_6
+; CI-NEXT: ; %bb.7: ; %Flow
+; CI-NEXT: v_mov_b32_e32 v5, v7
+; CI-NEXT: .LBB0_8: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v4, vcc, -10, v4
-; CI-NEXT: v_ldexp_f32_e32 v4, v7, v4
-; CI-NEXT: v_mul_f32_e32 v5, v4, v5
+; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
+; CI-NEXT: v_mul_f32_e32 v5, v4, v6
; CI-NEXT: v_rndne_f32_e32 v5, v5
; CI-NEXT: v_fma_f32 v4, -v5, v3, v4
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -201,7 +217,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_and_b32_e32 v3, 0x8000, v0
; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; CI-NEXT: v_or_b32_e32 v2, v2, v3
-; CI-NEXT: .LBB0_7:
+; CI-NEXT: .LBB0_9: ; %Flow19
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; CI-NEXT: s_mov_b32 s0, 0x7f800000
@@ -229,64 +245,72 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_mov_b32_e32 v2, s3
; VI-NEXT: flat_load_ushort v1, v[1:2]
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; VI-NEXT: v_cvt_f32_f16_e64 v4, |v0|
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e64 v2, |v1|
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
-; VI-NEXT: s_cbranch_vccz .LBB0_4
-; VI-NEXT: ; %bb.1: ; %frem.compute
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
-; VI-NEXT: v_frexp_mant_f32_e32 v3, v3
-; VI-NEXT: v_ldexp_f32 v6, v3, 11
-; VI-NEXT: v_frexp_mant_f32_e32 v3, v2
-; VI-NEXT: v_ldexp_f32 v3, v3, 1
+; VI-NEXT: v_cvt_f32_f16_e64 v3, |v1|
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
+; VI-NEXT: s_cbranch_vccz .LBB0_2
+; VI-NEXT: ; %bb.1: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
+; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB0_3
+; VI-NEXT: .LBB0_2:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr2
+; VI-NEXT: .LBB0_3: ; %Flow18
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB0_9
+; VI-NEXT: ; %bb.4: ; %frem.compute
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
+; VI-NEXT: v_frexp_mant_f32_e32 v2, v4
+; VI-NEXT: v_frexp_mant_f32_e32 v4, v3
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
+; VI-NEXT: v_ldexp_f32 v3, v4, 1
; VI-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
+; VI-NEXT: v_ldexp_f32 v5, v2, 11
; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT: v_not_b32_e32 v4, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v7
-; VI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
+; VI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; VI-NEXT: v_rcp_f32_e32 v10, v9
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT: v_fma_f32 v10, v11, v10, v10
-; VI-NEXT: v_mul_f32_e32 v11, v5, v10
-; VI-NEXT: v_fma_f32 v12, -v9, v11, v5
+; VI-NEXT: v_mul_f32_e32 v11, v6, v10
+; VI-NEXT: v_fma_f32 v12, -v9, v11, v6
; VI-NEXT: v_fma_f32 v11, v12, v10, v11
-; VI-NEXT: v_fma_f32 v5, -v9, v11, v5
+; VI-NEXT: v_fma_f32 v6, -v9, v11, v6
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
+; VI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; VI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB0_5
-; VI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB0_8
+; VI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT: v_add_u32_e32 v4, vcc, 11, v4
-; VI-NEXT: .LBB0_3: ; %frem.loop_body
+; VI-NEXT: .LBB0_6: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v6
-; VI-NEXT: v_mul_f32_e32 v6, v7, v5
-; VI-NEXT: v_rndne_f32_e32 v6, v6
-; VI-NEXT: v_fma_f32 v6, -v6, v3, v7
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; VI-NEXT: v_add_f32_e32 v8, v6, v3
-; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; VI-NEXT: v_mov_b32_e32 v7, v5
+; VI-NEXT: v_mul_f32_e32 v5, v7, v6
+; VI-NEXT: v_rndne_f32_e32 v5, v5
+; VI-NEXT: v_fma_f32 v5, -v5, v3, v7
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; VI-NEXT: v_add_f32_e32 v8, v5, v3
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
-; VI-NEXT: v_ldexp_f32 v6, v6, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; VI-NEXT: s_cbranch_vccnz .LBB0_3
-; VI-NEXT: s_branch .LBB0_6
-; VI-NEXT: .LBB0_4: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v4, 0x8000, v0
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; VI-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc
-; VI-NEXT: s_branch .LBB0_7
-; VI-NEXT: .LBB0_5:
-; VI-NEXT: v_mov_b32_e32 v7, v6
-; VI-NEXT: .LBB0_6: ; %frem.loop_exit
+; VI-NEXT: v_ldexp_f32 v5, v5, 11
+; VI-NEXT: s_cbranch_vccnz .LBB0_6
+; VI-NEXT: ; %bb.7: ; %Flow
+; VI-NEXT: v_mov_b32_e32 v5, v7
+; VI-NEXT: .LBB0_8: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v4, vcc, -10, v4
-; VI-NEXT: v_ldexp_f32 v4, v7, v4
-; VI-NEXT: v_mul_f32_e32 v5, v4, v5
+; VI-NEXT: v_ldexp_f32 v4, v5, v4
+; VI-NEXT: v_mul_f32_e32 v5, v4, v6
; VI-NEXT: v_rndne_f32_e32 v5, v5
; VI-NEXT: v_fma_f32 v4, -v5, v3, v4
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -296,7 +320,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_cvt_f16_f32_e32 v2, v2
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; VI-NEXT: .LBB0_7:
+; VI-NEXT: .LBB0_9: ; %Flow19
; VI-NEXT: v_mov_b32_e32 v3, s0
; VI-NEXT: s_movk_i32 s0, 0x7c00
; VI-NEXT: v_mov_b32_e32 v4, s1
@@ -317,20 +341,34 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: global_load_ushort v0, v2, s[2:3]
; GFX9-NEXT: global_load_ushort v1, v2, s[6:7] offset:8
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; GFX9-NEXT: v_cvt_f32_f16_e64 v4, |v0|
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v2, |v1|
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
-; GFX9-NEXT: s_cbranch_vccz .LBB0_4
-; GFX9-NEXT: ; %bb.1: ; %frem.compute
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
-; GFX9-NEXT: v_frexp_mant_f32_e32 v3, v3
-; GFX9-NEXT: v_ldexp_f32 v6, v3, 11
-; GFX9-NEXT: v_frexp_mant_f32_e32 v3, v2
-; GFX9-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX9-NEXT: v_cvt_f32_f16_e64 v3, |v1|
+; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
+; GFX9-NEXT: s_cbranch_vccz .LBB0_2
+; GFX9-NEXT: ; %bb.1: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB0_3
+; GFX9-NEXT: .LBB0_2:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: .LBB0_3: ; %Flow18
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB0_9
+; GFX9-NEXT: ; %bb.4: ; %frem.compute
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
+; GFX9-NEXT: v_frexp_mant_f32_e32 v2, v4
+; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v3
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
+; GFX9-NEXT: v_ldexp_f32 v3, v4, 1
; GFX9-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
-; GFX9-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
+; GFX9-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; GFX9-NEXT: v_ldexp_f32 v5, v2, 11
; GFX9-NEXT: v_add_u32_e32 v2, -1, v8
; GFX9-NEXT: v_not_b32_e32 v4, v2
; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
@@ -338,43 +376,37 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT: v_fma_f32 v10, v11, v10, v10
-; GFX9-NEXT: v_mul_f32_e32 v11, v5, v10
-; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v5
+; GFX9-NEXT: v_mul_f32_e32 v11, v6, v10
+; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v6
; GFX9-NEXT: v_fma_f32 v11, v12, v10, v11
-; GFX9-NEXT: v_fma_f32 v5, -v9, v11, v5
+; GFX9-NEXT: v_fma_f32 v6, -v9, v11, v6
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v5, v5, v10, v11
+; GFX9-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; GFX9-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB0_5
-; GFX9-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB0_8
+; GFX9-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT: v_add_u32_e32 v4, 11, v4
-; GFX9-NEXT: .LBB0_3: ; %frem.loop_body
+; GFX9-NEXT: .LBB0_6: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v7, v6
-; GFX9-NEXT: v_mul_f32_e32 v6, v7, v5
-; GFX9-NEXT: v_rndne_f32_e32 v6, v6
-; GFX9-NEXT: v_fma_f32 v6, -v6, v3, v7
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; GFX9-NEXT: v_add_f32_e32 v8, v6, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, v7, v6
+; GFX9-NEXT: v_rndne_f32_e32 v5, v5
+; GFX9-NEXT: v_fma_f32 v5, -v5, v3, v7
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; GFX9-NEXT: v_add_f32_e32 v8, v5, v3
; GFX9-NEXT: v_add_u32_e32 v4, -11, v4
-; GFX9-NEXT: v_ldexp_f32 v6, v6, 11
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; GFX9-NEXT: s_cbranch_vccnz .LBB0_3
-; GFX9-NEXT: s_branch .LBB0_6
-; GFX9-NEXT: .LBB0_4: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v4, 0x8000, v0
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc
-; GFX9-NEXT: s_branch .LBB0_7
-; GFX9-NEXT: .LBB0_5:
-; GFX9-NEXT: v_mov_b32_e32 v7, v6
-; GFX9-NEXT: .LBB0_6: ; %frem.loop_exit
+; GFX9-NEXT: v_ldexp_f32 v5, v5, 11
+; GFX9-NEXT: s_cbranch_vccnz .LBB0_6
+; GFX9-NEXT: ; %bb.7: ; %Flow
+; GFX9-NEXT: v_mov_b32_e32 v5, v7
+; GFX9-NEXT: .LBB0_8: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v4, -10, v4
-; GFX9-NEXT: v_ldexp_f32 v4, v7, v4
-; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v6
; GFX9-NEXT: v_rndne_f32_e32 v5, v5
; GFX9-NEXT: v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -384,7 +416,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v2, s2, v2, v0
-; GFX9-NEXT: .LBB0_7:
+; GFX9-NEXT: .LBB0_9: ; %Flow19
; GFX9-NEXT: s_movk_i32 s2, 0x7c00
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v1
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v0|, s2
@@ -406,18 +438,32 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: global_load_ushort v0, v2, s[2:3]
; GFX10-NEXT: global_load_ushort v1, v2, s[6:7] offset:8
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; GFX10-NEXT: v_cvt_f32_f16_e64 v4, |v0|
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cvt_f32_f16_e64 v2, |v1|
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX10-NEXT: s_cbranch_vccz .LBB0_5
-; GFX10-NEXT: ; %bb.1: ; %frem.compute
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v3
-; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v3
-; GFX10-NEXT: v_readfirstlane_b32 s2, v5
+; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v2
+; GFX10-NEXT: s_cbranch_vccz .LBB0_2
+; GFX10-NEXT: ; %bb.1: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v3, 0x8000, v0
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v2
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc_lo
+; GFX10-NEXT: s_branch .LBB0_3
+; GFX10-NEXT: .LBB0_2:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr3
+; GFX10-NEXT: .LBB0_3: ; %Flow18
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB0_9
+; GFX10-NEXT: ; %bb.4: ; %frem.compute
+; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v4
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
; GFX10-NEXT: v_ldexp_f32 v4, v3, 11
; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v2
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s2, v5
; GFX10-NEXT: v_ldexp_f32 v3, v3, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v2
; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v2
@@ -437,11 +483,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX10-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB0_6
-; GFX10-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB0_8
+; GFX10-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB0_3: ; %frem.loop_body
+; GFX10-NEXT: .LBB0_6: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -453,20 +499,13 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_add_f32_e32 v6, v4, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX10-NEXT: ; %bb.4:
+; GFX10-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX10-NEXT: ; %bb.7: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v6, s2
-; GFX10-NEXT: s_branch .LBB0_7
-; GFX10-NEXT: .LBB0_5: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v4, 0x8000, v0
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc_lo
-; GFX10-NEXT: s_branch .LBB0_8
-; GFX10-NEXT: .LBB0_6:
-; GFX10-NEXT: v_mov_b32_e32 v7, v4
-; GFX10-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v4, -10, v6
-; GFX10-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX10-NEXT: v_mov_b32_e32 v4, v7
+; GFX10-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX10-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX10-NEXT: v_rndne_f32_e32 v5, v5
; GFX10-NEXT: v_fma_f32 v4, -v5, v3, v4
@@ -475,14 +514,14 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v2, v3, v2
; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX10-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX10-NEXT: .LBB0_8:
+; GFX10-NEXT: v_bfi_b32 v3, 0x7fff, v2, v0
+; GFX10-NEXT: .LBB0_9: ; %Flow19
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
-; GFX10-NEXT: v_mov_b32_e32 v3, 0
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX10-NEXT: global_store_short v3, v0, s[0:1]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
+; GFX10-NEXT: global_store_short v2, v0, s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-TRUE16-LABEL: frem_f16:
@@ -496,26 +535,43 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] offset:8
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, |v0.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.h|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v2
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB0_5
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v2
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v3, v2
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB0_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB0_3
+; GFX11-TRUE16-NEXT: .LBB0_2:
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: .LBB0_3: ; %Flow18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v3
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, v3
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v2
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v2
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v4, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v3
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v3, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v3, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX11-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
@@ -534,12 +590,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_4
-; GFX11-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB0_3: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -554,16 +610,10 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX11-TRUE16-NEXT: .LBB0_4: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX11-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX11-TRUE16-NEXT: s_branch .LBB0_6
-; GFX11-TRUE16-NEXT: .LBB0_5: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: .LBB0_6:
+; GFX11-TRUE16-NEXT: .LBB0_8: ; %Flow19
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.h
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
@@ -584,21 +634,37 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: global_load_u16 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: global_load_u16 v1, v1, s[4:5] offset:8
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v4, |v0|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v2, |v1|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB0_5
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.compute
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v3
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v2
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB0_2
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.else
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x8000, v0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v2
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB0_3
+; GFX11-FAKE16-NEXT: .LBB0_2:
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-FAKE16-NEXT: .LBB0_3: ; %Flow18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB0_9
+; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v4
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v3, 11
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v2
; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
@@ -625,12 +691,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB0_6
-; GFX11-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB0_8
+; GFX11-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB0_3: ; %frem.loop_body
+; GFX11-FAKE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -646,22 +712,14 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX11-FAKE16-NEXT: ; %bb.4:
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX11-FAKE16-NEXT: ; %bb.7: ; %Flow
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-FAKE16-NEXT: s_branch .LBB0_7
-; GFX11-FAKE16-NEXT: .LBB0_5: ; %frem.else
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x8000, v0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB0_8
-; GFX11-FAKE16-NEXT: .LBB0_6:
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v4
-; GFX11-FAKE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-FAKE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -674,13 +732,14 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, v3, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX11-FAKE16-NEXT: .LBB0_8:
+; GFX11-FAKE16-NEXT: v_bfi_b32 v3, 0x7fff, v2, v0
+; GFX11-FAKE16-NEXT: .LBB0_9: ; %Flow19
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, 0x7e00, v2
-; GFX11-FAKE16-NEXT: global_store_b16 v3, v0, s[0:1]
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
+; GFX11-FAKE16-NEXT: global_store_b16 v2, v0, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX1150-TRUE16-LABEL: frem_f16:
@@ -698,22 +757,39 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
; GFX1150-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s1, s1, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s0, s0
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s1, s1
+; GFX1150-TRUE16-NEXT: s_and_b32 s2, s1, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s1, s0
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s0, s2
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s0, s1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB0_5
-; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s1
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s0
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s0
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s1, s0
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB0_2
+; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s1, s0
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v0.l
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s2
+; GFX1150-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB0_3
+; GFX1150-TRUE16-NEXT: .LBB0_2:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1150-TRUE16-NEXT: .LBB0_3: ; %Flow18
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
+; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -737,12 +813,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_4
-; GFX1150-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s0, s0, s1
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s0, s1, s0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s0, s0, 11
-; GFX1150-TRUE16-NEXT: .LBB0_3: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -758,17 +834,10 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX1150-TRUE16-NEXT: .LBB0_4: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX1150-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: s_branch .LBB0_6
-; GFX1150-TRUE16-NEXT: .LBB0_5: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s0, s1
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v0.l
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s0
-; GFX1150-TRUE16-NEXT: .LBB0_6:
+; GFX1150-TRUE16-NEXT: .LBB0_8: ; %Flow19
; GFX1150-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1150-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
@@ -793,25 +862,42 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s1, v1
; GFX1150-FAKE16-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s1, s1, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s0, s0
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s1, s1
+; GFX1150-FAKE16-NEXT: s_and_b32 s2, s1, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s1, s0
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s0, s2
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s0, s1
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB0_5
-; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.compute
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s1
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s0
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
+; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s1, s0
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB0_2
+; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.else
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s1, s0
+; GFX1150-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; GFX1150-FAKE16-NEXT: s_mov_b32 s2, 0
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB0_3
+; GFX1150-FAKE16-NEXT: .LBB0_2:
+; GFX1150-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr2
+; GFX1150-FAKE16-NEXT: .LBB0_3: ; %Flow18
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB0_9
+; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s0
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s1
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s1
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s0, v5
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s1, v5
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s1, v2
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s0, v2
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -833,12 +919,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB0_6
-; GFX1150-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s0, s0, s1
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB0_8
+; GFX1150-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s0, s1, s0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s0, s0, 11
-; GFX1150-FAKE16-NEXT: .LBB0_3: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -856,23 +942,14 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX1150-FAKE16-NEXT: ; %bb.4:
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX1150-FAKE16-NEXT: ; %bb.7: ; %Flow
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, s0
-; GFX1150-FAKE16-NEXT: s_branch .LBB0_7
-; GFX1150-FAKE16-NEXT: .LBB0_5: ; %frem.else
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s0, s1
-; GFX1150-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB0_8
-; GFX1150-FAKE16-NEXT: .LBB0_6:
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, v4
-; GFX1150-FAKE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1150-FAKE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -888,7 +965,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX1150-FAKE16-NEXT: .LBB0_8:
+; GFX1150-FAKE16-NEXT: .LBB0_9: ; %Flow19
; GFX1150-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1150-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -901,224 +978,249 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-LABEL: frem_f16:
; GFX1200-TRUE16: ; %bb.0:
; GFX1200-TRUE16-NEXT: s_clause 0x1
-; GFX1200-TRUE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
-; GFX1200-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1200-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1200-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX1200-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT: s_clause 0x1
-; GFX1200-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[10:11]
-; GFX1200-TRUE16-NEXT: global_load_d16_b16 v1, v1, s[0:1] offset:8
+; GFX1200-TRUE16-NEXT: global_load_u16 v1, v0, s[2:3]
+; GFX1200-TRUE16-NEXT: global_load_u16 v0, v0, s[4:5] offset:8
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v1
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
-; GFX1200-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s1, s1, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s0, s0
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s1, s1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1200-TRUE16-NEXT: s_and_b32 s2, s6, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s4, s3, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s5, s2
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s4, s4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s0, s1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB0_5
-; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s1
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s0
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s0
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s5, s4
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB0_2
+; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s5, s4
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s6
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s6, v0.l, s7
+; GFX1200-TRUE16-NEXT: s_mov_b32 s6, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB0_3
+; GFX1200-TRUE16-NEXT: .LBB0_2:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-TRUE16-NEXT: .LBB0_3: ; %Flow18
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s6, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
+; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s4
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s4
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s5
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v4
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s4, v3
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v2
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v3, v3
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_4
-; GFX1200-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s0, s0, s1
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s4, s5, s4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, 11
-; GFX1200-TRUE16-NEXT: .LBB0_3: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s4, s4, 11
+; GFX1200-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s4, s4, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
-; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s4, 11
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX1200-TRUE16-NEXT: .LBB0_4: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: s_branch .LBB0_6
-; GFX1200-TRUE16-NEXT: .LBB0_5: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s0, s1
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v0.l
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s0
-; GFX1200-TRUE16-NEXT: .LBB0_6:
-; GFX1200-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
-; GFX1200-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, 0x7c00, v0.l
-; GFX1200-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
-; GFX1200-TRUE16-NEXT: global_store_b16 v3, v0, s[8:9]
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX1200-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-TRUE16-NEXT: .LBB0_8: ; %Flow19
+; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
+; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s2, 0x7c00
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: s_and_b32 s2, s2, s3
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
+; GFX1200-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
;
; GFX1200-FAKE16-LABEL: frem_f16:
; GFX1200-FAKE16: ; %bb.0:
; GFX1200-FAKE16-NEXT: s_clause 0x1
-; GFX1200-FAKE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
-; GFX1200-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1200-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1200-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; GFX1200-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT: s_clause 0x1
-; GFX1200-FAKE16-NEXT: global_load_u16 v0, v1, s[10:11]
-; GFX1200-FAKE16-NEXT: global_load_u16 v1, v1, s[0:1] offset:8
+; GFX1200-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3]
+; GFX1200-FAKE16-NEXT: global_load_u16 v0, v0, s[6:7] offset:8
; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x1
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s1, v1
-; GFX1200-FAKE16-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s1, s1, 0x7fff
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s0, s0
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s1, s1
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1200-FAKE16-NEXT: s_and_b32 s2, s4, 0x7fff
+; GFX1200-FAKE16-NEXT: s_and_b32 s5, s3, 0x7fff
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s6, s2
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s5, s5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s0, s1
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB0_5
-; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.compute
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s1
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s0
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
+; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s6, s5
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB0_2
+; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.else
+; GFX1200-FAKE16-NEXT: s_and_b32 s7, 0x8000, s4
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s6, s5
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, s7
+; GFX1200-FAKE16-NEXT: s_mov_b32 s7, 0
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB0_3
+; GFX1200-FAKE16-NEXT: .LBB0_2:
+; GFX1200-FAKE16-NEXT: s_mov_b32 s7, -1
+; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-FAKE16-NEXT: .LBB0_3: ; %Flow18
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1200-FAKE16-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s7, 1
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_9
+; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s5
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s1
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v1, v1, 1
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v0, 11
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s0, v5
-; GFX1200-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1200-FAKE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s1, v2
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
+; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_not_b32_e32 v6, v2
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX1200-FAKE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1200-FAKE16-NEXT: v_not_b32_e32 v4, v0
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-FAKE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-FAKE16-NEXT: s_denorm_mode 15
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
-; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX1200-FAKE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v9, v5, v8
-; GFX1200-FAKE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1200-FAKE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX1200-FAKE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1200-FAKE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB0_6
-; GFX1200-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s0, s0, s1
+; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB0_8
+; GFX1200-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s5, s6, s5
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_add_co_i32 s0, s0, 11
-; GFX1200-FAKE16-NEXT: .LBB0_3: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT: s_add_co_i32 s5, s5, 11
+; GFX1200-FAKE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_add_co_i32 s0, s0, -11
+; GFX1200-FAKE16-NEXT: s_add_co_i32 s5, s5, -11
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s0, 11
-; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s5, 11
+; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v2, v5, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v2, v2
+; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_fma_f32 v4, v4, v3, v7
-; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1200-FAKE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX1200-FAKE16-NEXT: v_fma_f32 v2, v2, v1, v5
+; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-FAKE16-NEXT: v_add_f32_e32 v4, v2, v1
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX1200-FAKE16-NEXT: ; %bb.4:
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, s0
-; GFX1200-FAKE16-NEXT: s_branch .LBB0_7
-; GFX1200-FAKE16-NEXT: .LBB0_5: ; %frem.else
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s0, s1
-; GFX1200-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB0_8
-; GFX1200-FAKE16-NEXT: .LBB0_6:
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
-; GFX1200-FAKE16-NEXT: .LBB0_7: ; %frem.loop_exit
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX1200-FAKE16-NEXT: ; %bb.7: ; %Flow
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, s5
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-FAKE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
-; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v4, v5, v3
+; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v2, v3, v1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-FAKE16-NEXT: v_add_f32_e32 v1, v2, v1
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX1200-FAKE16-NEXT: .LBB0_8:
-; GFX1200-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
-; GFX1200-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-FAKE16-NEXT: v_cmp_nle_f16_e64 s0, 0x7c00, v0
-; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
+; GFX1200-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s4
+; GFX1200-FAKE16-NEXT: .LBB0_9: ; %Flow19
+; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s3, 0
+; GFX1200-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
+; GFX1200-FAKE16-NEXT: s_cmp_nge_f16 s2, 0x7c00
+; GFX1200-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
-; GFX1200-FAKE16-NEXT: global_store_b16 v3, v0, s[8:9]
+; GFX1200-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_cndmask_b32 v0, 0x7e00, v0
+; GFX1200-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX1200-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %in2) #0 {
%gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4
@@ -1388,7 +1490,8 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX10-NEXT: v_mad_f32 v3, -v3, v5, v6
; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4
; GFX10-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX10-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v5 op_sel_hi:[0,1,0]
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX10-NEXT: v_div_fixup_f16 v3, v3, v2, v1
; GFX10-NEXT: v_trunc_f16_e32 v3, v3
; GFX10-NEXT: v_fma_f16 v1, -v3, v2, v1
@@ -1419,10 +1522,12 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
-; GFX11-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_f16 v0.l, -v0.l, v3.l, v2.l
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -1451,10 +1556,12 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
-; GFX11-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
; GFX11-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fma_f16 v1, -v3, v2, v1
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -1482,12 +1589,14 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX1150-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1150-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
-; GFX1150-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
; GFX1150-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
; GFX1150-TRUE16-NEXT: s_endpgm
@@ -1515,12 +1624,14 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX1150-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
+; GFX1150-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
-; GFX1150-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
; GFX1150-FAKE16-NEXT: v_xor_b32_e32 v3, 0x8000, v3
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_fmac_f16_e32 v1, v3, v2
; GFX1150-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1150-FAKE16-NEXT: s_endpgm
@@ -1530,32 +1641,35 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1200-TRUE16-NEXT: s_clause 0x1
; GFX1200-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1200-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT: s_clause 0x1
-; GFX1200-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[2:3]
-; GFX1200-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] offset:8
+; GFX1200-TRUE16-NEXT: global_load_u16 v3, v2, s[2:3]
+; GFX1200-TRUE16-NEXT: global_load_u16 v4, v2, s[4:5] offset:8
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l
+; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v4.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0]
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v1, v3, v0, neg(0) op_sel_hi:[1,0,0]
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v4, v1, v3 op_sel_hi:[1,0,1]
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v1, v5, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v4, v1, v3 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX1200-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v4.l, v1.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
; GFX1200-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
-; GFX1200-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v0.l, v4.l
+; GFX1200-TRUE16-NEXT: global_store_b16 v2, v3, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
;
; GFX1200-FAKE16-LABEL: fast_frem_f16:
@@ -1581,12 +1695,14 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX1200-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
+; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
-; GFX1200-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v3, 0x8000, v3
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_fmac_f16_e32 v1, v3, v2
; GFX1200-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1200-FAKE16-NEXT: s_endpgm
@@ -1858,7 +1974,8 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX10-NEXT: v_mad_f32 v3, -v3, v5, v6
; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4
; GFX10-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX10-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v5 op_sel_hi:[0,1,0]
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX10-NEXT: v_div_fixup_f16 v3, v3, v2, v1
; GFX10-NEXT: v_trunc_f16_e32 v3, v3
; GFX10-NEXT: v_fma_f16 v1, -v3, v2, v1
@@ -1889,10 +2006,12 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
-; GFX11-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_f16 v0.l, -v0.l, v3.l, v2.l
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -1921,10 +2040,12 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
-; GFX11-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
+; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
; GFX11-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fma_f16 v1, -v3, v2, v1
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -1952,12 +2073,14 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX1150-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1150-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
-; GFX1150-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
; GFX1150-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
; GFX1150-TRUE16-NEXT: s_endpgm
@@ -1985,12 +2108,14 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX1150-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
+; GFX1150-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
-; GFX1150-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
; GFX1150-FAKE16-NEXT: v_xor_b32_e32 v3, 0x8000, v3
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_fmac_f16_e32 v1, v3, v2
; GFX1150-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1150-FAKE16-NEXT: s_endpgm
@@ -2000,32 +2125,35 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1200-TRUE16-NEXT: s_clause 0x1
; GFX1200-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1200-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT: s_clause 0x1
-; GFX1200-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[2:3]
-; GFX1200-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] offset:8
+; GFX1200-TRUE16-NEXT: global_load_u16 v3, v2, s[2:3]
+; GFX1200-TRUE16-NEXT: global_load_u16 v4, v2, s[4:5] offset:8
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l
+; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v4.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0]
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v1, v3, v0, neg(0) op_sel_hi:[1,0,0]
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v4, v1, v3 op_sel_hi:[1,0,1]
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v1, v5, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v4, v1, v3 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX1200-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v4.l, v1.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
; GFX1200-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
-; GFX1200-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v0.l, v4.l
+; GFX1200-TRUE16-NEXT: global_store_b16 v2, v3, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
;
; GFX1200-FAKE16-LABEL: unsafe_frem_f16:
@@ -2051,12 +2179,14 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX1200-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
+; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
-; GFX1200-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v3, 0x8000, v3
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_fmac_f16_e32 v1, v3, v2
; GFX1200-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1200-FAKE16-NEXT: s_endpgm
@@ -2084,9 +2214,24 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; SI-NEXT: buffer_load_dword v1, off, s[4:7], 0 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v1|
-; SI-NEXT: s_cbranch_vccz .LBB3_4
-; SI-NEXT: ; %bb.1: ; %frem.compute
+; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
+; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT: s_cbranch_vccz .LBB3_2
+; SI-NEXT: ; %bb.1: ; %frem.else
+; SI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; SI-NEXT: s_mov_b64 s[2:3], 0
+; SI-NEXT: s_branch .LBB3_3
+; SI-NEXT: .LBB3_2:
+; SI-NEXT: s_mov_b64 s[2:3], -1
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: .LBB3_3: ; %Flow16
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cselect_b32 s2, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s2, 1
+; SI-NEXT: s_cbranch_scc1 .LBB3_9
+; SI-NEXT: ; %bb.4: ; %frem.compute
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
@@ -2121,11 +2266,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB3_5
-; SI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB3_8
+; SI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB3_3: ; %frem.loop_body
+; SI-NEXT: .LBB3_6: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v5, v3
; SI-NEXT: v_mul_f32_e32 v3, v5, v4
@@ -2137,18 +2282,12 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v3, v3, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB3_3
-; SI-NEXT: s_branch .LBB3_6
-; SI-NEXT: .LBB3_4: ; %frem.else
-; SI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
-; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; SI-NEXT: s_branch .LBB3_7
-; SI-NEXT: .LBB3_5:
-; SI-NEXT: v_mov_b32_e32 v5, v3
-; SI-NEXT: .LBB3_6: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB3_6
+; SI-NEXT: ; %bb.7: ; %Flow
+; SI-NEXT: v_mov_b32_e32 v3, v5
+; SI-NEXT: .LBB3_8: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v3, v5, s3
+; SI-NEXT: v_ldexp_f32_e64 v3, v3, s3
; SI-NEXT: v_mul_f32_e32 v4, v3, v4
; SI-NEXT: v_rndne_f32_e32 v4, v4
; SI-NEXT: v_fma_f32 v3, -v4, v2, v3
@@ -2158,7 +2297,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_ldexp_f32_e64 v2, v2, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; SI-NEXT: .LBB3_7:
+; SI-NEXT: .LBB3_9: ; %Flow17
; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT: v_cmp_nge_f32_e64 s[4:5], |v0|, s4
@@ -2184,61 +2323,70 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; CI-NEXT: buffer_load_dword v1, off, s[4:7], 0 offset:16
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v1|
-; CI-NEXT: s_cbranch_vccz .LBB3_4
-; CI-NEXT: ; %bb.1: ; %frem.compute
+; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB3_2
+; CI-NEXT: ; %bb.1: ; %frem.else
+; CI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: s_branch .LBB3_3
+; CI-NEXT: .LBB3_2:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr2
+; CI-NEXT: .LBB3_3: ; %Flow16
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB3_9
+; CI-NEXT: ; %bb.4: ; %frem.compute
; CI-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; CI-NEXT: v_ldexp_f32_e64 v3, v3, 1
; CI-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
-; CI-NEXT: v_ldexp_f32_e64 v6, v2, 12
+; CI-NEXT: v_ldexp_f32_e64 v5, v2, 12
; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8
; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
; CI-NEXT: v_not_b32_e32 v4, v2
; CI-NEXT: v_add_i32_e32 v4, vcc, v4, v7
-; CI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
+; CI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; CI-NEXT: v_rcp_f32_e32 v10, v9
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; CI-NEXT: v_fma_f32 v10, v11, v10, v10
-; CI-NEXT: v_mul_f32_e32 v11, v5, v10
-; CI-NEXT: v_fma_f32 v12, -v9, v11, v5
+; CI-NEXT: v_mul_f32_e32 v11, v6, v10
+; CI-NEXT: v_fma_f32 v12, -v9, v11, v6
; CI-NEXT: v_fma_f32 v11, v12, v10, v11
-; CI-NEXT: v_fma_f32 v5, -v9, v11, v5
+; CI-NEXT: v_fma_f32 v6, -v9, v11, v6
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
+; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
-; CI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB3_5
-; CI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB3_8
+; CI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT: v_add_i32_e32 v4, vcc, 12, v4
-; CI-NEXT: .LBB3_3: ; %frem.loop_body
+; CI-NEXT: .LBB3_6: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v6
-; CI-NEXT: v_mul_f32_e32 v6, v7, v5
-; CI-NEXT: v_rndne_f32_e32 v6, v6
-; CI-NEXT: v_fma_f32 v6, -v6, v3, v7
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; CI-NEXT: v_add_f32_e32 v8, v6, v3
-; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; CI-NEXT: v_mov_b32_e32 v7, v5
+; CI-NEXT: v_mul_f32_e32 v5, v7, v6
+; CI-NEXT: v_rndne_f32_e32 v5, v5
+; CI-NEXT: v_fma_f32 v5, -v5, v3, v7
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; CI-NEXT: v_add_f32_e32 v8, v5, v3
+; CI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; CI-NEXT: v_add_i32_e32 v4, vcc, -12, v4
-; CI-NEXT: v_ldexp_f32_e64 v6, v6, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
-; CI-NEXT: s_cbranch_vccnz .LBB3_3
-; CI-NEXT: s_branch .LBB3_6
-; CI-NEXT: .LBB3_4: ; %frem.else
-; CI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
-; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; CI-NEXT: s_branch .LBB3_7
-; CI-NEXT: .LBB3_5:
-; CI-NEXT: v_mov_b32_e32 v7, v6
-; CI-NEXT: .LBB3_6: ; %frem.loop_exit
+; CI-NEXT: v_ldexp_f32_e64 v5, v5, 12
+; CI-NEXT: s_cbranch_vccnz .LBB3_6
+; CI-NEXT: ; %bb.7: ; %Flow
+; CI-NEXT: v_mov_b32_e32 v5, v7
+; CI-NEXT: .LBB3_8: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
-; CI-NEXT: v_ldexp_f32_e32 v4, v7, v4
-; CI-NEXT: v_mul_f32_e32 v5, v4, v5
+; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
+; CI-NEXT: v_mul_f32_e32 v5, v4, v6
; CI-NEXT: v_rndne_f32_e32 v5, v5
; CI-NEXT: v_fma_f32 v4, -v5, v3, v4
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -2247,7 +2395,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; CI-NEXT: .LBB3_7:
+; CI-NEXT: .LBB3_9: ; %Flow17
; CI-NEXT: s_mov_b32 s4, 0x7f800000
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT: v_cmp_nge_f32_e64 s[4:5], |v0|, s4
@@ -2273,61 +2421,70 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_mov_b32_e32 v2, s3
; VI-NEXT: flat_load_dword v1, v[1:2]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v1|
-; VI-NEXT: s_cbranch_vccz .LBB3_4
-; VI-NEXT: ; %bb.1: ; %frem.compute
+; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB3_2
+; VI-NEXT: ; %bb.1: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB3_3
+; VI-NEXT: .LBB3_2:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr2
+; VI-NEXT: .LBB3_3: ; %Flow16
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB3_9
+; VI-NEXT: ; %bb.4: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; VI-NEXT: v_ldexp_f32 v3, v3, 1
; VI-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
-; VI-NEXT: v_ldexp_f32 v6, v2, 12
+; VI-NEXT: v_ldexp_f32 v5, v2, 12
; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
; VI-NEXT: v_not_b32_e32 v4, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v7
-; VI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
+; VI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; VI-NEXT: v_rcp_f32_e32 v10, v9
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT: v_fma_f32 v10, v11, v10, v10
-; VI-NEXT: v_mul_f32_e32 v11, v5, v10
-; VI-NEXT: v_fma_f32 v12, -v9, v11, v5
+; VI-NEXT: v_mul_f32_e32 v11, v6, v10
+; VI-NEXT: v_fma_f32 v12, -v9, v11, v6
; VI-NEXT: v_fma_f32 v11, v12, v10, v11
-; VI-NEXT: v_fma_f32 v5, -v9, v11, v5
+; VI-NEXT: v_fma_f32 v6, -v9, v11, v6
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
+; VI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
-; VI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB3_5
-; VI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB3_8
+; VI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v4
-; VI-NEXT: .LBB3_3: ; %frem.loop_body
+; VI-NEXT: .LBB3_6: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v6
-; VI-NEXT: v_mul_f32_e32 v6, v7, v5
-; VI-NEXT: v_rndne_f32_e32 v6, v6
-; VI-NEXT: v_fma_f32 v6, -v6, v3, v7
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; VI-NEXT: v_add_f32_e32 v8, v6, v3
-; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; VI-NEXT: v_mov_b32_e32 v7, v5
+; VI-NEXT: v_mul_f32_e32 v5, v7, v6
+; VI-NEXT: v_rndne_f32_e32 v5, v5
+; VI-NEXT: v_fma_f32 v5, -v5, v3, v7
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; VI-NEXT: v_add_f32_e32 v8, v5, v3
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, -12, v4
-; VI-NEXT: v_ldexp_f32 v6, v6, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
-; VI-NEXT: s_cbranch_vccnz .LBB3_3
-; VI-NEXT: s_branch .LBB3_6
-; VI-NEXT: .LBB3_4: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
-; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; VI-NEXT: s_branch .LBB3_7
-; VI-NEXT: .LBB3_5:
-; VI-NEXT: v_mov_b32_e32 v7, v6
-; VI-NEXT: .LBB3_6: ; %frem.loop_exit
+; VI-NEXT: v_ldexp_f32 v5, v5, 12
+; VI-NEXT: s_cbranch_vccnz .LBB3_6
+; VI-NEXT: ; %bb.7: ; %Flow
+; VI-NEXT: v_mov_b32_e32 v5, v7
+; VI-NEXT: .LBB3_8: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
-; VI-NEXT: v_ldexp_f32 v4, v7, v4
-; VI-NEXT: v_mul_f32_e32 v5, v4, v5
+; VI-NEXT: v_ldexp_f32 v4, v5, v4
+; VI-NEXT: v_mul_f32_e32 v5, v4, v6
; VI-NEXT: v_rndne_f32_e32 v5, v5
; VI-NEXT: v_fma_f32 v4, -v5, v3, v4
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -2336,7 +2493,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_ldexp_f32 v2, v3, v2
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; VI-NEXT: .LBB3_7:
+; VI-NEXT: .LBB3_9: ; %Flow17
; VI-NEXT: v_mov_b32_e32 v3, s0
; VI-NEXT: s_mov_b32 s0, 0x7f800000
; VI-NEXT: v_mov_b32_e32 v4, s1
@@ -2357,16 +2514,31 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: global_load_dword v0, v2, s[2:3]
; GFX9-NEXT: global_load_dword v1, v2, s[6:7] offset:16
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v1|
-; GFX9-NEXT: s_cbranch_vccz .LBB3_4
-; GFX9-NEXT: ; %bb.1: ; %frem.compute
+; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB3_2
+; GFX9-NEXT: ; %bb.1: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB3_3
+; GFX9-NEXT: .LBB3_2:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: .LBB3_3: ; %Flow16
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB3_9
+; GFX9-NEXT: ; %bb.4: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; GFX9-NEXT: v_ldexp_f32 v3, v3, 1
; GFX9-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
-; GFX9-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
+; GFX9-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
-; GFX9-NEXT: v_ldexp_f32 v6, v2, 12
+; GFX9-NEXT: v_ldexp_f32 v5, v2, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
; GFX9-NEXT: v_add_u32_e32 v2, -1, v8
; GFX9-NEXT: v_not_b32_e32 v4, v2
@@ -2375,43 +2547,37 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT: v_fma_f32 v10, v11, v10, v10
-; GFX9-NEXT: v_mul_f32_e32 v11, v5, v10
-; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v5
+; GFX9-NEXT: v_mul_f32_e32 v11, v6, v10
+; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v6
; GFX9-NEXT: v_fma_f32 v11, v12, v10, v11
-; GFX9-NEXT: v_fma_f32 v5, -v9, v11, v5
+; GFX9-NEXT: v_fma_f32 v6, -v9, v11, v6
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v5, v5, v10, v11
+; GFX9-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
-; GFX9-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB3_5
-; GFX9-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB3_8
+; GFX9-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT: v_add_u32_e32 v4, 12, v4
-; GFX9-NEXT: .LBB3_3: ; %frem.loop_body
+; GFX9-NEXT: .LBB3_6: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v7, v6
-; GFX9-NEXT: v_mul_f32_e32 v6, v7, v5
-; GFX9-NEXT: v_rndne_f32_e32 v6, v6
-; GFX9-NEXT: v_fma_f32 v6, -v6, v3, v7
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; GFX9-NEXT: v_add_f32_e32 v8, v6, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, v7, v6
+; GFX9-NEXT: v_rndne_f32_e32 v5, v5
+; GFX9-NEXT: v_fma_f32 v5, -v5, v3, v7
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; GFX9-NEXT: v_add_f32_e32 v8, v5, v3
; GFX9-NEXT: v_add_u32_e32 v4, -12, v4
-; GFX9-NEXT: v_ldexp_f32 v6, v6, 12
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
-; GFX9-NEXT: s_cbranch_vccnz .LBB3_3
-; GFX9-NEXT: s_branch .LBB3_6
-; GFX9-NEXT: .LBB3_4: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; GFX9-NEXT: s_branch .LBB3_7
-; GFX9-NEXT: .LBB3_5:
-; GFX9-NEXT: v_mov_b32_e32 v7, v6
-; GFX9-NEXT: .LBB3_6: ; %frem.loop_exit
+; GFX9-NEXT: v_ldexp_f32 v5, v5, 12
+; GFX9-NEXT: s_cbranch_vccnz .LBB3_6
+; GFX9-NEXT: ; %bb.7: ; %Flow
+; GFX9-NEXT: v_mov_b32_e32 v5, v7
+; GFX9-NEXT: .LBB3_8: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v4, -11, v4
-; GFX9-NEXT: v_ldexp_f32 v4, v7, v4
-; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v6
; GFX9-NEXT: v_rndne_f32_e32 v5, v5
; GFX9-NEXT: v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -2420,7 +2586,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_ldexp_f32 v2, v3, v2
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v2, s2, v2, v0
-; GFX9-NEXT: .LBB3_7:
+; GFX9-NEXT: .LBB3_9: ; %Flow17
; GFX9-NEXT: s_mov_b32 s2, 0x7f800000
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; GFX9-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s2
@@ -2442,9 +2608,24 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: global_load_dword v0, v2, s[2:3]
; GFX10-NEXT: global_load_dword v1, v2, s[6:7] offset:16
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v1|
-; GFX10-NEXT: s_cbranch_vccz .LBB3_5
-; GFX10-NEXT: ; %bb.1: ; %frem.compute
+; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v1|
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB3_2
+; GFX10-NEXT: ; %bb.1: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX10-NEXT: s_branch .LBB3_3
+; GFX10-NEXT: .LBB3_2:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr2
+; GFX10-NEXT: .LBB3_3: ; %Flow16
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB3_9
+; GFX10-NEXT: ; %bb.4: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; GFX10-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
@@ -2470,11 +2651,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX10-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB3_6
-; GFX10-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB3_8
+; GFX10-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB3_3: ; %frem.loop_body
+; GFX10-NEXT: .LBB3_6: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -2486,20 +2667,13 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_add_f32_e32 v6, v4, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB3_3
-; GFX10-NEXT: ; %bb.4:
+; GFX10-NEXT: s_cbranch_scc1 .LBB3_6
+; GFX10-NEXT: ; %bb.7: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v6, s2
-; GFX10-NEXT: s_branch .LBB3_7
-; GFX10-NEXT: .LBB3_5: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX10-NEXT: s_branch .LBB3_8
-; GFX10-NEXT: .LBB3_6:
-; GFX10-NEXT: v_mov_b32_e32 v7, v4
-; GFX10-NEXT: .LBB3_7: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v4, -11, v6
-; GFX10-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX10-NEXT: v_mov_b32_e32 v4, v7
+; GFX10-NEXT: .LBB3_8: ; %frem.loop_exit
+; GFX10-NEXT: v_add_nc_u32_e32 v6, -11, v6
+; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX10-NEXT: v_rndne_f32_e32 v5, v5
; GFX10-NEXT: v_fma_f32 v4, -v5, v3, v4
@@ -2508,7 +2682,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v2, v3, v2
; GFX10-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v0
-; GFX10-NEXT: .LBB3_8:
+; GFX10-NEXT: .LBB3_9: ; %Flow17
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v1
; GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX10-NEXT: v_mov_b32_e32 v3, 0
@@ -2528,9 +2702,25 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: global_load_b32 v0, v1, s[2:3]
; GFX11-NEXT: global_load_b32 v1, v1, s[4:5] offset:16
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v1|
-; GFX11-NEXT: s_cbranch_vccz .LBB3_5
-; GFX11-NEXT: ; %bb.1: ; %frem.compute
+; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v1|
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB3_2
+; GFX11-NEXT: ; %bb.1: ; %frem.else
+; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX11-NEXT: s_branch .LBB3_3
+; GFX11-NEXT: .LBB3_2:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr2
+; GFX11-NEXT: .LBB3_3: ; %Flow16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB3_9
+; GFX11-NEXT: ; %bb.4: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; GFX11-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
@@ -2565,12 +2755,12 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB3_6
-; GFX11-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB3_8
+; GFX11-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB3_3: ; %frem.loop_body
+; GFX11-NEXT: .LBB3_6: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v7, v4
@@ -2586,22 +2776,14 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB3_3
-; GFX11-NEXT: ; %bb.4:
+; GFX11-NEXT: s_cbranch_scc1 .LBB3_6
+; GFX11-NEXT: ; %bb.7: ; %Flow
; GFX11-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-NEXT: s_branch .LBB3_7
-; GFX11-NEXT: .LBB3_5: ; %frem.else
-; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX11-NEXT: s_branch .LBB3_8
-; GFX11-NEXT: .LBB3_6:
-; GFX11-NEXT: v_mov_b32_e32 v7, v4
-; GFX11-NEXT: .LBB3_7: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v4, -11, v6
-; GFX11-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX11-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-NEXT: .LBB3_8: ; %frem.loop_exit
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v6, -11, v6
+; GFX11-NEXT: v_ldexp_f32 v4, v4, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX11-NEXT: v_rndne_f32_e32 v5, v5
@@ -2614,7 +2796,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_ldexp_f32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v0
-; GFX11-NEXT: .LBB3_8:
+; GFX11-NEXT: .LBB3_9: ; %Flow17
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -2637,9 +2819,25 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: s_waitcnt vmcnt(0)
; GFX1150-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v3
-; GFX1150-NEXT: s_cbranch_vccz .LBB3_5
-; GFX1150-NEXT: ; %bb.1: ; %frem.compute
+; GFX1150-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v3
+; GFX1150-NEXT: s_cbranch_vccz .LBB3_2
+; GFX1150-NEXT: ; %bb.1: ; %frem.else
+; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v2
+; GFX1150-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v3
+; GFX1150-NEXT: s_mov_b32 s0, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-NEXT: v_cndmask_b32_e32 v3, v2, v4, vcc_lo
+; GFX1150-NEXT: s_branch .LBB3_3
+; GFX1150-NEXT: .LBB3_2:
+; GFX1150-NEXT: s_mov_b32 s0, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr3
+; GFX1150-NEXT: .LBB3_3: ; %Flow16
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s0, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB3_9
+; GFX1150-NEXT: ; %bb.4: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v3, |v2|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v6, v2
@@ -2673,12 +2871,12 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1150-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB3_6
-; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB3_8
+; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s0, s0, s1
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s0, s0, 12
-; GFX1150-NEXT: .LBB3_3: ; %frem.loop_body
+; GFX1150-NEXT: .LBB3_6: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v8, v5
@@ -2696,22 +2894,14 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB3_3
-; GFX1150-NEXT: ; %bb.4:
+; GFX1150-NEXT: s_cbranch_scc1 .LBB3_6
+; GFX1150-NEXT: ; %bb.7: ; %Flow
; GFX1150-NEXT: v_mov_b32_e32 v7, s0
-; GFX1150-NEXT: s_branch .LBB3_7
-; GFX1150-NEXT: .LBB3_5: ; %frem.else
-; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v2
-; GFX1150-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v3
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX1150-NEXT: s_branch .LBB3_8
-; GFX1150-NEXT: .LBB3_6:
-; GFX1150-NEXT: v_mov_b32_e32 v8, v5
-; GFX1150-NEXT: .LBB3_7: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v5, -11, v7
-; GFX1150-NEXT: v_ldexp_f32 v5, v8, v5
+; GFX1150-NEXT: v_mov_b32_e32 v5, v8
+; GFX1150-NEXT: .LBB3_8: ; %frem.loop_exit
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v7, -11, v7
+; GFX1150-NEXT: v_ldexp_f32 v5, v5, v7
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1150-NEXT: v_rndne_f32_e32 v6, v6
@@ -2724,13 +2914,14 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v4, v3
-; GFX1150-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
-; GFX1150-NEXT: .LBB3_8:
+; GFX1150-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v2
+; GFX1150-NEXT: .LBB3_9: ; %Flow17
; GFX1150-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v0
; GFX1150-NEXT: v_cmp_nle_f32_e64 s0, 0x7f800000, v1
+; GFX1150-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX1150-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, 0x7fc00000, v2
-; GFX1150-NEXT: global_store_b32 v3, v0, s[8:9]
+; GFX1150-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v3, vcc_lo
+; GFX1150-NEXT: global_store_b32 v2, v0, s[8:9]
; GFX1150-NEXT: s_endpgm
;
; GFX1200-LABEL: frem_f32:
@@ -2748,9 +2939,25 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v3
-; GFX1200-NEXT: s_cbranch_vccz .LBB3_5
-; GFX1200-NEXT: ; %bb.1: ; %frem.compute
+; GFX1200-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v3
+; GFX1200-NEXT: s_cbranch_vccz .LBB3_2
+; GFX1200-NEXT: ; %bb.1: ; %frem.else
+; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v2
+; GFX1200-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v3
+; GFX1200-NEXT: s_mov_b32 s0, 0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b32_e32 v3, v2, v4, vcc_lo
+; GFX1200-NEXT: s_branch .LBB3_3
+; GFX1200-NEXT: .LBB3_2:
+; GFX1200-NEXT: s_mov_b32 s0, -1
+; GFX1200-NEXT: ; implicit-def: $vgpr3
+; GFX1200-NEXT: .LBB3_3: ; %Flow16
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1200-NEXT: s_cmp_lg_u32 s0, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB3_9
+; GFX1200-NEXT: ; %bb.4: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v3, |v2|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, v2
@@ -2780,16 +2987,17 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_fmac_f32_e32 v10, v11, v9
; GFX1200-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX1200-NEXT: s_denorm_mode 12
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1200-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB3_6
-; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB3_8
+; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s0, s0, s1
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s0, s0, 12
-; GFX1200-NEXT: .LBB3_3: ; %frem.loop_body
+; GFX1200-NEXT: .LBB3_6: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1200-NEXT: v_mov_b32_e32 v8, v5
@@ -2808,22 +3016,14 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB3_3
-; GFX1200-NEXT: ; %bb.4:
+; GFX1200-NEXT: s_cbranch_scc1 .LBB3_6
+; GFX1200-NEXT: ; %bb.7: ; %Flow
; GFX1200-NEXT: v_mov_b32_e32 v7, s0
-; GFX1200-NEXT: s_branch .LBB3_7
-; GFX1200-NEXT: .LBB3_5: ; %frem.else
-; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v2
-; GFX1200-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v3
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX1200-NEXT: s_branch .LBB3_8
-; GFX1200-NEXT: .LBB3_6:
-; GFX1200-NEXT: v_mov_b32_e32 v8, v5
-; GFX1200-NEXT: .LBB3_7: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v5, -11, v7
-; GFX1200-NEXT: v_ldexp_f32 v5, v8, v5
+; GFX1200-NEXT: v_mov_b32_e32 v5, v8
+; GFX1200-NEXT: .LBB3_8: ; %frem.loop_exit
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v7, -11, v7
+; GFX1200-NEXT: v_ldexp_f32 v5, v5, v7
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1200-NEXT: v_rndne_f32_e32 v6, v6
@@ -2837,14 +3037,15 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v3, v4, v3
-; GFX1200-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
-; GFX1200-NEXT: .LBB3_8:
+; GFX1200-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v2
+; GFX1200-NEXT: .LBB3_9: ; %Flow17
; GFX1200-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: v_cmp_nle_f32_e64 s0, 0x7f800000, v1
+; GFX1200-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, 0x7fc00000, v2
-; GFX1200-NEXT: global_store_b32 v3, v0, s[8:9]
+; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v3, vcc_lo
+; GFX1200-NEXT: global_store_b32 v2, v0, s[8:9]
; GFX1200-NEXT: s_endpgm
ptr addrspace(1) %in2) #0 {
%gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4
@@ -3428,12 +3629,31 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_readfirstlane_b32 s2, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; SI-NEXT: v_cmp_ngt_f64_e64 s[0:1], |v[0:1]|, |v[2:3]|
; SI-NEXT: v_readfirstlane_b32 s3, v1
; SI-NEXT: v_readfirstlane_b32 s4, v2
; SI-NEXT: v_readfirstlane_b32 s5, v3
-; SI-NEXT: s_cbranch_vccz .LBB6_4
-; SI-NEXT: ; %bb.1: ; %frem.compute
+; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
+; SI-NEXT: s_cbranch_vccz .LBB6_2
+; SI-NEXT: ; %bb.1: ; %frem.else
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: v_mov_b32_e32 v1, s5
+; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[2:3]|, |v[0:1]|
+; SI-NEXT: s_and_b32 s6, s3, 0x80000000
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s1, s6, s3
+; SI-NEXT: s_cselect_b32 s0, 0, s2
+; SI-NEXT: s_mov_b64 s[6:7], 0
+; SI-NEXT: s_branch .LBB6_3
+; SI-NEXT: .LBB6_2:
+; SI-NEXT: s_mov_b64 s[6:7], -1
+; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
+; SI-NEXT: .LBB6_3: ; %Flow16
+; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; SI-NEXT: s_cselect_b32 s6, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s6, 1
+; SI-NEXT: s_cbranch_scc1 .LBB6_9
+; SI-NEXT: ; %bb.4: ; %frem.compute
; SI-NEXT: s_and_b32 s0, s3, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -3445,7 +3665,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[2:3]
; SI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: s_cselect_b32 s11, s0, 0
+; SI-NEXT: s_cselect_b32 s7, s0, 0
; SI-NEXT: s_and_b32 s0, s5, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -3457,12 +3677,13 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[4:5]
; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1
; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: s_cselect_b32 s12, s0, 0
-; SI-NEXT: s_add_i32 s7, s12, -1
-; SI-NEXT: s_not_b32 s0, s7
-; SI-NEXT: s_add_i32 s10, s0, s11
+; SI-NEXT: s_cselect_b32 s13, s0, 0
+; SI-NEXT: s_add_i32 s10, s13, -1
+; SI-NEXT: s_not_b32 s0, s10
+; SI-NEXT: s_add_i32 s12, s0, s7
; SI-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], 1.0
-; SI-NEXT: s_brev_b32 s6, -2
+; SI-NEXT: s_brev_b32 s11, -2
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: v_rcp_f64_e32 v[6:7], v[2:3]
; SI-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
; SI-NEXT: v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
@@ -3476,62 +3697,50 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], v[8:9]
; SI-NEXT: s_xor_b64 vcc, s[0:1], vcc
; SI-NEXT: v_div_fmas_f64 v[2:3], v[12:13], v[6:7], v[10:11]
-; SI-NEXT: s_cmp_lt_i32 s10, 27
+; SI-NEXT: s_cmp_lt_i32 s12, 27
; SI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
-; SI-NEXT: s_cbranch_scc1 .LBB6_5
-; SI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
-; SI-NEXT: s_sub_i32 s0, s11, s12
-; SI-NEXT: s_add_i32 s10, s0, 26
-; SI-NEXT: s_mov_b32 s0, -1
-; SI-NEXT: s_mov_b32 s1, 0x432fffff
+; SI-NEXT: s_cbranch_scc1 .LBB6_8
+; SI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; SI-NEXT: s_sub_i32 s0, s7, s13
+; SI-NEXT: s_add_i32 s12, s0, 26
+; SI-NEXT: s_mov_b32 s7, 0x432fffff
; SI-NEXT: v_mov_b32_e32 v10, 0x43300000
-; SI-NEXT: v_mov_b32_e32 v8, 0
-; SI-NEXT: .LBB6_3: ; %frem.loop_body
+; SI-NEXT: v_mov_b32_e32 v6, 0
+; SI-NEXT: .LBB6_6: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v7, v5
-; SI-NEXT: v_mov_b32_e32 v6, v4
-; SI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3]
-; SI-NEXT: s_sub_i32 s10, s10, 26
-; SI-NEXT: v_bfi_b32 v9, s6, v10, v5
-; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[8:9]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[0:1]
-; SI-NEXT: v_add_f64 v[11:12], v[11:12], -v[8:9]
-; SI-NEXT: s_cmp_gt_i32 s10, 26
+; SI-NEXT: v_mov_b32_e32 v9, v5
+; SI-NEXT: v_mov_b32_e32 v8, v4
+; SI-NEXT: v_mul_f64 v[4:5], v[8:9], v[2:3]
+; SI-NEXT: s_sub_i32 s12, s12, 26
+; SI-NEXT: v_bfi_b32 v7, s11, v10, v5
+; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[6:7]
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
+; SI-NEXT: v_add_f64 v[11:12], v[11:12], -v[6:7]
+; SI-NEXT: s_cmp_gt_i32 s12, 26
; SI-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v11, v4, vcc
-; SI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
+; SI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[0:1]
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc
; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; SI-NEXT: s_cbranch_scc1 .LBB6_3
-; SI-NEXT: s_branch .LBB6_6
-; SI-NEXT: .LBB6_4: ; %frem.else
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: v_mov_b32_e32 v1, s5
-; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[2:3]|, |v[0:1]|
-; SI-NEXT: s_and_b32 s6, s3, 0x80000000
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s1, s6, s3
-; SI-NEXT: s_cselect_b32 s0, 0, s2
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: s_branch .LBB6_7
-; SI-NEXT: .LBB6_5:
-; SI-NEXT: v_mov_b32_e32 v7, v5
-; SI-NEXT: v_mov_b32_e32 v6, v4
-; SI-NEXT: .LBB6_6: ; %frem.loop_exit
-; SI-NEXT: s_sub_i32 s0, s10, 25
-; SI-NEXT: v_ldexp_f64 v[4:5], v[6:7], s0
-; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
-; SI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
+; SI-NEXT: s_cbranch_scc1 .LBB6_6
+; SI-NEXT: ; %bb.7: ; %Flow
+; SI-NEXT: v_mov_b32_e32 v4, v8
+; SI-NEXT: v_mov_b32_e32 v5, v9
+; SI-NEXT: .LBB6_8: ; %frem.loop_exit
+; SI-NEXT: s_sub_i32 s0, s12, 25
+; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], s0
; SI-NEXT: s_mov_b32 s0, -1
-; SI-NEXT: v_bfi_b32 v7, s6, v6, v3
-; SI-NEXT: v_mov_b32_e32 v6, 0
-; SI-NEXT: v_add_f64 v[8:9], v[2:3], v[6:7]
+; SI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
; SI-NEXT: s_mov_b32 s1, 0x432fffff
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[0:1]
+; SI-NEXT: s_brev_b32 s0, -2
+; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
+; SI-NEXT: v_bfi_b32 v7, s0, v6, v3
+; SI-NEXT: v_mov_b32_e32 v6, 0
+; SI-NEXT: v_add_f64 v[8:9], v[2:3], v[6:7]
; SI-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
; SI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
@@ -3540,10 +3749,14 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], s7
+; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], s10
; SI-NEXT: v_mov_b32_e32 v2, s3
-; SI-NEXT: v_bfi_b32 v1, s6, v1, v2
-; SI-NEXT: .LBB6_7:
+; SI-NEXT: v_bfi_b32 v1, s0, v1, v2
+; SI-NEXT: s_branch .LBB6_10
+; SI-NEXT: .LBB6_9:
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: .LBB6_10: ; %Flow17
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: v_mov_b32_e32 v3, 0x7ff00000
; SI-NEXT: v_cmp_lg_f64_e64 s[0:1], s[4:5], 0
@@ -3571,9 +3784,25 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; CI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[2:3]|
-; CI-NEXT: s_cbranch_vccz .LBB6_4
-; CI-NEXT: ; %bb.1: ; %frem.compute
+; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB6_2
+; CI-NEXT: ; %bb.1: ; %frem.else
+; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
+; CI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
+; CI-NEXT: s_branch .LBB6_3
+; CI-NEXT: .LBB6_2:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr4_vgpr5
+; CI-NEXT: .LBB6_3: ; %Flow16
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB6_9
+; CI-NEXT: ; %bb.4: ; %frem.compute
; CI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v11, v[2:3]
; CI-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
@@ -3596,11 +3825,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v13
; CI-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB6_5
-; CI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB6_8
+; CI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v10, vcc, v10, v11
; CI-NEXT: v_add_i32_e32 v13, vcc, 26, v10
-; CI-NEXT: .LBB6_3: ; %frem.loop_body
+; CI-NEXT: .LBB6_6: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v11, v9
; CI-NEXT: v_mov_b32_e32 v10, v8
@@ -3614,20 +3843,13 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
; CI-NEXT: v_subrev_i32_e32 v13, vcc, 26, v13
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v13
-; CI-NEXT: s_cbranch_vccnz .LBB6_3
-; CI-NEXT: s_branch .LBB6_6
-; CI-NEXT: .LBB6_4: ; %frem.else
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
-; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; CI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
-; CI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; CI-NEXT: s_branch .LBB6_7
-; CI-NEXT: .LBB6_5:
-; CI-NEXT: v_mov_b32_e32 v11, v9
-; CI-NEXT: v_mov_b32_e32 v10, v8
-; CI-NEXT: .LBB6_6: ; %frem.loop_exit
-; CI-NEXT: v_subrev_i32_e32 v8, vcc, 25, v13
-; CI-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
+; CI-NEXT: s_cbranch_vccnz .LBB6_6
+; CI-NEXT: ; %bb.7: ; %Flow
+; CI-NEXT: v_mov_b32_e32 v8, v10
+; CI-NEXT: v_mov_b32_e32 v9, v11
+; CI-NEXT: .LBB6_8: ; %frem.loop_exit
+; CI-NEXT: v_subrev_i32_e32 v10, vcc, 25, v13
+; CI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
; CI-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
@@ -3638,7 +3860,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; CI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; CI-NEXT: .LBB6_7:
+; CI-NEXT: .LBB6_9: ; %Flow17
; CI-NEXT: s_mov_b32 s4, 0
; CI-NEXT: s_mov_b32 s5, 0x7ff00000
; CI-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[2:3]
@@ -3664,9 +3886,25 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[2:3]|
-; VI-NEXT: s_cbranch_vccz .LBB6_4
-; VI-NEXT: ; %bb.1: ; %frem.compute
+; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB6_2
+; VI-NEXT: ; %bb.1: ; %frem.else
+; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
+; VI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
+; VI-NEXT: s_branch .LBB6_3
+; VI-NEXT: .LBB6_2:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr4_vgpr5
+; VI-NEXT: .LBB6_3: ; %Flow16
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB6_9
+; VI-NEXT: ; %bb.4: ; %frem.compute
; VI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v11, v[2:3]
; VI-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
@@ -3689,11 +3927,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v13
; VI-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB6_5
-; VI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB6_8
+; VI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v10, vcc, v10, v11
; VI-NEXT: v_add_u32_e32 v13, vcc, 26, v10
-; VI-NEXT: .LBB6_3: ; %frem.loop_body
+; VI-NEXT: .LBB6_6: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v11, v9
; VI-NEXT: v_mov_b32_e32 v10, v8
@@ -3707,20 +3945,13 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
; VI-NEXT: v_subrev_u32_e32 v13, vcc, 26, v13
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v13
-; VI-NEXT: s_cbranch_vccnz .LBB6_3
-; VI-NEXT: s_branch .LBB6_6
-; VI-NEXT: .LBB6_4: ; %frem.else
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
-; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; VI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
-; VI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; VI-NEXT: s_branch .LBB6_7
-; VI-NEXT: .LBB6_5:
-; VI-NEXT: v_mov_b32_e32 v11, v9
-; VI-NEXT: v_mov_b32_e32 v10, v8
-; VI-NEXT: .LBB6_6: ; %frem.loop_exit
-; VI-NEXT: v_subrev_u32_e32 v8, vcc, 25, v13
-; VI-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
+; VI-NEXT: s_cbranch_vccnz .LBB6_6
+; VI-NEXT: ; %bb.7: ; %Flow
+; VI-NEXT: v_mov_b32_e32 v8, v10
+; VI-NEXT: v_mov_b32_e32 v9, v11
+; VI-NEXT: .LBB6_8: ; %frem.loop_exit
+; VI-NEXT: v_subrev_u32_e32 v10, vcc, 25, v13
+; VI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
; VI-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
@@ -3731,7 +3962,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; VI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; VI-NEXT: .LBB6_7:
+; VI-NEXT: .LBB6_9: ; %Flow17
; VI-NEXT: v_mov_b32_e32 v6, s0
; VI-NEXT: v_mov_b32_e32 v7, s1
; VI-NEXT: s_mov_b32 s0, 0
@@ -3754,9 +3985,25 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[2:3]|
-; GFX9-NEXT: s_cbranch_vccz .LBB6_4
-; GFX9-NEXT: ; %bb.1: ; %frem.compute
+; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB6_2
+; GFX9-NEXT: ; %bb.1: ; %frem.else
+; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
+; GFX9-NEXT: s_branch .LBB6_3
+; GFX9-NEXT: .LBB6_2:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX9-NEXT: .LBB6_3: ; %Flow16
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB6_9
+; GFX9-NEXT: ; %bb.4: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v11, v[2:3]
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
@@ -3779,11 +4026,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v13
; GFX9-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB6_5
-; GFX9-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB6_8
+; GFX9-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v10, v10, v11
; GFX9-NEXT: v_add_u32_e32 v13, 26, v10
-; GFX9-NEXT: .LBB6_3: ; %frem.loop_body
+; GFX9-NEXT: .LBB6_6: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v11, v9
; GFX9-NEXT: v_mov_b32_e32 v10, v8
@@ -3797,20 +4044,13 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc
; GFX9-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v13
-; GFX9-NEXT: s_cbranch_vccnz .LBB6_3
-; GFX9-NEXT: s_branch .LBB6_6
-; GFX9-NEXT: .LBB6_4: ; %frem.else
-; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
-; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; GFX9-NEXT: s_branch .LBB6_7
-; GFX9-NEXT: .LBB6_5:
-; GFX9-NEXT: v_mov_b32_e32 v11, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, v8
-; GFX9-NEXT: .LBB6_6: ; %frem.loop_exit
-; GFX9-NEXT: v_subrev_u32_e32 v8, 25, v13
-; GFX9-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
+; GFX9-NEXT: s_cbranch_vccnz .LBB6_6
+; GFX9-NEXT: ; %bb.7: ; %Flow
+; GFX9-NEXT: v_mov_b32_e32 v8, v10
+; GFX9-NEXT: v_mov_b32_e32 v9, v11
+; GFX9-NEXT: .LBB6_8: ; %frem.loop_exit
+; GFX9-NEXT: v_subrev_u32_e32 v10, 25, v13
+; GFX9-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
; GFX9-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
@@ -3821,7 +4061,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v1
-; GFX9-NEXT: .LBB6_7:
+; GFX9-NEXT: .LBB6_9: ; %Flow17
; GFX9-NEXT: s_mov_b32 s2, 0
; GFX9-NEXT: s_mov_b32 s3, 0x7ff00000
; GFX9-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[2:3]
@@ -3845,76 +4085,84 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX10-NEXT: s_cbranch_vccz .LBB6_5
-; GFX10-NEXT: ; %bb.1: ; %frem.compute
+; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB6_2
+; GFX10-NEXT: ; %bb.1: ; %frem.else
+; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX10-NEXT: s_branch .LBB6_3
+; GFX10-NEXT: .LBB6_2:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX10-NEXT: .LBB6_3: ; %Flow16
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB6_9
+; GFX10-NEXT: ; %bb.4: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v7, v[2:3]
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; GFX10-NEXT: v_ldexp_f64 v[8:9], v[4:5], 26
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
+; GFX10-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX10-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX10-NEXT: v_add_nc_u32_e32 v12, -1, v7
-; GFX10-NEXT: v_readfirstlane_b32 s3, v7
-; GFX10-NEXT: v_readfirstlane_b32 s2, v6
-; GFX10-NEXT: v_not_b32_e32 v7, v12
-; GFX10-NEXT: v_add_nc_u32_e32 v13, v7, v6
+; GFX10-NEXT: v_add_nc_u32_e32 v12, -1, v9
+; GFX10-NEXT: v_readfirstlane_b32 s3, v9
+; GFX10-NEXT: v_readfirstlane_b32 s2, v8
+; GFX10-NEXT: v_not_b32_e32 v9, v12
+; GFX10-NEXT: v_add_nc_u32_e32 v13, v9, v8
; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], 1
-; GFX10-NEXT: v_div_scale_f64 v[6:7], s4, v[4:5], v[4:5], 1.0
-; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
-; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
+; GFX10-NEXT: v_div_scale_f64 v[8:9], s4, v[4:5], v[4:5], 1.0
+; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX10-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
-; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
+; GFX10-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX10-NEXT: v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
; GFX10-NEXT: v_mul_f64 v[16:17], v[14:15], v[10:11]
-; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[16:17], v[14:15]
-; GFX10-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[16:17]
+; GFX10-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
+; GFX10-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
-; GFX10-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB6_6
-; GFX10-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX10-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; GFX10-NEXT: s_cbranch_vccnz .LBB6_8
+; GFX10-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 26
-; GFX10-NEXT: .LBB6_3: ; %frem.loop_body
+; GFX10-NEXT: .LBB6_6: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v11, v9
-; GFX10-NEXT: v_mov_b32_e32 v10, v8
+; GFX10-NEXT: v_mov_b32_e32 v11, v7
+; GFX10-NEXT: v_mov_b32_e32 v10, v6
; GFX10-NEXT: s_sub_i32 s2, s2, 26
; GFX10-NEXT: s_cmp_gt_i32 s2, 26
-; GFX10-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7]
-; GFX10-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
-; GFX10-NEXT: v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
-; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
-; GFX10-NEXT: v_add_f64 v[13:14], v[8:9], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v14, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v13, vcc_lo
-; GFX10-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB6_3
-; GFX10-NEXT: ; %bb.4:
-; GFX10-NEXT: v_mov_b32_e32 v13, s2
-; GFX10-NEXT: s_branch .LBB6_7
-; GFX10-NEXT: .LBB6_5: ; %frem.else
-; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX10-NEXT: s_branch .LBB6_8
-; GFX10-NEXT: .LBB6_6:
-; GFX10-NEXT: v_mov_b32_e32 v11, v9
-; GFX10-NEXT: v_mov_b32_e32 v10, v8
-; GFX10-NEXT: .LBB6_7: ; %frem.loop_exit
-; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 25, v13
-; GFX10-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
-; GFX10-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
+; GFX10-NEXT: v_mul_f64 v[6:7], v[10:11], v[8:9]
; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
-; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
+; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX10-NEXT: v_add_f64 v[13:14], v[6:7], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX10-NEXT: s_cbranch_scc1 .LBB6_6
+; GFX10-NEXT: ; %bb.7: ; %Flow
+; GFX10-NEXT: v_mov_b32_e32 v13, s2
+; GFX10-NEXT: v_mov_b32_e32 v6, v10
+; GFX10-NEXT: v_mov_b32_e32 v7, v11
+; GFX10-NEXT: .LBB6_8: ; %frem.loop_exit
+; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
+; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
+; GFX10-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
+; GFX10-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX10-NEXT: v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX10-NEXT: v_add_f64 v[4:5], v[6:7], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX10-NEXT: .LBB6_8:
+; GFX10-NEXT: .LBB6_9: ; %Flow17
; GFX10-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX10-NEXT: v_mov_b32_e32 v6, 0
@@ -3935,84 +4183,93 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-NEXT: global_load_b64 v[2:3], v2, s[4:5]
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX11-NEXT: s_cbranch_vccz .LBB6_5
-; GFX11-NEXT: ; %bb.1: ; %frem.compute
+; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB6_2
+; GFX11-NEXT: ; %bb.1: ; %frem.else
+; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX11-NEXT: s_branch .LBB6_3
+; GFX11-NEXT: .LBB6_2:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: .LBB6_3: ; %Flow16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB6_9
+; GFX11-NEXT: ; %bb.4: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v7, v[2:3]
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_ldexp_f64 v[8:9], v[4:5], 26
+; GFX11-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX11-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX11-NEXT: v_add_nc_u32_e32 v12, -1, v7
-; GFX11-NEXT: v_readfirstlane_b32 s3, v7
-; GFX11-NEXT: v_readfirstlane_b32 s2, v6
+; GFX11-NEXT: v_add_nc_u32_e32 v12, -1, v9
+; GFX11-NEXT: v_readfirstlane_b32 s3, v9
+; GFX11-NEXT: v_readfirstlane_b32 s2, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_not_b32_e32 v7, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v13, v7, v6
+; GFX11-NEXT: v_not_b32_e32 v9, v12
+; GFX11-NEXT: v_add_nc_u32_e32 v13, v9, v8
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
-; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
+; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
+; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
+; GFX11-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
-; GFX11-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
+; GFX11-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX11-NEXT: v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
; GFX11-NEXT: v_mul_f64 v[16:17], v[14:15], v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[6:7], -v[6:7], v[16:17], v[14:15]
-; GFX11-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[16:17]
+; GFX11-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
+; GFX11-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB6_6
-; GFX11-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX11-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; GFX11-NEXT: s_cbranch_vccnz .LBB6_8
+; GFX11-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 26
; GFX11-NEXT: .p2align 6
-; GFX11-NEXT: .LBB6_3: ; %frem.loop_body
+; GFX11-NEXT: .LBB6_6: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
+; GFX11-NEXT: v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
; GFX11-NEXT: s_sub_i32 s2, s2, 26
; GFX11-NEXT: s_cmp_gt_i32 s2, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7]
-; GFX11-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX11-NEXT: v_mul_f64 v[6:7], v[10:11], v[8:9]
+; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
-; GFX11-NEXT: v_add_f64 v[13:14], v[8:9], v[4:5]
+; GFX11-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX11-NEXT: v_add_f64 v[13:14], v[6:7], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_cndmask_b32 v8, v8, v13
-; GFX11-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB6_3
-; GFX11-NEXT: ; %bb.4:
-; GFX11-NEXT: v_mov_b32_e32 v13, s2
-; GFX11-NEXT: s_branch .LBB6_7
-; GFX11-NEXT: .LBB6_5: ; %frem.else
-; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX11-NEXT: s_branch .LBB6_8
-; GFX11-NEXT: .LBB6_6:
-; GFX11-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
-; GFX11-NEXT: .LBB6_7: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_nc_u32_e32 v8, 25, v13
-; GFX11-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
+; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX11-NEXT: s_cbranch_scc1 .LBB6_6
+; GFX11-NEXT: ; %bb.7: ; %Flow
+; GFX11-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
+; GFX11-NEXT: v_mov_b32_e32 v7, v11
+; GFX11-NEXT: .LBB6_8: ; %frem.loop_exit
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
+; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
-; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX11-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
+; GFX11-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
+; GFX11-NEXT: v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX11-NEXT: v_add_f64 v[4:5], v[6:7], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4020,7 +4277,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX11-NEXT: .LBB6_8:
+; GFX11-NEXT: .LBB6_9: ; %Flow17
; GFX11-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX11-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -4040,83 +4297,92 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX1150-NEXT: global_load_b64 v[2:3], v2, s[4:5]
; GFX1150-NEXT: s_waitcnt vmcnt(0)
-; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX1150-NEXT: s_cbranch_vccz .LBB6_5
-; GFX1150-NEXT: ; %bb.1: ; %frem.compute
+; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
+; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX1150-NEXT: s_cbranch_vccz .LBB6_2
+; GFX1150-NEXT: ; %bb.1: ; %frem.else
+; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX1150-NEXT: s_mov_b32 s2, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX1150-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB6_3
+; GFX1150-NEXT: .LBB6_2:
+; GFX1150-NEXT: s_mov_b32 s2, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1150-NEXT: .LBB6_3: ; %Flow16
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB6_9
+; GFX1150-NEXT: ; %bb.4: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v7, v[2:3]
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[4:5], 26
+; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX1150-NEXT: v_add_nc_u32_e32 v12, -1, v7
-; GFX1150-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1150-NEXT: v_readfirstlane_b32 s2, v6
+; GFX1150-NEXT: v_add_nc_u32_e32 v12, -1, v9
+; GFX1150-NEXT: v_readfirstlane_b32 s3, v9
+; GFX1150-NEXT: v_readfirstlane_b32 s2, v8
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_not_b32_e32 v7, v12
-; GFX1150-NEXT: v_add_nc_u32_e32 v13, v7, v6
+; GFX1150-NEXT: v_not_b32_e32 v9, v12
+; GFX1150-NEXT: v_add_nc_u32_e32 v13, v9, v8
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], 1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
-; GFX1150-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
+; GFX1150-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
+; GFX1150-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
+; GFX1150-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX1150-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
+; GFX1150-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX1150-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX1150-NEXT: v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f64 v[16:17], v[14:15], v[10:11]
-; GFX1150-NEXT: v_fma_f64 v[6:7], -v[6:7], v[16:17], v[14:15]
+; GFX1150-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[16:17]
+; GFX1150-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
-; GFX1150-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB6_6
-; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX1150-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; GFX1150-NEXT: s_cbranch_vccnz .LBB6_8
+; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s2, s2, s3
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s2, s2, 26
; GFX1150-NEXT: .p2align 6
-; GFX1150-NEXT: .LBB6_3: ; %frem.loop_body
+; GFX1150-NEXT: .LBB6_6: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
+; GFX1150-NEXT: v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
; GFX1150-NEXT: s_sub_i32 s2, s2, 26
; GFX1150-NEXT: s_cmp_gt_i32 s2, 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7]
-; GFX1150-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
-; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
-; GFX1150-NEXT: v_add_f64 v[13:14], v[8:9], v[4:5]
+; GFX1150-NEXT: v_mul_f64 v[6:7], v[10:11], v[8:9]
+; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_cndmask_b32 v8, v8, v13
-; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB6_3
-; GFX1150-NEXT: ; %bb.4:
-; GFX1150-NEXT: v_mov_b32_e32 v13, s2
-; GFX1150-NEXT: s_branch .LBB6_7
-; GFX1150-NEXT: .LBB6_5: ; %frem.else
-; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB6_8
-; GFX1150-NEXT: .LBB6_6:
-; GFX1150-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
-; GFX1150-NEXT: .LBB6_7: ; %frem.loop_exit
+; GFX1150-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1150-NEXT: v_add_f64 v[13:14], v[6:7], v[4:5]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_subrev_nc_u32_e32 v8, 25, v13
-; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
+; GFX1150-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
+; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX1150-NEXT: s_cbranch_scc1 .LBB6_6
+; GFX1150-NEXT: ; %bb.7: ; %Flow
+; GFX1150-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
+; GFX1150-NEXT: v_mov_b32_e32 v7, v11
+; GFX1150-NEXT: .LBB6_8: ; %frem.loop_exit
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
+; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
-; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX1150-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
+; GFX1150-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
+; GFX1150-NEXT: v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1150-NEXT: v_add_f64 v[4:5], v[6:7], v[4:5]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4124,7 +4390,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX1150-NEXT: .LBB6_8:
+; GFX1150-NEXT: .LBB6_9: ; %Flow17
; GFX1150-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1150-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1150-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -4144,83 +4410,93 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX1200-NEXT: global_load_b64 v[2:3], v2, s[4:5]
; GFX1200-NEXT: s_wait_loadcnt 0x0
-; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX1200-NEXT: s_cbranch_vccz .LBB6_5
-; GFX1200-NEXT: ; %bb.1: ; %frem.compute
+; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
+; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX1200-NEXT: s_cbranch_vccz .LBB6_2
+; GFX1200-NEXT: ; %bb.1: ; %frem.else
+; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX1200-NEXT: s_mov_b32 s2, 0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX1200-NEXT: s_branch .LBB6_3
+; GFX1200-NEXT: .LBB6_2:
+; GFX1200-NEXT: s_mov_b32 s2, -1
+; GFX1200-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1200-NEXT: .LBB6_3: ; %Flow16
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1200-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB6_9
+; GFX1200-NEXT: ; %bb.4: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v7, v[2:3]
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[4:5], 26
+; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX1200-NEXT: v_add_nc_u32_e32 v12, -1, v7
-; GFX1200-NEXT: v_readfirstlane_b32 s3, v7
-; GFX1200-NEXT: v_readfirstlane_b32 s2, v6
+; GFX1200-NEXT: v_add_nc_u32_e32 v12, -1, v9
+; GFX1200-NEXT: v_readfirstlane_b32 s3, v9
+; GFX1200-NEXT: v_readfirstlane_b32 s2, v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_not_b32_e32 v7, v12
-; GFX1200-NEXT: v_add_nc_u32_e32 v13, v7, v6
+; GFX1200-NEXT: v_not_b32_e32 v9, v12
+; GFX1200-NEXT: v_add_nc_u32_e32 v13, v9, v8
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], 1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
-; GFX1200-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
+; GFX1200-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
+; GFX1200-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
+; GFX1200-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX1200-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
+; GFX1200-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
; GFX1200-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX1200-NEXT: v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f64_e32 v[16:17], v[14:15], v[10:11]
-; GFX1200-NEXT: v_fma_f64 v[6:7], -v[6:7], v[16:17], v[14:15]
+; GFX1200-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[16:17]
+; GFX1200-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
-; GFX1200-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB6_6
-; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX1200-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; GFX1200-NEXT: s_cbranch_vccnz .LBB6_8
+; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s2, s2, s3
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 26
-; GFX1200-NEXT: .LBB6_3: ; %frem.loop_body
+; GFX1200-NEXT: .LBB6_6: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
+; GFX1200-NEXT: v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_mul_f64_e32 v[8:9], v[10:11], v[6:7]
-; GFX1200-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX1200-NEXT: v_mul_f64_e32 v[6:7], v[10:11], v[8:9]
+; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
-; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
-; GFX1200-NEXT: v_add_f64_e32 v[13:14], v[8:9], v[4:5]
+; GFX1200-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1200-NEXT: v_add_f64_e32 v[13:14], v[6:7], v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_cndmask_b32 v8, v8, v13
-; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB6_3
-; GFX1200-NEXT: ; %bb.4:
-; GFX1200-NEXT: v_mov_b32_e32 v13, s2
-; GFX1200-NEXT: s_branch .LBB6_7
-; GFX1200-NEXT: .LBB6_5: ; %frem.else
-; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX1200-NEXT: s_branch .LBB6_8
-; GFX1200-NEXT: .LBB6_6:
-; GFX1200-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
-; GFX1200-NEXT: .LBB6_7: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_subrev_nc_u32_e32 v8, 25, v13
-; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
+; GFX1200-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
+; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX1200-NEXT: s_cbranch_scc1 .LBB6_6
+; GFX1200-NEXT: ; %bb.7: ; %Flow
+; GFX1200-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
+; GFX1200-NEXT: v_mov_b32_e32 v7, v11
+; GFX1200-NEXT: .LBB6_8: ; %frem.loop_exit
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
+; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_mul_f64_e32 v[6:7], v[8:9], v[6:7]
-; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX1200-NEXT: v_mul_f64_e32 v[8:9], v[6:7], v[8:9]
+; GFX1200-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
+; GFX1200-NEXT: v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT: v_add_f64_e32 v[4:5], v[6:7], v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -4229,7 +4505,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX1200-NEXT: .LBB6_8:
+; GFX1200-NEXT: .LBB6_9: ; %Flow17
; GFX1200-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1200-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -4812,114 +5088,136 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_mov_b32 s4, s10
; SI-NEXT: s_mov_b32 s5, s11
; SI-NEXT: s_mov_b32 s3, s7
-; SI-NEXT: buffer_load_dword v2, off, s[4:7], 0
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], 0 offset:16
+; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:16
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cvt_f32_f16_e64 v5, |v2|
+; SI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e64 v4, |v3|
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
-; SI-NEXT: s_cbranch_vccz .LBB9_4
-; SI-NEXT: ; %bb.1: ; %frem.compute19
+; SI-NEXT: v_cvt_f32_f16_e64 v4, |v1|
+; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v4
+; SI-NEXT: s_cbranch_vccz .LBB9_2
+; SI-NEXT: ; %bb.1: ; %frem.else20
+; SI-NEXT: v_and_b32_e32 v2, 0xffff8000, v0
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v4
+; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; SI-NEXT: s_mov_b64 s[0:1], 0
+; SI-NEXT: s_branch .LBB9_3
+; SI-NEXT: .LBB9_2:
+; SI-NEXT: s_mov_b64 s[0:1], -1
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: .LBB9_3: ; %Flow57
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s0, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s0, 1
+; SI-NEXT: s_cbranch_scc1 .LBB9_9
+; SI-NEXT: ; %bb.4: ; %frem.compute19
; SI-NEXT: s_mov_b32 s3, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s3
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v6, v5
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v6
-; SI-NEXT: v_frexp_mant_f32_e32 v6, v5
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; SI-NEXT: v_readfirstlane_b32 s0, v2
+; SI-NEXT: v_frexp_mant_f32_e32 v2, v3
+; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; SI-NEXT: v_ldexp_f32_e64 v3, v2, 11
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s3
-; SI-NEXT: v_frexp_mant_f32_e32 v6, v4
+; SI-NEXT: v_frexp_mant_f32_e32 v2, v4
+; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; SI-NEXT: v_ldexp_f32_e64 v2, v2, 1
+; SI-NEXT: v_div_scale_f32 v5, s[4:5], v2, v2, 1.0
+; SI-NEXT: v_rcp_f32_e32 v6, v5
; SI-NEXT: s_cselect_b32 s2, s0, 0
-; SI-NEXT: v_cndmask_b32_e32 v6, v4, v6, vcc
; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s0, v4
-; SI-NEXT: v_ldexp_f32_e64 v4, v6, 1
-; SI-NEXT: v_div_scale_f32 v7, s[4:5], v4, v4, 1.0
-; SI-NEXT: v_rcp_f32_e32 v8, v7
-; SI-NEXT: v_ldexp_f32_e64 v5, v5, 11
-; SI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
+; SI-NEXT: v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT: v_fma_f32 v9, -v7, v8, 1.0
-; SI-NEXT: v_fma_f32 v8, v9, v8, v8
-; SI-NEXT: v_mul_f32_e32 v9, v6, v8
+; SI-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; SI-NEXT: v_fma_f32 v6, v7, v6, v6
+; SI-NEXT: v_mul_f32_e32 v7, v4, v6
; SI-NEXT: s_cselect_b32 s3, s0, 0
-; SI-NEXT: v_fma_f32 v10, -v7, v9, v6
+; SI-NEXT: v_fma_f32 v8, -v5, v7, v4
; SI-NEXT: s_add_i32 s0, s3, -1
-; SI-NEXT: v_fma_f32 v9, v10, v8, v9
+; SI-NEXT: v_fma_f32 v7, v8, v6, v7
; SI-NEXT: s_not_b32 s1, s0
-; SI-NEXT: v_fma_f32 v6, -v7, v9, v6
+; SI-NEXT: v_fma_f32 v4, -v5, v7, v4
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT: s_add_i32 s1, s1, s2
-; SI-NEXT: v_div_fmas_f32 v6, v6, v8, v9
-; SI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
+; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
+; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB9_5
-; SI-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB9_8
+; SI-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; SI-NEXT: s_sub_i32 s1, s2, s3
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB9_3: ; %frem.loop_body27
+; SI-NEXT: .LBB9_6: ; %frem.loop_body27
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v7, v5
-; SI-NEXT: v_mul_f32_e32 v5, v7, v6
-; SI-NEXT: v_rndne_f32_e32 v5, v5
-; SI-NEXT: v_fma_f32 v5, -v5, v4, v7
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; SI-NEXT: v_add_f32_e32 v8, v5, v4
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; SI-NEXT: v_mov_b32_e32 v5, v3
+; SI-NEXT: v_mul_f32_e32 v3, v5, v4
+; SI-NEXT: v_rndne_f32_e32 v3, v3
+; SI-NEXT: v_fma_f32 v3, -v3, v2, v5
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
+; SI-NEXT: v_add_f32_e32 v6, v3, v2
+; SI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; SI-NEXT: s_add_i32 s1, s1, -11
-; SI-NEXT: v_ldexp_f32_e64 v5, v5, 11
+; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB9_3
-; SI-NEXT: s_branch .LBB9_6
-; SI-NEXT: .LBB9_4: ; %frem.else20
-; SI-NEXT: v_and_b32_e32 v6, 0xffff8000, v2
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
-; SI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
-; SI-NEXT: s_branch .LBB9_7
-; SI-NEXT: .LBB9_5:
-; SI-NEXT: v_mov_b32_e32 v7, v5
-; SI-NEXT: .LBB9_6: ; %frem.loop_exit28
+; SI-NEXT: s_cbranch_scc1 .LBB9_6
+; SI-NEXT: ; %bb.7: ; %Flow55
+; SI-NEXT: v_mov_b32_e32 v3, v5
+; SI-NEXT: .LBB9_8: ; %frem.loop_exit28
; SI-NEXT: s_add_i32 s1, s1, -10
-; SI-NEXT: v_ldexp_f32_e64 v5, v7, s1
-; SI-NEXT: v_mul_f32_e32 v6, v5, v6
-; SI-NEXT: v_rndne_f32_e32 v6, v6
-; SI-NEXT: v_fma_f32 v5, -v6, v4, v5
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; SI-NEXT: v_add_f32_e32 v4, v5, v4
-; SI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; SI-NEXT: v_ldexp_f32_e64 v4, v4, s0
-; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-NEXT: v_and_b32_e32 v5, 0xffff8000, v2
-; SI-NEXT: v_and_b32_e32 v4, 0x7fff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v5
-; SI-NEXT: .LBB9_7:
-; SI-NEXT: v_cvt_f32_f16_e64 v6, |v0|
-; SI-NEXT: v_cvt_f32_f16_e64 v5, |v1|
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5
+; SI-NEXT: v_ldexp_f32_e64 v3, v3, s1
+; SI-NEXT: v_mul_f32_e32 v4, v3, v4
+; SI-NEXT: v_rndne_f32_e32 v4, v4
+; SI-NEXT: v_fma_f32 v3, -v4, v2, v3
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
+; SI-NEXT: v_add_f32_e32 v2, v3, v2
+; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; SI-NEXT: v_ldexp_f32_e64 v2, v2, s0
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_and_b32_e32 v3, 0xffff8000, v0
+; SI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: .LBB9_9: ; %Flow58
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_cvt_f32_f16_e64 v6, |v3|
+; SI-NEXT: v_cvt_f32_f16_e64 v7, |v4|
+; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v7
; SI-NEXT: s_cbranch_vccz .LBB9_11
-; SI-NEXT: ; %bb.8: ; %frem.compute
+; SI-NEXT: ; %bb.10: ; %frem.else
+; SI-NEXT: v_and_b32_e32 v5, 0x8000, v3
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v7
+; SI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
+; SI-NEXT: s_mov_b64 s[0:1], 0
+; SI-NEXT: s_branch .LBB9_12
+; SI-NEXT: .LBB9_11:
+; SI-NEXT: s_mov_b64 s[0:1], -1
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: .LBB9_12: ; %Flow53
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s0, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s0, 1
+; SI-NEXT: s_cbranch_scc1 .LBB9_18
+; SI-NEXT: ; %bb.13: ; %frem.compute
; SI-NEXT: s_mov_b32 s3, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s3
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v7
-; SI-NEXT: v_frexp_mant_f32_e32 v7, v6
-; SI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s3
-; SI-NEXT: v_frexp_mant_f32_e32 v7, v5
-; SI-NEXT: s_cselect_b32 s2, s0, 0
-; SI-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v6
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s0, v5
-; SI-NEXT: v_ldexp_f32_e64 v5, v7, 1
+; SI-NEXT: v_frexp_mant_f32_e32 v5, v6
+; SI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; SI-NEXT: v_ldexp_f32_e64 v6, v5, 11
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s3
+; SI-NEXT: v_frexp_mant_f32_e32 v5, v7
+; SI-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
+; SI-NEXT: v_ldexp_f32_e64 v5, v5, 1
; SI-NEXT: v_div_scale_f32 v8, s[4:5], v5, v5, 1.0
; SI-NEXT: v_rcp_f32_e32 v9, v8
-; SI-NEXT: v_ldexp_f32_e64 v6, v6, 11
+; SI-NEXT: s_cselect_b32 s2, s0, 0
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v7, v7
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v7
; SI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT: v_fma_f32 v10, -v8, v9, 1.0
@@ -4936,11 +5234,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v7, v7, v9, v10
; SI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB9_12
-; SI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB9_17
+; SI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s1, s2, s3
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB9_10: ; %frem.loop_body
+; SI-NEXT: .LBB9_15: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v8, v6
; SI-NEXT: v_mul_f32_e32 v6, v8, v7
@@ -4952,18 +5250,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v6, v6, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB9_10
-; SI-NEXT: s_branch .LBB9_13
-; SI-NEXT: .LBB9_11: ; %frem.else
-; SI-NEXT: v_and_b32_e32 v7, 0x8000, v0
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
-; SI-NEXT: v_cndmask_b32_e32 v5, v0, v7, vcc
-; SI-NEXT: s_branch .LBB9_14
-; SI-NEXT: .LBB9_12:
-; SI-NEXT: v_mov_b32_e32 v8, v6
-; SI-NEXT: .LBB9_13: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB9_15
+; SI-NEXT: ; %bb.16: ; %Flow
+; SI-NEXT: v_mov_b32_e32 v6, v8
+; SI-NEXT: .LBB9_17: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s1, s1, -10
-; SI-NEXT: v_ldexp_f32_e64 v6, v8, s1
+; SI-NEXT: v_ldexp_f32_e64 v6, v6, s1
; SI-NEXT: v_mul_f32_e32 v7, v6, v7
; SI-NEXT: v_rndne_f32_e32 v7, v7
; SI-NEXT: v_fma_f32 v6, -v7, v5, v6
@@ -4972,28 +5264,28 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; SI-NEXT: v_ldexp_f32_e64 v5, v5, s0
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-NEXT: v_and_b32_e32 v6, 0x8000, v0
+; SI-NEXT: v_and_b32_e32 v6, 0x8000, v3
; SI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: .LBB9_14:
-; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NEXT: v_cvt_f32_f16_e64 v2, |v2|
+; SI-NEXT: .LBB9_18: ; %Flow54
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; SI-NEXT: s_mov_b32 s2, 0x7f800000
-; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v3
-; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v2
-; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; SI-NEXT: v_mov_b32_e32 v2, 0x7e00
-; SI-NEXT: v_cndmask_b32_e32 v3, v2, v4, vcc
+; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v0
; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; SI-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: v_mov_b32_e32 v0, 0x7e00
+; SI-NEXT: v_cndmask_b32_e32 v1, v0, v2, vcc
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v4
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_mov_b32 s10, -1
+; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
+; SI-NEXT: v_cvt_f32_f16_e64 v2, |v3|
+; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v2
+; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
+; SI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_endpgm
@@ -5009,137 +5301,153 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_mov_b32 s4, s10
; CI-NEXT: s_mov_b32 s5, s11
; CI-NEXT: s_mov_b32 s3, s7
-; CI-NEXT: buffer_load_dword v2, off, s[4:7], 0
-; CI-NEXT: buffer_load_dword v3, off, s[0:3], 0 offset:16
+; CI-NEXT: buffer_load_dword v0, off, s[4:7], 0
+; CI-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:16
; CI-NEXT: s_waitcnt vmcnt(1)
-; CI-NEXT: v_cvt_f32_f16_e64 v5, |v2|
+; CI-NEXT: v_cvt_f32_f16_e64 v4, |v0|
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |v3|
-; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
-; CI-NEXT: s_cbranch_vccz .LBB9_4
-; CI-NEXT: ; %bb.1: ; %frem.compute19
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v9, v5
-; CI-NEXT: v_frexp_mant_f32_e32 v5, v5
-; CI-NEXT: v_ldexp_f32_e64 v8, v5, 11
-; CI-NEXT: v_frexp_mant_f32_e32 v5, v4
-; CI-NEXT: v_ldexp_f32_e64 v5, v5, 1
-; CI-NEXT: v_div_scale_f32 v11, s[0:1], v5, v5, 1.0
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v4
-; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v10
-; CI-NEXT: v_not_b32_e32 v6, v4
-; CI-NEXT: v_add_i32_e32 v6, vcc, v6, v9
-; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
-; CI-NEXT: v_rcp_f32_e32 v12, v11
+; CI-NEXT: v_cvt_f32_f16_e64 v3, |v1|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
+; CI-NEXT: s_cbranch_vccz .LBB9_2
+; CI-NEXT: ; %bb.1: ; %frem.else20
+; CI-NEXT: v_and_b32_e32 v2, 0xffff8000, v0
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
+; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; CI-NEXT: s_mov_b64 s[0:1], 0
+; CI-NEXT: s_branch .LBB9_3
+; CI-NEXT: .LBB9_2:
+; CI-NEXT: s_mov_b64 s[0:1], -1
+; CI-NEXT: ; implicit-def: $vgpr2
+; CI-NEXT: .LBB9_3: ; %Flow57
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cselect_b32 s0, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s0, 1
+; CI-NEXT: s_cbranch_scc1 .LBB9_9
+; CI-NEXT: ; %bb.4: ; %frem.compute19
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
+; CI-NEXT: v_frexp_mant_f32_e32 v2, v4
+; CI-NEXT: v_frexp_mant_f32_e32 v4, v3
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
+; CI-NEXT: v_ldexp_f32_e64 v3, v4, 1
+; CI-NEXT: v_div_scale_f32 v9, s[0:1], v3, v3, 1.0
+; CI-NEXT: v_ldexp_f32_e64 v5, v2, 11
+; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8
+; CI-NEXT: v_not_b32_e32 v4, v2
+; CI-NEXT: v_add_i32_e32 v4, vcc, v4, v7
+; CI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; CI-NEXT: v_rcp_f32_e32 v10, v9
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v13, -v11, v12, 1.0
-; CI-NEXT: v_fma_f32 v12, v13, v12, v12
-; CI-NEXT: v_mul_f32_e32 v13, v7, v12
-; CI-NEXT: v_fma_f32 v14, -v11, v13, v7
-; CI-NEXT: v_fma_f32 v13, v14, v12, v13
-; CI-NEXT: v_fma_f32 v7, -v11, v13, v7
+; CI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
+; CI-NEXT: v_fma_f32 v10, v11, v10, v10
+; CI-NEXT: v_mul_f32_e32 v11, v6, v10
+; CI-NEXT: v_fma_f32 v12, -v9, v11, v6
+; CI-NEXT: v_fma_f32 v11, v12, v10, v11
+; CI-NEXT: v_fma_f32 v6, -v9, v11, v6
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v7, v7, v12, v13
-; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
-; CI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB9_5
-; CI-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
-; CI-NEXT: v_sub_i32_e32 v6, vcc, v9, v10
-; CI-NEXT: v_add_i32_e32 v6, vcc, 11, v6
-; CI-NEXT: .LBB9_3: ; %frem.loop_body27
+; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
+; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
+; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB9_8
+; CI-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
+; CI-NEXT: v_add_i32_e32 v4, vcc, 11, v4
+; CI-NEXT: .LBB9_6: ; %frem.loop_body27
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v9, v8
-; CI-NEXT: v_mul_f32_e32 v8, v9, v7
-; CI-NEXT: v_rndne_f32_e32 v8, v8
-; CI-NEXT: v_fma_f32 v8, -v8, v5, v9
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; CI-NEXT: v_add_f32_e32 v10, v8, v5
-; CI-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
-; CI-NEXT: v_add_i32_e32 v6, vcc, -11, v6
-; CI-NEXT: v_ldexp_f32_e64 v8, v8, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
-; CI-NEXT: s_cbranch_vccnz .LBB9_3
-; CI-NEXT: s_branch .LBB9_6
-; CI-NEXT: .LBB9_4: ; %frem.else20
-; CI-NEXT: v_and_b32_e32 v6, 0xffff8000, v2
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
-; CI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
-; CI-NEXT: s_branch .LBB9_7
-; CI-NEXT: .LBB9_5:
-; CI-NEXT: v_mov_b32_e32 v9, v8
-; CI-NEXT: .LBB9_6: ; %frem.loop_exit28
-; CI-NEXT: v_add_i32_e32 v6, vcc, -10, v6
-; CI-NEXT: v_ldexp_f32_e32 v6, v9, v6
-; CI-NEXT: v_mul_f32_e32 v7, v6, v7
-; CI-NEXT: v_rndne_f32_e32 v7, v7
-; CI-NEXT: v_fma_f32 v6, -v7, v5, v6
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; CI-NEXT: v_add_f32_e32 v5, v6, v5
-; CI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; CI-NEXT: v_mov_b32_e32 v7, v5
+; CI-NEXT: v_mul_f32_e32 v5, v7, v6
+; CI-NEXT: v_rndne_f32_e32 v5, v5
+; CI-NEXT: v_fma_f32 v5, -v5, v3, v7
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; CI-NEXT: v_add_f32_e32 v8, v5, v3
+; CI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
+; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
+; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11
+; CI-NEXT: s_cbranch_vccnz .LBB9_6
+; CI-NEXT: ; %bb.7: ; %Flow55
+; CI-NEXT: v_mov_b32_e32 v5, v7
+; CI-NEXT: .LBB9_8: ; %frem.loop_exit28
+; CI-NEXT: v_add_i32_e32 v4, vcc, -10, v4
; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: v_and_b32_e32 v5, 0xffff8000, v2
-; CI-NEXT: v_and_b32_e32 v4, 0x7fff, v4
-; CI-NEXT: v_or_b32_e32 v4, v4, v5
-; CI-NEXT: .LBB9_7:
-; CI-NEXT: v_cvt_f32_f16_e64 v6, |v0|
-; CI-NEXT: v_cvt_f32_f16_e64 v5, |v1|
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5
+; CI-NEXT: v_mul_f32_e32 v5, v4, v6
+; CI-NEXT: v_rndne_f32_e32 v5, v5
+; CI-NEXT: v_fma_f32 v4, -v5, v3, v4
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
+; CI-NEXT: v_add_f32_e32 v3, v4, v3
+; CI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2
+; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_and_b32_e32 v3, 0xffff8000, v0
+; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; CI-NEXT: v_or_b32_e32 v2, v2, v3
+; CI-NEXT: .LBB9_9: ; %Flow58
+; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; CI-NEXT: v_cvt_f32_f16_e64 v7, |v3|
+; CI-NEXT: v_cvt_f32_f16_e64 v6, |v4|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
; CI-NEXT: s_cbranch_vccz .LBB9_11
-; CI-NEXT: ; %bb.8: ; %frem.compute
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v6
-; CI-NEXT: v_frexp_mant_f32_e32 v6, v6
-; CI-NEXT: v_ldexp_f32_e64 v9, v6, 11
-; CI-NEXT: v_frexp_mant_f32_e32 v6, v5
-; CI-NEXT: v_ldexp_f32_e64 v6, v6, 1
+; CI-NEXT: ; %bb.10: ; %frem.else
+; CI-NEXT: v_and_b32_e32 v5, 0x8000, v3
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
+; CI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
+; CI-NEXT: s_mov_b64 s[0:1], 0
+; CI-NEXT: s_branch .LBB9_12
+; CI-NEXT: .LBB9_11:
+; CI-NEXT: s_mov_b64 s[0:1], -1
+; CI-NEXT: ; implicit-def: $vgpr5
+; CI-NEXT: .LBB9_12: ; %Flow53
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cselect_b32 s0, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s0, 1
+; CI-NEXT: s_cbranch_scc1 .LBB9_18
+; CI-NEXT: ; %bb.13: ; %frem.compute
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v7
+; CI-NEXT: v_frexp_mant_f32_e32 v5, v7
+; CI-NEXT: v_frexp_mant_f32_e32 v7, v6
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v6
+; CI-NEXT: v_ldexp_f32_e64 v6, v7, 1
; CI-NEXT: v_div_scale_f32 v12, s[0:1], v6, v6, 1.0
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v5
+; CI-NEXT: v_ldexp_f32_e64 v8, v5, 11
; CI-NEXT: v_add_i32_e32 v5, vcc, -1, v11
; CI-NEXT: v_not_b32_e32 v7, v5
; CI-NEXT: v_add_i32_e32 v7, vcc, v7, v10
-; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
+; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; CI-NEXT: v_rcp_f32_e32 v13, v12
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; CI-NEXT: v_fma_f32 v13, v14, v13, v13
-; CI-NEXT: v_mul_f32_e32 v14, v8, v13
-; CI-NEXT: v_fma_f32 v15, -v12, v14, v8
+; CI-NEXT: v_mul_f32_e32 v14, v9, v13
+; CI-NEXT: v_fma_f32 v15, -v12, v14, v9
; CI-NEXT: v_fma_f32 v14, v15, v13, v14
-; CI-NEXT: v_fma_f32 v8, -v12, v14, v8
+; CI-NEXT: v_fma_f32 v9, -v12, v14, v9
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v8, v8, v13, v14
+; CI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v7
-; CI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB9_12
-; CI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB9_17
+; CI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v7, vcc, v10, v11
; CI-NEXT: v_add_i32_e32 v7, vcc, 11, v7
-; CI-NEXT: .LBB9_10: ; %frem.loop_body
+; CI-NEXT: .LBB9_15: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v10, v9
-; CI-NEXT: v_mul_f32_e32 v9, v10, v8
-; CI-NEXT: v_rndne_f32_e32 v9, v9
-; CI-NEXT: v_fma_f32 v9, -v9, v6, v10
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
-; CI-NEXT: v_add_f32_e32 v11, v9, v6
-; CI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; CI-NEXT: v_mov_b32_e32 v10, v8
+; CI-NEXT: v_mul_f32_e32 v8, v10, v9
+; CI-NEXT: v_rndne_f32_e32 v8, v8
+; CI-NEXT: v_fma_f32 v8, -v8, v6, v10
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; CI-NEXT: v_add_f32_e32 v11, v8, v6
+; CI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
; CI-NEXT: v_add_i32_e32 v7, vcc, -11, v7
-; CI-NEXT: v_ldexp_f32_e64 v9, v9, 11
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v7
-; CI-NEXT: s_cbranch_vccnz .LBB9_10
-; CI-NEXT: s_branch .LBB9_13
-; CI-NEXT: .LBB9_11: ; %frem.else
-; CI-NEXT: v_and_b32_e32 v7, 0x8000, v0
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
-; CI-NEXT: v_cndmask_b32_e32 v5, v0, v7, vcc
-; CI-NEXT: s_branch .LBB9_14
-; CI-NEXT: .LBB9_12:
-; CI-NEXT: v_mov_b32_e32 v10, v9
-; CI-NEXT: .LBB9_13: ; %frem.loop_exit
+; CI-NEXT: v_ldexp_f32_e64 v8, v8, 11
+; CI-NEXT: s_cbranch_vccnz .LBB9_15
+; CI-NEXT: ; %bb.16: ; %Flow
+; CI-NEXT: v_mov_b32_e32 v8, v10
+; CI-NEXT: .LBB9_17: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v7, vcc, -10, v7
-; CI-NEXT: v_ldexp_f32_e32 v7, v10, v7
-; CI-NEXT: v_mul_f32_e32 v8, v7, v8
+; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
+; CI-NEXT: v_mul_f32_e32 v8, v7, v9
; CI-NEXT: v_rndne_f32_e32 v8, v8
; CI-NEXT: v_fma_f32 v7, -v8, v6, v7
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
@@ -5147,28 +5455,28 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; CI-NEXT: v_ldexp_f32_e32 v5, v6, v5
; CI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; CI-NEXT: v_and_b32_e32 v6, 0x8000, v0
+; CI-NEXT: v_and_b32_e32 v6, 0x8000, v3
; CI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
; CI-NEXT: v_or_b32_e32 v5, v5, v6
-; CI-NEXT: .LBB9_14:
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |v2|
+; CI-NEXT: .LBB9_18: ; %Flow54
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; CI-NEXT: s_mov_b32 s2, 0x7f800000
-; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v3
-; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v2
-; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; CI-NEXT: v_mov_b32_e32 v2, 0x7e00
-; CI-NEXT: v_cndmask_b32_e32 v3, v2, v4, vcc
+; CI-NEXT: s_mov_b32 s11, 0xf000
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v0
; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; CI-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
-; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; CI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; CI-NEXT: s_mov_b32 s11, 0xf000
+; CI-NEXT: v_mov_b32_e32 v0, 0x7e00
+; CI-NEXT: v_cndmask_b32_e32 v1, v0, v2, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v4
+; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; CI-NEXT: s_mov_b32 s10, -1
+; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
+; CI-NEXT: v_cvt_f32_f16_e64 v2, |v3|
+; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v2
+; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
+; CI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; CI-NEXT: v_or_b32_e32 v0, v1, v0
; CI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; CI-NEXT: s_endpgm
@@ -5187,64 +5495,72 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_mov_b32_e32 v2, s3
; VI-NEXT: flat_load_dword v1, v[1:2]
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; VI-NEXT: v_cvt_f32_f16_e64 v4, |v0|
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e64 v2, |v1|
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
-; VI-NEXT: s_cbranch_vccz .LBB9_4
-; VI-NEXT: ; %bb.1: ; %frem.compute19
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
-; VI-NEXT: v_frexp_mant_f32_e32 v3, v3
-; VI-NEXT: v_ldexp_f32 v6, v3, 11
-; VI-NEXT: v_frexp_mant_f32_e32 v3, v2
-; VI-NEXT: v_ldexp_f32 v3, v3, 1
+; VI-NEXT: v_cvt_f32_f16_e64 v3, |v1|
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
+; VI-NEXT: s_cbranch_vccz .LBB9_2
+; VI-NEXT: ; %bb.1: ; %frem.else20
+; VI-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
+; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB9_3
+; VI-NEXT: .LBB9_2:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr2
+; VI-NEXT: .LBB9_3: ; %Flow57
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB9_9
+; VI-NEXT: ; %bb.4: ; %frem.compute19
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
+; VI-NEXT: v_frexp_mant_f32_e32 v2, v4
+; VI-NEXT: v_frexp_mant_f32_e32 v4, v3
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
+; VI-NEXT: v_ldexp_f32 v3, v4, 1
; VI-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
+; VI-NEXT: v_ldexp_f32 v5, v2, 11
; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT: v_not_b32_e32 v4, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v7
-; VI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
+; VI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
; VI-NEXT: v_rcp_f32_e32 v10, v9
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT: v_fma_f32 v10, v11, v10, v10
-; VI-NEXT: v_mul_f32_e32 v11, v5, v10
-; VI-NEXT: v_fma_f32 v12, -v9, v11, v5
+; VI-NEXT: v_mul_f32_e32 v11, v6, v10
+; VI-NEXT: v_fma_f32 v12, -v9, v11, v6
; VI-NEXT: v_fma_f32 v11, v12, v10, v11
-; VI-NEXT: v_fma_f32 v5, -v9, v11, v5
+; VI-NEXT: v_fma_f32 v6, -v9, v11, v6
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
+; VI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; VI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB9_5
-; VI-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; VI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB9_8
+; VI-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; VI-NEXT: v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT: v_add_u32_e32 v4, vcc, 11, v4
-; VI-NEXT: .LBB9_3: ; %frem.loop_body27
+; VI-NEXT: .LBB9_6: ; %frem.loop_body27
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v6
-; VI-NEXT: v_mul_f32_e32 v6, v7, v5
-; VI-NEXT: v_rndne_f32_e32 v6, v6
-; VI-NEXT: v_fma_f32 v6, -v6, v3, v7
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; VI-NEXT: v_add_f32_e32 v8, v6, v3
-; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; VI-NEXT: v_mov_b32_e32 v7, v5
+; VI-NEXT: v_mul_f32_e32 v5, v7, v6
+; VI-NEXT: v_rndne_f32_e32 v5, v5
+; VI-NEXT: v_fma_f32 v5, -v5, v3, v7
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; VI-NEXT: v_add_f32_e32 v8, v5, v3
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
-; VI-NEXT: v_ldexp_f32 v6, v6, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; VI-NEXT: s_cbranch_vccnz .LBB9_3
-; VI-NEXT: s_branch .LBB9_6
-; VI-NEXT: .LBB9_4: ; %frem.else20
-; VI-NEXT: v_and_b32_e32 v4, 0x8000, v0
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; VI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
-; VI-NEXT: s_branch .LBB9_7
-; VI-NEXT: .LBB9_5:
-; VI-NEXT: v_mov_b32_e32 v7, v6
-; VI-NEXT: .LBB9_6: ; %frem.loop_exit28
+; VI-NEXT: v_ldexp_f32 v5, v5, 11
+; VI-NEXT: s_cbranch_vccnz .LBB9_6
+; VI-NEXT: ; %bb.7: ; %Flow55
+; VI-NEXT: v_mov_b32_e32 v5, v7
+; VI-NEXT: .LBB9_8: ; %frem.loop_exit28
; VI-NEXT: v_add_u32_e32 v4, vcc, -10, v4
-; VI-NEXT: v_ldexp_f32 v4, v7, v4
-; VI-NEXT: v_mul_f32_e32 v5, v4, v5
+; VI-NEXT: v_ldexp_f32 v4, v5, v4
+; VI-NEXT: v_mul_f32_e32 v5, v4, v6
; VI-NEXT: v_rndne_f32_e32 v5, v5
; VI-NEXT: v_fma_f32 v4, -v5, v3, v4
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -5253,67 +5569,75 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v2, v3, v2
; VI-NEXT: v_cvt_f16_f32_e32 v2, v2
; VI-NEXT: s_movk_i32 s2, 0x7fff
-; VI-NEXT: v_bfi_b32 v3, s2, v2, v0
-; VI-NEXT: .LBB9_7:
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; VI-NEXT: v_bfi_b32 v2, s2, v2, v0
+; VI-NEXT: .LBB9_9:
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; VI-NEXT: v_cvt_f32_f16_e64 v6, |v2|
-; VI-NEXT: v_cvt_f32_f16_e64 v5, |v4|
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5
+; VI-NEXT: v_cvt_f32_f16_e64 v7, |v3|
+; VI-NEXT: v_cvt_f32_f16_e64 v6, |v4|
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
; VI-NEXT: s_cbranch_vccz .LBB9_11
-; VI-NEXT: ; %bb.8: ; %frem.compute
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v6
-; VI-NEXT: v_frexp_mant_f32_e32 v6, v6
-; VI-NEXT: v_ldexp_f32 v9, v6, 11
-; VI-NEXT: v_frexp_mant_f32_e32 v6, v5
-; VI-NEXT: v_ldexp_f32 v6, v6, 1
+; VI-NEXT: ; %bb.10: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v5, 0x8000, v3
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
+; VI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB9_12
+; VI-NEXT: .LBB9_11:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: .LBB9_12: ; %Flow53
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB9_18
+; VI-NEXT: ; %bb.13: ; %frem.compute
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v7
+; VI-NEXT: v_frexp_mant_f32_e32 v5, v7
+; VI-NEXT: v_frexp_mant_f32_e32 v7, v6
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v11, v6
+; VI-NEXT: v_ldexp_f32 v6, v7, 1
; VI-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v11, v5
+; VI-NEXT: v_ldexp_f32 v8, v5, 11
; VI-NEXT: v_add_u32_e32 v5, vcc, -1, v11
; VI-NEXT: v_not_b32_e32 v7, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v10
-; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
+; VI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; VI-NEXT: v_rcp_f32_e32 v13, v12
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; VI-NEXT: v_fma_f32 v13, v14, v13, v13
-; VI-NEXT: v_mul_f32_e32 v14, v8, v13
-; VI-NEXT: v_fma_f32 v15, -v12, v14, v8
+; VI-NEXT: v_mul_f32_e32 v14, v9, v13
+; VI-NEXT: v_fma_f32 v15, -v12, v14, v9
; VI-NEXT: v_fma_f32 v14, v15, v13, v14
-; VI-NEXT: v_fma_f32 v8, -v12, v14, v8
+; VI-NEXT: v_fma_f32 v9, -v12, v14, v9
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v8, v8, v13, v14
+; VI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v7
-; VI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB9_12
-; VI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB9_17
+; VI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v7, vcc, v10, v11
; VI-NEXT: v_add_u32_e32 v7, vcc, 11, v7
-; VI-NEXT: .LBB9_10: ; %frem.loop_body
+; VI-NEXT: .LBB9_15: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v10, v9
-; VI-NEXT: v_mul_f32_e32 v9, v10, v8
-; VI-NEXT: v_rndne_f32_e32 v9, v9
-; VI-NEXT: v_fma_f32 v9, -v9, v6, v10
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
-; VI-NEXT: v_add_f32_e32 v11, v9, v6
-; VI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; VI-NEXT: v_mov_b32_e32 v10, v8
+; VI-NEXT: v_mul_f32_e32 v8, v10, v9
+; VI-NEXT: v_rndne_f32_e32 v8, v8
+; VI-NEXT: v_fma_f32 v8, -v8, v6, v10
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; VI-NEXT: v_add_f32_e32 v11, v8, v6
+; VI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
; VI-NEXT: v_add_u32_e32 v7, vcc, -11, v7
-; VI-NEXT: v_ldexp_f32 v9, v9, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v7
-; VI-NEXT: s_cbranch_vccnz .LBB9_10
-; VI-NEXT: s_branch .LBB9_13
-; VI-NEXT: .LBB9_11: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v7, 0x8000, v2
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
-; VI-NEXT: v_cndmask_b32_e32 v5, v2, v7, vcc
-; VI-NEXT: s_branch .LBB9_14
-; VI-NEXT: .LBB9_12:
-; VI-NEXT: v_mov_b32_e32 v10, v9
-; VI-NEXT: .LBB9_13: ; %frem.loop_exit
+; VI-NEXT: v_ldexp_f32 v8, v8, 11
+; VI-NEXT: s_cbranch_vccnz .LBB9_15
+; VI-NEXT: ; %bb.16: ; %Flow
+; VI-NEXT: v_mov_b32_e32 v8, v10
+; VI-NEXT: .LBB9_17: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v7, vcc, -10, v7
-; VI-NEXT: v_ldexp_f32 v7, v10, v7
-; VI-NEXT: v_mul_f32_e32 v8, v7, v8
+; VI-NEXT: v_ldexp_f32 v7, v8, v7
+; VI-NEXT: v_mul_f32_e32 v8, v7, v9
; VI-NEXT: v_rndne_f32_e32 v8, v8
; VI-NEXT: v_fma_f32 v7, -v8, v6, v7
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
@@ -5322,21 +5646,21 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v5, v6, v5
; VI-NEXT: v_cvt_f16_f32_e32 v5, v5
; VI-NEXT: s_movk_i32 s2, 0x7fff
-; VI-NEXT: v_bfi_b32 v5, s2, v5, v2
-; VI-NEXT: .LBB9_14:
+; VI-NEXT: v_bfi_b32 v5, s2, v5, v3
+; VI-NEXT: .LBB9_18: ; %Flow54
; VI-NEXT: s_movk_i32 s4, 0x7c00
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v1
; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |v0|, s4
; VI-NEXT: s_and_b64 vcc, s[2:3], vcc
; VI-NEXT: v_mov_b32_e32 v6, 0x7e00
-; VI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v4
-; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |v2|, s4
+; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |v3|, s4
; VI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; VI-NEXT: v_cndmask_b32_sdwa v2, v6, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_cndmask_b32_sdwa v3, v6, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -5349,20 +5673,34 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: global_load_dword v1, v2, s[2:3]
; GFX9-NEXT: global_load_dword v0, v2, s[6:7] offset:16
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v3, |v1|
+; GFX9-NEXT: v_cvt_f32_f16_e64 v4, |v1|
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v2, |v0|
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
-; GFX9-NEXT: s_cbranch_vccz .LBB9_4
-; GFX9-NEXT: ; %bb.1: ; %frem.compute19
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
-; GFX9-NEXT: v_frexp_mant_f32_e32 v3, v3
-; GFX9-NEXT: v_ldexp_f32 v6, v3, 11
-; GFX9-NEXT: v_frexp_mant_f32_e32 v3, v2
-; GFX9-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX9-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
+; GFX9-NEXT: s_cbranch_vccz .LBB9_2
+; GFX9-NEXT: ; %bb.1: ; %frem.else20
+; GFX9-NEXT: v_and_b32_e32 v2, 0x8000, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB9_3
+; GFX9-NEXT: .LBB9_2:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr2
+; GFX9-NEXT: .LBB9_3: ; %Flow57
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX9-NEXT: ; %bb.4: ; %frem.compute19
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
+; GFX9-NEXT: v_frexp_mant_f32_e32 v2, v4
+; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v3
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
+; GFX9-NEXT: v_ldexp_f32 v3, v4, 1
; GFX9-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
-; GFX9-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
+; GFX9-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; GFX9-NEXT: v_ldexp_f32 v5, v2, 11
; GFX9-NEXT: v_add_u32_e32 v2, -1, v8
; GFX9-NEXT: v_not_b32_e32 v4, v2
; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
@@ -5370,43 +5708,37 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT: v_fma_f32 v10, v11, v10, v10
-; GFX9-NEXT: v_mul_f32_e32 v11, v5, v10
-; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v5
+; GFX9-NEXT: v_mul_f32_e32 v11, v6, v10
+; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v6
; GFX9-NEXT: v_fma_f32 v11, v12, v10, v11
-; GFX9-NEXT: v_fma_f32 v5, -v9, v11, v5
+; GFX9-NEXT: v_fma_f32 v6, -v9, v11, v6
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v5, v5, v10, v11
+; GFX9-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; GFX9-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_5
-; GFX9-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; GFX9-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_8
+; GFX9-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX9-NEXT: v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT: v_add_u32_e32 v4, 11, v4
-; GFX9-NEXT: .LBB9_3: ; %frem.loop_body27
+; GFX9-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v7, v6
-; GFX9-NEXT: v_mul_f32_e32 v6, v7, v5
-; GFX9-NEXT: v_rndne_f32_e32 v6, v6
-; GFX9-NEXT: v_fma_f32 v6, -v6, v3, v7
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; GFX9-NEXT: v_add_f32_e32 v8, v6, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, v7, v6
+; GFX9-NEXT: v_rndne_f32_e32 v5, v5
+; GFX9-NEXT: v_fma_f32 v5, -v5, v3, v7
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; GFX9-NEXT: v_add_f32_e32 v8, v5, v3
; GFX9-NEXT: v_add_u32_e32 v4, -11, v4
-; GFX9-NEXT: v_ldexp_f32 v6, v6, 11
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_3
-; GFX9-NEXT: s_branch .LBB9_6
-; GFX9-NEXT: .LBB9_4: ; %frem.else20
-; GFX9-NEXT: v_and_b32_e32 v4, 0x8000, v1
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v4, vcc
-; GFX9-NEXT: s_branch .LBB9_7
-; GFX9-NEXT: .LBB9_5:
-; GFX9-NEXT: v_mov_b32_e32 v7, v6
-; GFX9-NEXT: .LBB9_6: ; %frem.loop_exit28
+; GFX9-NEXT: v_ldexp_f32 v5, v5, 11
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_6
+; GFX9-NEXT: ; %bb.7: ; %Flow55
+; GFX9-NEXT: v_mov_b32_e32 v5, v7
+; GFX9-NEXT: .LBB9_8: ; %frem.loop_exit28
; GFX9-NEXT: v_add_u32_e32 v4, -10, v4
-; GFX9-NEXT: v_ldexp_f32 v4, v7, v4
-; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v6
; GFX9-NEXT: v_rndne_f32_e32 v5, v5
; GFX9-NEXT: v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -5416,21 +5748,35 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v2, s2, v2, v1
-; GFX9-NEXT: .LBB9_7:
+; GFX9-NEXT: .LBB9_9:
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX9-NEXT: v_cvt_f32_f16_e64 v5, |v3|
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v4, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
+; GFX9-NEXT: v_cvt_f32_f16_e64 v6, |v3|
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v5, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
; GFX9-NEXT: s_cbranch_vccz .LBB9_11
-; GFX9-NEXT: ; %bb.8: ; %frem.compute
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v5
-; GFX9-NEXT: v_frexp_mant_f32_e32 v5, v5
-; GFX9-NEXT: v_ldexp_f32 v8, v5, 11
-; GFX9-NEXT: v_frexp_mant_f32_e32 v5, v4
-; GFX9-NEXT: v_ldexp_f32 v5, v5, 1
+; GFX9-NEXT: ; %bb.10: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v4, 0x8000, v3
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB9_12
+; GFX9-NEXT: .LBB9_11:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr4
+; GFX9-NEXT: .LBB9_12: ; %Flow53
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX9-NEXT: ; %bb.13: ; %frem.compute
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v6
+; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v6
+; GFX9-NEXT: v_frexp_mant_f32_e32 v6, v5
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v5
+; GFX9-NEXT: v_ldexp_f32 v5, v6, 1
; GFX9-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
-; GFX9-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v4
+; GFX9-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; GFX9-NEXT: v_ldexp_f32 v7, v4, 11
; GFX9-NEXT: v_add_u32_e32 v4, -1, v10
; GFX9-NEXT: v_not_b32_e32 v6, v4
; GFX9-NEXT: v_add_u32_e32 v6, v6, v9
@@ -5438,43 +5784,37 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; GFX9-NEXT: v_fma_f32 v12, v13, v12, v12
-; GFX9-NEXT: v_mul_f32_e32 v13, v7, v12
-; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v7
+; GFX9-NEXT: v_mul_f32_e32 v13, v8, v12
+; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v8
; GFX9-NEXT: v_fma_f32 v13, v14, v12, v13
-; GFX9-NEXT: v_fma_f32 v7, -v11, v13, v7
+; GFX9-NEXT: v_fma_f32 v8, -v11, v13, v8
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v7, v7, v12, v13
+; GFX9-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
-; GFX9-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_12
-; GFX9-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX9-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT: v_add_u32_e32 v6, 11, v6
-; GFX9-NEXT: .LBB9_10: ; %frem.loop_body
+; GFX9-NEXT: .LBB9_15: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v9, v8
-; GFX9-NEXT: v_mul_f32_e32 v8, v9, v7
-; GFX9-NEXT: v_rndne_f32_e32 v8, v8
-; GFX9-NEXT: v_fma_f32 v8, -v8, v5, v9
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; GFX9-NEXT: v_add_f32_e32 v10, v8, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX9-NEXT: v_mov_b32_e32 v9, v7
+; GFX9-NEXT: v_mul_f32_e32 v7, v9, v8
+; GFX9-NEXT: v_rndne_f32_e32 v7, v7
+; GFX9-NEXT: v_fma_f32 v7, -v7, v5, v9
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
+; GFX9-NEXT: v_add_f32_e32 v10, v7, v5
; GFX9-NEXT: v_add_u32_e32 v6, -11, v6
-; GFX9-NEXT: v_ldexp_f32 v8, v8, 11
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_10
-; GFX9-NEXT: s_branch .LBB9_13
-; GFX9-NEXT: .LBB9_11: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v6, 0x8000, v3
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v6, vcc
-; GFX9-NEXT: s_branch .LBB9_14
-; GFX9-NEXT: .LBB9_12:
-; GFX9-NEXT: v_mov_b32_e32 v9, v8
-; GFX9-NEXT: .LBB9_13: ; %frem.loop_exit
+; GFX9-NEXT: v_ldexp_f32 v7, v7, 11
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX9-NEXT: ; %bb.16: ; %Flow
+; GFX9-NEXT: v_mov_b32_e32 v7, v9
+; GFX9-NEXT: .LBB9_17: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v6, -10, v6
-; GFX9-NEXT: v_ldexp_f32 v6, v9, v6
-; GFX9-NEXT: v_mul_f32_e32 v7, v6, v7
+; GFX9-NEXT: v_ldexp_f32 v6, v7, v6
+; GFX9-NEXT: v_mul_f32_e32 v7, v6, v8
; GFX9-NEXT: v_rndne_f32_e32 v7, v7
; GFX9-NEXT: v_fma_f32 v6, -v7, v5, v6
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -5484,7 +5824,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v3
-; GFX9-NEXT: .LBB9_14:
+; GFX9-NEXT: .LBB9_18: ; %Flow54
; GFX9-NEXT: s_movk_i32 s4, 0x7c00
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v0
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v1|, s4
@@ -5511,24 +5851,38 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: global_load_dword v1, v2, s[2:3]
; GFX10-NEXT: global_load_dword v0, v2, s[6:7] offset:16
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v3, |v1|
+; GFX10-NEXT: v_cvt_f32_f16_e64 v4, |v1|
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v2, |v0|
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX10-NEXT: s_cbranch_vccz .LBB9_5
-; GFX10-NEXT: ; %bb.1: ; %frem.compute19
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v3
-; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v3
+; GFX10-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v3
+; GFX10-NEXT: s_cbranch_vccz .LBB9_2
+; GFX10-NEXT: ; %bb.1: ; %frem.else20
+; GFX10-NEXT: v_and_b32_e32 v2, 0x8000, v1
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc_lo
+; GFX10-NEXT: s_branch .LBB9_3
+; GFX10-NEXT: .LBB9_2:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr2
+; GFX10-NEXT: .LBB9_3: ; %Flow57
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX10-NEXT: ; %bb.4: ; %frem.compute19
+; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v4
+; GFX10-NEXT: v_frexp_mant_f32_e32 v6, v3
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
+; GFX10-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
+; GFX10-NEXT: v_ldexp_f32 v3, v6, 1
; GFX10-NEXT: v_readfirstlane_b32 s2, v5
-; GFX10-NEXT: v_ldexp_f32 v4, v3, 11
-; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v2
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX10-NEXT: v_ldexp_f32 v3, v3, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v2
-; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX10-NEXT: v_div_scale_f32 v7, s4, v3, v3, 1.0
-; GFX10-NEXT: v_not_b32_e32 v6, v2
+; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX10-NEXT: v_rcp_f32_e32 v8, v7
+; GFX10-NEXT: v_not_b32_e32 v6, v2
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -5542,11 +5896,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX10-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB9_6
-; GFX10-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB9_8
+; GFX10-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB9_3: ; %frem.loop_body27
+; GFX10-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -5558,20 +5912,13 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v6, v4, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX10-NEXT: ; %bb.4:
+; GFX10-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX10-NEXT: ; %bb.7: ; %Flow55
; GFX10-NEXT: v_mov_b32_e32 v6, s2
-; GFX10-NEXT: s_branch .LBB9_7
-; GFX10-NEXT: .LBB9_5: ; %frem.else20
-; GFX10-NEXT: v_and_b32_e32 v4, 0x8000, v1
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v4, vcc_lo
-; GFX10-NEXT: s_branch .LBB9_8
-; GFX10-NEXT: .LBB9_6:
-; GFX10-NEXT: v_mov_b32_e32 v7, v4
-; GFX10-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX10-NEXT: v_add_nc_u32_e32 v4, -10, v6
-; GFX10-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX10-NEXT: v_mov_b32_e32 v4, v7
+; GFX10-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX10-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX10-NEXT: v_rndne_f32_e32 v5, v5
; GFX10-NEXT: v_fma_f32 v4, -v5, v3, v4
@@ -5581,25 +5928,39 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v2, v3, v2
; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT: v_bfi_b32 v2, 0x7fff, v2, v1
-; GFX10-NEXT: .LBB9_8:
+; GFX10-NEXT: .LBB9_9:
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v4, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e64 v5, |v3|
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX10-NEXT: s_cbranch_vccz .LBB9_13
-; GFX10-NEXT: ; %bb.9: ; %frem.compute
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v5
-; GFX10-NEXT: v_frexp_mant_f32_e32 v5, v5
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v6, |v3|
+; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v6, v5
+; GFX10-NEXT: s_cbranch_vccz .LBB9_11
+; GFX10-NEXT: ; %bb.10: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v4, 0x8000, v3
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc_lo
+; GFX10-NEXT: s_branch .LBB9_12
+; GFX10-NEXT: .LBB9_11:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr4
+; GFX10-NEXT: .LBB9_12: ; %Flow53
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX10-NEXT: ; %bb.13: ; %frem.compute
+; GFX10-NEXT: v_frexp_mant_f32_e32 v4, v6
+; GFX10-NEXT: v_frexp_mant_f32_e32 v8, v5
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
+; GFX10-NEXT: v_ldexp_f32 v6, v4, 11
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v4, v5
+; GFX10-NEXT: v_ldexp_f32 v5, v8, 1
; GFX10-NEXT: v_readfirstlane_b32 s2, v7
-; GFX10-NEXT: v_ldexp_f32 v6, v5, 11
-; GFX10-NEXT: v_frexp_mant_f32_e32 v5, v4
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
-; GFX10-NEXT: v_ldexp_f32 v5, v5, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v4
-; GFX10-NEXT: v_add_nc_u32_e32 v4, -1, v4
; GFX10-NEXT: v_div_scale_f32 v9, s4, v5, v5, 1.0
-; GFX10-NEXT: v_not_b32_e32 v8, v4
+; GFX10-NEXT: v_add_nc_u32_e32 v4, -1, v4
; GFX10-NEXT: v_rcp_f32_e32 v10, v9
+; GFX10-NEXT: v_not_b32_e32 v8, v4
; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX10-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -5613,11 +5974,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX10-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB9_14
-; GFX10-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX10-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB9_11: ; %frem.loop_body
+; GFX10-NEXT: .LBB9_15: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -5629,20 +5990,13 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v8, v6, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v6, v6, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB9_11
-; GFX10-NEXT: ; %bb.12:
+; GFX10-NEXT: s_cbranch_scc1 .LBB9_15
+; GFX10-NEXT: ; %bb.16: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v8, s2
-; GFX10-NEXT: s_branch .LBB9_15
-; GFX10-NEXT: .LBB9_13: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v6, 0x8000, v3
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v6, vcc_lo
-; GFX10-NEXT: s_branch .LBB9_16
-; GFX10-NEXT: .LBB9_14:
-; GFX10-NEXT: v_mov_b32_e32 v9, v6
-; GFX10-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v6, -10, v8
-; GFX10-NEXT: v_ldexp_f32 v6, v9, v6
+; GFX10-NEXT: v_mov_b32_e32 v6, v9
+; GFX10-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX10-NEXT: v_add_nc_u32_e32 v8, -10, v8
+; GFX10-NEXT: v_ldexp_f32 v6, v6, v8
; GFX10-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX10-NEXT: v_rndne_f32_e32 v7, v7
; GFX10-NEXT: v_fma_f32 v6, -v7, v5, v6
@@ -5652,7 +6006,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v4, v5, v4
; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX10-NEXT: v_bfi_b32 v4, 0x7fff, v4, v3
-; GFX10-NEXT: .LBB9_16:
+; GFX10-NEXT: .LBB9_18: ; %Flow54
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v1|
; GFX10-NEXT: v_cmp_nle_f16_e64 s3, 0x7c00, |v3|
@@ -5678,27 +6032,44 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: global_load_b32 v0, v1, s[2:3]
; GFX11-TRUE16-NEXT: global_load_b32 v1, v1, s[4:5] offset:16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v4, |v0.l|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, |v1.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_5
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.compute19
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v3
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v3
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else20
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB9_3
+; GFX11-TRUE16-NEXT: .LBB9_2:
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: .LBB9_3: ; %Flow57
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v4
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v3
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v2
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v3
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v5, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v4
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v5, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v4, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX11-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
@@ -5717,12 +6088,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_4
-; GFX11-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB9_3: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -5737,39 +6108,50 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX11-TRUE16-NEXT: .LBB9_4: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX11-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX11-TRUE16-NEXT: s_branch .LBB9_6
-; GFX11-TRUE16-NEXT: .LBB9_5: ; %frem.else20
-; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v2, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: .LBB9_6:
+; GFX11-TRUE16-NEXT: .LBB9_8:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v5, |v3.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, |v3.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, |v4.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v6
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_11
-; GFX11-TRUE16-NEXT: ; %bb.7: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v6
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v6
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_10
+; GFX11-TRUE16-NEXT: ; %bb.9: ; %frem.else
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB9_11
+; GFX11-TRUE16-NEXT: .LBB9_10:
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
+; GFX11-TRUE16-NEXT: .LBB9_11: ; %Flow53
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
+; GFX11-TRUE16-NEXT: ; %bb.12: ; %frem.compute
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v7
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v6
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, v6
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v5
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v8
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, -1, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v8, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v7
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v8, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v7, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, null, v6, v6, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v7, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v10, v9
; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v6, 1.0
@@ -5788,12 +6170,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v7, v7, v6, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_10
-; GFX11-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB9_9: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v5, v7
@@ -5808,16 +6190,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
-; GFX11-TRUE16-NEXT: .LBB9_10: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
+; GFX11-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-TRUE16-NEXT: s_branch .LBB9_12
-; GFX11-TRUE16-NEXT: .LBB9_11: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: .LBB9_12:
+; GFX11-TRUE16-NEXT: .LBB9_16: ; %Flow54
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
@@ -5842,29 +6218,45 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: global_load_b32 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: global_load_b32 v1, v1, s[4:5] offset:16
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v4, |v0|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v2, |v1|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, |v1|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB9_5
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.compute19
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v3
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v3
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB9_2
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.else20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB9_3
+; GFX11-FAKE16-NEXT: .LBB9_2:
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT: .LBB9_3: ; %Flow57
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, v4
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v6, v3
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v6, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v3, 11
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v2
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX11-FAKE16-NEXT: v_not_b32_e32 v6, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_not_b32_e32 v6, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-FAKE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -5883,12 +6275,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_6
-; GFX11-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_8
+; GFX11-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB9_3: ; %frem.loop_body27
+; GFX11-FAKE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -5904,22 +6296,14 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX11-FAKE16-NEXT: ; %bb.4:
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX11-FAKE16-NEXT: ; %bb.7: ; %Flow55
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-FAKE16-NEXT: s_branch .LBB9_7
-; GFX11-FAKE16-NEXT: .LBB9_5: ; %frem.else20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x8000, v0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB9_8
-; GFX11-FAKE16-NEXT: .LBB9_6:
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v4
-; GFX11-FAKE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-FAKE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -5933,32 +6317,48 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX11-FAKE16-NEXT: .LBB9_8:
+; GFX11-FAKE16-NEXT: .LBB9_9:
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, |v3|
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v5, |v4|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v7, |v3|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, |v4|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v5
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB9_13
-; GFX11-FAKE16-NEXT: ; %bb.9: ; %frem.compute
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v6
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v6, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v6
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB9_11
+; GFX11-FAKE16-NEXT: ; %bb.10: ; %frem.else
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x8000, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB9_12
+; GFX11-FAKE16-NEXT: .LBB9_11:
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
+; GFX11-FAKE16-NEXT: .LBB9_12: ; %Flow53
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX11-FAKE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v5, v7
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v9, v6
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v5, 11
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v9, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v8
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v6, 11
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v6, v5
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v6, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_scale_f32 v10, null, v6, v6, 1.0
-; GFX11-FAKE16-NEXT: v_not_b32_e32 v9, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v11, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_not_b32_e32 v9, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v8
; GFX11-FAKE16-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -5977,12 +6377,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_14
-; GFX11-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX11-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB9_11: ; %frem.loop_body
+; GFX11-FAKE16-NEXT: .LBB9_15: ; %frem.loop_body
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, v7
@@ -5998,22 +6398,14 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
-; GFX11-FAKE16-NEXT: ; %bb.12:
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_15
+; GFX11-FAKE16-NEXT: ; %bb.16: ; %Flow
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, s2
-; GFX11-FAKE16-NEXT: s_branch .LBB9_15
-; GFX11-FAKE16-NEXT: .LBB9_13: ; %frem.else
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0x8000, v3
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB9_16
-; GFX11-FAKE16-NEXT: .LBB9_14:
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, v7
-; GFX11-FAKE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, -10, v9
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v10, v7
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v10
+; GFX11-FAKE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, -10, v9
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v7, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v8, v7, v8
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v8, v8
@@ -6027,7 +6419,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX11-FAKE16-NEXT: v_bfi_b32 v5, 0x7fff, v5, v3
-; GFX11-FAKE16-NEXT: .LBB9_16:
+; GFX11-FAKE16-NEXT: .LBB9_18: ; %Flow54
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@@ -6058,22 +6450,39 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
; GFX1150-TRUE16-NEXT: s_and_b32 s2, s4, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s6, s3, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s5, s2
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1150-TRUE16-NEXT: s_and_b32 s5, s3, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s2
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s5, s5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s5, s6
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_5
-; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.compute19
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s5
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s5
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s6, s5
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_2
+; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.else20
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s6, s5
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s4
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s7
+; GFX1150-TRUE16-NEXT: s_mov_b32 s7, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB9_3
+; GFX1150-TRUE16-NEXT: .LBB9_2:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s7, -1
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1150-TRUE16-NEXT: .LBB9_3: ; %Flow57
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s7, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
+; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v2
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6097,12 +6506,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_4
-; GFX1150-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s5, s5, s6
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s5, s6, s5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s5, s5, 11
-; GFX1150-TRUE16-NEXT: .LBB9_3: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -6118,36 +6527,46 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX1150-TRUE16-NEXT: .LBB9_4: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX1150-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: s_branch .LBB9_6
-; GFX1150-TRUE16-NEXT: .LBB9_5: ; %frem.else20
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s5, s6
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s4
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s5, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s5
-; GFX1150-TRUE16-NEXT: .LBB9_6:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
+; GFX1150-TRUE16-NEXT: .LBB9_8:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
+; GFX1150-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s6, s5, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s7, s4
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s8, s7
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_11
-; GFX1150-TRUE16-NEXT: ; %bb.7: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s7
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s7
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
+; GFX1150-TRUE16-NEXT: ; %bb.9: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
+; GFX1150-TRUE16-NEXT: s_mov_b32 s8, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB9_11
+; GFX1150-TRUE16-NEXT: .LBB9_10:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s8, -1
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX1150-TRUE16-NEXT: .LBB9_11: ; %Flow53
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s8, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
+; GFX1150-TRUE16-NEXT: ; %bb.12: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s7, v4
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6171,12 +6590,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_10
-; GFX1150-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s6, s7
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s7, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-TRUE16-NEXT: .LBB9_9: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -6192,17 +6611,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
-; GFX1150-TRUE16-NEXT: .LBB9_10: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
+; GFX1150-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: s_branch .LBB9_12
-; GFX1150-TRUE16-NEXT: .LBB9_11: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s8, s7
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s6
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s7
-; GFX1150-TRUE16-NEXT: .LBB9_12:
+; GFX1150-TRUE16-NEXT: .LBB9_16: ; %Flow54
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -6236,25 +6648,43 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s3, v0
; GFX1150-FAKE16-NEXT: s_and_b32 s2, s4, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s6, s3, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s5, s2
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1150-FAKE16-NEXT: s_and_b32 s5, s3, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s6, s2
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s5, s5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s5, s6
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_5
-; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.compute19
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s5
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
+; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s6, s5
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_2
+; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.else20
+; GFX1150-FAKE16-NEXT: s_and_b32 s7, 0x8000, s4
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s6, s5
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v0, s7
+; GFX1150-FAKE16-NEXT: s_mov_b32 s7, 0
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB9_3
+; GFX1150-FAKE16-NEXT: .LBB9_2:
+; GFX1150-FAKE16-NEXT: s_mov_b32 s7, -1
+; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1150-FAKE16-NEXT: .LBB9_3: ; %Flow57
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1150-FAKE16-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s7, 1
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s5
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v1, v1, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s5, v0
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6276,12 +6706,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_6
-; GFX1150-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s5, s5, s6
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_8
+; GFX1150-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s5, s6, s5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s5, s5, 11
-; GFX1150-FAKE16-NEXT: .LBB9_3: ; %frem.loop_body27
+; GFX1150-FAKE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -6299,24 +6729,14 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX1150-FAKE16-NEXT: ; %bb.4:
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX1150-FAKE16-NEXT: ; %bb.7: ; %Flow55
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, s5
-; GFX1150-FAKE16-NEXT: s_branch .LBB9_7
-; GFX1150-FAKE16-NEXT: .LBB9_5: ; %frem.else20
-; GFX1150-FAKE16-NEXT: s_and_b32 s7, 0x8000, s4
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s5, s6
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v0, s7
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB9_8
-; GFX1150-FAKE16-NEXT: .LBB9_6:
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX1150-FAKE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v2, -10, v4
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v5, v2
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-FAKE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v3, v3
@@ -6332,29 +6752,47 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s4
-; GFX1150-FAKE16-NEXT: .LBB9_8:
+; GFX1150-FAKE16-NEXT: .LBB9_9:
; GFX1150-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1150-FAKE16-NEXT: s_lshr_b32 s5, s3, 16
; GFX1150-FAKE16-NEXT: s_and_b32 s4, s6, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s8, s5, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s7, s4
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1150-FAKE16-NEXT: s_and_b32 s7, s5, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s8, s4
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s7, s7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s7, s8
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_13
-; GFX1150-FAKE16-NEXT: ; %bb.9: ; %frem.compute
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s8
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s7
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s7
+; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s8, s7
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_11
+; GFX1150-FAKE16-NEXT: ; %bb.10: ; %frem.else
+; GFX1150-FAKE16-NEXT: s_and_b32 s9, 0x8000, s6
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s8, s7
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v1, s9
+; GFX1150-FAKE16-NEXT: s_mov_b32 s9, 0
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB9_12
+; GFX1150-FAKE16-NEXT: .LBB9_11:
+; GFX1150-FAKE16-NEXT: s_mov_b32 s9, -1
+; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr1
+; GFX1150-FAKE16-NEXT: .LBB9_12: ; %Flow53
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1150-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s9, 1
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX1150-FAKE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s7
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s8
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s7, v4
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s8, v4
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s7, v1
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6376,12 +6814,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_14
-; GFX1150-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s7, s7, s8
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX1150-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s7, s8, s7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s7, s7, 11
-; GFX1150-FAKE16-NEXT: .LBB9_11: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT: .LBB9_15: ; %frem.loop_body
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -6399,24 +6837,14 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
-; GFX1150-FAKE16-NEXT: ; %bb.12:
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_15
+; GFX1150-FAKE16-NEXT: ; %bb.16: ; %Flow
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, s7
-; GFX1150-FAKE16-NEXT: s_branch .LBB9_15
-; GFX1150-FAKE16-NEXT: .LBB9_13: ; %frem.else
-; GFX1150-FAKE16-NEXT: s_and_b32 s9, 0x8000, s6
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s7, s8
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v1, s9
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB9_16
-; GFX1150-FAKE16-NEXT: .LBB9_14:
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX1150-FAKE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v3, -10, v5
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v6, v3
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-FAKE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v4, v4
@@ -6432,7 +6860,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s6
-; GFX1150-FAKE16-NEXT: .LBB9_16:
+; GFX1150-FAKE16-NEXT: .LBB9_18: ; %Flow54
; GFX1150-FAKE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -6468,22 +6896,40 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
; GFX1200-TRUE16-NEXT: s_and_b32 s2, s4, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s6, s3, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s5, s2
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1200-TRUE16-NEXT: s_and_b32 s5, s3, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s2
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s5, s5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s5, s6
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_5
-; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.compute19
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s5
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s5
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s6, s5
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_2
+; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.else20
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s6, s5
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s4
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s7
+; GFX1200-TRUE16-NEXT: s_mov_b32 s7, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB9_3
+; GFX1200-TRUE16-NEXT: .LBB9_2:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s7, -1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-TRUE16-NEXT: .LBB9_3: ; %Flow57
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s7, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
+; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v2
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6507,12 +6953,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_4
-; GFX1200-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s5, s5, s6
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s5, s6, s5
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s5, s5, 11
-; GFX1200-TRUE16-NEXT: .LBB9_3: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -6531,40 +6977,51 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX1200-TRUE16-NEXT: .LBB9_4: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX1200-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: s_branch .LBB9_6
-; GFX1200-TRUE16-NEXT: .LBB9_5: ; %frem.else20
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s5, s6
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s4
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s5, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s5
-; GFX1200-TRUE16-NEXT: .LBB9_6:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
+; GFX1200-TRUE16-NEXT: .LBB9_8:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
+; GFX1200-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s6, s5, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s8, s7
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_11
-; GFX1200-TRUE16-NEXT: ; %bb.7: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s7
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s7
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
+; GFX1200-TRUE16-NEXT: ; %bb.9: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
+; GFX1200-TRUE16-NEXT: s_mov_b32 s8, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB9_11
+; GFX1200-TRUE16-NEXT: .LBB9_10:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s8, -1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX1200-TRUE16-NEXT: .LBB9_11: ; %Flow53
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s8, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
+; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s7
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s7, v4
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6589,12 +7046,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_10
-; GFX1200-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s6, s7
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s7, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-TRUE16-NEXT: .LBB9_9: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -6613,18 +7070,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
-; GFX1200-TRUE16-NEXT: .LBB9_10: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
+; GFX1200-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: s_branch .LBB9_12
-; GFX1200-TRUE16-NEXT: .LBB9_11: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s8, s7
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s6
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s7
-; GFX1200-TRUE16-NEXT: .LBB9_12:
+; GFX1200-TRUE16-NEXT: .LBB9_16: ; %Flow54
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -6659,25 +7108,44 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s3, v0
; GFX1200-FAKE16-NEXT: s_and_b32 s2, s4, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s6, s3, 0x7fff
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s5, s2
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1200-FAKE16-NEXT: s_and_b32 s5, s3, 0x7fff
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s6, s2
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s5, s5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s5, s6
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_5
-; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.compute19
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s5
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
+; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s6, s5
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_2
+; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.else20
+; GFX1200-FAKE16-NEXT: s_and_b32 s7, 0x8000, s4
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s6, s5
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, s7
+; GFX1200-FAKE16-NEXT: s_mov_b32 s7, 0
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB9_3
+; GFX1200-FAKE16-NEXT: .LBB9_2:
+; GFX1200-FAKE16-NEXT: s_mov_b32 s7, -1
+; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-FAKE16-NEXT: .LBB9_3: ; %Flow57
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1200-FAKE16-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s7, 1
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s5
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v1, v1, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s5, v0
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6695,16 +7163,17 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v7, v8, v6
; GFX1200-FAKE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_6
-; GFX1200-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s5, s5, s6
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_8
+; GFX1200-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s5, s6, s5
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s5, s5, 11
-; GFX1200-FAKE16-NEXT: .LBB9_3: ; %frem.loop_body27
+; GFX1200-FAKE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -6724,24 +7193,14 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX1200-FAKE16-NEXT: ; %bb.4:
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX1200-FAKE16-NEXT: ; %bb.7: ; %Flow55
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, s5
-; GFX1200-FAKE16-NEXT: s_branch .LBB9_7
-; GFX1200-FAKE16-NEXT: .LBB9_5: ; %frem.else20
-; GFX1200-FAKE16-NEXT: s_and_b32 s7, 0x8000, s4
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s5, s6
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, s7
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB9_8
-; GFX1200-FAKE16-NEXT: .LBB9_6:
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX1200-FAKE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v2, -10, v4
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v5, v2
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-FAKE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v3, v3
@@ -6758,32 +7217,52 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s4
-; GFX1200-FAKE16-NEXT: .LBB9_8:
+; GFX1200-FAKE16-NEXT: .LBB9_9:
; GFX1200-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-FAKE16-NEXT: s_lshr_b32 s5, s3, 16
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 s4, s6, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s8, s5, 0x7fff
+; GFX1200-FAKE16-NEXT: s_and_b32 s7, s5, 0x7fff
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s7, s4
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s8, s4
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s7, s7
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s7, s8
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_13
-; GFX1200-FAKE16-NEXT: ; %bb.9: ; %frem.compute
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s8
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s7
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s7
+; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s8, s7
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_11
+; GFX1200-FAKE16-NEXT: ; %bb.10: ; %frem.else
+; GFX1200-FAKE16-NEXT: s_and_b32 s9, 0x8000, s6
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s8, s7
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, s9
+; GFX1200-FAKE16-NEXT: s_mov_b32 s9, 0
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB9_12
+; GFX1200-FAKE16-NEXT: .LBB9_11:
+; GFX1200-FAKE16-NEXT: s_mov_b32 s9, -1
+; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr1
+; GFX1200-FAKE16-NEXT: .LBB9_12: ; %Flow53
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1200-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s9, 1
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX1200-FAKE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s7
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s8
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s7
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s7, v4
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s8, v4
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s7, v1
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6806,12 +7285,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_14
-; GFX1200-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s7, s7, s8
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX1200-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s7, s8, s7
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s7, s7, 11
-; GFX1200-FAKE16-NEXT: .LBB9_11: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT: .LBB9_15: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -6831,25 +7310,14 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
-; GFX1200-FAKE16-NEXT: ; %bb.12:
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_15
+; GFX1200-FAKE16-NEXT: ; %bb.16: ; %Flow
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, s7
-; GFX1200-FAKE16-NEXT: s_branch .LBB9_15
-; GFX1200-FAKE16-NEXT: .LBB9_13: ; %frem.else
-; GFX1200-FAKE16-NEXT: s_and_b32 s9, 0x8000, s6
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s7, s8
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, s9
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB9_16
-; GFX1200-FAKE16-NEXT: .LBB9_14:
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX1200-FAKE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v3, -10, v5
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v6, v3
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1200-FAKE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v4, v4
@@ -6866,7 +7334,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s6
-; GFX1200-FAKE16-NEXT: .LBB9_16:
+; GFX1200-FAKE16-NEXT: .LBB9_18: ; %Flow54
; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -6912,219 +7380,255 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s2, v1
-; SI-NEXT: v_readfirstlane_b32 s0, v0
+; SI-NEXT: v_readfirstlane_b32 s3, v0
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 offset:32
-; SI-NEXT: v_cvt_f32_f16_e64 v4, |s0|
-; SI-NEXT: s_lshr_b32 s3, s0, 16
+; SI-NEXT: v_cvt_f32_f16_e64 v3, |s3|
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3
-; SI-NEXT: s_cbranch_vccz .LBB10_4
-; SI-NEXT: ; %bb.1: ; %frem.compute85
-; SI-NEXT: s_mov_b32 s1, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s1
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s4, v5
-; SI-NEXT: v_frexp_mant_f32_e32 v5, v4
-; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s1
-; SI-NEXT: v_frexp_mant_f32_e32 v5, v3
-; SI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
-; SI-NEXT: v_readfirstlane_b32 s1, v3
-; SI-NEXT: v_ldexp_f32_e64 v3, v5, 1
-; SI-NEXT: v_div_scale_f32 v6, s[10:11], v3, v3, 1.0
-; SI-NEXT: v_rcp_f32_e32 v7, v6
-; SI-NEXT: s_cselect_b32 s5, s4, 0
-; SI-NEXT: v_ldexp_f32_e64 v4, v4, 11
-; SI-NEXT: s_and_b64 s[6:7], vcc, exec
-; SI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
+; SI-NEXT: v_cvt_f32_f16_e64 v2, |v0|
+; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2
+; SI-NEXT: s_cbranch_vccz .LBB10_2
+; SI-NEXT: ; %bb.1: ; %frem.else86
+; SI-NEXT: s_and_b32 s4, s3, 0xffff8000
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: s_cselect_b32 s4, s4, s3
+; SI-NEXT: s_mov_b64 s[0:1], 0
+; SI-NEXT: s_branch .LBB10_3
+; SI-NEXT: .LBB10_2:
+; SI-NEXT: s_mov_b64 s[0:1], -1
+; SI-NEXT: ; implicit-def: $sgpr4
+; SI-NEXT: .LBB10_3: ; %Flow135
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s0, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s0, 1
+; SI-NEXT: s_cbranch_scc1 .LBB10_9
+; SI-NEXT: ; %bb.4: ; %frem.compute85
+; SI-NEXT: s_mov_b32 s5, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s5
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v3
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v4
+; SI-NEXT: v_frexp_mant_f32_e32 v4, v3
+; SI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s5
+; SI-NEXT: v_frexp_mant_f32_e32 v4, v2
+; SI-NEXT: s_cselect_b32 s4, s0, 0
+; SI-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v2
+; SI-NEXT: v_ldexp_f32_e64 v2, v4, 1
+; SI-NEXT: v_div_scale_f32 v5, s[6:7], v2, v2, 1.0
+; SI-NEXT: v_rcp_f32_e32 v6, v5
+; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
+; SI-NEXT: v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT: v_fma_f32 v8, -v6, v7, 1.0
-; SI-NEXT: v_fma_f32 v7, v8, v7, v7
-; SI-NEXT: v_mul_f32_e32 v8, v5, v7
-; SI-NEXT: s_cselect_b32 s6, s1, 0
-; SI-NEXT: v_fma_f32 v9, -v6, v8, v5
-; SI-NEXT: s_add_i32 s1, s6, -1
-; SI-NEXT: v_fma_f32 v8, v9, v7, v8
-; SI-NEXT: s_not_b32 s4, s1
-; SI-NEXT: v_fma_f32 v5, -v6, v8, v5
+; SI-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; SI-NEXT: v_fma_f32 v6, v7, v6, v6
+; SI-NEXT: v_mul_f32_e32 v7, v4, v6
+; SI-NEXT: s_cselect_b32 s5, s0, 0
+; SI-NEXT: v_fma_f32 v8, -v5, v7, v4
+; SI-NEXT: s_add_i32 s0, s5, -1
+; SI-NEXT: v_fma_f32 v7, v8, v6, v7
+; SI-NEXT: s_not_b32 s1, s0
+; SI-NEXT: v_fma_f32 v4, -v5, v7, v4
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT: s_add_i32 s4, s4, s5
-; SI-NEXT: v_div_fmas_f32 v5, v5, v7, v8
-; SI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; SI-NEXT: s_cmp_lt_i32 s4, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_5
-; SI-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
-; SI-NEXT: s_sub_i32 s4, s5, s6
-; SI-NEXT: s_add_i32 s4, s4, 11
-; SI-NEXT: .LBB10_3: ; %frem.loop_body93
+; SI-NEXT: s_add_i32 s1, s1, s4
+; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
+; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
+; SI-NEXT: s_cmp_lt_i32 s1, 12
+; SI-NEXT: s_cbranch_scc1 .LBB10_8
+; SI-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; SI-NEXT: s_sub_i32 s1, s4, s5
+; SI-NEXT: s_add_i32 s1, s1, 11
+; SI-NEXT: .LBB10_6: ; %frem.loop_body93
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v6, v4
-; SI-NEXT: v_mul_f32_e32 v4, v6, v5
-; SI-NEXT: v_rndne_f32_e32 v4, v4
-; SI-NEXT: v_fma_f32 v4, -v4, v3, v6
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; SI-NEXT: v_add_f32_e32 v7, v4, v3
-; SI-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; SI-NEXT: s_add_i32 s4, s4, -11
-; SI-NEXT: v_ldexp_f32_e64 v4, v4, 11
-; SI-NEXT: s_cmp_gt_i32 s4, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_3
-; SI-NEXT: s_branch .LBB10_6
-; SI-NEXT: .LBB10_4: ; %frem.else86
-; SI-NEXT: s_and_b32 s1, s0, 0xffff8000
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: s_cselect_b32 s1, s1, s0
-; SI-NEXT: v_mov_b32_e32 v3, s1
-; SI-NEXT: s_branch .LBB10_7
-; SI-NEXT: .LBB10_5:
-; SI-NEXT: v_mov_b32_e32 v6, v4
-; SI-NEXT: .LBB10_6: ; %frem.loop_exit94
-; SI-NEXT: s_add_i32 s4, s4, -10
-; SI-NEXT: v_ldexp_f32_e64 v4, v6, s4
-; SI-NEXT: v_mul_f32_e32 v5, v4, v5
-; SI-NEXT: v_rndne_f32_e32 v5, v5
-; SI-NEXT: v_fma_f32 v4, -v5, v3, v4
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; SI-NEXT: v_add_f32_e32 v3, v4, v3
-; SI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; SI-NEXT: v_ldexp_f32_e64 v3, v3, s1
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NEXT: s_and_b32 s1, s0, 0xffff8000
-; SI-NEXT: v_and_b32_e32 v3, 0x7fff, v3
-; SI-NEXT: v_or_b32_e32 v3, s1, v3
-; SI-NEXT: .LBB10_7:
-; SI-NEXT: v_cvt_f32_f16_e64 v5, |s3|
-; SI-NEXT: v_cvt_f32_f16_e64 v4, |v2|
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
-; SI-NEXT: s_cbranch_vccz .LBB10_11
-; SI-NEXT: ; %bb.8: ; %frem.compute52
-; SI-NEXT: s_mov_b32 s1, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s1
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v6, v5
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s4, v6
-; SI-NEXT: v_frexp_mant_f32_e32 v6, v5
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s1
-; SI-NEXT: v_frexp_mant_f32_e32 v6, v4
-; SI-NEXT: v_cndmask_b32_e32 v6, v4, v6, vcc
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
-; SI-NEXT: v_readfirstlane_b32 s1, v4
-; SI-NEXT: v_ldexp_f32_e64 v4, v6, 1
-; SI-NEXT: v_div_scale_f32 v7, s[10:11], v4, v4, 1.0
-; SI-NEXT: v_rcp_f32_e32 v8, v7
-; SI-NEXT: s_cselect_b32 s5, s4, 0
-; SI-NEXT: v_ldexp_f32_e64 v5, v5, 11
-; SI-NEXT: s_and_b64 s[6:7], vcc, exec
-; SI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
+; SI-NEXT: v_mov_b32_e32 v5, v3
+; SI-NEXT: v_mul_f32_e32 v3, v5, v4
+; SI-NEXT: v_rndne_f32_e32 v3, v3
+; SI-NEXT: v_fma_f32 v3, -v3, v2, v5
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
+; SI-NEXT: v_add_f32_e32 v6, v3, v2
+; SI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; SI-NEXT: s_add_i32 s1, s1, -11
+; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
+; SI-NEXT: s_cmp_gt_i32 s1, 11
+; SI-NEXT: s_cbranch_scc1 .LBB10_6
+; SI-NEXT: ; %bb.7: ; %Flow133
+; SI-NEXT: v_mov_b32_e32 v3, v5
+; SI-NEXT: .LBB10_8: ; %frem.loop_exit94
+; SI-NEXT: s_add_i32 s1, s1, -10
+; SI-NEXT: v_ldexp_f32_e64 v3, v3, s1
+; SI-NEXT: v_mul_f32_e32 v4, v3, v4
+; SI-NEXT: v_rndne_f32_e32 v4, v4
+; SI-NEXT: v_fma_f32 v3, -v4, v2, v3
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
+; SI-NEXT: v_add_f32_e32 v2, v3, v2
+; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; SI-NEXT: v_ldexp_f32_e64 v2, v2, s0
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: s_and_b32 s0, s3, 0xffff8000
+; SI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; SI-NEXT: v_or_b32_e32 v3, s0, v2
+; SI-NEXT: s_branch .LBB10_10
+; SI-NEXT: .LBB10_9:
+; SI-NEXT: v_mov_b32_e32 v3, s4
+; SI-NEXT: .LBB10_10: ; %Flow136
+; SI-NEXT: s_lshr_b32 s4, s2, 16
+; SI-NEXT: s_lshr_b32 s5, s3, 16
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; SI-NEXT: ; %bb.11:
+; SI-NEXT: v_cvt_f32_f16_e64 v6, |s5|
+; SI-NEXT: v_cvt_f32_f16_e64 v5, |v4|
+; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
+; SI-NEXT: s_cbranch_vccz .LBB10_13
+; SI-NEXT: ; %bb.12: ; %frem.else53
+; SI-NEXT: s_and_b32 s6, s5, 0x8000
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: s_cselect_b32 s6, s6, s5
+; SI-NEXT: s_mov_b64 s[0:1], 0
+; SI-NEXT: s_branch .LBB10_14
+; SI-NEXT: .LBB10_13:
+; SI-NEXT: s_mov_b64 s[0:1], -1
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: .LBB10_14: ; %Flow131
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s0, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s0, 1
+; SI-NEXT: s_cbranch_scc1 .LBB10_20
+; SI-NEXT: ; %bb.15: ; %frem.compute52
+; SI-NEXT: s_mov_b32 s7, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v7
+; SI-NEXT: v_frexp_mant_f32_e32 v7, v6
+; SI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s7
+; SI-NEXT: v_frexp_mant_f32_e32 v7, v5
+; SI-NEXT: s_cselect_b32 s6, s0, 0
+; SI-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v5
+; SI-NEXT: v_ldexp_f32_e64 v5, v7, 1
+; SI-NEXT: v_div_scale_f32 v8, s[10:11], v5, v5, 1.0
+; SI-NEXT: v_rcp_f32_e32 v9, v8
+; SI-NEXT: v_ldexp_f32_e64 v6, v6, 11
+; SI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT: v_fma_f32 v9, -v7, v8, 1.0
-; SI-NEXT: v_fma_f32 v8, v9, v8, v8
-; SI-NEXT: v_mul_f32_e32 v9, v6, v8
-; SI-NEXT: s_cselect_b32 s6, s1, 0
-; SI-NEXT: v_fma_f32 v10, -v7, v9, v6
-; SI-NEXT: s_add_i32 s1, s6, -1
-; SI-NEXT: v_fma_f32 v9, v10, v8, v9
-; SI-NEXT: s_not_b32 s4, s1
-; SI-NEXT: v_fma_f32 v6, -v7, v9, v6
+; SI-NEXT: v_fma_f32 v10, -v8, v9, 1.0
+; SI-NEXT: v_fma_f32 v9, v10, v9, v9
+; SI-NEXT: v_mul_f32_e32 v10, v7, v9
+; SI-NEXT: s_cselect_b32 s7, s0, 0
+; SI-NEXT: v_fma_f32 v11, -v8, v10, v7
+; SI-NEXT: s_add_i32 s0, s7, -1
+; SI-NEXT: v_fma_f32 v10, v11, v9, v10
+; SI-NEXT: s_not_b32 s1, s0
+; SI-NEXT: v_fma_f32 v7, -v8, v10, v7
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT: s_add_i32 s4, s4, s5
-; SI-NEXT: v_div_fmas_f32 v6, v6, v8, v9
-; SI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; SI-NEXT: s_cmp_lt_i32 s4, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_12
-; SI-NEXT: ; %bb.9: ; %frem.loop_body60.preheader
-; SI-NEXT: s_sub_i32 s4, s5, s6
-; SI-NEXT: s_add_i32 s4, s4, 11
-; SI-NEXT: .LBB10_10: ; %frem.loop_body60
+; SI-NEXT: s_add_i32 s1, s1, s6
+; SI-NEXT: v_div_fmas_f32 v7, v7, v9, v10
+; SI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
+; SI-NEXT: s_cmp_lt_i32 s1, 12
+; SI-NEXT: s_cbranch_scc1 .LBB10_19
+; SI-NEXT: ; %bb.16: ; %frem.loop_body60.preheader
+; SI-NEXT: s_sub_i32 s1, s6, s7
+; SI-NEXT: s_add_i32 s1, s1, 11
+; SI-NEXT: .LBB10_17: ; %frem.loop_body60
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v7, v5
-; SI-NEXT: v_mul_f32_e32 v5, v7, v6
-; SI-NEXT: v_rndne_f32_e32 v5, v5
-; SI-NEXT: v_fma_f32 v5, -v5, v4, v7
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; SI-NEXT: v_add_f32_e32 v8, v5, v4
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
-; SI-NEXT: s_add_i32 s4, s4, -11
-; SI-NEXT: v_ldexp_f32_e64 v5, v5, 11
-; SI-NEXT: s_cmp_gt_i32 s4, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_10
-; SI-NEXT: s_branch .LBB10_13
-; SI-NEXT: .LBB10_11: ; %frem.else53
-; SI-NEXT: s_and_b32 s1, s3, 0x8000
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: s_cselect_b32 s1, s1, s3
-; SI-NEXT: v_mov_b32_e32 v5, s1
-; SI-NEXT: s_branch .LBB10_14
-; SI-NEXT: .LBB10_12:
-; SI-NEXT: v_mov_b32_e32 v7, v5
-; SI-NEXT: .LBB10_13: ; %frem.loop_exit61
-; SI-NEXT: s_add_i32 s4, s4, -10
-; SI-NEXT: v_ldexp_f32_e64 v5, v7, s4
-; SI-NEXT: v_mul_f32_e32 v6, v5, v6
+; SI-NEXT: v_mov_b32_e32 v8, v6
+; SI-NEXT: v_mul_f32_e32 v6, v8, v7
; SI-NEXT: v_rndne_f32_e32 v6, v6
-; SI-NEXT: v_fma_f32 v5, -v6, v4, v5
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; SI-NEXT: v_add_f32_e32 v4, v5, v4
-; SI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; SI-NEXT: v_ldexp_f32_e64 v4, v4, s1
-; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; SI-NEXT: s_and_b32 s1, s3, 0x8000
-; SI-NEXT: v_and_b32_e32 v4, 0x7fff, v4
-; SI-NEXT: v_or_b32_e32 v5, s1, v4
-; SI-NEXT: .LBB10_14:
+; SI-NEXT: v_fma_f32 v6, -v6, v5, v8
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; SI-NEXT: v_add_f32_e32 v9, v6, v5
+; SI-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; SI-NEXT: s_add_i32 s1, s1, -11
+; SI-NEXT: v_ldexp_f32_e64 v6, v6, 11
+; SI-NEXT: s_cmp_gt_i32 s1, 11
+; SI-NEXT: s_cbranch_scc1 .LBB10_17
+; SI-NEXT: ; %bb.18: ; %Flow129
+; SI-NEXT: v_mov_b32_e32 v6, v8
+; SI-NEXT: .LBB10_19: ; %frem.loop_exit61
+; SI-NEXT: s_add_i32 s1, s1, -10
+; SI-NEXT: v_ldexp_f32_e64 v6, v6, s1
+; SI-NEXT: v_mul_f32_e32 v7, v6, v7
+; SI-NEXT: v_rndne_f32_e32 v7, v7
+; SI-NEXT: v_fma_f32 v6, -v7, v5, v6
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; SI-NEXT: v_add_f32_e32 v5, v6, v5
+; SI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; SI-NEXT: v_ldexp_f32_e64 v5, v5, s0
+; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT: s_and_b32 s0, s5, 0x8000
+; SI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
+; SI-NEXT: v_or_b32_e32 v5, s0, v5
+; SI-NEXT: s_branch .LBB10_21
+; SI-NEXT: .LBB10_20:
+; SI-NEXT: v_mov_b32_e32 v5, s6
+; SI-NEXT: .LBB10_21:
; SI-NEXT: v_cvt_f32_f16_e64 v7, |s2|
; SI-NEXT: v_cvt_f32_f16_e64 v6, |v1|
-; SI-NEXT: s_lshr_b32 s4, s2, 16
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6
-; SI-NEXT: s_cbranch_vccz .LBB10_18
-; SI-NEXT: ; %bb.15: ; %frem.compute19
-; SI-NEXT: s_mov_b32 s1, 0x7f800000
+; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
+; SI-NEXT: s_cbranch_vccz .LBB10_23
+; SI-NEXT: ; %bb.22: ; %frem.else20
+; SI-NEXT: s_and_b32 s6, s2, 0xffff8000
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: s_cselect_b32 s6, s6, s2
+; SI-NEXT: s_mov_b64 s[0:1], 0
+; SI-NEXT: s_branch .LBB10_24
+; SI-NEXT: .LBB10_23:
+; SI-NEXT: s_mov_b64 s[0:1], -1
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: .LBB10_24: ; %Flow127
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s0, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s0, 1
+; SI-NEXT: s_cbranch_scc1 .LBB10_30
+; SI-NEXT: ; %bb.25: ; %frem.compute19
+; SI-NEXT: s_mov_b32 s7, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s7
; SI-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s1
-; SI-NEXT: v_readfirstlane_b32 s5, v8
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v8
; SI-NEXT: v_frexp_mant_f32_e32 v8, v7
-; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s1
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
; SI-NEXT: v_frexp_mant_f32_e32 v8, v6
+; SI-NEXT: s_cselect_b32 s6, s0, 0
; SI-NEXT: v_cndmask_b32_e32 v8, v6, v8, vcc
; SI-NEXT: v_frexp_exp_i32_f32_e32 v6, v6
-; SI-NEXT: v_readfirstlane_b32 s1, v6
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v6
; SI-NEXT: v_ldexp_f32_e64 v6, v8, 1
; SI-NEXT: v_div_scale_f32 v9, s[10:11], v6, v6, 1.0
; SI-NEXT: v_rcp_f32_e32 v10, v9
-; SI-NEXT: s_cselect_b32 s6, s5, 0
; SI-NEXT: v_ldexp_f32_e64 v7, v7, 11
-; SI-NEXT: s_and_b64 s[10:11], vcc, exec
; SI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; SI-NEXT: v_fma_f32 v10, v11, v10, v10
; SI-NEXT: v_mul_f32_e32 v11, v8, v10
-; SI-NEXT: s_cselect_b32 s7, s1, 0
+; SI-NEXT: s_cselect_b32 s7, s0, 0
; SI-NEXT: v_fma_f32 v12, -v9, v11, v8
-; SI-NEXT: s_add_i32 s1, s7, -1
+; SI-NEXT: s_add_i32 s0, s7, -1
; SI-NEXT: v_fma_f32 v11, v12, v10, v11
-; SI-NEXT: s_not_b32 s5, s1
+; SI-NEXT: s_not_b32 s1, s0
; SI-NEXT: v_fma_f32 v8, -v9, v11, v8
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT: s_add_i32 s5, s5, s6
+; SI-NEXT: s_add_i32 s1, s1, s6
; SI-NEXT: v_div_fmas_f32 v8, v8, v10, v11
; SI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; SI-NEXT: s_cmp_lt_i32 s5, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_19
-; SI-NEXT: ; %bb.16: ; %frem.loop_body27.preheader
-; SI-NEXT: s_sub_i32 s5, s6, s7
-; SI-NEXT: s_add_i32 s5, s5, 11
-; SI-NEXT: .LBB10_17: ; %frem.loop_body27
+; SI-NEXT: s_cmp_lt_i32 s1, 12
+; SI-NEXT: s_cbranch_scc1 .LBB10_29
+; SI-NEXT: ; %bb.26: ; %frem.loop_body27.preheader
+; SI-NEXT: s_sub_i32 s1, s6, s7
+; SI-NEXT: s_add_i32 s1, s1, 11
+; SI-NEXT: .LBB10_27: ; %frem.loop_body27
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v9, v7
; SI-NEXT: v_mul_f32_e32 v7, v9, v8
@@ -7133,79 +7637,89 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
; SI-NEXT: v_add_f32_e32 v10, v7, v6
; SI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
-; SI-NEXT: s_add_i32 s5, s5, -11
+; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v7, v7, 11
-; SI-NEXT: s_cmp_gt_i32 s5, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_17
-; SI-NEXT: s_branch .LBB10_20
-; SI-NEXT: .LBB10_18: ; %frem.else20
-; SI-NEXT: s_and_b32 s1, s2, 0xffff8000
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
-; SI-NEXT: s_and_b64 s[6:7], vcc, exec
-; SI-NEXT: s_cselect_b32 s1, s1, s2
-; SI-NEXT: v_mov_b32_e32 v6, s1
-; SI-NEXT: s_branch .LBB10_21
-; SI-NEXT: .LBB10_19:
-; SI-NEXT: v_mov_b32_e32 v9, v7
-; SI-NEXT: .LBB10_20: ; %frem.loop_exit28
-; SI-NEXT: s_add_i32 s5, s5, -10
-; SI-NEXT: v_ldexp_f32_e64 v7, v9, s5
+; SI-NEXT: s_cmp_gt_i32 s1, 11
+; SI-NEXT: s_cbranch_scc1 .LBB10_27
+; SI-NEXT: ; %bb.28: ; %Flow125
+; SI-NEXT: v_mov_b32_e32 v7, v9
+; SI-NEXT: .LBB10_29: ; %frem.loop_exit28
+; SI-NEXT: s_add_i32 s1, s1, -10
+; SI-NEXT: v_ldexp_f32_e64 v7, v7, s1
; SI-NEXT: v_mul_f32_e32 v8, v7, v8
; SI-NEXT: v_rndne_f32_e32 v8, v8
; SI-NEXT: v_fma_f32 v7, -v8, v6, v7
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
; SI-NEXT: v_add_f32_e32 v6, v7, v6
; SI-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
-; SI-NEXT: v_ldexp_f32_e64 v6, v6, s1
+; SI-NEXT: v_ldexp_f32_e64 v6, v6, s0
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-NEXT: s_and_b32 s1, s2, 0xffff8000
+; SI-NEXT: s_and_b32 s0, s2, 0xffff8000
; SI-NEXT: v_and_b32_e32 v6, 0x7fff, v6
-; SI-NEXT: v_or_b32_e32 v6, s1, v6
-; SI-NEXT: .LBB10_21:
+; SI-NEXT: v_or_b32_e32 v6, s0, v6
+; SI-NEXT: s_branch .LBB10_31
+; SI-NEXT: .LBB10_30:
+; SI-NEXT: v_mov_b32_e32 v6, s6
+; SI-NEXT: .LBB10_31:
; SI-NEXT: v_cvt_f32_f16_e64 v8, |s4|
-; SI-NEXT: v_cvt_f32_f16_e64 v7, |v4|
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, v8, v7
-; SI-NEXT: s_cbranch_vccz .LBB10_25
-; SI-NEXT: ; %bb.22: ; %frem.compute
-; SI-NEXT: s_mov_b32 s1, 0x7f800000
+; SI-NEXT: v_cvt_f32_f16_e64 v7, |v2|
+; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v8, v7
+; SI-NEXT: s_cbranch_vccz .LBB10_33
+; SI-NEXT: ; %bb.32: ; %frem.else
+; SI-NEXT: s_and_b32 s6, s4, 0x8000
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: s_cselect_b32 s6, s6, s4
+; SI-NEXT: s_mov_b64 s[0:1], 0
+; SI-NEXT: s_branch .LBB10_34
+; SI-NEXT: .LBB10_33:
+; SI-NEXT: s_mov_b64 s[0:1], -1
+; SI-NEXT: ; implicit-def: $sgpr6
+; SI-NEXT: .LBB10_34: ; %Flow123
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s0, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s0, 1
+; SI-NEXT: s_cbranch_scc1 .LBB10_40
+; SI-NEXT: ; %bb.35: ; %frem.compute
+; SI-NEXT: s_mov_b32 s7, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s7
; SI-NEXT: v_frexp_exp_i32_f32_e32 v9, v8
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s1
-; SI-NEXT: v_readfirstlane_b32 s5, v9
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v9
; SI-NEXT: v_frexp_mant_f32_e32 v9, v8
-; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s1
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s7
; SI-NEXT: v_frexp_mant_f32_e32 v9, v7
+; SI-NEXT: s_cselect_b32 s6, s0, 0
; SI-NEXT: v_cndmask_b32_e32 v9, v7, v9, vcc
; SI-NEXT: v_frexp_exp_i32_f32_e32 v7, v7
-; SI-NEXT: v_readfirstlane_b32 s1, v7
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v7
; SI-NEXT: v_ldexp_f32_e64 v7, v9, 1
; SI-NEXT: v_div_scale_f32 v10, s[10:11], v7, v7, 1.0
; SI-NEXT: v_rcp_f32_e32 v11, v10
-; SI-NEXT: s_cselect_b32 s6, s5, 0
; SI-NEXT: v_ldexp_f32_e64 v8, v8, 11
-; SI-NEXT: s_and_b64 s[10:11], vcc, exec
; SI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v7, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT: v_fma_f32 v12, -v10, v11, 1.0
; SI-NEXT: v_fma_f32 v11, v12, v11, v11
; SI-NEXT: v_mul_f32_e32 v12, v9, v11
-; SI-NEXT: s_cselect_b32 s7, s1, 0
+; SI-NEXT: s_cselect_b32 s7, s0, 0
; SI-NEXT: v_fma_f32 v13, -v10, v12, v9
-; SI-NEXT: s_add_i32 s1, s7, -1
+; SI-NEXT: s_add_i32 s0, s7, -1
; SI-NEXT: v_fma_f32 v12, v13, v11, v12
-; SI-NEXT: s_not_b32 s5, s1
+; SI-NEXT: s_not_b32 s1, s0
; SI-NEXT: v_fma_f32 v9, -v10, v12, v9
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT: s_add_i32 s5, s5, s6
+; SI-NEXT: s_add_i32 s1, s1, s6
; SI-NEXT: v_div_fmas_f32 v9, v9, v11, v12
; SI-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
-; SI-NEXT: s_cmp_lt_i32 s5, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_26
-; SI-NEXT: ; %bb.23: ; %frem.loop_body.preheader
-; SI-NEXT: s_sub_i32 s5, s6, s7
-; SI-NEXT: s_add_i32 s5, s5, 11
-; SI-NEXT: .LBB10_24: ; %frem.loop_body
+; SI-NEXT: s_cmp_lt_i32 s1, 12
+; SI-NEXT: s_cbranch_scc1 .LBB10_39
+; SI-NEXT: ; %bb.36: ; %frem.loop_body.preheader
+; SI-NEXT: s_sub_i32 s1, s6, s7
+; SI-NEXT: s_add_i32 s1, s1, 11
+; SI-NEXT: .LBB10_37: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v10, v8
; SI-NEXT: v_mul_f32_e32 v8, v10, v9
@@ -7214,67 +7728,62 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
; SI-NEXT: v_add_f32_e32 v11, v8, v7
; SI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
-; SI-NEXT: s_add_i32 s5, s5, -11
+; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v8, v8, 11
-; SI-NEXT: s_cmp_gt_i32 s5, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_24
-; SI-NEXT: s_branch .LBB10_27
-; SI-NEXT: .LBB10_25: ; %frem.else
-; SI-NEXT: s_and_b32 s1, s4, 0x8000
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
-; SI-NEXT: s_and_b64 s[6:7], vcc, exec
-; SI-NEXT: s_cselect_b32 s1, s1, s4
-; SI-NEXT: v_mov_b32_e32 v7, s1
-; SI-NEXT: s_branch .LBB10_28
-; SI-NEXT: .LBB10_26:
-; SI-NEXT: v_mov_b32_e32 v10, v8
-; SI-NEXT: .LBB10_27: ; %frem.loop_exit
-; SI-NEXT: s_add_i32 s5, s5, -10
-; SI-NEXT: v_ldexp_f32_e64 v8, v10, s5
+; SI-NEXT: s_cmp_gt_i32 s1, 11
+; SI-NEXT: s_cbranch_scc1 .LBB10_37
+; SI-NEXT: ; %bb.38: ; %Flow
+; SI-NEXT: v_mov_b32_e32 v8, v10
+; SI-NEXT: .LBB10_39: ; %frem.loop_exit
+; SI-NEXT: s_add_i32 s1, s1, -10
+; SI-NEXT: v_ldexp_f32_e64 v8, v8, s1
; SI-NEXT: v_mul_f32_e32 v9, v8, v9
; SI-NEXT: v_rndne_f32_e32 v9, v9
; SI-NEXT: v_fma_f32 v8, -v9, v7, v8
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
; SI-NEXT: v_add_f32_e32 v7, v8, v7
; SI-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
-; SI-NEXT: v_ldexp_f32_e64 v7, v7, s1
+; SI-NEXT: v_ldexp_f32_e64 v7, v7, s0
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-NEXT: s_and_b32 s1, s4, 0x8000
+; SI-NEXT: s_and_b32 s0, s4, 0x8000
; SI-NEXT: v_and_b32_e32 v7, 0x7fff, v7
-; SI-NEXT: v_or_b32_e32 v7, s1, v7
-; SI-NEXT: .LBB10_28:
+; SI-NEXT: v_or_b32_e32 v7, s0, v7
+; SI-NEXT: s_branch .LBB10_41
+; SI-NEXT: .LBB10_40:
+; SI-NEXT: v_mov_b32_e32 v7, s6
+; SI-NEXT: .LBB10_41: ; %Flow124
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NEXT: s_mov_b32 s5, 0x7f800000
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0
-; SI-NEXT: v_cvt_f32_f16_e64 v0, |s0|
-; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
+; SI-NEXT: s_mov_b32 s3, 0x7f800000
; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1
-; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v0
+; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v0
; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
; SI-NEXT: v_mov_b32_e32 v0, 0x7e00
; SI-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
-; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
-; SI-NEXT: v_cvt_f32_f16_e64 v2, |s3|
-; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v2
+; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
+; SI-NEXT: v_cvt_f32_f16_e64 v4, |s5|
+; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v4
; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; SI-NEXT: v_cndmask_b32_e32 v2, v0, v5, vcc
+; SI-NEXT: v_cndmask_b32_e32 v4, v0, v5, vcc
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
-; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v1
+; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v1
; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v6, vcc
-; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
-; SI-NEXT: v_cvt_f32_f16_e64 v4, |s4|
+; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
+; SI-NEXT: v_cvt_f32_f16_e64 v2, |s4|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v4
+; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v2
; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v1, v1, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
@@ -7294,212 +7803,240 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_mov_b32 s7, s3
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_readfirstlane_b32 s2, v1
-; CI-NEXT: v_readfirstlane_b32 s0, v0
+; CI-NEXT: v_readfirstlane_b32 s3, v0
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 offset:32
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |s0|
-; CI-NEXT: s_lshr_b32 s3, s0, 16
+; CI-NEXT: v_cvt_f32_f16_e64 v3, |s3|
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
-; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3
-; CI-NEXT: s_cbranch_vccz .LBB10_4
-; CI-NEXT: ; %bb.1: ; %frem.compute85
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v4
-; CI-NEXT: v_frexp_mant_f32_e32 v4, v4
-; CI-NEXT: v_ldexp_f32_e64 v7, v4, 11
-; CI-NEXT: v_frexp_mant_f32_e32 v4, v3
-; CI-NEXT: v_ldexp_f32_e64 v4, v4, 1
-; CI-NEXT: v_div_scale_f32 v10, s[4:5], v4, v4, 1.0
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v9, v3
-; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v9
-; CI-NEXT: v_not_b32_e32 v5, v3
-; CI-NEXT: v_add_i32_e32 v5, vcc, v5, v8
-; CI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
-; CI-NEXT: v_rcp_f32_e32 v11, v10
+; CI-NEXT: v_cvt_f32_f16_e64 v2, |v0|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2
+; CI-NEXT: s_cbranch_vccz .LBB10_2
+; CI-NEXT: ; %bb.1: ; %frem.else86
+; CI-NEXT: s_and_b32 s4, s3, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
+; CI-NEXT: s_and_b64 s[0:1], vcc, exec
+; CI-NEXT: s_cselect_b32 s4, s4, s3
+; CI-NEXT: s_mov_b64 s[0:1], 0
+; CI-NEXT: s_branch .LBB10_3
+; CI-NEXT: .LBB10_2:
+; CI-NEXT: s_mov_b64 s[0:1], -1
+; CI-NEXT: ; implicit-def: $sgpr4
+; CI-NEXT: .LBB10_3: ; %Flow135
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cselect_b32 s0, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s0, 1
+; CI-NEXT: s_cbranch_scc1 .LBB10_9
+; CI-NEXT: ; %bb.4: ; %frem.compute85
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
+; CI-NEXT: v_frexp_mant_f32_e32 v3, v3
+; CI-NEXT: v_ldexp_f32_e64 v5, v3, 11
+; CI-NEXT: v_frexp_mant_f32_e32 v3, v2
+; CI-NEXT: v_ldexp_f32_e64 v3, v3, 1
+; CI-NEXT: v_div_scale_f32 v9, s[0:1], v3, v3, 1.0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
+; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8
+; CI-NEXT: v_not_b32_e32 v4, v2
+; CI-NEXT: v_add_i32_e32 v4, vcc, v4, v7
+; CI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; CI-NEXT: v_rcp_f32_e32 v10, v9
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v12, -v10, v11, 1.0
-; CI-NEXT: v_fma_f32 v11, v12, v11, v11
-; CI-NEXT: v_mul_f32_e32 v12, v6, v11
-; CI-NEXT: v_fma_f32 v13, -v10, v12, v6
-; CI-NEXT: v_fma_f32 v12, v13, v11, v12
-; CI-NEXT: v_fma_f32 v6, -v10, v12, v6
+; CI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
+; CI-NEXT: v_fma_f32 v10, v11, v10, v10
+; CI-NEXT: v_mul_f32_e32 v11, v6, v10
+; CI-NEXT: v_fma_f32 v12, -v9, v11, v6
+; CI-NEXT: v_fma_f32 v11, v12, v10, v11
+; CI-NEXT: v_fma_f32 v6, -v9, v11, v6
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v6, v6, v11, v12
-; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v5
-; CI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_5
-; CI-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
-; CI-NEXT: v_sub_i32_e32 v5, vcc, v8, v9
-; CI-NEXT: v_add_i32_e32 v5, vcc, 11, v5
-; CI-NEXT: .LBB10_3: ; %frem.loop_body93
+; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
+; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
+; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB10_8
+; CI-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
+; CI-NEXT: v_add_i32_e32 v4, vcc, 11, v4
+; CI-NEXT: .LBB10_6: ; %frem.loop_body93
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v8, v7
-; CI-NEXT: v_mul_f32_e32 v7, v8, v6
-; CI-NEXT: v_rndne_f32_e32 v7, v7
-; CI-NEXT: v_fma_f32 v7, -v7, v4, v8
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; CI-NEXT: v_add_f32_e32 v9, v7, v4
-; CI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; CI-NEXT: v_add_i32_e32 v5, vcc, -11, v5
-; CI-NEXT: v_ldexp_f32_e64 v7, v7, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v5
-; CI-NEXT: s_cbranch_vccnz .LBB10_3
-; CI-NEXT: s_branch .LBB10_6
-; CI-NEXT: .LBB10_4: ; %frem.else86
-; CI-NEXT: s_and_b32 s1, s0, 0xffff8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
-; CI-NEXT: s_and_b64 s[4:5], vcc, exec
-; CI-NEXT: s_cselect_b32 s1, s1, s0
-; CI-NEXT: v_mov_b32_e32 v3, s1
-; CI-NEXT: s_branch .LBB10_7
-; CI-NEXT: .LBB10_5:
-; CI-NEXT: v_mov_b32_e32 v8, v7
-; CI-NEXT: .LBB10_6: ; %frem.loop_exit94
-; CI-NEXT: v_add_i32_e32 v5, vcc, -10, v5
-; CI-NEXT: v_ldexp_f32_e32 v5, v8, v5
-; CI-NEXT: v_mul_f32_e32 v6, v5, v6
-; CI-NEXT: v_rndne_f32_e32 v6, v6
-; CI-NEXT: v_fma_f32 v5, -v6, v4, v5
+; CI-NEXT: v_mov_b32_e32 v7, v5
+; CI-NEXT: v_mul_f32_e32 v5, v7, v6
+; CI-NEXT: v_rndne_f32_e32 v5, v5
+; CI-NEXT: v_fma_f32 v5, -v5, v3, v7
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v4, v5, v4
-; CI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; CI-NEXT: v_ldexp_f32_e32 v3, v4, v3
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: s_and_b32 s1, s0, 0xffff8000
-; CI-NEXT: v_and_b32_e32 v3, 0x7fff, v3
-; CI-NEXT: v_or_b32_e32 v3, s1, v3
-; CI-NEXT: .LBB10_7:
-; CI-NEXT: v_cvt_f32_f16_e64 v5, |s3|
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |v2|
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
-; CI-NEXT: s_cbranch_vccz .LBB10_11
-; CI-NEXT: ; %bb.8: ; %frem.compute52
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v9, v5
-; CI-NEXT: v_frexp_mant_f32_e32 v5, v5
-; CI-NEXT: v_ldexp_f32_e64 v8, v5, 11
-; CI-NEXT: v_frexp_mant_f32_e32 v5, v4
-; CI-NEXT: v_ldexp_f32_e64 v5, v5, 1
-; CI-NEXT: v_div_scale_f32 v11, s[4:5], v5, v5, 1.0
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v4
-; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v10
-; CI-NEXT: v_not_b32_e32 v6, v4
-; CI-NEXT: v_add_i32_e32 v6, vcc, v6, v9
-; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
-; CI-NEXT: v_rcp_f32_e32 v12, v11
+; CI-NEXT: v_add_f32_e32 v8, v5, v3
+; CI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
+; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
+; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11
+; CI-NEXT: s_cbranch_vccnz .LBB10_6
+; CI-NEXT: ; %bb.7: ; %Flow133
+; CI-NEXT: v_mov_b32_e32 v5, v7
+; CI-NEXT: .LBB10_8: ; %frem.loop_exit94
+; CI-NEXT: v_add_i32_e32 v4, vcc, -10, v4
+; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
+; CI-NEXT: v_mul_f32_e32 v5, v4, v6
+; CI-NEXT: v_rndne_f32_e32 v5, v5
+; CI-NEXT: v_fma_f32 v4, -v5, v3, v4
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
+; CI-NEXT: v_add_f32_e32 v3, v4, v3
+; CI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2
+; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: s_and_b32 s0, s3, 0xffff8000
+; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; CI-NEXT: v_or_b32_e32 v3, s0, v2
+; CI-NEXT: s_branch .LBB10_10
+; CI-NEXT: .LBB10_9:
+; CI-NEXT: v_mov_b32_e32 v3, s4
+; CI-NEXT: .LBB10_10: ; %Flow136
+; CI-NEXT: s_lshr_b32 s4, s2, 16
+; CI-NEXT: s_lshr_b32 s5, s3, 16
+; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; CI-NEXT: ; %bb.11:
+; CI-NEXT: v_cvt_f32_f16_e64 v6, |s5|
+; CI-NEXT: v_cvt_f32_f16_e64 v5, |v4|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
+; CI-NEXT: s_cbranch_vccz .LBB10_13
+; CI-NEXT: ; %bb.12: ; %frem.else53
+; CI-NEXT: s_and_b32 s6, s5, 0x8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
+; CI-NEXT: s_and_b64 s[0:1], vcc, exec
+; CI-NEXT: s_cselect_b32 s6, s6, s5
+; CI-NEXT: s_mov_b64 s[0:1], 0
+; CI-NEXT: s_branch .LBB10_14
+; CI-NEXT: .LBB10_13:
+; CI-NEXT: s_mov_b64 s[0:1], -1
+; CI-NEXT: ; implicit-def: $sgpr6
+; CI-NEXT: .LBB10_14: ; %Flow131
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cselect_b32 s0, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s0, 1
+; CI-NEXT: s_cbranch_scc1 .LBB10_20
+; CI-NEXT: ; %bb.15: ; %frem.compute52
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v6
+; CI-NEXT: v_frexp_mant_f32_e32 v6, v6
+; CI-NEXT: v_ldexp_f32_e64 v8, v6, 11
+; CI-NEXT: v_frexp_mant_f32_e32 v6, v5
+; CI-NEXT: v_ldexp_f32_e64 v6, v6, 1
+; CI-NEXT: v_div_scale_f32 v12, s[0:1], v6, v6, 1.0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v5
+; CI-NEXT: v_add_i32_e32 v5, vcc, -1, v11
+; CI-NEXT: v_not_b32_e32 v7, v5
+; CI-NEXT: v_add_i32_e32 v7, vcc, v7, v10
+; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; CI-NEXT: v_rcp_f32_e32 v13, v12
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v13, -v11, v12, 1.0
-; CI-NEXT: v_fma_f32 v12, v13, v12, v12
-; CI-NEXT: v_mul_f32_e32 v13, v7, v12
-; CI-NEXT: v_fma_f32 v14, -v11, v13, v7
-; CI-NEXT: v_fma_f32 v13, v14, v12, v13
-; CI-NEXT: v_fma_f32 v7, -v11, v13, v7
+; CI-NEXT: v_fma_f32 v14, -v12, v13, 1.0
+; CI-NEXT: v_fma_f32 v13, v14, v13, v13
+; CI-NEXT: v_mul_f32_e32 v14, v9, v13
+; CI-NEXT: v_fma_f32 v15, -v12, v14, v9
+; CI-NEXT: v_fma_f32 v14, v15, v13, v14
+; CI-NEXT: v_fma_f32 v9, -v12, v14, v9
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v7, v7, v12, v13
-; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
-; CI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_12
-; CI-NEXT: ; %bb.9: ; %frem.loop_body60.preheader
-; CI-NEXT: v_sub_i32_e32 v6, vcc, v9, v10
-; CI-NEXT: v_add_i32_e32 v6, vcc, 11, v6
-; CI-NEXT: .LBB10_10: ; %frem.loop_body60
+; CI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
+; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v7
+; CI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB10_19
+; CI-NEXT: ; %bb.16: ; %frem.loop_body60.preheader
+; CI-NEXT: v_sub_i32_e32 v7, vcc, v10, v11
+; CI-NEXT: v_add_i32_e32 v7, vcc, 11, v7
+; CI-NEXT: .LBB10_17: ; %frem.loop_body60
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v9, v8
-; CI-NEXT: v_mul_f32_e32 v8, v9, v7
+; CI-NEXT: v_mov_b32_e32 v10, v8
+; CI-NEXT: v_mul_f32_e32 v8, v10, v9
; CI-NEXT: v_rndne_f32_e32 v8, v8
-; CI-NEXT: v_fma_f32 v8, -v8, v5, v9
+; CI-NEXT: v_fma_f32 v8, -v8, v6, v10
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; CI-NEXT: v_add_f32_e32 v10, v8, v5
-; CI-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
-; CI-NEXT: v_add_i32_e32 v6, vcc, -11, v6
+; CI-NEXT: v_add_f32_e32 v11, v8, v6
+; CI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; CI-NEXT: v_add_i32_e32 v7, vcc, -11, v7
+; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v7
; CI-NEXT: v_ldexp_f32_e64 v8, v8, 11
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
-; CI-NEXT: s_cbranch_vccnz .LBB10_10
-; CI-NEXT: s_branch .LBB10_13
-; CI-NEXT: .LBB10_11: ; %frem.else53
-; CI-NEXT: s_and_b32 s1, s3, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
-; CI-NEXT: s_and_b64 s[4:5], vcc, exec
-; CI-NEXT: s_cselect_b32 s1, s1, s3
-; CI-NEXT: v_mov_b32_e32 v5, s1
-; CI-NEXT: s_branch .LBB10_14
-; CI-NEXT: .LBB10_12:
-; CI-NEXT: v_mov_b32_e32 v9, v8
-; CI-NEXT: .LBB10_13: ; %frem.loop_exit61
-; CI-NEXT: v_add_i32_e32 v6, vcc, -10, v6
-; CI-NEXT: v_ldexp_f32_e32 v6, v9, v6
-; CI-NEXT: v_mul_f32_e32 v7, v6, v7
-; CI-NEXT: v_rndne_f32_e32 v7, v7
-; CI-NEXT: v_fma_f32 v6, -v7, v5, v6
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; CI-NEXT: v_add_f32_e32 v5, v6, v5
-; CI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
-; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: s_and_b32 s1, s3, 0x8000
-; CI-NEXT: v_and_b32_e32 v4, 0x7fff, v4
-; CI-NEXT: v_or_b32_e32 v5, s1, v4
-; CI-NEXT: .LBB10_14:
+; CI-NEXT: s_cbranch_vccnz .LBB10_17
+; CI-NEXT: ; %bb.18: ; %Flow129
+; CI-NEXT: v_mov_b32_e32 v8, v10
+; CI-NEXT: .LBB10_19: ; %frem.loop_exit61
+; CI-NEXT: v_add_i32_e32 v7, vcc, -10, v7
+; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
+; CI-NEXT: v_mul_f32_e32 v8, v7, v9
+; CI-NEXT: v_rndne_f32_e32 v8, v8
+; CI-NEXT: v_fma_f32 v7, -v8, v6, v7
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
+; CI-NEXT: v_add_f32_e32 v6, v7, v6
+; CI-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
+; CI-NEXT: v_ldexp_f32_e32 v5, v6, v5
+; CI-NEXT: v_cvt_f16_f32_e32 v5, v5
+; CI-NEXT: s_and_b32 s0, s5, 0x8000
+; CI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
+; CI-NEXT: v_or_b32_e32 v5, s0, v5
+; CI-NEXT: s_branch .LBB10_21
+; CI-NEXT: .LBB10_20:
+; CI-NEXT: v_mov_b32_e32 v5, s6
+; CI-NEXT: .LBB10_21:
; CI-NEXT: v_cvt_f32_f16_e64 v7, |s2|
; CI-NEXT: v_cvt_f32_f16_e64 v6, |v1|
-; CI-NEXT: s_lshr_b32 s4, s2, 16
-; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6
-; CI-NEXT: s_cbranch_vccz .LBB10_18
-; CI-NEXT: ; %bb.15: ; %frem.compute19
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
+; CI-NEXT: s_cbranch_vccz .LBB10_23
+; CI-NEXT: ; %bb.22: ; %frem.else20
+; CI-NEXT: s_and_b32 s6, s2, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
+; CI-NEXT: s_and_b64 s[0:1], vcc, exec
+; CI-NEXT: s_cselect_b32 s6, s6, s2
+; CI-NEXT: s_mov_b64 s[0:1], 0
+; CI-NEXT: s_branch .LBB10_24
+; CI-NEXT: .LBB10_23:
+; CI-NEXT: s_mov_b64 s[0:1], -1
+; CI-NEXT: ; implicit-def: $sgpr6
+; CI-NEXT: .LBB10_24: ; %Flow127
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cselect_b32 s0, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s0, 1
+; CI-NEXT: s_cbranch_scc1 .LBB10_30
+; CI-NEXT: ; %bb.25: ; %frem.compute19
; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v7
; CI-NEXT: v_frexp_mant_f32_e32 v7, v7
-; CI-NEXT: v_ldexp_f32_e64 v10, v7, 11
+; CI-NEXT: v_ldexp_f32_e64 v9, v7, 11
; CI-NEXT: v_frexp_mant_f32_e32 v7, v6
; CI-NEXT: v_ldexp_f32_e64 v7, v7, 1
-; CI-NEXT: v_div_scale_f32 v13, s[6:7], v7, v7, 1.0
+; CI-NEXT: v_div_scale_f32 v13, s[0:1], v7, v7, 1.0
; CI-NEXT: v_frexp_exp_i32_f32_e32 v12, v6
; CI-NEXT: v_add_i32_e32 v6, vcc, -1, v12
; CI-NEXT: v_not_b32_e32 v8, v6
; CI-NEXT: v_add_i32_e32 v8, vcc, v8, v11
-; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v7, 1.0
+; CI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v7, 1.0
; CI-NEXT: v_rcp_f32_e32 v14, v13
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v15, -v13, v14, 1.0
; CI-NEXT: v_fma_f32 v14, v15, v14, v14
-; CI-NEXT: v_mul_f32_e32 v15, v9, v14
-; CI-NEXT: v_fma_f32 v16, -v13, v15, v9
+; CI-NEXT: v_mul_f32_e32 v15, v10, v14
+; CI-NEXT: v_fma_f32 v16, -v13, v15, v10
; CI-NEXT: v_fma_f32 v15, v16, v14, v15
-; CI-NEXT: v_fma_f32 v9, -v13, v15, v9
+; CI-NEXT: v_fma_f32 v10, -v13, v15, v10
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v9, v9, v14, v15
+; CI-NEXT: v_div_fmas_f32 v10, v10, v14, v15
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v8
-; CI-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_19
-; CI-NEXT: ; %bb.16: ; %frem.loop_body27.preheader
+; CI-NEXT: v_div_fixup_f32 v10, v10, v7, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB10_29
+; CI-NEXT: ; %bb.26: ; %frem.loop_body27.preheader
; CI-NEXT: v_sub_i32_e32 v8, vcc, v11, v12
; CI-NEXT: v_add_i32_e32 v8, vcc, 11, v8
-; CI-NEXT: .LBB10_17: ; %frem.loop_body27
+; CI-NEXT: .LBB10_27: ; %frem.loop_body27
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v11, v10
-; CI-NEXT: v_mul_f32_e32 v10, v11, v9
-; CI-NEXT: v_rndne_f32_e32 v10, v10
-; CI-NEXT: v_fma_f32 v10, -v10, v7, v11
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
-; CI-NEXT: v_add_f32_e32 v12, v10, v7
-; CI-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
+; CI-NEXT: v_mov_b32_e32 v11, v9
+; CI-NEXT: v_mul_f32_e32 v9, v11, v10
+; CI-NEXT: v_rndne_f32_e32 v9, v9
+; CI-NEXT: v_fma_f32 v9, -v9, v7, v11
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
+; CI-NEXT: v_add_f32_e32 v12, v9, v7
+; CI-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; CI-NEXT: v_add_i32_e32 v8, vcc, -11, v8
-; CI-NEXT: v_ldexp_f32_e64 v10, v10, 11
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v8
-; CI-NEXT: s_cbranch_vccnz .LBB10_17
-; CI-NEXT: s_branch .LBB10_20
-; CI-NEXT: .LBB10_18: ; %frem.else20
-; CI-NEXT: s_and_b32 s1, s2, 0xffff8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
-; CI-NEXT: s_and_b64 s[6:7], vcc, exec
-; CI-NEXT: s_cselect_b32 s1, s1, s2
-; CI-NEXT: v_mov_b32_e32 v6, s1
-; CI-NEXT: s_branch .LBB10_21
-; CI-NEXT: .LBB10_19:
-; CI-NEXT: v_mov_b32_e32 v11, v10
-; CI-NEXT: .LBB10_20: ; %frem.loop_exit28
+; CI-NEXT: v_ldexp_f32_e64 v9, v9, 11
+; CI-NEXT: s_cbranch_vccnz .LBB10_27
+; CI-NEXT: ; %bb.28: ; %Flow125
+; CI-NEXT: v_mov_b32_e32 v9, v11
+; CI-NEXT: .LBB10_29: ; %frem.loop_exit28
; CI-NEXT: v_add_i32_e32 v8, vcc, -10, v8
-; CI-NEXT: v_ldexp_f32_e32 v8, v11, v8
-; CI-NEXT: v_mul_f32_e32 v9, v8, v9
+; CI-NEXT: v_ldexp_f32_e32 v8, v9, v8
+; CI-NEXT: v_mul_f32_e32 v9, v8, v10
; CI-NEXT: v_rndne_f32_e32 v9, v9
; CI-NEXT: v_fma_f32 v8, -v9, v7, v8
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
@@ -7507,69 +8044,79 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; CI-NEXT: v_ldexp_f32_e32 v6, v7, v6
; CI-NEXT: v_cvt_f16_f32_e32 v6, v6
-; CI-NEXT: s_and_b32 s1, s2, 0xffff8000
+; CI-NEXT: s_and_b32 s0, s2, 0xffff8000
; CI-NEXT: v_and_b32_e32 v6, 0x7fff, v6
-; CI-NEXT: v_or_b32_e32 v6, s1, v6
-; CI-NEXT: .LBB10_21:
+; CI-NEXT: v_or_b32_e32 v6, s0, v6
+; CI-NEXT: s_branch .LBB10_31
+; CI-NEXT: .LBB10_30:
+; CI-NEXT: v_mov_b32_e32 v6, s6
+; CI-NEXT: .LBB10_31:
; CI-NEXT: v_cvt_f32_f16_e64 v8, |s4|
-; CI-NEXT: v_cvt_f32_f16_e64 v7, |v4|
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, v8, v7
-; CI-NEXT: s_cbranch_vccz .LBB10_25
-; CI-NEXT: ; %bb.22: ; %frem.compute
+; CI-NEXT: v_cvt_f32_f16_e64 v7, |v2|
+; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v8, v7
+; CI-NEXT: s_cbranch_vccz .LBB10_33
+; CI-NEXT: ; %bb.32: ; %frem.else
+; CI-NEXT: s_and_b32 s6, s4, 0x8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
+; CI-NEXT: s_and_b64 s[0:1], vcc, exec
+; CI-NEXT: s_cselect_b32 s6, s6, s4
+; CI-NEXT: s_mov_b64 s[0:1], 0
+; CI-NEXT: s_branch .LBB10_34
+; CI-NEXT: .LBB10_33:
+; CI-NEXT: s_mov_b64 s[0:1], -1
+; CI-NEXT: ; implicit-def: $sgpr6
+; CI-NEXT: .LBB10_34: ; %Flow123
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cselect_b32 s0, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s0, 1
+; CI-NEXT: s_cbranch_scc1 .LBB10_40
+; CI-NEXT: ; %bb.35: ; %frem.compute
; CI-NEXT: v_frexp_exp_i32_f32_e32 v12, v8
; CI-NEXT: v_frexp_mant_f32_e32 v8, v8
-; CI-NEXT: v_ldexp_f32_e64 v11, v8, 11
+; CI-NEXT: v_ldexp_f32_e64 v10, v8, 11
; CI-NEXT: v_frexp_mant_f32_e32 v8, v7
; CI-NEXT: v_ldexp_f32_e64 v8, v8, 1
-; CI-NEXT: v_div_scale_f32 v14, s[6:7], v8, v8, 1.0
+; CI-NEXT: v_div_scale_f32 v14, s[0:1], v8, v8, 1.0
; CI-NEXT: v_frexp_exp_i32_f32_e32 v13, v7
; CI-NEXT: v_add_i32_e32 v7, vcc, -1, v13
; CI-NEXT: v_not_b32_e32 v9, v7
; CI-NEXT: v_add_i32_e32 v9, vcc, v9, v12
-; CI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v8, 1.0
+; CI-NEXT: v_div_scale_f32 v11, vcc, 1.0, v8, 1.0
; CI-NEXT: v_rcp_f32_e32 v15, v14
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v16, -v14, v15, 1.0
; CI-NEXT: v_fma_f32 v15, v16, v15, v15
-; CI-NEXT: v_mul_f32_e32 v16, v10, v15
-; CI-NEXT: v_fma_f32 v17, -v14, v16, v10
+; CI-NEXT: v_mul_f32_e32 v16, v11, v15
+; CI-NEXT: v_fma_f32 v17, -v14, v16, v11
; CI-NEXT: v_fma_f32 v16, v17, v15, v16
-; CI-NEXT: v_fma_f32 v10, -v14, v16, v10
+; CI-NEXT: v_fma_f32 v11, -v14, v16, v11
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v10, v10, v15, v16
+; CI-NEXT: v_div_fmas_f32 v11, v11, v15, v16
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v9
-; CI-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_26
-; CI-NEXT: ; %bb.23: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v11, v11, v8, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB10_39
+; CI-NEXT: ; %bb.36: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v9, vcc, v12, v13
; CI-NEXT: v_add_i32_e32 v9, vcc, 11, v9
-; CI-NEXT: .LBB10_24: ; %frem.loop_body
+; CI-NEXT: .LBB10_37: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v12, v11
-; CI-NEXT: v_mul_f32_e32 v11, v12, v10
-; CI-NEXT: v_rndne_f32_e32 v11, v11
-; CI-NEXT: v_fma_f32 v11, -v11, v8, v12
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
-; CI-NEXT: v_add_f32_e32 v13, v11, v8
-; CI-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
+; CI-NEXT: v_mov_b32_e32 v12, v10
+; CI-NEXT: v_mul_f32_e32 v10, v12, v11
+; CI-NEXT: v_rndne_f32_e32 v10, v10
+; CI-NEXT: v_fma_f32 v10, -v10, v8, v12
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
+; CI-NEXT: v_add_f32_e32 v13, v10, v8
+; CI-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; CI-NEXT: v_add_i32_e32 v9, vcc, -11, v9
-; CI-NEXT: v_ldexp_f32_e64 v11, v11, 11
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v9
-; CI-NEXT: s_cbranch_vccnz .LBB10_24
-; CI-NEXT: s_branch .LBB10_27
-; CI-NEXT: .LBB10_25: ; %frem.else
-; CI-NEXT: s_and_b32 s1, s4, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
-; CI-NEXT: s_and_b64 s[6:7], vcc, exec
-; CI-NEXT: s_cselect_b32 s1, s1, s4
-; CI-NEXT: v_mov_b32_e32 v7, s1
-; CI-NEXT: s_branch .LBB10_28
-; CI-NEXT: .LBB10_26:
-; CI-NEXT: v_mov_b32_e32 v12, v11
-; CI-NEXT: .LBB10_27: ; %frem.loop_exit
+; CI-NEXT: v_ldexp_f32_e64 v10, v10, 11
+; CI-NEXT: s_cbranch_vccnz .LBB10_37
+; CI-NEXT: ; %bb.38: ; %Flow
+; CI-NEXT: v_mov_b32_e32 v10, v12
+; CI-NEXT: .LBB10_39: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v9, vcc, -10, v9
-; CI-NEXT: v_ldexp_f32_e32 v9, v12, v9
-; CI-NEXT: v_mul_f32_e32 v10, v9, v10
+; CI-NEXT: v_ldexp_f32_e32 v9, v10, v9
+; CI-NEXT: v_mul_f32_e32 v10, v9, v11
; CI-NEXT: v_rndne_f32_e32 v10, v10
; CI-NEXT: v_fma_f32 v9, -v10, v8, v9
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
@@ -7577,42 +8124,45 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
; CI-NEXT: v_cvt_f16_f32_e32 v7, v7
-; CI-NEXT: s_and_b32 s1, s4, 0x8000
+; CI-NEXT: s_and_b32 s0, s4, 0x8000
; CI-NEXT: v_and_b32_e32 v7, 0x7fff, v7
-; CI-NEXT: v_or_b32_e32 v7, s1, v7
-; CI-NEXT: .LBB10_28:
+; CI-NEXT: v_or_b32_e32 v7, s0, v7
+; CI-NEXT: s_branch .LBB10_41
+; CI-NEXT: .LBB10_40:
+; CI-NEXT: v_mov_b32_e32 v7, s6
+; CI-NEXT: .LBB10_41: ; %Flow124
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: s_mov_b32 s5, 0x7f800000
+; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v0, |s0|
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
+; CI-NEXT: s_mov_b32 s3, 0x7f800000
; CI-NEXT: s_mov_b32 s11, 0xf000
; CI-NEXT: s_mov_b32 s10, -1
-; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v0
+; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v0
; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
; CI-NEXT: v_mov_b32_e32 v0, 0x7e00
; CI-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
-; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |s3|
-; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v2
+; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
+; CI-NEXT: v_cvt_f32_f16_e64 v4, |s5|
+; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v4
; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; CI-NEXT: v_cndmask_b32_e32 v2, v0, v5, vcc
+; CI-NEXT: v_cndmask_b32_e32 v4, v0, v5, vcc
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
-; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v1
+; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v1
; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
; CI-NEXT: v_cndmask_b32_e32 v1, v0, v6, vcc
-; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |s4|
+; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
+; CI-NEXT: v_cvt_f32_f16_e64 v2, |s4|
; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v4
+; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v2
; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
; CI-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; CI-NEXT: v_or_b32_e32 v1, v1, v0
-; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
; CI-NEXT: v_and_b32_e32 v2, 0xffff, v3
; CI-NEXT: v_or_b32_e32 v0, v2, v0
; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
@@ -7632,64 +8182,72 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_cvt_f32_f16_e64 v5, |v0|
+; VI-NEXT: v_cvt_f32_f16_e64 v6, |v0|
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e64 v4, |v2|
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
-; VI-NEXT: s_cbranch_vccz .LBB10_4
-; VI-NEXT: ; %bb.1: ; %frem.compute85
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v9, v5
-; VI-NEXT: v_frexp_mant_f32_e32 v5, v5
-; VI-NEXT: v_ldexp_f32 v8, v5, 11
-; VI-NEXT: v_frexp_mant_f32_e32 v5, v4
-; VI-NEXT: v_ldexp_f32 v5, v5, 1
+; VI-NEXT: v_cvt_f32_f16_e64 v5, |v2|
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
+; VI-NEXT: s_cbranch_vccz .LBB10_2
+; VI-NEXT: ; %bb.1: ; %frem.else86
+; VI-NEXT: v_and_b32_e32 v4, 0x8000, v0
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
+; VI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB10_3
+; VI-NEXT: .LBB10_2:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr4
+; VI-NEXT: .LBB10_3: ; %Flow135
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB10_9
+; VI-NEXT: ; %bb.4: ; %frem.compute85
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v9, v6
+; VI-NEXT: v_frexp_mant_f32_e32 v4, v6
+; VI-NEXT: v_frexp_mant_f32_e32 v6, v5
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v5
+; VI-NEXT: v_ldexp_f32 v5, v6, 1
; VI-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v4
+; VI-NEXT: v_ldexp_f32 v7, v4, 11
; VI-NEXT: v_add_u32_e32 v4, vcc, -1, v10
; VI-NEXT: v_not_b32_e32 v6, v4
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v9
-; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; VI-NEXT: v_rcp_f32_e32 v12, v11
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; VI-NEXT: v_fma_f32 v12, v13, v12, v12
-; VI-NEXT: v_mul_f32_e32 v13, v7, v12
-; VI-NEXT: v_fma_f32 v14, -v11, v13, v7
+; VI-NEXT: v_mul_f32_e32 v13, v8, v12
+; VI-NEXT: v_fma_f32 v14, -v11, v13, v8
; VI-NEXT: v_fma_f32 v13, v14, v12, v13
-; VI-NEXT: v_fma_f32 v7, -v11, v13, v7
+; VI-NEXT: v_fma_f32 v8, -v11, v13, v8
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v7, v7, v12, v13
+; VI-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
-; VI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_5
-; VI-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; VI-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB10_8
+; VI-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; VI-NEXT: v_sub_u32_e32 v6, vcc, v9, v10
; VI-NEXT: v_add_u32_e32 v6, vcc, 11, v6
-; VI-NEXT: .LBB10_3: ; %frem.loop_body93
+; VI-NEXT: .LBB10_6: ; %frem.loop_body93
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v9, v8
-; VI-NEXT: v_mul_f32_e32 v8, v9, v7
-; VI-NEXT: v_rndne_f32_e32 v8, v8
-; VI-NEXT: v_fma_f32 v8, -v8, v5, v9
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; VI-NEXT: v_add_f32_e32 v10, v8, v5
-; VI-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; VI-NEXT: v_mov_b32_e32 v9, v7
+; VI-NEXT: v_mul_f32_e32 v7, v9, v8
+; VI-NEXT: v_rndne_f32_e32 v7, v7
+; VI-NEXT: v_fma_f32 v7, -v7, v5, v9
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
+; VI-NEXT: v_add_f32_e32 v10, v7, v5
+; VI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, -11, v6
-; VI-NEXT: v_ldexp_f32 v8, v8, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
-; VI-NEXT: s_cbranch_vccnz .LBB10_3
-; VI-NEXT: s_branch .LBB10_6
-; VI-NEXT: .LBB10_4: ; %frem.else86
-; VI-NEXT: v_and_b32_e32 v6, 0x8000, v0
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, v0, v6, vcc
-; VI-NEXT: s_branch .LBB10_7
-; VI-NEXT: .LBB10_5:
-; VI-NEXT: v_mov_b32_e32 v9, v8
-; VI-NEXT: .LBB10_6: ; %frem.loop_exit94
+; VI-NEXT: v_ldexp_f32 v7, v7, 11
+; VI-NEXT: s_cbranch_vccnz .LBB10_6
+; VI-NEXT: ; %bb.7: ; %Flow133
+; VI-NEXT: v_mov_b32_e32 v7, v9
+; VI-NEXT: .LBB10_8: ; %frem.loop_exit94
; VI-NEXT: v_add_u32_e32 v6, vcc, -10, v6
-; VI-NEXT: v_ldexp_f32 v6, v9, v6
-; VI-NEXT: v_mul_f32_e32 v7, v6, v7
+; VI-NEXT: v_ldexp_f32 v6, v7, v6
+; VI-NEXT: v_mul_f32_e32 v7, v6, v8
; VI-NEXT: v_rndne_f32_e32 v7, v7
; VI-NEXT: v_fma_f32 v6, -v7, v5, v6
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -7699,66 +8257,74 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cvt_f16_f32_e32 v4, v4
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; VI-NEXT: .LBB10_7:
+; VI-NEXT: .LBB10_9:
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; VI-NEXT: v_cvt_f32_f16_e64 v8, |v5|
-; VI-NEXT: v_cvt_f32_f16_e64 v7, |v6|
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, v8, v7
+; VI-NEXT: v_cvt_f32_f16_e64 v9, |v5|
+; VI-NEXT: v_cvt_f32_f16_e64 v8, |v6|
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v9, v8
; VI-NEXT: s_cbranch_vccz .LBB10_11
-; VI-NEXT: ; %bb.8: ; %frem.compute52
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v12, v8
-; VI-NEXT: v_frexp_mant_f32_e32 v8, v8
-; VI-NEXT: v_ldexp_f32 v11, v8, 11
-; VI-NEXT: v_frexp_mant_f32_e32 v8, v7
-; VI-NEXT: v_ldexp_f32 v8, v8, 1
+; VI-NEXT: ; %bb.10: ; %frem.else53
+; VI-NEXT: v_and_b32_e32 v7, 0x8000, v5
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v9, v8
+; VI-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB10_12
+; VI-NEXT: .LBB10_11:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr7
+; VI-NEXT: .LBB10_12: ; %Flow131
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB10_18
+; VI-NEXT: ; %bb.13: ; %frem.compute52
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v12, v9
+; VI-NEXT: v_frexp_mant_f32_e32 v7, v9
+; VI-NEXT: v_frexp_mant_f32_e32 v9, v8
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v8
+; VI-NEXT: v_ldexp_f32 v8, v9, 1
; VI-NEXT: v_div_scale_f32 v14, s[2:3], v8, v8, 1.0
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v7
+; VI-NEXT: v_ldexp_f32 v10, v7, 11
; VI-NEXT: v_add_u32_e32 v7, vcc, -1, v13
; VI-NEXT: v_not_b32_e32 v9, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v12
-; VI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v8, 1.0
+; VI-NEXT: v_div_scale_f32 v11, vcc, 1.0, v8, 1.0
; VI-NEXT: v_rcp_f32_e32 v15, v14
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v16, -v14, v15, 1.0
; VI-NEXT: v_fma_f32 v15, v16, v15, v15
-; VI-NEXT: v_mul_f32_e32 v16, v10, v15
-; VI-NEXT: v_fma_f32 v17, -v14, v16, v10
+; VI-NEXT: v_mul_f32_e32 v16, v11, v15
+; VI-NEXT: v_fma_f32 v17, -v14, v16, v11
; VI-NEXT: v_fma_f32 v16, v17, v15, v16
-; VI-NEXT: v_fma_f32 v10, -v14, v16, v10
+; VI-NEXT: v_fma_f32 v11, -v14, v16, v11
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v10, v10, v15, v16
+; VI-NEXT: v_div_fmas_f32 v11, v11, v15, v16
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v9
-; VI-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_12
-; VI-NEXT: ; %bb.9: ; %frem.loop_body60.preheader
+; VI-NEXT: v_div_fixup_f32 v11, v11, v8, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB10_17
+; VI-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
; VI-NEXT: v_sub_u32_e32 v9, vcc, v12, v13
; VI-NEXT: v_add_u32_e32 v9, vcc, 11, v9
-; VI-NEXT: .LBB10_10: ; %frem.loop_body60
+; VI-NEXT: .LBB10_15: ; %frem.loop_body60
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v12, v11
-; VI-NEXT: v_mul_f32_e32 v11, v12, v10
-; VI-NEXT: v_rndne_f32_e32 v11, v11
-; VI-NEXT: v_fma_f32 v11, -v11, v8, v12
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
-; VI-NEXT: v_add_f32_e32 v13, v11, v8
-; VI-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
+; VI-NEXT: v_mov_b32_e32 v12, v10
+; VI-NEXT: v_mul_f32_e32 v10, v12, v11
+; VI-NEXT: v_rndne_f32_e32 v10, v10
+; VI-NEXT: v_fma_f32 v10, -v10, v8, v12
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
+; VI-NEXT: v_add_f32_e32 v13, v10, v8
+; VI-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; VI-NEXT: v_add_u32_e32 v9, vcc, -11, v9
-; VI-NEXT: v_ldexp_f32 v11, v11, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v9
-; VI-NEXT: s_cbranch_vccnz .LBB10_10
-; VI-NEXT: s_branch .LBB10_13
-; VI-NEXT: .LBB10_11: ; %frem.else53
-; VI-NEXT: v_and_b32_e32 v9, 0x8000, v5
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
-; VI-NEXT: v_cndmask_b32_e32 v7, v5, v9, vcc
-; VI-NEXT: s_branch .LBB10_14
-; VI-NEXT: .LBB10_12:
-; VI-NEXT: v_mov_b32_e32 v12, v11
-; VI-NEXT: .LBB10_13: ; %frem.loop_exit61
+; VI-NEXT: v_ldexp_f32 v10, v10, 11
+; VI-NEXT: s_cbranch_vccnz .LBB10_15
+; VI-NEXT: ; %bb.16: ; %Flow129
+; VI-NEXT: v_mov_b32_e32 v10, v12
+; VI-NEXT: .LBB10_17: ; %frem.loop_exit61
; VI-NEXT: v_add_u32_e32 v9, vcc, -10, v9
-; VI-NEXT: v_ldexp_f32 v9, v12, v9
-; VI-NEXT: v_mul_f32_e32 v10, v9, v10
+; VI-NEXT: v_ldexp_f32 v9, v10, v9
+; VI-NEXT: v_mul_f32_e32 v10, v9, v11
; VI-NEXT: v_rndne_f32_e32 v10, v10
; VI-NEXT: v_fma_f32 v9, -v10, v8, v9
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
@@ -7768,64 +8334,72 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cvt_f16_f32_e32 v7, v7
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v7, s2, v7, v5
-; VI-NEXT: .LBB10_14:
-; VI-NEXT: v_cvt_f32_f16_e64 v9, |v1|
-; VI-NEXT: v_cvt_f32_f16_e64 v8, |v3|
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, v9, v8
-; VI-NEXT: s_cbranch_vccz .LBB10_18
-; VI-NEXT: ; %bb.15: ; %frem.compute19
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v9
-; VI-NEXT: v_frexp_mant_f32_e32 v9, v9
-; VI-NEXT: v_ldexp_f32 v12, v9, 11
-; VI-NEXT: v_frexp_mant_f32_e32 v9, v8
-; VI-NEXT: v_ldexp_f32 v9, v9, 1
+; VI-NEXT: .LBB10_18:
+; VI-NEXT: v_cvt_f32_f16_e64 v10, |v1|
+; VI-NEXT: v_cvt_f32_f16_e64 v9, |v3|
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v10, v9
+; VI-NEXT: s_cbranch_vccz .LBB10_20
+; VI-NEXT: ; %bb.19: ; %frem.else20
+; VI-NEXT: v_and_b32_e32 v8, 0x8000, v1
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v10, v9
+; VI-NEXT: v_cndmask_b32_e32 v8, v1, v8, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB10_21
+; VI-NEXT: .LBB10_20:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr8
+; VI-NEXT: .LBB10_21: ; %Flow127
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB10_27
+; VI-NEXT: ; %bb.22: ; %frem.compute19
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v10
+; VI-NEXT: v_frexp_mant_f32_e32 v8, v10
+; VI-NEXT: v_frexp_mant_f32_e32 v10, v9
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v14, v9
+; VI-NEXT: v_ldexp_f32 v9, v10, 1
; VI-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v14, v8
+; VI-NEXT: v_ldexp_f32 v11, v8, 11
; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v14
; VI-NEXT: v_not_b32_e32 v10, v8
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v13
-; VI-NEXT: v_div_scale_f32 v11, vcc, 1.0, v9, 1.0
+; VI-NEXT: v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
; VI-NEXT: v_rcp_f32_e32 v16, v15
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v17, -v15, v16, 1.0
; VI-NEXT: v_fma_f32 v16, v17, v16, v16
-; VI-NEXT: v_mul_f32_e32 v17, v11, v16
-; VI-NEXT: v_fma_f32 v18, -v15, v17, v11
+; VI-NEXT: v_mul_f32_e32 v17, v12, v16
+; VI-NEXT: v_fma_f32 v18, -v15, v17, v12
; VI-NEXT: v_fma_f32 v17, v18, v16, v17
-; VI-NEXT: v_fma_f32 v11, -v15, v17, v11
+; VI-NEXT: v_fma_f32 v12, -v15, v17, v12
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v11, v11, v16, v17
+; VI-NEXT: v_div_fmas_f32 v12, v12, v16, v17
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v10
-; VI-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_19
-; VI-NEXT: ; %bb.16: ; %frem.loop_body27.preheader
+; VI-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB10_26
+; VI-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
; VI-NEXT: v_sub_u32_e32 v10, vcc, v13, v14
; VI-NEXT: v_add_u32_e32 v10, vcc, 11, v10
-; VI-NEXT: .LBB10_17: ; %frem.loop_body27
+; VI-NEXT: .LBB10_24: ; %frem.loop_body27
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v13, v12
-; VI-NEXT: v_mul_f32_e32 v12, v13, v11
-; VI-NEXT: v_rndne_f32_e32 v12, v12
-; VI-NEXT: v_fma_f32 v12, -v12, v9, v13
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
-; VI-NEXT: v_add_f32_e32 v14, v12, v9
-; VI-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc
+; VI-NEXT: v_mov_b32_e32 v13, v11
+; VI-NEXT: v_mul_f32_e32 v11, v13, v12
+; VI-NEXT: v_rndne_f32_e32 v11, v11
+; VI-NEXT: v_fma_f32 v11, -v11, v9, v13
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
+; VI-NEXT: v_add_f32_e32 v14, v11, v9
+; VI-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, -11, v10
-; VI-NEXT: v_ldexp_f32 v12, v12, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v10
-; VI-NEXT: s_cbranch_vccnz .LBB10_17
-; VI-NEXT: s_branch .LBB10_20
-; VI-NEXT: .LBB10_18: ; %frem.else20
-; VI-NEXT: v_and_b32_e32 v10, 0x8000, v1
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v9, v8
-; VI-NEXT: v_cndmask_b32_e32 v9, v1, v10, vcc
-; VI-NEXT: s_branch .LBB10_21
-; VI-NEXT: .LBB10_19:
-; VI-NEXT: v_mov_b32_e32 v13, v12
-; VI-NEXT: .LBB10_20: ; %frem.loop_exit28
+; VI-NEXT: v_ldexp_f32 v11, v11, 11
+; VI-NEXT: s_cbranch_vccnz .LBB10_24
+; VI-NEXT: ; %bb.25: ; %Flow125
+; VI-NEXT: v_mov_b32_e32 v11, v13
+; VI-NEXT: .LBB10_26: ; %frem.loop_exit28
; VI-NEXT: v_add_u32_e32 v10, vcc, -10, v10
-; VI-NEXT: v_ldexp_f32 v10, v13, v10
-; VI-NEXT: v_mul_f32_e32 v11, v10, v11
+; VI-NEXT: v_ldexp_f32 v10, v11, v10
+; VI-NEXT: v_mul_f32_e32 v11, v10, v12
; VI-NEXT: v_rndne_f32_e32 v11, v11
; VI-NEXT: v_fma_f32 v10, -v11, v9, v10
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
@@ -7834,67 +8408,75 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v8, v9, v8
; VI-NEXT: v_cvt_f16_f32_e32 v8, v8
; VI-NEXT: s_movk_i32 s2, 0x7fff
-; VI-NEXT: v_bfi_b32 v9, s2, v8, v1
-; VI-NEXT: .LBB10_21:
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; VI-NEXT: v_bfi_b32 v8, s2, v8, v1
+; VI-NEXT: .LBB10_27:
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v3
-; VI-NEXT: v_cvt_f32_f16_e64 v12, |v8|
-; VI-NEXT: v_cvt_f32_f16_e64 v11, |v10|
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, v12, v11
-; VI-NEXT: s_cbranch_vccz .LBB10_25
-; VI-NEXT: ; %bb.22: ; %frem.compute
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v16, v12
-; VI-NEXT: v_frexp_mant_f32_e32 v12, v12
-; VI-NEXT: v_ldexp_f32 v15, v12, 11
-; VI-NEXT: v_frexp_mant_f32_e32 v12, v11
-; VI-NEXT: v_ldexp_f32 v12, v12, 1
+; VI-NEXT: v_cvt_f32_f16_e64 v13, |v9|
+; VI-NEXT: v_cvt_f32_f16_e64 v12, |v10|
+; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v13, v12
+; VI-NEXT: s_cbranch_vccz .LBB10_29
+; VI-NEXT: ; %bb.28: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v11, 0x8000, v9
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v13, v12
+; VI-NEXT: v_cndmask_b32_e32 v11, v9, v11, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB10_30
+; VI-NEXT: .LBB10_29:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: .LBB10_30: ; %Flow123
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB10_36
+; VI-NEXT: ; %bb.31: ; %frem.compute
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v16, v13
+; VI-NEXT: v_frexp_mant_f32_e32 v11, v13
+; VI-NEXT: v_frexp_mant_f32_e32 v13, v12
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v17, v12
+; VI-NEXT: v_ldexp_f32 v12, v13, 1
; VI-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v17, v11
+; VI-NEXT: v_ldexp_f32 v14, v11, 11
; VI-NEXT: v_add_u32_e32 v11, vcc, -1, v17
; VI-NEXT: v_not_b32_e32 v13, v11
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v16
-; VI-NEXT: v_div_scale_f32 v14, vcc, 1.0, v12, 1.0
+; VI-NEXT: v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; VI-NEXT: v_rcp_f32_e32 v19, v18
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v20, -v18, v19, 1.0
; VI-NEXT: v_fma_f32 v19, v20, v19, v19
-; VI-NEXT: v_mul_f32_e32 v20, v14, v19
-; VI-NEXT: v_fma_f32 v21, -v18, v20, v14
+; VI-NEXT: v_mul_f32_e32 v20, v15, v19
+; VI-NEXT: v_fma_f32 v21, -v18, v20, v15
; VI-NEXT: v_fma_f32 v20, v21, v19, v20
-; VI-NEXT: v_fma_f32 v14, -v18, v20, v14
+; VI-NEXT: v_fma_f32 v15, -v18, v20, v15
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v14, v14, v19, v20
+; VI-NEXT: v_div_fmas_f32 v15, v15, v19, v20
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v13
-; VI-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_26
-; VI-NEXT: ; %bb.23: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB10_35
+; VI-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v13, vcc, v16, v17
; VI-NEXT: v_add_u32_e32 v13, vcc, 11, v13
-; VI-NEXT: .LBB10_24: ; %frem.loop_body
+; VI-NEXT: .LBB10_33: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v16, v15
-; VI-NEXT: v_mul_f32_e32 v15, v16, v14
-; VI-NEXT: v_rndne_f32_e32 v15, v15
-; VI-NEXT: v_fma_f32 v15, -v15, v12, v16
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v15
-; VI-NEXT: v_add_f32_e32 v17, v15, v12
-; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; VI-NEXT: v_mov_b32_e32 v16, v14
+; VI-NEXT: v_mul_f32_e32 v14, v16, v15
+; VI-NEXT: v_rndne_f32_e32 v14, v14
+; VI-NEXT: v_fma_f32 v14, -v14, v12, v16
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
+; VI-NEXT: v_add_f32_e32 v17, v14, v12
+; VI-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
; VI-NEXT: v_add_u32_e32 v13, vcc, -11, v13
-; VI-NEXT: v_ldexp_f32 v15, v15, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v13
-; VI-NEXT: s_cbranch_vccnz .LBB10_24
-; VI-NEXT: s_branch .LBB10_27
-; VI-NEXT: .LBB10_25: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v13, 0x8000, v8
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v12, v11
-; VI-NEXT: v_cndmask_b32_e32 v11, v8, v13, vcc
-; VI-NEXT: s_branch .LBB10_28
-; VI-NEXT: .LBB10_26:
-; VI-NEXT: v_mov_b32_e32 v16, v15
-; VI-NEXT: .LBB10_27: ; %frem.loop_exit
+; VI-NEXT: v_ldexp_f32 v14, v14, 11
+; VI-NEXT: s_cbranch_vccnz .LBB10_33
+; VI-NEXT: ; %bb.34: ; %Flow
+; VI-NEXT: v_mov_b32_e32 v14, v16
+; VI-NEXT: .LBB10_35: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v13, vcc, -10, v13
-; VI-NEXT: v_ldexp_f32 v13, v16, v13
-; VI-NEXT: v_mul_f32_e32 v14, v13, v14
+; VI-NEXT: v_ldexp_f32 v13, v14, v13
+; VI-NEXT: v_mul_f32_e32 v14, v13, v15
; VI-NEXT: v_rndne_f32_e32 v14, v14
; VI-NEXT: v_fma_f32 v13, -v14, v12, v13
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
@@ -7903,8 +8485,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v11, v12, v11
; VI-NEXT: v_cvt_f16_f32_e32 v11, v11
; VI-NEXT: s_movk_i32 s2, 0x7fff
-; VI-NEXT: v_bfi_b32 v11, s2, v11, v8
-; VI-NEXT: .LBB10_28:
+; VI-NEXT: v_bfi_b32 v11, s2, v11, v9
+; VI-NEXT: .LBB10_36: ; %Flow124
; VI-NEXT: s_movk_i32 s4, 0x7c00
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v2
; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |v0|, s4
@@ -7918,11 +8500,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v3
; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |v1|, s4
; VI-NEXT: s_and_b64 vcc, s[2:3], vcc
-; VI-NEXT: v_cndmask_b32_e32 v3, v2, v9, vcc
+; VI-NEXT: v_cndmask_b32_e32 v3, v2, v8, vcc
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v10
-; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |v8|, s4
+; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |v9|, s4
; VI-NEXT: s_and_b64 vcc, s[0:1], vcc
; VI-NEXT: v_cndmask_b32_sdwa v2, v2, v11, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
@@ -7939,20 +8521,34 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7] offset:32
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v5, |v2|
+; GFX9-NEXT: v_cvt_f32_f16_e64 v6, |v2|
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v4, |v0|
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
-; GFX9-NEXT: s_cbranch_vccz .LBB10_4
-; GFX9-NEXT: ; %bb.1: ; %frem.compute85
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v5
-; GFX9-NEXT: v_frexp_mant_f32_e32 v5, v5
-; GFX9-NEXT: v_ldexp_f32 v8, v5, 11
-; GFX9-NEXT: v_frexp_mant_f32_e32 v5, v4
-; GFX9-NEXT: v_ldexp_f32 v5, v5, 1
+; GFX9-NEXT: v_cvt_f32_f16_e64 v5, |v0|
+; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
+; GFX9-NEXT: s_cbranch_vccz .LBB10_2
+; GFX9-NEXT: ; %bb.1: ; %frem.else86
+; GFX9-NEXT: v_and_b32_e32 v4, 0x8000, v2
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB10_3
+; GFX9-NEXT: .LBB10_2:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr4
+; GFX9-NEXT: .LBB10_3: ; %Flow135
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX9-NEXT: ; %bb.4: ; %frem.compute85
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v6
+; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v6
+; GFX9-NEXT: v_frexp_mant_f32_e32 v6, v5
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v5
+; GFX9-NEXT: v_ldexp_f32 v5, v6, 1
; GFX9-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
-; GFX9-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v4
+; GFX9-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; GFX9-NEXT: v_ldexp_f32 v7, v4, 11
; GFX9-NEXT: v_add_u32_e32 v4, -1, v10
; GFX9-NEXT: v_not_b32_e32 v6, v4
; GFX9-NEXT: v_add_u32_e32 v6, v6, v9
@@ -7960,43 +8556,37 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; GFX9-NEXT: v_fma_f32 v12, v13, v12, v12
-; GFX9-NEXT: v_mul_f32_e32 v13, v7, v12
-; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v7
+; GFX9-NEXT: v_mul_f32_e32 v13, v8, v12
+; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v8
; GFX9-NEXT: v_fma_f32 v13, v14, v12, v13
-; GFX9-NEXT: v_fma_f32 v7, -v11, v13, v7
+; GFX9-NEXT: v_fma_f32 v8, -v11, v13, v8
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v7, v7, v12, v13
+; GFX9-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
-; GFX9-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_5
-; GFX9-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; GFX9-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_8
+; GFX9-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX9-NEXT: v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT: v_add_u32_e32 v6, 11, v6
-; GFX9-NEXT: .LBB10_3: ; %frem.loop_body93
+; GFX9-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v9, v8
-; GFX9-NEXT: v_mul_f32_e32 v8, v9, v7
-; GFX9-NEXT: v_rndne_f32_e32 v8, v8
-; GFX9-NEXT: v_fma_f32 v8, -v8, v5, v9
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; GFX9-NEXT: v_add_f32_e32 v10, v8, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX9-NEXT: v_mov_b32_e32 v9, v7
+; GFX9-NEXT: v_mul_f32_e32 v7, v9, v8
+; GFX9-NEXT: v_rndne_f32_e32 v7, v7
+; GFX9-NEXT: v_fma_f32 v7, -v7, v5, v9
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
+; GFX9-NEXT: v_add_f32_e32 v10, v7, v5
; GFX9-NEXT: v_add_u32_e32 v6, -11, v6
-; GFX9-NEXT: v_ldexp_f32 v8, v8, 11
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_3
-; GFX9-NEXT: s_branch .LBB10_6
-; GFX9-NEXT: .LBB10_4: ; %frem.else86
-; GFX9-NEXT: v_and_b32_e32 v6, 0x8000, v2
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
-; GFX9-NEXT: s_branch .LBB10_7
-; GFX9-NEXT: .LBB10_5:
-; GFX9-NEXT: v_mov_b32_e32 v9, v8
-; GFX9-NEXT: .LBB10_6: ; %frem.loop_exit94
+; GFX9-NEXT: v_ldexp_f32 v7, v7, 11
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_6
+; GFX9-NEXT: ; %bb.7: ; %Flow133
+; GFX9-NEXT: v_mov_b32_e32 v7, v9
+; GFX9-NEXT: .LBB10_8: ; %frem.loop_exit94
; GFX9-NEXT: v_add_u32_e32 v6, -10, v6
-; GFX9-NEXT: v_ldexp_f32 v6, v9, v6
-; GFX9-NEXT: v_mul_f32_e32 v7, v6, v7
+; GFX9-NEXT: v_ldexp_f32 v6, v7, v6
+; GFX9-NEXT: v_mul_f32_e32 v7, v6, v8
; GFX9-NEXT: v_rndne_f32_e32 v7, v7
; GFX9-NEXT: v_fma_f32 v6, -v7, v5, v6
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -8006,21 +8596,35 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v2
-; GFX9-NEXT: .LBB10_7:
+; GFX9-NEXT: .LBB10_9:
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX9-NEXT: v_cvt_f32_f16_e64 v7, |v5|
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v6, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6
+; GFX9-NEXT: v_cvt_f32_f16_e64 v8, |v5|
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v7, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v8, v7
; GFX9-NEXT: s_cbranch_vccz .LBB10_11
-; GFX9-NEXT: ; %bb.8: ; %frem.compute52
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v11, v7
-; GFX9-NEXT: v_frexp_mant_f32_e32 v7, v7
-; GFX9-NEXT: v_ldexp_f32 v10, v7, 11
-; GFX9-NEXT: v_frexp_mant_f32_e32 v7, v6
-; GFX9-NEXT: v_ldexp_f32 v7, v7, 1
+; GFX9-NEXT: ; %bb.10: ; %frem.else53
+; GFX9-NEXT: v_and_b32_e32 v6, 0x8000, v5
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB10_12
+; GFX9-NEXT: .LBB10_11:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr6
+; GFX9-NEXT: .LBB10_12: ; %Flow131
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX9-NEXT: ; %bb.13: ; %frem.compute52
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v11, v8
+; GFX9-NEXT: v_frexp_mant_f32_e32 v6, v8
+; GFX9-NEXT: v_frexp_mant_f32_e32 v8, v7
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v12, v7
+; GFX9-NEXT: v_ldexp_f32 v7, v8, 1
; GFX9-NEXT: v_div_scale_f32 v13, s[2:3], v7, v7, 1.0
-; GFX9-NEXT: v_div_scale_f32 v9, vcc, 1.0, v7, 1.0
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v12, v6
+; GFX9-NEXT: v_div_scale_f32 v10, vcc, 1.0, v7, 1.0
+; GFX9-NEXT: v_ldexp_f32 v9, v6, 11
; GFX9-NEXT: v_add_u32_e32 v6, -1, v12
; GFX9-NEXT: v_not_b32_e32 v8, v6
; GFX9-NEXT: v_add_u32_e32 v8, v8, v11
@@ -8028,43 +8632,37 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v15, -v13, v14, 1.0
; GFX9-NEXT: v_fma_f32 v14, v15, v14, v14
-; GFX9-NEXT: v_mul_f32_e32 v15, v9, v14
-; GFX9-NEXT: v_fma_f32 v16, -v13, v15, v9
+; GFX9-NEXT: v_mul_f32_e32 v15, v10, v14
+; GFX9-NEXT: v_fma_f32 v16, -v13, v15, v10
; GFX9-NEXT: v_fma_f32 v15, v16, v14, v15
-; GFX9-NEXT: v_fma_f32 v9, -v13, v15, v9
+; GFX9-NEXT: v_fma_f32 v10, -v13, v15, v10
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v9, v9, v14, v15
+; GFX9-NEXT: v_div_fmas_f32 v10, v10, v14, v15
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v8
-; GFX9-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_12
-; GFX9-NEXT: ; %bb.9: ; %frem.loop_body60.preheader
+; GFX9-NEXT: v_div_fixup_f32 v10, v10, v7, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX9-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
; GFX9-NEXT: v_sub_u32_e32 v8, v11, v12
; GFX9-NEXT: v_add_u32_e32 v8, 11, v8
-; GFX9-NEXT: .LBB10_10: ; %frem.loop_body60
+; GFX9-NEXT: .LBB10_15: ; %frem.loop_body60
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v11, v10
-; GFX9-NEXT: v_mul_f32_e32 v10, v11, v9
-; GFX9-NEXT: v_rndne_f32_e32 v10, v10
-; GFX9-NEXT: v_fma_f32 v10, -v10, v7, v11
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
-; GFX9-NEXT: v_add_f32_e32 v12, v10, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
+; GFX9-NEXT: v_mov_b32_e32 v11, v9
+; GFX9-NEXT: v_mul_f32_e32 v9, v11, v10
+; GFX9-NEXT: v_rndne_f32_e32 v9, v9
+; GFX9-NEXT: v_fma_f32 v9, -v9, v7, v11
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
+; GFX9-NEXT: v_add_f32_e32 v12, v9, v7
; GFX9-NEXT: v_add_u32_e32 v8, -11, v8
-; GFX9-NEXT: v_ldexp_f32 v10, v10, 11
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v8
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_10
-; GFX9-NEXT: s_branch .LBB10_13
-; GFX9-NEXT: .LBB10_11: ; %frem.else53
-; GFX9-NEXT: v_and_b32_e32 v8, 0x8000, v5
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
-; GFX9-NEXT: s_branch .LBB10_14
-; GFX9-NEXT: .LBB10_12:
-; GFX9-NEXT: v_mov_b32_e32 v11, v10
-; GFX9-NEXT: .LBB10_13: ; %frem.loop_exit61
+; GFX9-NEXT: v_ldexp_f32 v9, v9, 11
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX9-NEXT: ; %bb.16: ; %Flow129
+; GFX9-NEXT: v_mov_b32_e32 v9, v11
+; GFX9-NEXT: .LBB10_17: ; %frem.loop_exit61
; GFX9-NEXT: v_add_u32_e32 v8, -10, v8
-; GFX9-NEXT: v_ldexp_f32 v8, v11, v8
-; GFX9-NEXT: v_mul_f32_e32 v9, v8, v9
+; GFX9-NEXT: v_ldexp_f32 v8, v9, v8
+; GFX9-NEXT: v_mul_f32_e32 v9, v8, v10
; GFX9-NEXT: v_rndne_f32_e32 v9, v9
; GFX9-NEXT: v_fma_f32 v8, -v9, v7, v8
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
@@ -8074,20 +8672,34 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v6, s2, v6, v5
-; GFX9-NEXT: .LBB10_14:
-; GFX9-NEXT: v_cvt_f32_f16_e64 v8, |v3|
-; GFX9-NEXT: v_cvt_f32_f16_e64 v7, |v1|
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v8, v7
-; GFX9-NEXT: s_cbranch_vccz .LBB10_18
-; GFX9-NEXT: ; %bb.15: ; %frem.compute19
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v12, v8
-; GFX9-NEXT: v_frexp_mant_f32_e32 v8, v8
-; GFX9-NEXT: v_ldexp_f32 v11, v8, 11
-; GFX9-NEXT: v_frexp_mant_f32_e32 v8, v7
-; GFX9-NEXT: v_ldexp_f32 v8, v8, 1
+; GFX9-NEXT: .LBB10_18:
+; GFX9-NEXT: v_cvt_f32_f16_e64 v9, |v3|
+; GFX9-NEXT: v_cvt_f32_f16_e64 v8, |v1|
+; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v9, v8
+; GFX9-NEXT: s_cbranch_vccz .LBB10_20
+; GFX9-NEXT: ; %bb.19: ; %frem.else20
+; GFX9-NEXT: v_and_b32_e32 v7, 0x8000, v3
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v9, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v7, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB10_21
+; GFX9-NEXT: .LBB10_20:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr7
+; GFX9-NEXT: .LBB10_21: ; %Flow127
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX9-NEXT: ; %bb.22: ; %frem.compute19
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v12, v9
+; GFX9-NEXT: v_frexp_mant_f32_e32 v7, v9
+; GFX9-NEXT: v_frexp_mant_f32_e32 v9, v8
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v13, v8
+; GFX9-NEXT: v_ldexp_f32 v8, v9, 1
; GFX9-NEXT: v_div_scale_f32 v14, s[2:3], v8, v8, 1.0
-; GFX9-NEXT: v_div_scale_f32 v10, vcc, 1.0, v8, 1.0
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v13, v7
+; GFX9-NEXT: v_div_scale_f32 v11, vcc, 1.0, v8, 1.0
+; GFX9-NEXT: v_ldexp_f32 v10, v7, 11
; GFX9-NEXT: v_add_u32_e32 v7, -1, v13
; GFX9-NEXT: v_not_b32_e32 v9, v7
; GFX9-NEXT: v_add_u32_e32 v9, v9, v12
@@ -8095,43 +8707,37 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v16, -v14, v15, 1.0
; GFX9-NEXT: v_fma_f32 v15, v16, v15, v15
-; GFX9-NEXT: v_mul_f32_e32 v16, v10, v15
-; GFX9-NEXT: v_fma_f32 v17, -v14, v16, v10
+; GFX9-NEXT: v_mul_f32_e32 v16, v11, v15
+; GFX9-NEXT: v_fma_f32 v17, -v14, v16, v11
; GFX9-NEXT: v_fma_f32 v16, v17, v15, v16
-; GFX9-NEXT: v_fma_f32 v10, -v14, v16, v10
+; GFX9-NEXT: v_fma_f32 v11, -v14, v16, v11
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v10, v10, v15, v16
+; GFX9-NEXT: v_div_fmas_f32 v11, v11, v15, v16
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v9
-; GFX9-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_19
-; GFX9-NEXT: ; %bb.16: ; %frem.loop_body27.preheader
+; GFX9-NEXT: v_div_fixup_f32 v11, v11, v8, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX9-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
; GFX9-NEXT: v_sub_u32_e32 v9, v12, v13
; GFX9-NEXT: v_add_u32_e32 v9, 11, v9
-; GFX9-NEXT: .LBB10_17: ; %frem.loop_body27
+; GFX9-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v12, v11
-; GFX9-NEXT: v_mul_f32_e32 v11, v12, v10
-; GFX9-NEXT: v_rndne_f32_e32 v11, v11
-; GFX9-NEXT: v_fma_f32 v11, -v11, v8, v12
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
-; GFX9-NEXT: v_add_f32_e32 v13, v11, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
+; GFX9-NEXT: v_mov_b32_e32 v12, v10
+; GFX9-NEXT: v_mul_f32_e32 v10, v12, v11
+; GFX9-NEXT: v_rndne_f32_e32 v10, v10
+; GFX9-NEXT: v_fma_f32 v10, -v10, v8, v12
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
+; GFX9-NEXT: v_add_f32_e32 v13, v10, v8
; GFX9-NEXT: v_add_u32_e32 v9, -11, v9
-; GFX9-NEXT: v_ldexp_f32 v11, v11, 11
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v9
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_17
-; GFX9-NEXT: s_branch .LBB10_20
-; GFX9-NEXT: .LBB10_18: ; %frem.else20
-; GFX9-NEXT: v_and_b32_e32 v9, 0x8000, v3
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
-; GFX9-NEXT: s_branch .LBB10_21
-; GFX9-NEXT: .LBB10_19:
-; GFX9-NEXT: v_mov_b32_e32 v12, v11
-; GFX9-NEXT: .LBB10_20: ; %frem.loop_exit28
+; GFX9-NEXT: v_ldexp_f32 v10, v10, 11
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_24
+; GFX9-NEXT: ; %bb.25: ; %Flow125
+; GFX9-NEXT: v_mov_b32_e32 v10, v12
+; GFX9-NEXT: .LBB10_26: ; %frem.loop_exit28
; GFX9-NEXT: v_add_u32_e32 v9, -10, v9
-; GFX9-NEXT: v_ldexp_f32 v9, v12, v9
-; GFX9-NEXT: v_mul_f32_e32 v10, v9, v10
+; GFX9-NEXT: v_ldexp_f32 v9, v10, v9
+; GFX9-NEXT: v_mul_f32_e32 v10, v9, v11
; GFX9-NEXT: v_rndne_f32_e32 v10, v10
; GFX9-NEXT: v_fma_f32 v9, -v10, v8, v9
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
@@ -8141,21 +8747,35 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v7, v7
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v7, s2, v7, v3
-; GFX9-NEXT: .LBB10_21:
+; GFX9-NEXT: .LBB10_27:
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX9-NEXT: v_cvt_f32_f16_e64 v10, |v8|
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v9, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v10, v9
-; GFX9-NEXT: s_cbranch_vccz .LBB10_25
-; GFX9-NEXT: ; %bb.22: ; %frem.compute
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v14, v10
-; GFX9-NEXT: v_frexp_mant_f32_e32 v10, v10
-; GFX9-NEXT: v_ldexp_f32 v13, v10, 11
-; GFX9-NEXT: v_frexp_mant_f32_e32 v10, v9
-; GFX9-NEXT: v_ldexp_f32 v10, v10, 1
+; GFX9-NEXT: v_cvt_f32_f16_e64 v11, |v8|
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v10, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v11, v10
+; GFX9-NEXT: s_cbranch_vccz .LBB10_29
+; GFX9-NEXT: ; %bb.28: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v9, 0x8000, v8
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v11, v10
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB10_30
+; GFX9-NEXT: .LBB10_29:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: .LBB10_30: ; %Flow123
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX9-NEXT: ; %bb.31: ; %frem.compute
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v14, v11
+; GFX9-NEXT: v_frexp_mant_f32_e32 v9, v11
+; GFX9-NEXT: v_frexp_mant_f32_e32 v11, v10
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v15, v10
+; GFX9-NEXT: v_ldexp_f32 v10, v11, 1
; GFX9-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
-; GFX9-NEXT: v_div_scale_f32 v12, vcc, 1.0, v10, 1.0
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v15, v9
+; GFX9-NEXT: v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
+; GFX9-NEXT: v_ldexp_f32 v12, v9, 11
; GFX9-NEXT: v_add_u32_e32 v9, -1, v15
; GFX9-NEXT: v_not_b32_e32 v11, v9
; GFX9-NEXT: v_add_u32_e32 v11, v11, v14
@@ -8163,43 +8783,37 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; GFX9-NEXT: v_fma_f32 v17, v18, v17, v17
-; GFX9-NEXT: v_mul_f32_e32 v18, v12, v17
-; GFX9-NEXT: v_fma_f32 v19, -v16, v18, v12
+; GFX9-NEXT: v_mul_f32_e32 v18, v13, v17
+; GFX9-NEXT: v_fma_f32 v19, -v16, v18, v13
; GFX9-NEXT: v_fma_f32 v18, v19, v17, v18
-; GFX9-NEXT: v_fma_f32 v12, -v16, v18, v12
+; GFX9-NEXT: v_fma_f32 v13, -v16, v18, v13
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v12, v12, v17, v18
+; GFX9-NEXT: v_div_fmas_f32 v13, v13, v17, v18
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v11
-; GFX9-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_26
-; GFX9-NEXT: ; %bb.23: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX9-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v11, v14, v15
; GFX9-NEXT: v_add_u32_e32 v11, 11, v11
-; GFX9-NEXT: .LBB10_24: ; %frem.loop_body
+; GFX9-NEXT: .LBB10_33: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v14, v13
-; GFX9-NEXT: v_mul_f32_e32 v13, v14, v12
-; GFX9-NEXT: v_rndne_f32_e32 v13, v13
-; GFX9-NEXT: v_fma_f32 v13, -v13, v10, v14
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
-; GFX9-NEXT: v_add_f32_e32 v15, v13, v10
-; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
+; GFX9-NEXT: v_mov_b32_e32 v14, v12
+; GFX9-NEXT: v_mul_f32_e32 v12, v14, v13
+; GFX9-NEXT: v_rndne_f32_e32 v12, v12
+; GFX9-NEXT: v_fma_f32 v12, -v12, v10, v14
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
+; GFX9-NEXT: v_add_f32_e32 v15, v12, v10
; GFX9-NEXT: v_add_u32_e32 v11, -11, v11
-; GFX9-NEXT: v_ldexp_f32 v13, v13, 11
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v11
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_24
-; GFX9-NEXT: s_branch .LBB10_27
-; GFX9-NEXT: .LBB10_25: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v11, 0x8000, v8
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v9
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v8, v11, vcc
-; GFX9-NEXT: s_branch .LBB10_28
-; GFX9-NEXT: .LBB10_26:
-; GFX9-NEXT: v_mov_b32_e32 v14, v13
-; GFX9-NEXT: .LBB10_27: ; %frem.loop_exit
+; GFX9-NEXT: v_ldexp_f32 v12, v12, 11
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_33
+; GFX9-NEXT: ; %bb.34: ; %Flow
+; GFX9-NEXT: v_mov_b32_e32 v12, v14
+; GFX9-NEXT: .LBB10_35: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v11, -10, v11
-; GFX9-NEXT: v_ldexp_f32 v11, v14, v11
-; GFX9-NEXT: v_mul_f32_e32 v12, v11, v12
+; GFX9-NEXT: v_ldexp_f32 v11, v12, v11
+; GFX9-NEXT: v_mul_f32_e32 v12, v11, v13
; GFX9-NEXT: v_rndne_f32_e32 v12, v12
; GFX9-NEXT: v_fma_f32 v11, -v12, v10, v11
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
@@ -8209,7 +8823,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v9, v9
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v9, s2, v9, v8
-; GFX9-NEXT: .LBB10_28:
+; GFX9-NEXT: .LBB10_36: ; %Flow124
; GFX9-NEXT: s_movk_i32 s6, 0x7c00
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v0
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v2|, s6
@@ -8220,7 +8834,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cmp_nge_f16_e64 s[4:5], |v5|, s6
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[2:3]
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v2, v6, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v1
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v3|, s6
; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
@@ -8229,7 +8843,6 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v3, v2, v7, vcc
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[2:3]
; GFX9-NEXT: v_cndmask_b32_sdwa v1, v2, v9, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -8246,24 +8859,38 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7] offset:32
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v5, |v2|
+; GFX10-NEXT: v_cvt_f32_f16_e64 v6, |v2|
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v4, |v0|
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX10-NEXT: s_cbranch_vccz .LBB10_5
-; GFX10-NEXT: ; %bb.1: ; %frem.compute85
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v5
-; GFX10-NEXT: v_frexp_mant_f32_e32 v5, v5
+; GFX10-NEXT: v_cvt_f32_f16_e64 v5, |v0|
+; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v6, v5
+; GFX10-NEXT: s_cbranch_vccz .LBB10_2
+; GFX10-NEXT: ; %bb.1: ; %frem.else86
+; GFX10-NEXT: v_and_b32_e32 v4, 0x8000, v2
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc_lo
+; GFX10-NEXT: s_branch .LBB10_3
+; GFX10-NEXT: .LBB10_2:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr4
+; GFX10-NEXT: .LBB10_3: ; %Flow135
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX10-NEXT: ; %bb.4: ; %frem.compute85
+; GFX10-NEXT: v_frexp_mant_f32_e32 v4, v6
+; GFX10-NEXT: v_frexp_mant_f32_e32 v8, v5
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
+; GFX10-NEXT: v_ldexp_f32 v6, v4, 11
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v4, v5
+; GFX10-NEXT: v_ldexp_f32 v5, v8, 1
; GFX10-NEXT: v_readfirstlane_b32 s2, v7
-; GFX10-NEXT: v_ldexp_f32 v6, v5, 11
-; GFX10-NEXT: v_frexp_mant_f32_e32 v5, v4
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
-; GFX10-NEXT: v_ldexp_f32 v5, v5, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v4
-; GFX10-NEXT: v_add_nc_u32_e32 v4, -1, v4
; GFX10-NEXT: v_div_scale_f32 v9, s4, v5, v5, 1.0
-; GFX10-NEXT: v_not_b32_e32 v8, v4
+; GFX10-NEXT: v_add_nc_u32_e32 v4, -1, v4
; GFX10-NEXT: v_rcp_f32_e32 v10, v9
+; GFX10-NEXT: v_not_b32_e32 v8, v4
; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX10-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -8277,11 +8904,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX10-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_6
-; GFX10-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_8
+; GFX10-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_3: ; %frem.loop_body93
+; GFX10-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -8293,20 +8920,13 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v8, v6, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v6, v6, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX10-NEXT: ; %bb.4:
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX10-NEXT: ; %bb.7: ; %Flow133
; GFX10-NEXT: v_mov_b32_e32 v8, s2
-; GFX10-NEXT: s_branch .LBB10_7
-; GFX10-NEXT: .LBB10_5: ; %frem.else86
-; GFX10-NEXT: v_and_b32_e32 v6, 0x8000, v2
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc_lo
-; GFX10-NEXT: s_branch .LBB10_8
-; GFX10-NEXT: .LBB10_6:
-; GFX10-NEXT: v_mov_b32_e32 v9, v6
-; GFX10-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX10-NEXT: v_add_nc_u32_e32 v6, -10, v8
-; GFX10-NEXT: v_ldexp_f32 v6, v9, v6
+; GFX10-NEXT: v_mov_b32_e32 v6, v9
+; GFX10-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX10-NEXT: v_add_nc_u32_e32 v8, -10, v8
+; GFX10-NEXT: v_ldexp_f32 v6, v6, v8
; GFX10-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX10-NEXT: v_rndne_f32_e32 v7, v7
; GFX10-NEXT: v_fma_f32 v6, -v7, v5, v6
@@ -8316,25 +8936,39 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v4, v5, v4
; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX10-NEXT: v_bfi_b32 v4, 0x7fff, v4, v2
-; GFX10-NEXT: .LBB10_8:
+; GFX10-NEXT: .LBB10_9:
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v6, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e64 v7, |v5|
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v6
-; GFX10-NEXT: s_cbranch_vccz .LBB10_13
-; GFX10-NEXT: ; %bb.9: ; %frem.compute52
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v9, v7
-; GFX10-NEXT: v_frexp_mant_f32_e32 v7, v7
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v8, |v5|
+; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v8, v7
+; GFX10-NEXT: s_cbranch_vccz .LBB10_11
+; GFX10-NEXT: ; %bb.10: ; %frem.else53
+; GFX10-NEXT: v_and_b32_e32 v6, 0x8000, v5
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo
+; GFX10-NEXT: s_branch .LBB10_12
+; GFX10-NEXT: .LBB10_11:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr6
+; GFX10-NEXT: .LBB10_12: ; %Flow131
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX10-NEXT: ; %bb.13: ; %frem.compute52
+; GFX10-NEXT: v_frexp_mant_f32_e32 v6, v8
+; GFX10-NEXT: v_frexp_mant_f32_e32 v10, v7
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v9, v8
+; GFX10-NEXT: v_ldexp_f32 v8, v6, 11
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v6, v7
+; GFX10-NEXT: v_ldexp_f32 v7, v10, 1
; GFX10-NEXT: v_readfirstlane_b32 s2, v9
-; GFX10-NEXT: v_ldexp_f32 v8, v7, 11
-; GFX10-NEXT: v_frexp_mant_f32_e32 v7, v6
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v6, v6
-; GFX10-NEXT: v_ldexp_f32 v7, v7, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v6
-; GFX10-NEXT: v_add_nc_u32_e32 v6, -1, v6
; GFX10-NEXT: v_div_scale_f32 v11, s4, v7, v7, 1.0
-; GFX10-NEXT: v_not_b32_e32 v10, v6
+; GFX10-NEXT: v_add_nc_u32_e32 v6, -1, v6
; GFX10-NEXT: v_rcp_f32_e32 v12, v11
+; GFX10-NEXT: v_not_b32_e32 v10, v6
; GFX10-NEXT: v_add_nc_u32_e32 v10, v10, v9
; GFX10-NEXT: v_div_scale_f32 v9, vcc_lo, 1.0, v7, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -8348,11 +8982,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v9, v9, v12, v13
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v10
; GFX10-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_14
-; GFX10-NEXT: ; %bb.10: ; %frem.loop_body60.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX10-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_11: ; %frem.loop_body60
+; GFX10-NEXT: .LBB10_15: ; %frem.loop_body60
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v11, v8
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -8364,20 +8998,13 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v10, v8, v7
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_11
-; GFX10-NEXT: ; %bb.12:
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX10-NEXT: ; %bb.16: ; %Flow129
; GFX10-NEXT: v_mov_b32_e32 v10, s2
-; GFX10-NEXT: s_branch .LBB10_15
-; GFX10-NEXT: .LBB10_13: ; %frem.else53
-; GFX10-NEXT: v_and_b32_e32 v8, 0x8000, v5
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc_lo
-; GFX10-NEXT: s_branch .LBB10_16
-; GFX10-NEXT: .LBB10_14:
-; GFX10-NEXT: v_mov_b32_e32 v11, v8
-; GFX10-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX10-NEXT: v_add_nc_u32_e32 v8, -10, v10
-; GFX10-NEXT: v_ldexp_f32 v8, v11, v8
+; GFX10-NEXT: v_mov_b32_e32 v8, v11
+; GFX10-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX10-NEXT: v_add_nc_u32_e32 v10, -10, v10
+; GFX10-NEXT: v_ldexp_f32 v8, v8, v10
; GFX10-NEXT: v_mul_f32_e32 v9, v8, v9
; GFX10-NEXT: v_rndne_f32_e32 v9, v9
; GFX10-NEXT: v_fma_f32 v8, -v9, v7, v8
@@ -8387,24 +9014,38 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v6, v7, v6
; GFX10-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX10-NEXT: v_bfi_b32 v6, 0x7fff, v6, v5
-; GFX10-NEXT: .LBB10_16:
-; GFX10-NEXT: v_cvt_f32_f16_e64 v8, |v3|
-; GFX10-NEXT: v_cvt_f32_f16_e64 v7, |v1|
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7
-; GFX10-NEXT: s_cbranch_vccz .LBB10_21
-; GFX10-NEXT: ; %bb.17: ; %frem.compute19
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v10, v8
-; GFX10-NEXT: v_frexp_mant_f32_e32 v8, v8
+; GFX10-NEXT: .LBB10_18:
+; GFX10-NEXT: v_cvt_f32_f16_e64 v9, |v3|
+; GFX10-NEXT: v_cvt_f32_f16_e64 v8, |v1|
+; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
+; GFX10-NEXT: s_cbranch_vccz .LBB10_20
+; GFX10-NEXT: ; %bb.19: ; %frem.else20
+; GFX10-NEXT: v_and_b32_e32 v7, 0x8000, v3
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v7, vcc_lo
+; GFX10-NEXT: s_branch .LBB10_21
+; GFX10-NEXT: .LBB10_20:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr7
+; GFX10-NEXT: .LBB10_21: ; %Flow127
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX10-NEXT: ; %bb.22: ; %frem.compute19
+; GFX10-NEXT: v_frexp_mant_f32_e32 v7, v9
+; GFX10-NEXT: v_frexp_mant_f32_e32 v11, v8
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
+; GFX10-NEXT: v_ldexp_f32 v9, v7, 11
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v8
+; GFX10-NEXT: v_ldexp_f32 v8, v11, 1
; GFX10-NEXT: v_readfirstlane_b32 s2, v10
-; GFX10-NEXT: v_ldexp_f32 v9, v8, 11
-; GFX10-NEXT: v_frexp_mant_f32_e32 v8, v7
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v7
-; GFX10-NEXT: v_ldexp_f32 v8, v8, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v7
-; GFX10-NEXT: v_add_nc_u32_e32 v7, -1, v7
; GFX10-NEXT: v_div_scale_f32 v12, s4, v8, v8, 1.0
-; GFX10-NEXT: v_not_b32_e32 v11, v7
+; GFX10-NEXT: v_add_nc_u32_e32 v7, -1, v7
; GFX10-NEXT: v_rcp_f32_e32 v13, v12
+; GFX10-NEXT: v_not_b32_e32 v11, v7
; GFX10-NEXT: v_add_nc_u32_e32 v11, v11, v10
; GFX10-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -8418,11 +9059,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v10, v10, v13, v14
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
; GFX10-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_22
-; GFX10-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX10-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_19: ; %frem.loop_body27
+; GFX10-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v12, v9
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -8434,20 +9075,13 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v11, v9, v8
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v9, v9, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX10-NEXT: ; %bb.20:
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX10-NEXT: ; %bb.25: ; %Flow125
; GFX10-NEXT: v_mov_b32_e32 v11, s2
-; GFX10-NEXT: s_branch .LBB10_23
-; GFX10-NEXT: .LBB10_21: ; %frem.else20
-; GFX10-NEXT: v_and_b32_e32 v9, 0x8000, v3
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc_lo
-; GFX10-NEXT: s_branch .LBB10_24
-; GFX10-NEXT: .LBB10_22:
-; GFX10-NEXT: v_mov_b32_e32 v12, v9
-; GFX10-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX10-NEXT: v_add_nc_u32_e32 v9, -10, v11
-; GFX10-NEXT: v_ldexp_f32 v9, v12, v9
+; GFX10-NEXT: v_mov_b32_e32 v9, v12
+; GFX10-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX10-NEXT: v_add_nc_u32_e32 v11, -10, v11
+; GFX10-NEXT: v_ldexp_f32 v9, v9, v11
; GFX10-NEXT: v_mul_f32_e32 v10, v9, v10
; GFX10-NEXT: v_rndne_f32_e32 v10, v10
; GFX10-NEXT: v_fma_f32 v9, -v10, v8, v9
@@ -8457,25 +9091,39 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v7, v8, v7
; GFX10-NEXT: v_cvt_f16_f32_e32 v7, v7
; GFX10-NEXT: v_bfi_b32 v7, 0x7fff, v7, v3
-; GFX10-NEXT: .LBB10_24:
+; GFX10-NEXT: .LBB10_27:
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v9, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e64 v10, |v8|
-; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v9
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v10, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v11, |v8|
+; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v11, v10
; GFX10-NEXT: s_cbranch_vccz .LBB10_29
-; GFX10-NEXT: ; %bb.25: ; %frem.compute
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v12, v10
-; GFX10-NEXT: v_frexp_mant_f32_e32 v10, v10
+; GFX10-NEXT: ; %bb.28: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v9, 0x8000, v8
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v11, v10
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc_lo
+; GFX10-NEXT: s_branch .LBB10_30
+; GFX10-NEXT: .LBB10_29:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr9
+; GFX10-NEXT: .LBB10_30: ; %Flow123
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX10-NEXT: ; %bb.31: ; %frem.compute
+; GFX10-NEXT: v_frexp_mant_f32_e32 v9, v11
+; GFX10-NEXT: v_frexp_mant_f32_e32 v13, v10
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v12, v11
+; GFX10-NEXT: v_ldexp_f32 v11, v9, 11
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v9, v10
+; GFX10-NEXT: v_ldexp_f32 v10, v13, 1
; GFX10-NEXT: v_readfirstlane_b32 s2, v12
-; GFX10-NEXT: v_ldexp_f32 v11, v10, 11
-; GFX10-NEXT: v_frexp_mant_f32_e32 v10, v9
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v9, v9
-; GFX10-NEXT: v_ldexp_f32 v10, v10, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v9
-; GFX10-NEXT: v_add_nc_u32_e32 v9, -1, v9
; GFX10-NEXT: v_div_scale_f32 v14, s4, v10, v10, 1.0
-; GFX10-NEXT: v_not_b32_e32 v13, v9
+; GFX10-NEXT: v_add_nc_u32_e32 v9, -1, v9
; GFX10-NEXT: v_rcp_f32_e32 v15, v14
+; GFX10-NEXT: v_not_b32_e32 v13, v9
; GFX10-NEXT: v_add_nc_u32_e32 v13, v13, v12
; GFX10-NEXT: v_div_scale_f32 v12, vcc_lo, 1.0, v10, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -8489,11 +9137,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v12, v12, v15, v16
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v13
; GFX10-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_30
-; GFX10-NEXT: ; %bb.26: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX10-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_27: ; %frem.loop_body
+; GFX10-NEXT: .LBB10_33: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v14, v11
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -8505,20 +9153,13 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v13, v11, v10
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX10-NEXT: ; %bb.28:
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_33
+; GFX10-NEXT: ; %bb.34: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v13, s2
-; GFX10-NEXT: s_branch .LBB10_31
-; GFX10-NEXT: .LBB10_29: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v11, 0x8000, v8
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v11, vcc_lo
-; GFX10-NEXT: s_branch .LBB10_32
-; GFX10-NEXT: .LBB10_30:
-; GFX10-NEXT: v_mov_b32_e32 v14, v11
-; GFX10-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v11, -10, v13
-; GFX10-NEXT: v_ldexp_f32 v11, v14, v11
+; GFX10-NEXT: v_mov_b32_e32 v11, v14
+; GFX10-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX10-NEXT: v_add_nc_u32_e32 v13, -10, v13
+; GFX10-NEXT: v_ldexp_f32 v11, v11, v13
; GFX10-NEXT: v_mul_f32_e32 v12, v11, v12
; GFX10-NEXT: v_rndne_f32_e32 v12, v12
; GFX10-NEXT: v_fma_f32 v11, -v12, v10, v11
@@ -8528,7 +9169,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v9, v10, v9
; GFX10-NEXT: v_cvt_f16_f32_e32 v9, v9
; GFX10-NEXT: v_bfi_b32 v9, 0x7fff, v9, v8
-; GFX10-NEXT: .LBB10_32:
+; GFX10-NEXT: .LBB10_36: ; %Flow124
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v2|
; GFX10-NEXT: v_cmp_nle_f16_e64 s3, 0x7c00, |v5|
@@ -8563,27 +9204,44 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v2, s[4:5] offset:32
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v4, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, |v0.l|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v5, |v2.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_5
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.compute85
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v5
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v6, v5
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else86
+; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB10_3
+; GFX11-TRUE16-NEXT: .LBB10_2:
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: .LBB10_3: ; %Flow135
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v6
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v5
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, v4
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v7
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, -1, v5
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v7, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v7, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v6, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, null, v5, v5, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v6, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v5, 1.0
@@ -8602,12 +9260,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v5, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_4
-; GFX11-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_3: ; %frem.loop_body93
+; GFX11-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v4, v6
@@ -8622,39 +9280,50 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX11-TRUE16-NEXT: .LBB10_4: ; %frem.loop_exit94
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX11-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
-; GFX11-TRUE16-NEXT: s_branch .LBB10_6
-; GFX11-TRUE16-NEXT: .LBB10_5: ; %frem.else86
-; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: .LBB10_6:
+; GFX11-TRUE16-NEXT: .LBB10_8:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, |v5.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, |v5.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, |v6.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_11
-; GFX11-TRUE16-NEXT: ; %bb.7: ; %frem.compute52
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v10, v8
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_10
+; GFX11-TRUE16-NEXT: ; %bb.9: ; %frem.else53
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB10_11
+; GFX11-TRUE16-NEXT: .LBB10_10:
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
+; GFX11-TRUE16-NEXT: .LBB10_11: ; %Flow131
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
+; GFX11-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v9
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v9, v8
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v8
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v9, v7
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v10
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v8
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v10, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v9
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v10, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v9, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v9, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v11, null, v8, v8, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v10, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v9, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v12, v11
; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, vcc_lo, 1.0, v8, 1.0
@@ -8673,12 +9342,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v9, v9, v12, v13
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v10
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v9, v9, v8, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_10
-; GFX11-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body60.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_9: ; %frem.loop_body60
+; GFX11-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v7, v9
@@ -8693,36 +9362,47 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
-; GFX11-TRUE16-NEXT: .LBB10_10: ; %frem.loop_exit61
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
+; GFX11-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-TRUE16-NEXT: s_branch .LBB10_12
-; GFX11-TRUE16-NEXT: .LBB10_11: ; %frem.else53
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: .LBB10_12:
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, |v1.l|
+; GFX11-TRUE16-NEXT: .LBB10_16:
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v10, |v1.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, |v3.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_17
-; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.compute19
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v9
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v10, v9
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_18
+; GFX11-TRUE16-NEXT: ; %bb.17: ; %frem.else20
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB10_19
+; GFX11-TRUE16-NEXT: .LBB10_18:
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
+; GFX11-TRUE16-NEXT: .LBB10_19: ; %Flow127
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX11-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v10
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v10, v9
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v9, v9
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v8
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v11
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, -1, v9
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v11, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v10
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v11, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v10, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v10, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v12, null, v9, v9, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v10, v11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v13, v12
; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v9, 1.0
@@ -8741,12 +9421,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v10, v10, v13, v14
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v10, v10, v9, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_16
-; GFX11-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX11-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v8, v10
@@ -8761,39 +9441,50 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
-; GFX11-TRUE16-NEXT: .LBB10_16: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
+; GFX11-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-TRUE16-NEXT: s_branch .LBB10_18
-; GFX11-TRUE16-NEXT: .LBB10_17: ; %frem.else20
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: .LBB10_18:
+; GFX11-TRUE16-NEXT: .LBB10_24:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v11, |v9.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v13, |v9.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v12, |v10.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_23
-; GFX11-TRUE16-NEXT: ; %bb.19: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v14, v12
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v13, v12
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_26
+; GFX11-TRUE16-NEXT: ; %bb.25: ; %frem.else
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v13, v12
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB10_27
+; GFX11-TRUE16-NEXT: .LBB10_26:
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
+; GFX11-TRUE16-NEXT: .LBB10_27: ; %Flow123
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
+; GFX11-TRUE16-NEXT: ; %bb.28: ; %frem.compute
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v13
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v13
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v13, v12
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v12, v12
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v13, v11
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v14
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, -1, v12
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v12, v14, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v13
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v14, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v12, v13, 1
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v15, null, v12, v12, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v14, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v13, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v16, v15
; GFX11-TRUE16-NEXT: v_div_scale_f32 v13, vcc_lo, 1.0, v12, 1.0
@@ -8812,12 +9503,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v13, v13, v16, v17
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v14
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v13, v13, v12, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_22
-; GFX11-TRUE16-NEXT: ; %bb.20: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX11-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_21: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v11, v13
@@ -8832,16 +9523,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_21
-; GFX11-TRUE16-NEXT: .LBB10_22: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
+; GFX11-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-TRUE16-NEXT: s_branch .LBB10_24
-; GFX11-TRUE16-NEXT: .LBB10_23: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v11, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: .LBB10_24:
+; GFX11-TRUE16-NEXT: .LBB10_32: ; %Flow124
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
@@ -8874,29 +9559,45 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-FAKE16-NEXT: global_load_b64 v[2:3], v2, s[4:5] offset:32
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v5, |v0|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, |v0|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v4, |v2|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v5, |v2|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_5
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.compute85
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v5
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v6, v5
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_2
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.else86
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x8000, v0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB10_3
+; GFX11-FAKE16-NEXT: .LBB10_2:
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT: .LBB10_3: ; %Flow135
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, v6
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v8, v5
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v4, 11
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v5
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, v8, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v7
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v5, 11
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v5, v4
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, v5, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_scale_f32 v9, null, v5, v5, 1.0
-; GFX11-FAKE16-NEXT: v_not_b32_e32 v8, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v10, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_not_b32_e32 v8, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX11-FAKE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -8915,12 +9616,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_6
-; GFX11-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_8
+; GFX11-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_3: ; %frem.loop_body93
+; GFX11-FAKE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v6
@@ -8936,22 +9637,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v6, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX11-FAKE16-NEXT: ; %bb.4:
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX11-FAKE16-NEXT: ; %bb.7: ; %Flow133
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s2
-; GFX11-FAKE16-NEXT: s_branch .LBB10_7
-; GFX11-FAKE16-NEXT: .LBB10_5: ; %frem.else86
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0x8000, v0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v0, v6, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB10_8
-; GFX11-FAKE16-NEXT: .LBB10_6:
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v6
-; GFX11-FAKE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v8
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v9, v6
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v9
+; GFX11-FAKE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, -10, v8
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v6, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v7, v7
@@ -8965,32 +9658,48 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: v_bfi_b32 v4, 0x7fff, v4, v0
-; GFX11-FAKE16-NEXT: .LBB10_8:
+; GFX11-FAKE16-NEXT: .LBB10_9:
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v8, |v5|
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v7, |v6|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, |v5|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v8, |v6|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_13
-; GFX11-FAKE16-NEXT: ; %bb.9: ; %frem.compute52
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v8
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v8, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_11
+; GFX11-FAKE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0x8000, v5
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB10_12
+; GFX11-FAKE16-NEXT: .LBB10_11:
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT: .LBB10_12: ; %Flow131
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX11-FAKE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v7, v9
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v11, v8
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v7, 11
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v8
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v8, v11, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v10
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v8, 11
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v8, v7
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v8, v8, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, -1, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_scale_f32 v12, null, v8, v8, 1.0
-; GFX11-FAKE16-NEXT: v_not_b32_e32 v11, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, -1, v7
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v13, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_not_b32_e32 v11, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v10
; GFX11-FAKE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -9009,12 +9718,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_14
-; GFX11-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body60.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX11-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_11: ; %frem.loop_body60
+; GFX11-FAKE16-NEXT: .LBB10_15: ; %frem.loop_body60
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v12, v9
@@ -9030,22 +9739,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v9, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
-; GFX11-FAKE16-NEXT: ; %bb.12:
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX11-FAKE16-NEXT: ; %bb.16: ; %Flow129
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, s2
-; GFX11-FAKE16-NEXT: s_branch .LBB10_15
-; GFX11-FAKE16-NEXT: .LBB10_13: ; %frem.else53
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0x8000, v5
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v5, v9, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB10_16
-; GFX11-FAKE16-NEXT: .LBB10_14:
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v12, v9
-; GFX11-FAKE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, -10, v11
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v12, v9
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v12
+; GFX11-FAKE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, -10, v11
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v9, v11
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v10, v9, v10
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v10, v10
@@ -9059,29 +9760,45 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v7, v7
; GFX11-FAKE16-NEXT: v_bfi_b32 v7, 0x7fff, v7, v5
-; GFX11-FAKE16-NEXT: .LBB10_16:
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, |v1|
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v8, |v3|
+; GFX11-FAKE16-NEXT: .LBB10_18:
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v10, |v1|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, |v3|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_21
-; GFX11-FAKE16-NEXT: ; %bb.17: ; %frem.compute19
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v9
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v9, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v10, v9
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_20
+; GFX11-FAKE16-NEXT: ; %bb.19: ; %frem.else20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x8000, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v1, v8, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB10_21
+; GFX11-FAKE16-NEXT: .LBB10_20:
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT: .LBB10_21: ; %Flow127
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX11-FAKE16-NEXT: ; %bb.22: ; %frem.compute19
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v8, v10
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v12, v9
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v8, 11
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v9
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v12, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v11
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v9, 11
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v9, v8
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v9, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, -1, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_scale_f32 v13, null, v9, v9, 1.0
-; GFX11-FAKE16-NEXT: v_not_b32_e32 v12, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, -1, v8
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v14, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_not_b32_e32 v12, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v11
; GFX11-FAKE16-NEXT: v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -9100,12 +9817,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v12
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_22
-; GFX11-FAKE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX11-FAKE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_19: ; %frem.loop_body27
+; GFX11-FAKE16-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, v10
@@ -9121,22 +9838,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v10, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX11-FAKE16-NEXT: ; %bb.20:
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX11-FAKE16-NEXT: ; %bb.25: ; %Flow125
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v12, s2
-; GFX11-FAKE16-NEXT: s_branch .LBB10_23
-; GFX11-FAKE16-NEXT: .LBB10_21: ; %frem.else20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0x8000, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v1, v10, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB10_24
-; GFX11-FAKE16-NEXT: .LBB10_22:
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, v10
-; GFX11-FAKE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, -10, v12
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v13, v10
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, v13
+; GFX11-FAKE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, -10, v12
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v10, v12
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v11, v10, v11
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v11, v11
@@ -9150,32 +9859,48 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v8, v8
; GFX11-FAKE16-NEXT: v_bfi_b32 v8, 0x7fff, v8, v1
-; GFX11-FAKE16-NEXT: .LBB10_24:
+; GFX11-FAKE16-NEXT: .LBB10_27:
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v12, |v9|
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v11, |v10|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v13, |v9|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v12, |v10|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v11
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v13, v12
; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_29
-; GFX11-FAKE16-NEXT: ; %bb.25: ; %frem.compute
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v12
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v12, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: ; %bb.28: ; %frem.else
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0x8000, v9
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v13, v12
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v11, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB10_30
+; GFX11-FAKE16-NEXT: .LBB10_29:
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT: .LBB10_30: ; %Flow123
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX11-FAKE16-NEXT: ; %bb.31: ; %frem.compute
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v11, v13
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v15, v12
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v13
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v11, 11
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v12
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v12, v15, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v14
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v12, 11
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v12, v11
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v12, v12, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, -1, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_scale_f32 v16, null, v12, v12, 1.0
-; GFX11-FAKE16-NEXT: v_not_b32_e32 v15, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, -1, v11
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v17, v16
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_not_b32_e32 v15, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v14
; GFX11-FAKE16-NEXT: v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -9194,12 +9919,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_30
-; GFX11-FAKE16-NEXT: ; %bb.26: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX11-FAKE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_27: ; %frem.loop_body
+; GFX11-FAKE16-NEXT: .LBB10_33: ; %frem.loop_body
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v16, v13
@@ -9215,22 +9940,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v13, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX11-FAKE16-NEXT: ; %bb.28:
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_33
+; GFX11-FAKE16-NEXT: ; %bb.34: ; %Flow
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v15, s2
-; GFX11-FAKE16-NEXT: s_branch .LBB10_31
-; GFX11-FAKE16-NEXT: .LBB10_29: ; %frem.else
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0x8000, v9
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v12, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v13, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB10_32
-; GFX11-FAKE16-NEXT: .LBB10_30:
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v16, v13
-; GFX11-FAKE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, -10, v15
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v16, v13
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, v16
+; GFX11-FAKE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, -10, v15
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v13, v15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v14, v13, v14
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v14, v14
@@ -9244,7 +9961,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v11, v11
; GFX11-FAKE16-NEXT: v_bfi_b32 v11, 0x7fff, v11, v9
-; GFX11-FAKE16-NEXT: .LBB10_32:
+; GFX11-FAKE16-NEXT: .LBB10_36: ; %Flow124
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -9283,25 +10000,42 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[8:9] offset:32
; GFX1150-TRUE16-NEXT: s_and_b32 s3, s5, 0x7fff
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s3
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s3
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1150-TRUE16-NEXT: s_and_b32 s8, s4, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1150-TRUE16-NEXT: s_and_b32 s6, s4, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s6, s8
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_5
-; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.compute85
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s8, s6
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_2
+; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.else86
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s8, s6
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s5
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s9
+; GFX1150-TRUE16-NEXT: s_mov_b32 s9, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_3
+; GFX1150-TRUE16-NEXT: .LBB10_2:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s9, -1
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1150-TRUE16-NEXT: .LBB10_3: ; %Flow135
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
+; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v2
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9325,12 +10059,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_4
-; GFX1150-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s6, s8
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s8, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-TRUE16-NEXT: .LBB10_3: ; %frem.loop_body93
+; GFX1150-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -9346,36 +10080,46 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX1150-TRUE16-NEXT: .LBB10_4: ; %frem.loop_exit94
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX1150-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_6
-; GFX1150-TRUE16-NEXT: .LBB10_5: ; %frem.else86
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s6, s8
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s5
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s6, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s6
-; GFX1150-TRUE16-NEXT: .LBB10_6:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
+; GFX1150-TRUE16-NEXT: .LBB10_8:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
+; GFX1150-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s8, s6, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s5
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s10, s9
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_11
-; GFX1150-TRUE16-NEXT: ; %bb.7: ; %frem.compute52
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s10
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s10
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
+; GFX1150-TRUE16-NEXT: ; %bb.9: ; %frem.else53
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
+; GFX1150-TRUE16-NEXT: s_mov_b32 s10, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_11
+; GFX1150-TRUE16-NEXT: .LBB10_10:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s10, -1
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX1150-TRUE16-NEXT: .LBB10_11: ; %Flow131
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s10, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s10, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
+; GFX1150-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v4
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v3
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9399,12 +10143,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_10
-; GFX1150-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body60.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s8, s8, s9
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s8, s9, s8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s8, s8, 11
-; GFX1150-TRUE16-NEXT: .LBB10_9: ; %frem.loop_body60
+; GFX1150-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -9420,34 +10164,44 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
-; GFX1150-TRUE16-NEXT: .LBB10_10: ; %frem.loop_exit61
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
+; GFX1150-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_12
-; GFX1150-TRUE16-NEXT: .LBB10_11: ; %frem.else53
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
-; GFX1150-TRUE16-NEXT: .LBB10_12:
+; GFX1150-TRUE16-NEXT: .LBB10_16:
; GFX1150-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s10, s2, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s8
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1150-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s8
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s9, s10
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_17
-; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.compute19
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s10
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
+; GFX1150-TRUE16-NEXT: ; %bb.17: ; %frem.else20
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
+; GFX1150-TRUE16-NEXT: s_mov_b32 s11, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_19
+; GFX1150-TRUE16-NEXT: .LBB10_18:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s11, -1
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1150-TRUE16-NEXT: .LBB10_19: ; %Flow127
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1150-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s10
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v4
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9471,12 +10225,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_16
-; GFX1150-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body27.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s9, s10
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX1150-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -9492,36 +10246,46 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
-; GFX1150-TRUE16-NEXT: .LBB10_16: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
+; GFX1150-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_18
-; GFX1150-TRUE16-NEXT: .LBB10_17: ; %frem.else20
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s9, s10
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s9
-; GFX1150-TRUE16-NEXT: .LBB10_18:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
+; GFX1150-TRUE16-NEXT: .LBB10_24:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
+; GFX1150-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s10, s9, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s11, s7
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s12, s11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_23
-; GFX1150-TRUE16-NEXT: ; %bb.19: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s11
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s11
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s12
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s12
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
+; GFX1150-TRUE16-NEXT: ; %bb.25: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
+; GFX1150-TRUE16-NEXT: s_mov_b32 s12, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_27
+; GFX1150-TRUE16-NEXT: .LBB10_26:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s12, -1
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX1150-TRUE16-NEXT: .LBB10_27: ; %Flow123
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
+; GFX1150-TRUE16-NEXT: ; %bb.28: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s11, v5
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v4, v4, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9545,12 +10309,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_22
-; GFX1150-TRUE16-NEXT: ; %bb.20: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s10, s10, s11
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX1150-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s10, s11, s10
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s10, s10, 11
-; GFX1150-TRUE16-NEXT: .LBB10_21: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
@@ -9566,17 +10330,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_21
-; GFX1150-TRUE16-NEXT: .LBB10_22: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
+; GFX1150-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_24
-; GFX1150-TRUE16-NEXT: .LBB10_23: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s12, s11
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s11
-; GFX1150-TRUE16-NEXT: .LBB10_24:
+; GFX1150-TRUE16-NEXT: .LBB10_32: ; %Flow124
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1150-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -9623,28 +10380,46 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: global_load_b64 v[0:1], v2, s[8:9] offset:32
; GFX1150-FAKE16-NEXT: s_and_b32 s3, s5, 0x7fff
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s6, s3
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s8, s3
; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1150-FAKE16-NEXT: s_and_b32 s8, s4, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1150-FAKE16-NEXT: s_and_b32 s6, s4, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s6, s8
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_5
-; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.compute85
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s8
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s8, s6
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_2
+; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.else86
+; GFX1150-FAKE16-NEXT: s_and_b32 s9, 0x8000, s5
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s8, s6
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v0, s9
+; GFX1150-FAKE16-NEXT: s_mov_b32 s9, 0
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_3
+; GFX1150-FAKE16-NEXT: .LBB10_2:
+; GFX1150-FAKE16-NEXT: s_mov_b32 s9, -1
+; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1150-FAKE16-NEXT: .LBB10_3: ; %Flow135
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1150-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s9, 1
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s6
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s8
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v1, v1, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s8
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s8, v0
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -9666,12 +10441,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_6
-; GFX1150-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s6, s6, s8
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_8
+; GFX1150-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s6, s8, s6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-FAKE16-NEXT: .LBB10_3: ; %frem.loop_body93
+; GFX1150-FAKE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -9689,24 +10464,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX1150-FAKE16-NEXT: ; %bb.4:
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX1150-FAKE16-NEXT: ; %bb.7: ; %Flow133
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, s6
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_7
-; GFX1150-FAKE16-NEXT: .LBB10_5: ; %frem.else86
-; GFX1150-FAKE16-NEXT: s_and_b32 s9, 0x8000, s5
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s6, s8
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v0, s9
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_8
-; GFX1150-FAKE16-NEXT: .LBB10_6:
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX1150-FAKE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v2, -10, v4
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v5, v2
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-FAKE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v3, v3
@@ -9722,29 +10487,47 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s5
-; GFX1150-FAKE16-NEXT: .LBB10_8:
+; GFX1150-FAKE16-NEXT: .LBB10_9:
; GFX1150-FAKE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1150-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1150-FAKE16-NEXT: s_and_b32 s5, s8, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s10, s6, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s9, s5
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1150-FAKE16-NEXT: s_and_b32 s9, s6, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s10, s5
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s9, s10
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_13
-; GFX1150-FAKE16-NEXT: ; %bb.9: ; %frem.compute52
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s9
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
+; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_11
+; GFX1150-FAKE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX1150-FAKE16-NEXT: s_and_b32 s11, 0x8000, s8
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v1, s11
+; GFX1150-FAKE16-NEXT: s_mov_b32 s11, 0
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_12
+; GFX1150-FAKE16-NEXT: .LBB10_11:
+; GFX1150-FAKE16-NEXT: s_mov_b32 s11, -1
+; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr1
+; GFX1150-FAKE16-NEXT: .LBB10_12: ; %Flow131
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-FAKE16-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX1150-FAKE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s10
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s10
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s9, v4
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s10, v4
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s10, v1
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s9, v1
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -9766,12 +10549,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_14
-; GFX1150-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body60.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s9, s9, s10
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX1150-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-FAKE16-NEXT: .LBB10_11: ; %frem.loop_body60
+; GFX1150-FAKE16-NEXT: .LBB10_15: ; %frem.loop_body60
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -9789,24 +10572,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
-; GFX1150-FAKE16-NEXT: ; %bb.12:
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX1150-FAKE16-NEXT: ; %bb.16: ; %Flow129
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, s9
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_15
-; GFX1150-FAKE16-NEXT: .LBB10_13: ; %frem.else53
-; GFX1150-FAKE16-NEXT: s_and_b32 s11, 0x8000, s8
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s9, s10
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v1, s11
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_16
-; GFX1150-FAKE16-NEXT: .LBB10_14:
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX1150-FAKE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v3, -10, v5
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v6, v3
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-FAKE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v4, v4
@@ -9822,27 +10595,45 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s8
-; GFX1150-FAKE16-NEXT: .LBB10_16:
+; GFX1150-FAKE16-NEXT: .LBB10_18:
; GFX1150-FAKE16-NEXT: s_and_b32 s8, s7, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s10, s2, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s9, s8
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1150-FAKE16-NEXT: s_and_b32 s9, s2, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s10, s8
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s9, s10
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_21
-; GFX1150-FAKE16-NEXT: ; %bb.17: ; %frem.compute19
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s10
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s9
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
+; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_20
+; GFX1150-FAKE16-NEXT: ; %bb.19: ; %frem.else20
+; GFX1150-FAKE16-NEXT: s_and_b32 s11, 0x8000, s7
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, s11
+; GFX1150-FAKE16-NEXT: s_mov_b32 s11, 0
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_21
+; GFX1150-FAKE16-NEXT: .LBB10_20:
+; GFX1150-FAKE16-NEXT: s_mov_b32 s11, -1
+; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr2
+; GFX1150-FAKE16-NEXT: .LBB10_21: ; %Flow127
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-FAKE16-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX1150-FAKE16-NEXT: ; %bb.22: ; %frem.compute19
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s9
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s10
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s10
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s9, v5
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s10, v5
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s10, v2
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s9, v2
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -9864,12 +10655,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_22
-; GFX1150-FAKE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s9, s9, s10
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX1150-FAKE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-FAKE16-NEXT: .LBB10_19: ; %frem.loop_body27
+; GFX1150-FAKE16-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -9887,24 +10678,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX1150-FAKE16-NEXT: ; %bb.20:
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1150-FAKE16-NEXT: ; %bb.25: ; %Flow125
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, s9
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_23
-; GFX1150-FAKE16-NEXT: .LBB10_21: ; %frem.else20
-; GFX1150-FAKE16-NEXT: s_and_b32 s11, 0x8000, s7
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s9, s10
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, s11
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_24
-; GFX1150-FAKE16-NEXT: .LBB10_22:
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, v4
-; GFX1150-FAKE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1150-FAKE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -9920,29 +10701,47 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, s7
-; GFX1150-FAKE16-NEXT: .LBB10_24:
+; GFX1150-FAKE16-NEXT: .LBB10_27:
; GFX1150-FAKE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1150-FAKE16-NEXT: s_lshr_b32 s9, s2, 16
; GFX1150-FAKE16-NEXT: s_and_b32 s7, s10, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s12, s9, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s11, s7
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s12, s12
+; GFX1150-FAKE16-NEXT: s_and_b32 s11, s9, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s12, s7
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s11, s11
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s11, s12
+; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s12, s11
; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_29
-; GFX1150-FAKE16-NEXT: ; %bb.25: ; %frem.compute
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, s12
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s11
+; GFX1150-FAKE16-NEXT: ; %bb.28: ; %frem.else
+; GFX1150-FAKE16-NEXT: s_and_b32 s13, 0x8000, s10
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s12, s11
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, s13
+; GFX1150-FAKE16-NEXT: s_mov_b32 s13, 0
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_30
+; GFX1150-FAKE16-NEXT: .LBB10_29:
+; GFX1150-FAKE16-NEXT: s_mov_b32 s13, -1
+; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr3
+; GFX1150-FAKE16-NEXT: .LBB10_30: ; %Flow123
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_and_b32 s13, s13, exec_lo
+; GFX1150-FAKE16-NEXT: s_cselect_b32 s13, 1, 0
+; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s13, 1
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX1150-FAKE16-NEXT: ; %bb.31: ; %frem.compute
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, s11
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s12
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v5, v3, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s12
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s11
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s12, v6
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s12, v3
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s11, v3
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v9, v8
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -9964,12 +10763,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_30
-; GFX1150-FAKE16-NEXT: ; %bb.26: ; %frem.loop_body.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s11, s11, s12
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX1150-FAKE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s11, s12, s11
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s11, s11, 11
-; GFX1150-FAKE16-NEXT: .LBB10_27: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT: .LBB10_33: ; %frem.loop_body
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v8, v5
@@ -9987,24 +10786,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX1150-FAKE16-NEXT: ; %bb.28:
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_33
+; GFX1150-FAKE16-NEXT: ; %bb.34: ; %Flow
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, s11
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_31
-; GFX1150-FAKE16-NEXT: .LBB10_29: ; %frem.else
-; GFX1150-FAKE16-NEXT: s_and_b32 s13, 0x8000, s10
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s11, s12
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, s13
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_32
-; GFX1150-FAKE16-NEXT: .LBB10_30:
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v8, v5
-; GFX1150-FAKE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v7
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v5, v8, v5
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v8
+; GFX1150-FAKE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v5, v5, v7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v6, v6
@@ -10020,7 +10809,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, s10
-; GFX1150-FAKE16-NEXT: .LBB10_32:
+; GFX1150-FAKE16-NEXT: .LBB10_36: ; %Flow124
; GFX1150-FAKE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1150-FAKE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1150-FAKE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -10071,25 +10860,43 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[8:9] offset:32
; GFX1200-TRUE16-NEXT: s_and_b32 s3, s5, 0x7fff
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s3
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s3
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1200-TRUE16-NEXT: s_and_b32 s8, s4, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1200-TRUE16-NEXT: s_and_b32 s6, s4, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s6, s8
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_5
-; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.compute85
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s8, s6
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_2
+; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.else86
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s8, s6
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s5
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s9
+; GFX1200-TRUE16-NEXT: s_mov_b32 s9, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_3
+; GFX1200-TRUE16-NEXT: .LBB10_2:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s9, -1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-TRUE16-NEXT: .LBB10_3: ; %Flow135
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
+; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s8
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v2
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -10113,12 +10920,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_4
-; GFX1200-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s6, s8
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s8, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-TRUE16-NEXT: .LBB10_3: ; %frem.loop_body93
+; GFX1200-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -10137,39 +10944,51 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX1200-TRUE16-NEXT: .LBB10_4: ; %frem.loop_exit94
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX1200-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_6
-; GFX1200-TRUE16-NEXT: .LBB10_5: ; %frem.else86
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s6, s8
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s5
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s6, -1, 0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s6
-; GFX1200-TRUE16-NEXT: .LBB10_6:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
+; GFX1200-TRUE16-NEXT: .LBB10_8:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
+; GFX1200-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s8, s6, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s5
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s10, s9
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_11
-; GFX1200-TRUE16-NEXT: ; %bb.7: ; %frem.compute52
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s10
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s10
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
+; GFX1200-TRUE16-NEXT: ; %bb.9: ; %frem.else53
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
+; GFX1200-TRUE16-NEXT: s_mov_b32 s10, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_11
+; GFX1200-TRUE16-NEXT: .LBB10_10:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s10, -1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX1200-TRUE16-NEXT: .LBB10_11: ; %Flow131
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s10, 1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s10, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
+; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s9
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v4
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v3
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -10194,12 +11013,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_10
-; GFX1200-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body60.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s8, s8, s9
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s8, s9, s8
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s8, s8, 11
-; GFX1200-TRUE16-NEXT: .LBB10_9: ; %frem.loop_body60
+; GFX1200-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -10218,37 +11037,48 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
-; GFX1200-TRUE16-NEXT: .LBB10_10: ; %frem.loop_exit61
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
+; GFX1200-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_12
-; GFX1200-TRUE16-NEXT: .LBB10_11: ; %frem.else53
+; GFX1200-TRUE16-NEXT: .LBB10_16:
+; GFX1200-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s8
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
+; GFX1200-TRUE16-NEXT: ; %bb.17: ; %frem.else20
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
-; GFX1200-TRUE16-NEXT: .LBB10_12:
-; GFX1200-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s10, s2, 0x7fff
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
+; GFX1200-TRUE16-NEXT: s_mov_b32 s11, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_19
+; GFX1200-TRUE16-NEXT: .LBB10_18:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s11, -1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1200-TRUE16-NEXT: .LBB10_19: ; %Flow127
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s8
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s9, s10
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_17
-; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.compute19
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s10
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1200-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s10
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v4
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -10273,12 +11103,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_16
-; GFX1200-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body27.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s9, s10
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX1200-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -10297,40 +11127,51 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
-; GFX1200-TRUE16-NEXT: .LBB10_16: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
+; GFX1200-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_18
-; GFX1200-TRUE16-NEXT: .LBB10_17: ; %frem.else20
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s9, s10
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s9
-; GFX1200-TRUE16-NEXT: .LBB10_18:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
+; GFX1200-TRUE16-NEXT: .LBB10_24:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
+; GFX1200-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s10, s9, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s7
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s12, s11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_23
-; GFX1200-TRUE16-NEXT: ; %bb.19: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s11
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s11
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s12
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s12
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
+; GFX1200-TRUE16-NEXT: ; %bb.25: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
+; GFX1200-TRUE16-NEXT: s_mov_b32 s12, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_27
+; GFX1200-TRUE16-NEXT: .LBB10_26:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s12, -1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX1200-TRUE16-NEXT: .LBB10_27: ; %Flow123
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
+; GFX1200-TRUE16-NEXT: ; %bb.28: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s11
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s11, v5
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v4, v4, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -10355,12 +11196,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_22
-; GFX1200-TRUE16-NEXT: ; %bb.20: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s10, s10, s11
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX1200-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s10, s11, s10
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s10, s10, 11
-; GFX1200-TRUE16-NEXT: .LBB10_21: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
@@ -10379,18 +11220,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_21
-; GFX1200-TRUE16-NEXT: .LBB10_22: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
+; GFX1200-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_24
-; GFX1200-TRUE16-NEXT: .LBB10_23: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s12, s11
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s11
-; GFX1200-TRUE16-NEXT: .LBB10_24:
+; GFX1200-TRUE16-NEXT: .LBB10_32: ; %Flow124
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -10440,28 +11273,47 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: global_load_b64 v[0:1], v2, s[8:9] offset:32
; GFX1200-FAKE16-NEXT: s_and_b32 s3, s5, 0x7fff
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s6, s3
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s8, s3
; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1200-FAKE16-NEXT: s_and_b32 s8, s4, 0x7fff
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1200-FAKE16-NEXT: s_and_b32 s6, s4, 0x7fff
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s6, s8
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_5
-; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.compute85
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s8
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s8, s6
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_2
+; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.else86
+; GFX1200-FAKE16-NEXT: s_and_b32 s9, 0x8000, s5
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s8, s6
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, s9
+; GFX1200-FAKE16-NEXT: s_mov_b32 s9, 0
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_3
+; GFX1200-FAKE16-NEXT: .LBB10_2:
+; GFX1200-FAKE16-NEXT: s_mov_b32 s9, -1
+; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-FAKE16-NEXT: .LBB10_3: ; %Flow135
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1200-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s9, 1
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s6
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s8
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v1, v1, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s8
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s8, v0
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10479,16 +11331,17 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v7, v8, v6
; GFX1200-FAKE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_6
-; GFX1200-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s6, s6, s8
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_8
+; GFX1200-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s6, s8, s6
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-FAKE16-NEXT: .LBB10_3: ; %frem.loop_body93
+; GFX1200-FAKE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -10508,24 +11361,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX1200-FAKE16-NEXT: ; %bb.4:
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX1200-FAKE16-NEXT: ; %bb.7: ; %Flow133
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, s6
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_7
-; GFX1200-FAKE16-NEXT: .LBB10_5: ; %frem.else86
-; GFX1200-FAKE16-NEXT: s_and_b32 s9, 0x8000, s5
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s6, s8
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, s9
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_8
-; GFX1200-FAKE16-NEXT: .LBB10_6:
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX1200-FAKE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v2, -10, v4
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v5, v2
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-FAKE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v3, v3
@@ -10542,32 +11385,52 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s5
-; GFX1200-FAKE16-NEXT: .LBB10_8:
+; GFX1200-FAKE16-NEXT: .LBB10_9:
; GFX1200-FAKE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1200-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 s5, s8, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s10, s6, 0x7fff
+; GFX1200-FAKE16-NEXT: s_and_b32 s9, s6, 0x7fff
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s9, s5
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s10, s5
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s9, s10
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_13
-; GFX1200-FAKE16-NEXT: ; %bb.9: ; %frem.compute52
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s9
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
+; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_11
+; GFX1200-FAKE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX1200-FAKE16-NEXT: s_and_b32 s11, 0x8000, s8
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, s11
+; GFX1200-FAKE16-NEXT: s_mov_b32 s11, 0
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_12
+; GFX1200-FAKE16-NEXT: .LBB10_11:
+; GFX1200-FAKE16-NEXT: s_mov_b32 s11, -1
+; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr1
+; GFX1200-FAKE16-NEXT: .LBB10_12: ; %Flow131
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1200-FAKE16-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX1200-FAKE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s10
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s10
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s9
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s9, v4
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s10, v4
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s10, v1
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s9, v1
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10590,12 +11453,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_14
-; GFX1200-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body60.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s9, s10
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX1200-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-FAKE16-NEXT: .LBB10_11: ; %frem.loop_body60
+; GFX1200-FAKE16-NEXT: .LBB10_15: ; %frem.loop_body60
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -10615,25 +11478,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
-; GFX1200-FAKE16-NEXT: ; %bb.12:
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX1200-FAKE16-NEXT: ; %bb.16: ; %Flow129
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, s9
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_15
-; GFX1200-FAKE16-NEXT: .LBB10_13: ; %frem.else53
-; GFX1200-FAKE16-NEXT: s_and_b32 s11, 0x8000, s8
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s9, s10
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, s11
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_16
-; GFX1200-FAKE16-NEXT: .LBB10_14:
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
-; GFX1200-FAKE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v3, -10, v5
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v6, v3
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1200-FAKE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v4, v4
@@ -10650,29 +11502,50 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s8
-; GFX1200-FAKE16-NEXT: .LBB10_16:
+; GFX1200-FAKE16-NEXT: .LBB10_18:
; GFX1200-FAKE16-NEXT: s_and_b32 s8, s7, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s10, s2, 0x7fff
+; GFX1200-FAKE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s9, s8
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s10, s8
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s9, s10
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_21
-; GFX1200-FAKE16-NEXT: ; %bb.17: ; %frem.compute19
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s10
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s9
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
+; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_20
+; GFX1200-FAKE16-NEXT: ; %bb.19: ; %frem.else20
+; GFX1200-FAKE16-NEXT: s_and_b32 s11, 0x8000, s7
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, s11
+; GFX1200-FAKE16-NEXT: s_mov_b32 s11, 0
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_21
+; GFX1200-FAKE16-NEXT: .LBB10_20:
+; GFX1200-FAKE16-NEXT: s_mov_b32 s11, -1
+; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr2
+; GFX1200-FAKE16-NEXT: .LBB10_21: ; %Flow127
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1200-FAKE16-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX1200-FAKE16-NEXT: ; %bb.22: ; %frem.compute19
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s9
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s10
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s10
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s9
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s9, v5
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s10, v5
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s10, v2
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s9, v2
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10695,12 +11568,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_22
-; GFX1200-FAKE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s9, s10
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX1200-FAKE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-FAKE16-NEXT: .LBB10_19: ; %frem.loop_body27
+; GFX1200-FAKE16-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -10720,26 +11593,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX1200-FAKE16-NEXT: ; %bb.20:
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1200-FAKE16-NEXT: ; %bb.25: ; %Flow125
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, s9
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_23
-; GFX1200-FAKE16-NEXT: .LBB10_21: ; %frem.else20
-; GFX1200-FAKE16-NEXT: s_and_b32 s11, 0x8000, s7
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s9, s10
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, s11
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_24
-; GFX1200-FAKE16-NEXT: .LBB10_22:
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
-; GFX1200-FAKE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1200-FAKE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -10756,32 +11617,52 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, s7
-; GFX1200-FAKE16-NEXT: .LBB10_24:
+; GFX1200-FAKE16-NEXT: .LBB10_27:
; GFX1200-FAKE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1200-FAKE16-NEXT: s_lshr_b32 s9, s2, 16
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 s7, s10, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s12, s9, 0x7fff
+; GFX1200-FAKE16-NEXT: s_and_b32 s11, s9, 0x7fff
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s11, s7
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s12, s12
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s12, s7
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s11, s11
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s11, s12
+; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s12, s11
; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_29
-; GFX1200-FAKE16-NEXT: ; %bb.25: ; %frem.compute
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, s12
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s11
+; GFX1200-FAKE16-NEXT: ; %bb.28: ; %frem.else
+; GFX1200-FAKE16-NEXT: s_and_b32 s13, 0x8000, s10
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s12, s11
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, s13
+; GFX1200-FAKE16-NEXT: s_mov_b32 s13, 0
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_30
+; GFX1200-FAKE16-NEXT: .LBB10_29:
+; GFX1200-FAKE16-NEXT: s_mov_b32 s13, -1
+; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr3
+; GFX1200-FAKE16-NEXT: .LBB10_30: ; %Flow123
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT: s_and_b32 s13, s13, exec_lo
+; GFX1200-FAKE16-NEXT: s_cselect_b32 s13, 1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s13, 1
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX1200-FAKE16-NEXT: ; %bb.31: ; %frem.compute
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, s11
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s12
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v3, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s12
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s11
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s11, v6
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s12, v6
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s12, v3
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s11, v3
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v9, v8
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10804,12 +11685,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_30
-; GFX1200-FAKE16-NEXT: ; %bb.26: ; %frem.loop_body.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s11, s11, s12
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX1200-FAKE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s11, s12, s11
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s11, s11, 11
-; GFX1200-FAKE16-NEXT: .LBB10_27: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT: .LBB10_33: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v8, v5
@@ -10829,25 +11710,14 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX1200-FAKE16-NEXT: ; %bb.28:
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_33
+; GFX1200-FAKE16-NEXT: ; %bb.34: ; %Flow
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, s11
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_31
-; GFX1200-FAKE16-NEXT: .LBB10_29: ; %frem.else
-; GFX1200-FAKE16-NEXT: s_and_b32 s13, 0x8000, s10
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s11, s12
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, s13
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_32
-; GFX1200-FAKE16-NEXT: .LBB10_30:
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v8, v5
-; GFX1200-FAKE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v7
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v8, v5
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v8
+; GFX1200-FAKE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v5, v7
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v6, v6
@@ -10864,7 +11734,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, s10
-; GFX1200-FAKE16-NEXT: .LBB10_32:
+; GFX1200-FAKE16-NEXT: .LBB10_36: ; %Flow124
; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1200-FAKE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-FAKE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -10928,9 +11798,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0 offset:32
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v2|
-; SI-NEXT: s_cbranch_vccz .LBB11_4
-; SI-NEXT: ; %bb.1: ; %frem.compute15
+; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
+; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT: s_cbranch_vccz .LBB11_2
+; SI-NEXT: ; %bb.1: ; %frem.else16
+; SI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; SI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; SI-NEXT: s_mov_b64 s[2:3], 0
+; SI-NEXT: s_branch .LBB11_3
+; SI-NEXT: .LBB11_2:
+; SI-NEXT: s_mov_b64 s[2:3], -1
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: .LBB11_3: ; %Flow53
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cselect_b32 s2, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s2, 1
+; SI-NEXT: s_cbranch_scc1 .LBB11_9
+; SI-NEXT: ; %bb.4: ; %frem.compute15
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
@@ -10965,11 +11850,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v6, v6, v8, v9
; SI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB11_6
-; SI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB11_8
+; SI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB11_3: ; %frem.loop_body23
+; SI-NEXT: .LBB11_6: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v7, v5
; SI-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -10981,24 +11866,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v5, v5, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB11_3
-; SI-NEXT: s_branch .LBB11_7
-; SI-NEXT: .LBB11_4: ; %frem.else16
-; SI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
-; SI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
-; SI-NEXT: s_cbranch_vccnz .LBB11_8
-; SI-NEXT: .LBB11_5: ; %frem.else
-; SI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
-; SI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
-; SI-NEXT: s_branch .LBB11_13
-; SI-NEXT: .LBB11_6:
-; SI-NEXT: v_mov_b32_e32 v7, v5
-; SI-NEXT: .LBB11_7: ; %frem.loop_exit24
+; SI-NEXT: s_cbranch_scc1 .LBB11_6
+; SI-NEXT: ; %bb.7: ; %Flow51
+; SI-NEXT: v_mov_b32_e32 v5, v7
+; SI-NEXT: .LBB11_8: ; %frem.loop_exit24
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v5, v7, s3
+; SI-NEXT: v_ldexp_f32_e64 v5, v5, s3
; SI-NEXT: v_mul_f32_e32 v6, v5, v6
; SI-NEXT: v_rndne_f32_e32 v6, v6
; SI-NEXT: v_fma_f32 v5, -v6, v4, v5
@@ -11008,9 +11881,25 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v4, v4, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
-; SI-NEXT: s_cbranch_vccz .LBB11_5
-; SI-NEXT: .LBB11_8: ; %frem.compute
+; SI-NEXT: .LBB11_9:
+; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
+; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT: s_cbranch_vccz .LBB11_11
+; SI-NEXT: ; %bb.10: ; %frem.else
+; SI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; SI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
+; SI-NEXT: s_mov_b64 s[2:3], 0
+; SI-NEXT: s_branch .LBB11_12
+; SI-NEXT: .LBB11_11:
+; SI-NEXT: s_mov_b64 s[2:3], -1
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: .LBB11_12: ; %Flow49
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cselect_b32 s2, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s2, 1
+; SI-NEXT: s_cbranch_scc1 .LBB11_18
+; SI-NEXT: ; %bb.13: ; %frem.compute
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v1
@@ -11045,11 +11934,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v7, v7, v9, v10
; SI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB11_11
-; SI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB11_17
+; SI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB11_10: ; %frem.loop_body
+; SI-NEXT: .LBB11_15: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v8, v6
; SI-NEXT: v_mul_f32_e32 v6, v8, v7
@@ -11061,13 +11950,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v6, v6, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB11_10
-; SI-NEXT: s_branch .LBB11_12
-; SI-NEXT: .LBB11_11:
-; SI-NEXT: v_mov_b32_e32 v8, v6
-; SI-NEXT: .LBB11_12: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB11_15
+; SI-NEXT: ; %bb.16: ; %Flow
+; SI-NEXT: v_mov_b32_e32 v6, v8
+; SI-NEXT: .LBB11_17: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v6, v8, s3
+; SI-NEXT: v_ldexp_f32_e64 v6, v6, s3
; SI-NEXT: v_mul_f32_e32 v7, v6, v7
; SI-NEXT: v_rndne_f32_e32 v7, v7
; SI-NEXT: v_fma_f32 v6, -v7, v5, v6
@@ -11077,7 +11965,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v5, v5, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; SI-NEXT: .LBB11_13:
+; SI-NEXT: .LBB11_18: ; %Flow50
; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; SI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -11107,67 +11995,70 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; CI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v2|
-; CI-NEXT: s_cbranch_vccz .LBB11_4
-; CI-NEXT: ; %bb.1: ; %frem.compute15
+; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB11_2
+; CI-NEXT: ; %bb.1: ; %frem.else16
+; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; CI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: s_branch .LBB11_3
+; CI-NEXT: .LBB11_2:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr4
+; CI-NEXT: .LBB11_3: ; %Flow53
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB11_9
+; CI-NEXT: ; %bb.4: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; CI-NEXT: v_ldexp_f32_e64 v5, v5, 1
; CI-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v2
-; CI-NEXT: v_ldexp_f32_e64 v8, v4, 12
+; CI-NEXT: v_ldexp_f32_e64 v7, v4, 12
; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v10
; CI-NEXT: v_frexp_exp_i32_f32_e32 v9, v0
; CI-NEXT: v_not_b32_e32 v6, v4
; CI-NEXT: v_add_i32_e32 v6, vcc, v6, v9
-; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; CI-NEXT: v_rcp_f32_e32 v12, v11
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; CI-NEXT: v_fma_f32 v12, v13, v12, v12
-; CI-NEXT: v_mul_f32_e32 v13, v7, v12
-; CI-NEXT: v_fma_f32 v14, -v11, v13, v7
+; CI-NEXT: v_mul_f32_e32 v13, v8, v12
+; CI-NEXT: v_fma_f32 v14, -v11, v13, v8
; CI-NEXT: v_fma_f32 v13, v14, v12, v13
-; CI-NEXT: v_fma_f32 v7, -v11, v13, v7
+; CI-NEXT: v_fma_f32 v8, -v11, v13, v8
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v7, v7, v12, v13
+; CI-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v6
-; CI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB11_6
-; CI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; CI-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB11_8
+; CI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; CI-NEXT: v_sub_i32_e32 v6, vcc, v9, v10
; CI-NEXT: v_add_i32_e32 v6, vcc, 12, v6
-; CI-NEXT: .LBB11_3: ; %frem.loop_body23
+; CI-NEXT: .LBB11_6: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v9, v8
-; CI-NEXT: v_mul_f32_e32 v8, v9, v7
-; CI-NEXT: v_rndne_f32_e32 v8, v8
-; CI-NEXT: v_fma_f32 v8, -v8, v5, v9
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; CI-NEXT: v_add_f32_e32 v10, v8, v5
-; CI-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; CI-NEXT: v_mov_b32_e32 v9, v7
+; CI-NEXT: v_mul_f32_e32 v7, v9, v8
+; CI-NEXT: v_rndne_f32_e32 v7, v7
+; CI-NEXT: v_fma_f32 v7, -v7, v5, v9
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
+; CI-NEXT: v_add_f32_e32 v10, v7, v5
+; CI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; CI-NEXT: v_add_i32_e32 v6, vcc, -12, v6
-; CI-NEXT: v_ldexp_f32_e64 v8, v8, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v6
-; CI-NEXT: s_cbranch_vccnz .LBB11_3
-; CI-NEXT: s_branch .LBB11_7
-; CI-NEXT: .LBB11_4: ; %frem.else16
-; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
-; CI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
-; CI-NEXT: s_cbranch_vccnz .LBB11_8
-; CI-NEXT: .LBB11_5: ; %frem.else
-; CI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
-; CI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
-; CI-NEXT: s_branch .LBB11_13
-; CI-NEXT: .LBB11_6:
-; CI-NEXT: v_mov_b32_e32 v9, v8
-; CI-NEXT: .LBB11_7: ; %frem.loop_exit24
+; CI-NEXT: v_ldexp_f32_e64 v7, v7, 12
+; CI-NEXT: s_cbranch_vccnz .LBB11_6
+; CI-NEXT: ; %bb.7: ; %Flow51
+; CI-NEXT: v_mov_b32_e32 v7, v9
+; CI-NEXT: .LBB11_8: ; %frem.loop_exit24
; CI-NEXT: v_add_i32_e32 v6, vcc, -11, v6
-; CI-NEXT: v_ldexp_f32_e32 v6, v9, v6
-; CI-NEXT: v_mul_f32_e32 v7, v6, v7
+; CI-NEXT: v_ldexp_f32_e32 v6, v7, v6
+; CI-NEXT: v_mul_f32_e32 v7, v6, v8
; CI-NEXT: v_rndne_f32_e32 v7, v7
; CI-NEXT: v_fma_f32 v6, -v7, v5, v6
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -11176,56 +12067,71 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
-; CI-NEXT: s_cbranch_vccz .LBB11_5
-; CI-NEXT: .LBB11_8: ; %frem.compute
+; CI-NEXT: .LBB11_9:
+; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB11_11
+; CI-NEXT: ; %bb.10: ; %frem.else
+; CI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; CI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: s_branch .LBB11_12
+; CI-NEXT: .LBB11_11:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr5
+; CI-NEXT: .LBB11_12: ; %Flow49
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB11_18
+; CI-NEXT: ; %bb.13: ; %frem.compute
; CI-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; CI-NEXT: v_ldexp_f32_e64 v6, v6, 1
; CI-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v3
-; CI-NEXT: v_ldexp_f32_e64 v9, v5, 12
+; CI-NEXT: v_ldexp_f32_e64 v8, v5, 12
; CI-NEXT: v_add_i32_e32 v5, vcc, -1, v11
; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v1
; CI-NEXT: v_not_b32_e32 v7, v5
; CI-NEXT: v_add_i32_e32 v7, vcc, v7, v10
-; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
+; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; CI-NEXT: v_rcp_f32_e32 v13, v12
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; CI-NEXT: v_fma_f32 v13, v14, v13, v13
-; CI-NEXT: v_mul_f32_e32 v14, v8, v13
-; CI-NEXT: v_fma_f32 v15, -v12, v14, v8
+; CI-NEXT: v_mul_f32_e32 v14, v9, v13
+; CI-NEXT: v_fma_f32 v15, -v12, v14, v9
; CI-NEXT: v_fma_f32 v14, v15, v13, v14
-; CI-NEXT: v_fma_f32 v8, -v12, v14, v8
+; CI-NEXT: v_fma_f32 v9, -v12, v14, v9
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v8, v8, v13, v14
+; CI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v7
-; CI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB11_11
-; CI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB11_17
+; CI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v7, vcc, v10, v11
; CI-NEXT: v_add_i32_e32 v7, vcc, 12, v7
-; CI-NEXT: .LBB11_10: ; %frem.loop_body
+; CI-NEXT: .LBB11_15: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v10, v9
-; CI-NEXT: v_mul_f32_e32 v9, v10, v8
-; CI-NEXT: v_rndne_f32_e32 v9, v9
-; CI-NEXT: v_fma_f32 v9, -v9, v6, v10
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
-; CI-NEXT: v_add_f32_e32 v11, v9, v6
-; CI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; CI-NEXT: v_mov_b32_e32 v10, v8
+; CI-NEXT: v_mul_f32_e32 v8, v10, v9
+; CI-NEXT: v_rndne_f32_e32 v8, v8
+; CI-NEXT: v_fma_f32 v8, -v8, v6, v10
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; CI-NEXT: v_add_f32_e32 v11, v8, v6
+; CI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
; CI-NEXT: v_add_i32_e32 v7, vcc, -12, v7
-; CI-NEXT: v_ldexp_f32_e64 v9, v9, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v7
-; CI-NEXT: s_cbranch_vccnz .LBB11_10
-; CI-NEXT: s_branch .LBB11_12
-; CI-NEXT: .LBB11_11:
-; CI-NEXT: v_mov_b32_e32 v10, v9
-; CI-NEXT: .LBB11_12: ; %frem.loop_exit
+; CI-NEXT: v_ldexp_f32_e64 v8, v8, 12
+; CI-NEXT: s_cbranch_vccnz .LBB11_15
+; CI-NEXT: ; %bb.16: ; %Flow
+; CI-NEXT: v_mov_b32_e32 v8, v10
+; CI-NEXT: .LBB11_17: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v7, vcc, -11, v7
-; CI-NEXT: v_ldexp_f32_e32 v7, v10, v7
-; CI-NEXT: v_mul_f32_e32 v8, v7, v8
+; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
+; CI-NEXT: v_mul_f32_e32 v8, v7, v9
; CI-NEXT: v_rndne_f32_e32 v8, v8
; CI-NEXT: v_fma_f32 v7, -v8, v6, v7
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
@@ -11234,7 +12140,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v5, v6, v5
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; CI-NEXT: .LBB11_13:
+; CI-NEXT: .LBB11_18: ; %Flow50
; CI-NEXT: s_mov_b32 s4, 0x7f800000
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -11264,67 +12170,70 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v2|
-; VI-NEXT: s_cbranch_vccz .LBB11_4
-; VI-NEXT: ; %bb.1: ; %frem.compute15
+; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB11_2
+; VI-NEXT: ; %bb.1: ; %frem.else16
+; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; VI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB11_3
+; VI-NEXT: .LBB11_2:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr4
+; VI-NEXT: .LBB11_3: ; %Flow53
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB11_9
+; VI-NEXT: ; %bb.4: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; VI-NEXT: v_ldexp_f32 v5, v5, 1
; VI-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v2
-; VI-NEXT: v_ldexp_f32 v8, v4, 12
+; VI-NEXT: v_ldexp_f32 v7, v4, 12
; VI-NEXT: v_add_u32_e32 v4, vcc, -1, v10
; VI-NEXT: v_frexp_exp_i32_f32_e32 v9, v0
; VI-NEXT: v_not_b32_e32 v6, v4
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v9
-; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; VI-NEXT: v_rcp_f32_e32 v12, v11
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; VI-NEXT: v_fma_f32 v12, v13, v12, v12
-; VI-NEXT: v_mul_f32_e32 v13, v7, v12
-; VI-NEXT: v_fma_f32 v14, -v11, v13, v7
+; VI-NEXT: v_mul_f32_e32 v13, v8, v12
+; VI-NEXT: v_fma_f32 v14, -v11, v13, v8
; VI-NEXT: v_fma_f32 v13, v14, v12, v13
-; VI-NEXT: v_fma_f32 v7, -v11, v13, v7
+; VI-NEXT: v_fma_f32 v8, -v11, v13, v8
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v7, v7, v12, v13
+; VI-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v6
-; VI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB11_6
-; VI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; VI-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB11_8
+; VI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; VI-NEXT: v_sub_u32_e32 v6, vcc, v9, v10
; VI-NEXT: v_add_u32_e32 v6, vcc, 12, v6
-; VI-NEXT: .LBB11_3: ; %frem.loop_body23
+; VI-NEXT: .LBB11_6: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v9, v8
-; VI-NEXT: v_mul_f32_e32 v8, v9, v7
-; VI-NEXT: v_rndne_f32_e32 v8, v8
-; VI-NEXT: v_fma_f32 v8, -v8, v5, v9
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; VI-NEXT: v_add_f32_e32 v10, v8, v5
-; VI-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; VI-NEXT: v_mov_b32_e32 v9, v7
+; VI-NEXT: v_mul_f32_e32 v7, v9, v8
+; VI-NEXT: v_rndne_f32_e32 v7, v7
+; VI-NEXT: v_fma_f32 v7, -v7, v5, v9
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
+; VI-NEXT: v_add_f32_e32 v10, v7, v5
+; VI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, -12, v6
-; VI-NEXT: v_ldexp_f32 v8, v8, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v6
-; VI-NEXT: s_cbranch_vccnz .LBB11_3
-; VI-NEXT: s_branch .LBB11_7
-; VI-NEXT: .LBB11_4: ; %frem.else16
-; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
-; VI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
-; VI-NEXT: s_cbranch_vccnz .LBB11_8
-; VI-NEXT: .LBB11_5: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
-; VI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
-; VI-NEXT: s_branch .LBB11_13
-; VI-NEXT: .LBB11_6:
-; VI-NEXT: v_mov_b32_e32 v9, v8
-; VI-NEXT: .LBB11_7: ; %frem.loop_exit24
+; VI-NEXT: v_ldexp_f32 v7, v7, 12
+; VI-NEXT: s_cbranch_vccnz .LBB11_6
+; VI-NEXT: ; %bb.7: ; %Flow51
+; VI-NEXT: v_mov_b32_e32 v7, v9
+; VI-NEXT: .LBB11_8: ; %frem.loop_exit24
; VI-NEXT: v_add_u32_e32 v6, vcc, -11, v6
-; VI-NEXT: v_ldexp_f32 v6, v9, v6
-; VI-NEXT: v_mul_f32_e32 v7, v6, v7
+; VI-NEXT: v_ldexp_f32 v6, v7, v6
+; VI-NEXT: v_mul_f32_e32 v7, v6, v8
; VI-NEXT: v_rndne_f32_e32 v7, v7
; VI-NEXT: v_fma_f32 v6, -v7, v5, v6
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -11333,56 +12242,71 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v4, v5, v4
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
-; VI-NEXT: s_cbranch_vccz .LBB11_5
-; VI-NEXT: .LBB11_8: ; %frem.compute
+; VI-NEXT: .LBB11_9:
+; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB11_11
+; VI-NEXT: ; %bb.10: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; VI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB11_12
+; VI-NEXT: .LBB11_11:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr5
+; VI-NEXT: .LBB11_12: ; %Flow49
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB11_18
+; VI-NEXT: ; %bb.13: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; VI-NEXT: v_ldexp_f32 v6, v6, 1
; VI-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v11, v3
-; VI-NEXT: v_ldexp_f32 v9, v5, 12
+; VI-NEXT: v_ldexp_f32 v8, v5, 12
; VI-NEXT: v_add_u32_e32 v5, vcc, -1, v11
; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v1
; VI-NEXT: v_not_b32_e32 v7, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v10
-; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
+; VI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; VI-NEXT: v_rcp_f32_e32 v13, v12
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; VI-NEXT: v_fma_f32 v13, v14, v13, v13
-; VI-NEXT: v_mul_f32_e32 v14, v8, v13
-; VI-NEXT: v_fma_f32 v15, -v12, v14, v8
+; VI-NEXT: v_mul_f32_e32 v14, v9, v13
+; VI-NEXT: v_fma_f32 v15, -v12, v14, v9
; VI-NEXT: v_fma_f32 v14, v15, v13, v14
-; VI-NEXT: v_fma_f32 v8, -v12, v14, v8
+; VI-NEXT: v_fma_f32 v9, -v12, v14, v9
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v8, v8, v13, v14
+; VI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v7
-; VI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB11_11
-; VI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB11_17
+; VI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v7, vcc, v10, v11
; VI-NEXT: v_add_u32_e32 v7, vcc, 12, v7
-; VI-NEXT: .LBB11_10: ; %frem.loop_body
+; VI-NEXT: .LBB11_15: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v10, v9
-; VI-NEXT: v_mul_f32_e32 v9, v10, v8
-; VI-NEXT: v_rndne_f32_e32 v9, v9
-; VI-NEXT: v_fma_f32 v9, -v9, v6, v10
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
-; VI-NEXT: v_add_f32_e32 v11, v9, v6
-; VI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; VI-NEXT: v_mov_b32_e32 v10, v8
+; VI-NEXT: v_mul_f32_e32 v8, v10, v9
+; VI-NEXT: v_rndne_f32_e32 v8, v8
+; VI-NEXT: v_fma_f32 v8, -v8, v6, v10
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; VI-NEXT: v_add_f32_e32 v11, v8, v6
+; VI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
; VI-NEXT: v_add_u32_e32 v7, vcc, -12, v7
-; VI-NEXT: v_ldexp_f32 v9, v9, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v7
-; VI-NEXT: s_cbranch_vccnz .LBB11_10
-; VI-NEXT: s_branch .LBB11_12
-; VI-NEXT: .LBB11_11:
-; VI-NEXT: v_mov_b32_e32 v10, v9
-; VI-NEXT: .LBB11_12: ; %frem.loop_exit
+; VI-NEXT: v_ldexp_f32 v8, v8, 12
+; VI-NEXT: s_cbranch_vccnz .LBB11_15
+; VI-NEXT: ; %bb.16: ; %Flow
+; VI-NEXT: v_mov_b32_e32 v8, v10
+; VI-NEXT: .LBB11_17: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v7, vcc, -11, v7
-; VI-NEXT: v_ldexp_f32 v7, v10, v7
-; VI-NEXT: v_mul_f32_e32 v8, v7, v8
+; VI-NEXT: v_ldexp_f32 v7, v8, v7
+; VI-NEXT: v_mul_f32_e32 v8, v7, v9
; VI-NEXT: v_rndne_f32_e32 v8, v8
; VI-NEXT: v_fma_f32 v7, -v8, v6, v7
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
@@ -11391,7 +12315,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v5, v6, v5
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; VI-NEXT: .LBB11_13:
+; VI-NEXT: .LBB11_18: ; %Flow50
; VI-NEXT: s_mov_b32 s4, 0x7f800000
; VI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -11416,16 +12340,31 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7] offset:32
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v2|
-; GFX9-NEXT: s_cbranch_vccz .LBB11_4
-; GFX9-NEXT: ; %bb.1: ; %frem.compute15
+; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB11_2
+; GFX9-NEXT: ; %bb.1: ; %frem.else16
+; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB11_3
+; GFX9-NEXT: .LBB11_2:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr4
+; GFX9-NEXT: .LBB11_3: ; %Flow53
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB11_9
+; GFX9-NEXT: ; %bb.4: ; %frem.compute15
; GFX9-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; GFX9-NEXT: v_ldexp_f32 v5, v5, 1
; GFX9-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
-; GFX9-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; GFX9-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v0
-; GFX9-NEXT: v_ldexp_f32 v8, v4, 12
+; GFX9-NEXT: v_ldexp_f32 v7, v4, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v2
; GFX9-NEXT: v_add_u32_e32 v4, -1, v10
; GFX9-NEXT: v_not_b32_e32 v6, v4
@@ -11434,49 +12373,37 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; GFX9-NEXT: v_fma_f32 v12, v13, v12, v12
-; GFX9-NEXT: v_mul_f32_e32 v13, v7, v12
-; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v7
+; GFX9-NEXT: v_mul_f32_e32 v13, v8, v12
+; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v8
; GFX9-NEXT: v_fma_f32 v13, v14, v12, v13
-; GFX9-NEXT: v_fma_f32 v7, -v11, v13, v7
+; GFX9-NEXT: v_fma_f32 v8, -v11, v13, v8
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v7, v7, v12, v13
+; GFX9-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v6
-; GFX9-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_6
-; GFX9-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX9-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_8
+; GFX9-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX9-NEXT: v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT: v_add_u32_e32 v6, 12, v6
-; GFX9-NEXT: .LBB11_3: ; %frem.loop_body23
+; GFX9-NEXT: .LBB11_6: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v9, v8
-; GFX9-NEXT: v_mul_f32_e32 v8, v9, v7
-; GFX9-NEXT: v_rndne_f32_e32 v8, v8
-; GFX9-NEXT: v_fma_f32 v8, -v8, v5, v9
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; GFX9-NEXT: v_add_f32_e32 v10, v8, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX9-NEXT: v_mov_b32_e32 v9, v7
+; GFX9-NEXT: v_mul_f32_e32 v7, v9, v8
+; GFX9-NEXT: v_rndne_f32_e32 v7, v7
+; GFX9-NEXT: v_fma_f32 v7, -v7, v5, v9
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
+; GFX9-NEXT: v_add_f32_e32 v10, v7, v5
; GFX9-NEXT: v_add_u32_e32 v6, -12, v6
-; GFX9-NEXT: v_ldexp_f32 v8, v8, 12
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v6
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_3
-; GFX9-NEXT: s_branch .LBB11_7
-; GFX9-NEXT: .LBB11_4: ; %frem.else16
-; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_8
-; GFX9-NEXT: .LBB11_5: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
-; GFX9-NEXT: s_branch .LBB11_13
-; GFX9-NEXT: .LBB11_6:
-; GFX9-NEXT: v_mov_b32_e32 v9, v8
-; GFX9-NEXT: .LBB11_7: ; %frem.loop_exit24
+; GFX9-NEXT: v_ldexp_f32 v7, v7, 12
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_6
+; GFX9-NEXT: ; %bb.7: ; %Flow51
+; GFX9-NEXT: v_mov_b32_e32 v7, v9
+; GFX9-NEXT: .LBB11_8: ; %frem.loop_exit24
; GFX9-NEXT: v_add_u32_e32 v6, -11, v6
-; GFX9-NEXT: v_ldexp_f32 v6, v9, v6
-; GFX9-NEXT: v_mul_f32_e32 v7, v6, v7
+; GFX9-NEXT: v_ldexp_f32 v6, v7, v6
+; GFX9-NEXT: v_mul_f32_e32 v7, v6, v8
; GFX9-NEXT: v_rndne_f32_e32 v7, v7
; GFX9-NEXT: v_fma_f32 v6, -v7, v5, v6
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -11485,16 +12412,32 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v0
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
-; GFX9-NEXT: s_cbranch_vccz .LBB11_5
-; GFX9-NEXT: .LBB11_8: ; %frem.compute
+; GFX9-NEXT: .LBB11_9:
+; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB11_11
+; GFX9-NEXT: ; %bb.10: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB11_12
+; GFX9-NEXT: .LBB11_11:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr5
+; GFX9-NEXT: .LBB11_12: ; %Flow49
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB11_18
+; GFX9-NEXT: ; %bb.13: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; GFX9-NEXT: v_ldexp_f32 v6, v6, 1
; GFX9-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
-; GFX9-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
+; GFX9-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v1
-; GFX9-NEXT: v_ldexp_f32 v9, v5, 12
+; GFX9-NEXT: v_ldexp_f32 v8, v5, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v11, v3
; GFX9-NEXT: v_add_u32_e32 v5, -1, v11
; GFX9-NEXT: v_not_b32_e32 v7, v5
@@ -11503,38 +12446,37 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; GFX9-NEXT: v_fma_f32 v13, v14, v13, v13
-; GFX9-NEXT: v_mul_f32_e32 v14, v8, v13
-; GFX9-NEXT: v_fma_f32 v15, -v12, v14, v8
+; GFX9-NEXT: v_mul_f32_e32 v14, v9, v13
+; GFX9-NEXT: v_fma_f32 v15, -v12, v14, v9
; GFX9-NEXT: v_fma_f32 v14, v15, v13, v14
-; GFX9-NEXT: v_fma_f32 v8, -v12, v14, v8
+; GFX9-NEXT: v_fma_f32 v9, -v12, v14, v9
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v8, v8, v13, v14
+; GFX9-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v7
-; GFX9-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_11
-; GFX9-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_17
+; GFX9-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v7, v10, v11
; GFX9-NEXT: v_add_u32_e32 v7, 12, v7
-; GFX9-NEXT: .LBB11_10: ; %frem.loop_body
+; GFX9-NEXT: .LBB11_15: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v10, v9
-; GFX9-NEXT: v_mul_f32_e32 v9, v10, v8
-; GFX9-NEXT: v_rndne_f32_e32 v9, v9
-; GFX9-NEXT: v_fma_f32 v9, -v9, v6, v10
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
-; GFX9-NEXT: v_add_f32_e32 v11, v9, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; GFX9-NEXT: v_mov_b32_e32 v10, v8
+; GFX9-NEXT: v_mul_f32_e32 v8, v10, v9
+; GFX9-NEXT: v_rndne_f32_e32 v8, v8
+; GFX9-NEXT: v_fma_f32 v8, -v8, v6, v10
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; GFX9-NEXT: v_add_f32_e32 v11, v8, v6
; GFX9-NEXT: v_add_u32_e32 v7, -12, v7
-; GFX9-NEXT: v_ldexp_f32 v9, v9, 12
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v7
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_10
-; GFX9-NEXT: s_branch .LBB11_12
-; GFX9-NEXT: .LBB11_11:
-; GFX9-NEXT: v_mov_b32_e32 v10, v9
-; GFX9-NEXT: .LBB11_12: ; %frem.loop_exit
+; GFX9-NEXT: v_ldexp_f32 v8, v8, 12
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_15
+; GFX9-NEXT: ; %bb.16: ; %Flow
+; GFX9-NEXT: v_mov_b32_e32 v8, v10
+; GFX9-NEXT: .LBB11_17: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v7, -11, v7
-; GFX9-NEXT: v_ldexp_f32 v7, v10, v7
-; GFX9-NEXT: v_mul_f32_e32 v8, v7, v8
+; GFX9-NEXT: v_ldexp_f32 v7, v8, v7
+; GFX9-NEXT: v_mul_f32_e32 v8, v7, v9
; GFX9-NEXT: v_rndne_f32_e32 v8, v8
; GFX9-NEXT: v_fma_f32 v7, -v8, v6, v7
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
@@ -11543,7 +12485,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v5, v6, v5
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v1
-; GFX9-NEXT: .LBB11_13:
+; GFX9-NEXT: .LBB11_18: ; %Flow50
; GFX9-NEXT: s_mov_b32 s4, 0x7f800000
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; GFX9-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -11569,9 +12511,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7] offset:32
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v2|
-; GFX10-NEXT: s_cbranch_vccz .LBB11_5
-; GFX10-NEXT: ; %bb.1: ; %frem.compute15
+; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v2|
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB11_2
+; GFX10-NEXT: ; %bb.1: ; %frem.else16
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
+; GFX10-NEXT: s_branch .LBB11_3
+; GFX10-NEXT: .LBB11_2:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr4
+; GFX10-NEXT: .LBB11_3: ; %Flow53
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB11_9
+; GFX10-NEXT: ; %bb.4: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; GFX10-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
@@ -11597,11 +12554,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v8
; GFX10-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB11_7
-; GFX10-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB11_8
+; GFX10-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB11_3: ; %frem.loop_body23
+; GFX10-NEXT: .LBB11_6: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -11613,26 +12570,13 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v8, v6, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v6, v6, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB11_3
-; GFX10-NEXT: ; %bb.4:
+; GFX10-NEXT: s_cbranch_scc1 .LBB11_6
+; GFX10-NEXT: ; %bb.7: ; %Flow51
; GFX10-NEXT: v_mov_b32_e32 v8, s2
-; GFX10-NEXT: s_branch .LBB11_8
-; GFX10-NEXT: .LBB11_5: ; %frem.else16
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v3|
-; GFX10-NEXT: s_cbranch_vccnz .LBB11_9
-; GFX10-NEXT: .LBB11_6: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc_lo
-; GFX10-NEXT: s_branch .LBB11_15
-; GFX10-NEXT: .LBB11_7:
-; GFX10-NEXT: v_mov_b32_e32 v9, v6
+; GFX10-NEXT: v_mov_b32_e32 v6, v9
; GFX10-NEXT: .LBB11_8: ; %frem.loop_exit24
-; GFX10-NEXT: v_add_nc_u32_e32 v6, -11, v8
-; GFX10-NEXT: v_ldexp_f32 v6, v9, v6
+; GFX10-NEXT: v_add_nc_u32_e32 v8, -11, v8
+; GFX10-NEXT: v_ldexp_f32 v6, v6, v8
; GFX10-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX10-NEXT: v_rndne_f32_e32 v7, v7
; GFX10-NEXT: v_fma_f32 v6, -v7, v5, v6
@@ -11641,9 +12585,25 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v5, v4
; GFX10-NEXT: v_bfi_b32 v4, 0x7fffffff, v4, v0
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v3|
-; GFX10-NEXT: s_cbranch_vccz .LBB11_6
-; GFX10-NEXT: .LBB11_9: ; %frem.compute
+; GFX10-NEXT: .LBB11_9:
+; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v3|
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB11_11
+; GFX10-NEXT: ; %bb.10: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc_lo
+; GFX10-NEXT: s_branch .LBB11_12
+; GFX10-NEXT: .LBB11_11:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr5
+; GFX10-NEXT: .LBB11_12: ; %Flow49
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB11_18
+; GFX10-NEXT: ; %bb.13: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; GFX10-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
@@ -11669,11 +12629,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v8, v8, v11, v12
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v9
; GFX10-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB11_13
-; GFX10-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB11_17
+; GFX10-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB11_11: ; %frem.loop_body
+; GFX10-NEXT: .LBB11_15: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v10, v7
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -11685,15 +12645,13 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v9, v7, v6
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v7, v7, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB11_11
-; GFX10-NEXT: ; %bb.12:
+; GFX10-NEXT: s_cbranch_scc1 .LBB11_15
+; GFX10-NEXT: ; %bb.16: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v9, s2
-; GFX10-NEXT: s_branch .LBB11_14
-; GFX10-NEXT: .LBB11_13:
-; GFX10-NEXT: v_mov_b32_e32 v10, v7
-; GFX10-NEXT: .LBB11_14: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v7, -11, v9
-; GFX10-NEXT: v_ldexp_f32 v7, v10, v7
+; GFX10-NEXT: v_mov_b32_e32 v7, v10
+; GFX10-NEXT: .LBB11_17: ; %frem.loop_exit
+; GFX10-NEXT: v_add_nc_u32_e32 v9, -11, v9
+; GFX10-NEXT: v_ldexp_f32 v7, v7, v9
; GFX10-NEXT: v_mul_f32_e32 v8, v7, v8
; GFX10-NEXT: v_rndne_f32_e32 v8, v8
; GFX10-NEXT: v_fma_f32 v7, -v8, v6, v7
@@ -11702,7 +12660,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v5, v6, v5
; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX10-NEXT: .LBB11_15:
+; GFX10-NEXT: .LBB11_18: ; %Flow50
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
@@ -11726,9 +12684,25 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-NEXT: global_load_b64 v[2:3], v2, s[4:5] offset:32
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v2|
-; GFX11-NEXT: s_cbranch_vccz .LBB11_5
-; GFX11-NEXT: ; %bb.1: ; %frem.compute15
+; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v2|
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB11_2
+; GFX11-NEXT: ; %bb.1: ; %frem.else16
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
+; GFX11-NEXT: s_branch .LBB11_3
+; GFX11-NEXT: .LBB11_2:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr4
+; GFX11-NEXT: .LBB11_3: ; %Flow53
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB11_9
+; GFX11-NEXT: ; %bb.4: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; GFX11-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
@@ -11763,12 +12737,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB11_7
-; GFX11-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB11_8
+; GFX11-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB11_3: ; %frem.loop_body23
+; GFX11-NEXT: .LBB11_6: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v9, v6
@@ -11784,29 +12758,14 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v6, v6, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB11_3
-; GFX11-NEXT: ; %bb.4:
+; GFX11-NEXT: s_cbranch_scc1 .LBB11_6
+; GFX11-NEXT: ; %bb.7: ; %Flow51
; GFX11-NEXT: v_mov_b32_e32 v8, s2
-; GFX11-NEXT: s_branch .LBB11_8
-; GFX11-NEXT: .LBB11_5: ; %frem.else16
-; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v3|
-; GFX11-NEXT: s_cbranch_vccnz .LBB11_9
-; GFX11-NEXT: .LBB11_6: ; %frem.else
-; GFX11-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc_lo
-; GFX11-NEXT: s_branch .LBB11_15
-; GFX11-NEXT: .LBB11_7:
-; GFX11-NEXT: v_mov_b32_e32 v9, v6
+; GFX11-NEXT: v_mov_b32_e32 v6, v9
; GFX11-NEXT: .LBB11_8: ; %frem.loop_exit24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v6, -11, v8
-; GFX11-NEXT: v_ldexp_f32 v6, v9, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v8, -11, v8
+; GFX11-NEXT: v_ldexp_f32 v6, v6, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX11-NEXT: v_rndne_f32_e32 v7, v7
@@ -11819,9 +12778,26 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v4, v5, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v4, 0x7fffffff, v4, v0
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v3|
-; GFX11-NEXT: s_cbranch_vccz .LBB11_6
-; GFX11-NEXT: .LBB11_9: ; %frem.compute
+; GFX11-NEXT: .LBB11_9:
+; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v3|
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB11_11
+; GFX11-NEXT: ; %bb.10: ; %frem.else
+; GFX11-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc_lo
+; GFX11-NEXT: s_branch .LBB11_12
+; GFX11-NEXT: .LBB11_11:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr5
+; GFX11-NEXT: .LBB11_12: ; %Flow49
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB11_18
+; GFX11-NEXT: ; %bb.13: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; GFX11-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
@@ -11856,12 +12832,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB11_13
-; GFX11-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB11_17
+; GFX11-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB11_11: ; %frem.loop_body
+; GFX11-NEXT: .LBB11_15: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v10, v7
@@ -11877,16 +12853,14 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v7, v7, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB11_11
-; GFX11-NEXT: ; %bb.12:
+; GFX11-NEXT: s_cbranch_scc1 .LBB11_15
+; GFX11-NEXT: ; %bb.16: ; %Flow
; GFX11-NEXT: v_mov_b32_e32 v9, s2
-; GFX11-NEXT: s_branch .LBB11_14
-; GFX11-NEXT: .LBB11_13:
-; GFX11-NEXT: v_mov_b32_e32 v10, v7
-; GFX11-NEXT: .LBB11_14: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v7, -11, v9
-; GFX11-NEXT: v_ldexp_f32 v7, v10, v7
+; GFX11-NEXT: v_mov_b32_e32 v7, v10
+; GFX11-NEXT: .LBB11_17: ; %frem.loop_exit
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v9, -11, v9
+; GFX11-NEXT: v_ldexp_f32 v7, v7, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v8, v7, v8
; GFX11-NEXT: v_rndne_f32_e32 v8, v8
@@ -11899,7 +12873,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v5, v6, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX11-NEXT: .LBB11_15:
+; GFX11-NEXT: .LBB11_18: ; %Flow50
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
@@ -11930,9 +12904,27 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_readfirstlane_b32 s2, v2
; GFX1150-NEXT: s_and_b32 s7, s4, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_gt_f32 s3, s7
-; GFX1150-NEXT: s_cbranch_scc0 .LBB11_5
-; GFX1150-NEXT: ; %bb.1: ; %frem.compute15
+; GFX1150-NEXT: s_cmp_ngt_f32 s3, s7
+; GFX1150-NEXT: s_cbranch_scc0 .LBB11_2
+; GFX1150-NEXT: ; %bb.1: ; %frem.else16
+; GFX1150-NEXT: s_and_b32 s8, 0x80000000, s6
+; GFX1150-NEXT: s_cmp_eq_f32 s3, s7
+; GFX1150-NEXT: v_mov_b32_e32 v0, s8
+; GFX1150-NEXT: s_mov_b32 s7, 0
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v0, s6, v0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB11_3
+; GFX1150-NEXT: .LBB11_2:
+; GFX1150-NEXT: s_mov_b32 s7, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr0
+; GFX1150-NEXT: .LBB11_3: ; %Flow53
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s7, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB11_9
+; GFX1150-NEXT: ; %bb.4: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s4|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v0, |s6|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
@@ -11966,12 +12958,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1150-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB11_6
-; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB11_8
+; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_sub_i32 s7, s7, s8
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s7, s7, 12
-; GFX1150-NEXT: .LBB11_3: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB11_6: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v5, v2
@@ -11989,24 +12981,14 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v2, v2, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB11_3
-; GFX1150-NEXT: ; %bb.4:
+; GFX1150-NEXT: s_cbranch_scc1 .LBB11_6
+; GFX1150-NEXT: ; %bb.7: ; %Flow51
; GFX1150-NEXT: v_mov_b32_e32 v4, s7
-; GFX1150-NEXT: s_branch .LBB11_7
-; GFX1150-NEXT: .LBB11_5: ; %frem.else16
-; GFX1150-NEXT: s_and_b32 s8, 0x80000000, s6
-; GFX1150-NEXT: s_cmp_eq_f32 s3, s7
-; GFX1150-NEXT: v_mov_b32_e32 v0, s8
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v0, s6, v0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB11_8
-; GFX1150-NEXT: .LBB11_6:
-; GFX1150-NEXT: v_mov_b32_e32 v5, v2
-; GFX1150-NEXT: .LBB11_7: ; %frem.loop_exit24
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v2, -11, v4
-; GFX1150-NEXT: v_ldexp_f32 v2, v5, v2
+; GFX1150-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-NEXT: .LBB11_8: ; %frem.loop_exit24
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v4, -11, v4
+; GFX1150-NEXT: v_ldexp_f32 v2, v2, v4
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-NEXT: v_rndne_f32_e32 v3, v3
@@ -12020,13 +13002,31 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1150-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s6
-; GFX1150-NEXT: .LBB11_8:
+; GFX1150-NEXT: .LBB11_9:
; GFX1150-NEXT: s_and_b32 s6, s5, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s7, s2, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_gt_f32 s6, s7
-; GFX1150-NEXT: s_cbranch_scc0 .LBB11_13
-; GFX1150-NEXT: ; %bb.9: ; %frem.compute
+; GFX1150-NEXT: s_cmp_ngt_f32 s6, s7
+; GFX1150-NEXT: s_cbranch_scc0 .LBB11_11
+; GFX1150-NEXT: ; %bb.10: ; %frem.else
+; GFX1150-NEXT: s_and_b32 s8, 0x80000000, s5
+; GFX1150-NEXT: s_cmp_eq_f32 s6, s7
+; GFX1150-NEXT: v_mov_b32_e32 v1, s8
+; GFX1150-NEXT: s_mov_b32 s7, 0
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
+; GFX1150-NEXT: s_branch .LBB11_12
+; GFX1150-NEXT: .LBB11_11:
+; GFX1150-NEXT: s_mov_b32 s7, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr1
+; GFX1150-NEXT: .LBB11_12: ; %Flow49
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s7, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB11_18
+; GFX1150-NEXT: ; %bb.13: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f32_e64 v2, |s2|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s5|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v4, s5
@@ -12060,12 +13060,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1150-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB11_14
-; GFX1150-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB11_17
+; GFX1150-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s7, s7, s8
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s7, s7, 12
-; GFX1150-NEXT: .LBB11_11: ; %frem.loop_body
+; GFX1150-NEXT: .LBB11_15: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v6, v3
@@ -12083,24 +13083,14 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB11_11
-; GFX1150-NEXT: ; %bb.12:
+; GFX1150-NEXT: s_cbranch_scc1 .LBB11_15
+; GFX1150-NEXT: ; %bb.16: ; %Flow
; GFX1150-NEXT: v_mov_b32_e32 v5, s7
-; GFX1150-NEXT: s_branch .LBB11_15
-; GFX1150-NEXT: .LBB11_13: ; %frem.else
-; GFX1150-NEXT: s_and_b32 s8, 0x80000000, s5
-; GFX1150-NEXT: s_cmp_eq_f32 s6, s7
-; GFX1150-NEXT: v_mov_b32_e32 v1, s8
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
-; GFX1150-NEXT: s_branch .LBB11_16
-; GFX1150-NEXT: .LBB11_14:
-; GFX1150-NEXT: v_mov_b32_e32 v6, v3
-; GFX1150-NEXT: .LBB11_15: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v3, -11, v5
-; GFX1150-NEXT: v_ldexp_f32 v3, v6, v3
+; GFX1150-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-NEXT: .LBB11_17: ; %frem.loop_exit
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v5, -11, v5
+; GFX1150-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-NEXT: v_rndne_f32_e32 v4, v4
@@ -12114,7 +13104,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1150-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s5
-; GFX1150-NEXT: .LBB11_16:
+; GFX1150-NEXT: .LBB11_18: ; %Flow50
; GFX1150-NEXT: s_cmp_lg_f32 s4, 0
; GFX1150-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-NEXT: s_cselect_b32 s4, -1, 0
@@ -12151,9 +13141,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_readfirstlane_b32 s2, v2
; GFX1200-NEXT: s_and_b32 s7, s4, 0x7fffffff
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_cmp_gt_f32 s3, s7
-; GFX1200-NEXT: s_cbranch_scc0 .LBB11_5
-; GFX1200-NEXT: ; %bb.1: ; %frem.compute15
+; GFX1200-NEXT: s_cmp_ngt_f32 s3, s7
+; GFX1200-NEXT: s_cbranch_scc0 .LBB11_2
+; GFX1200-NEXT: ; %bb.1: ; %frem.else16
+; GFX1200-NEXT: s_and_b32 s8, 0x80000000, s6
+; GFX1200-NEXT: s_cmp_eq_f32 s3, s7
+; GFX1200-NEXT: s_cselect_b32 s7, s8, s6
+; GFX1200-NEXT: s_mov_b32 s8, 0
+; GFX1200-NEXT: s_branch .LBB11_3
+; GFX1200-NEXT: .LBB11_2:
+; GFX1200-NEXT: s_mov_b32 s8, -1
+; GFX1200-NEXT: ; implicit-def: $sgpr7
+; GFX1200-NEXT: .LBB11_3: ; %Flow53
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1200-NEXT: s_cmp_lg_u32 s8, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB11_9
+; GFX1200-NEXT: ; %bb.4: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s4|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v0, |s6|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
@@ -12187,12 +13192,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1200-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB11_6
-; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB11_8
+; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_sub_co_i32 s7, s7, s8
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s7, s7, 12
-; GFX1200-NEXT: .LBB11_3: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB11_6: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v2
@@ -12212,23 +13217,14 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v2, v2, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB11_3
-; GFX1200-NEXT: ; %bb.4:
+; GFX1200-NEXT: s_cbranch_scc1 .LBB11_6
+; GFX1200-NEXT: ; %bb.7: ; %Flow51
; GFX1200-NEXT: v_mov_b32_e32 v4, s7
-; GFX1200-NEXT: s_branch .LBB11_7
-; GFX1200-NEXT: .LBB11_5: ; %frem.else16
-; GFX1200-NEXT: s_and_b32 s8, 0x80000000, s6
-; GFX1200-NEXT: s_cmp_eq_f32 s3, s7
-; GFX1200-NEXT: s_cselect_b32 s6, s8, s6
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: v_mov_b32_e32 v0, s6
-; GFX1200-NEXT: s_branch .LBB11_8
-; GFX1200-NEXT: .LBB11_6:
-; GFX1200-NEXT: v_mov_b32_e32 v5, v2
-; GFX1200-NEXT: .LBB11_7: ; %frem.loop_exit24
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v2, -11, v4
-; GFX1200-NEXT: v_ldexp_f32 v2, v5, v2
+; GFX1200-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-NEXT: .LBB11_8: ; %frem.loop_exit24
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v4, -11, v4
+; GFX1200-NEXT: v_ldexp_f32 v2, v2, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-NEXT: v_rndne_f32_e32 v3, v3
@@ -12243,13 +13239,31 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1200-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s6
-; GFX1200-NEXT: .LBB11_8:
+; GFX1200-NEXT: s_branch .LBB11_10
+; GFX1200-NEXT: .LBB11_9:
+; GFX1200-NEXT: v_mov_b32_e32 v0, s7
+; GFX1200-NEXT: .LBB11_10:
; GFX1200-NEXT: s_and_b32 s6, s5, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s7, s2, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cmp_gt_f32 s6, s7
-; GFX1200-NEXT: s_cbranch_scc0 .LBB11_13
-; GFX1200-NEXT: ; %bb.9: ; %frem.compute
+; GFX1200-NEXT: s_cmp_ngt_f32 s6, s7
+; GFX1200-NEXT: s_cbranch_scc0 .LBB11_12
+; GFX1200-NEXT: ; %bb.11: ; %frem.else
+; GFX1200-NEXT: s_and_b32 s8, 0x80000000, s5
+; GFX1200-NEXT: s_cmp_eq_f32 s6, s7
+; GFX1200-NEXT: s_cselect_b32 s7, s8, s5
+; GFX1200-NEXT: s_mov_b32 s8, 0
+; GFX1200-NEXT: s_branch .LBB11_13
+; GFX1200-NEXT: .LBB11_12:
+; GFX1200-NEXT: s_mov_b32 s8, -1
+; GFX1200-NEXT: ; implicit-def: $sgpr7
+; GFX1200-NEXT: .LBB11_13: ; %Flow49
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1200-NEXT: s_cmp_lg_u32 s8, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB11_19
+; GFX1200-NEXT: ; %bb.14: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f32_e64 v2, |s2|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s5|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v4, s5
@@ -12284,12 +13298,13 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1200-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB11_14
-; GFX1200-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB11_18
+; GFX1200-NEXT: ; %bb.15: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s7, s7, s8
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s7, s7, 12
-; GFX1200-NEXT: .LBB11_11: ; %frem.loop_body
+; GFX1200-NEXT: .LBB11_16: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v6, v3
@@ -12309,23 +13324,14 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB11_11
-; GFX1200-NEXT: ; %bb.12:
+; GFX1200-NEXT: s_cbranch_scc1 .LBB11_16
+; GFX1200-NEXT: ; %bb.17: ; %Flow
; GFX1200-NEXT: v_mov_b32_e32 v5, s7
-; GFX1200-NEXT: s_branch .LBB11_15
-; GFX1200-NEXT: .LBB11_13: ; %frem.else
-; GFX1200-NEXT: s_and_b32 s8, 0x80000000, s5
-; GFX1200-NEXT: s_cmp_eq_f32 s6, s7
-; GFX1200-NEXT: s_cselect_b32 s5, s8, s5
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v1, s5
-; GFX1200-NEXT: s_branch .LBB11_16
-; GFX1200-NEXT: .LBB11_14:
-; GFX1200-NEXT: v_mov_b32_e32 v6, v3
-; GFX1200-NEXT: .LBB11_15: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v3, -11, v5
-; GFX1200-NEXT: v_ldexp_f32 v3, v6, v3
+; GFX1200-NEXT: v_mov_b32_e32 v3, v6
+; GFX1200-NEXT: .LBB11_18: ; %frem.loop_exit
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v5, -11, v5
+; GFX1200-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-NEXT: v_rndne_f32_e32 v4, v4
@@ -12340,7 +13346,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1200-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s5
-; GFX1200-NEXT: .LBB11_16:
+; GFX1200-NEXT: s_branch .LBB11_20
+; GFX1200-NEXT: .LBB11_19:
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v1, s7
+; GFX1200-NEXT: .LBB11_20: ; %Flow50
; GFX1200-NEXT: s_cmp_lg_f32 s4, 0
; GFX1200-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-NEXT: s_cselect_b32 s4, -1, 0
@@ -12384,9 +13394,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:64
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v4|
-; SI-NEXT: s_cbranch_vccz .LBB12_4
-; SI-NEXT: ; %bb.1: ; %frem.compute77
+; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
+; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT: s_cbranch_vccz .LBB12_2
+; SI-NEXT: ; %bb.1: ; %frem.else78
+; SI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; SI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
+; SI-NEXT: s_mov_b64 s[2:3], 0
+; SI-NEXT: s_branch .LBB12_3
+; SI-NEXT: .LBB12_2:
+; SI-NEXT: s_mov_b64 s[2:3], -1
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: .LBB12_3: ; %Flow127
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cselect_b32 s2, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s2, 1
+; SI-NEXT: s_cbranch_scc1 .LBB12_9
+; SI-NEXT: ; %bb.4: ; %frem.compute77
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v8, v0
@@ -12422,10 +13447,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
; SI-NEXT: s_cbranch_scc1 .LBB12_8
-; SI-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
+; SI-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_3: ; %frem.loop_body85
+; SI-NEXT: .LBB12_6: ; %frem.loop_body85
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v11, v9
; SI-NEXT: v_mul_f32_e32 v9, v11, v10
@@ -12437,36 +13462,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v9, v9, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_3
-; SI-NEXT: s_branch .LBB12_9
-; SI-NEXT: .LBB12_4: ; %frem.else78
-; SI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
-; SI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
-; SI-NEXT: s_cbranch_vccnz .LBB12_10
-; SI-NEXT: .LBB12_5: ; %frem.else47
-; SI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
-; SI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
-; SI-NEXT: s_cbranch_vccnz .LBB12_15
-; SI-NEXT: .LBB12_6: ; %frem.else16
-; SI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
-; SI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
-; SI-NEXT: s_cbranch_vccnz .LBB12_20
-; SI-NEXT: .LBB12_7: ; %frem.else
-; SI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
-; SI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
-; SI-NEXT: s_branch .LBB12_25
-; SI-NEXT: .LBB12_8:
-; SI-NEXT: v_mov_b32_e32 v11, v9
-; SI-NEXT: .LBB12_9: ; %frem.loop_exit86
+; SI-NEXT: s_cbranch_scc1 .LBB12_6
+; SI-NEXT: ; %bb.7: ; %Flow125
+; SI-NEXT: v_mov_b32_e32 v9, v11
+; SI-NEXT: .LBB12_8: ; %frem.loop_exit86
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v9, v11, s3
+; SI-NEXT: v_ldexp_f32_e64 v9, v9, s3
; SI-NEXT: v_mul_f32_e32 v10, v9, v10
; SI-NEXT: v_rndne_f32_e32 v10, v10
; SI-NEXT: v_fma_f32 v9, -v10, v8, v9
@@ -12476,9 +13477,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v8, v8, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v8, s2, v8, v0
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
-; SI-NEXT: s_cbranch_vccz .LBB12_5
-; SI-NEXT: .LBB12_10: ; %frem.compute46
+; SI-NEXT: .LBB12_9:
+; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
+; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT: s_cbranch_vccz .LBB12_11
+; SI-NEXT: ; %bb.10: ; %frem.else47
+; SI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; SI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
+; SI-NEXT: s_mov_b64 s[2:3], 0
+; SI-NEXT: s_branch .LBB12_12
+; SI-NEXT: .LBB12_11:
+; SI-NEXT: s_mov_b64 s[2:3], -1
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: .LBB12_12: ; %Flow123
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cselect_b32 s2, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s2, 1
+; SI-NEXT: s_cbranch_scc1 .LBB12_18
+; SI-NEXT: ; %bb.13: ; %frem.compute46
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v9, v1
@@ -12513,11 +13530,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v11, v11, v13, v14
; SI-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_13
-; SI-NEXT: ; %bb.11: ; %frem.loop_body54.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_17
+; SI-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_12: ; %frem.loop_body54
+; SI-NEXT: .LBB12_15: ; %frem.loop_body54
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v12, v10
; SI-NEXT: v_mul_f32_e32 v10, v12, v11
@@ -12529,13 +13546,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v10, v10, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_12
-; SI-NEXT: s_branch .LBB12_14
-; SI-NEXT: .LBB12_13:
-; SI-NEXT: v_mov_b32_e32 v12, v10
-; SI-NEXT: .LBB12_14: ; %frem.loop_exit55
+; SI-NEXT: s_cbranch_scc1 .LBB12_15
+; SI-NEXT: ; %bb.16: ; %Flow121
+; SI-NEXT: v_mov_b32_e32 v10, v12
+; SI-NEXT: .LBB12_17: ; %frem.loop_exit55
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v10, v12, s3
+; SI-NEXT: v_ldexp_f32_e64 v10, v10, s3
; SI-NEXT: v_mul_f32_e32 v11, v10, v11
; SI-NEXT: v_rndne_f32_e32 v11, v11
; SI-NEXT: v_fma_f32 v10, -v11, v9, v10
@@ -12545,9 +13561,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v9, v9, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
-; SI-NEXT: s_cbranch_vccz .LBB12_6
-; SI-NEXT: .LBB12_15: ; %frem.compute15
+; SI-NEXT: .LBB12_18:
+; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
+; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT: s_cbranch_vccz .LBB12_20
+; SI-NEXT: ; %bb.19: ; %frem.else16
+; SI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; SI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
+; SI-NEXT: s_mov_b64 s[2:3], 0
+; SI-NEXT: s_branch .LBB12_21
+; SI-NEXT: .LBB12_20:
+; SI-NEXT: s_mov_b64 s[2:3], -1
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: .LBB12_21: ; %Flow119
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cselect_b32 s2, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s2, 1
+; SI-NEXT: s_cbranch_scc1 .LBB12_27
+; SI-NEXT: ; %bb.22: ; %frem.compute15
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v2|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v10, v2
@@ -12582,11 +13614,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v12, v12, v14, v15
; SI-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_18
-; SI-NEXT: ; %bb.16: ; %frem.loop_body23.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_26
+; SI-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_17: ; %frem.loop_body23
+; SI-NEXT: .LBB12_24: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v13, v11
; SI-NEXT: v_mul_f32_e32 v11, v13, v12
@@ -12598,13 +13630,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v11, v11, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_17
-; SI-NEXT: s_branch .LBB12_19
-; SI-NEXT: .LBB12_18:
-; SI-NEXT: v_mov_b32_e32 v13, v11
-; SI-NEXT: .LBB12_19: ; %frem.loop_exit24
+; SI-NEXT: s_cbranch_scc1 .LBB12_24
+; SI-NEXT: ; %bb.25: ; %Flow117
+; SI-NEXT: v_mov_b32_e32 v11, v13
+; SI-NEXT: .LBB12_26: ; %frem.loop_exit24
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v11, v13, s3
+; SI-NEXT: v_ldexp_f32_e64 v11, v11, s3
; SI-NEXT: v_mul_f32_e32 v12, v11, v12
; SI-NEXT: v_rndne_f32_e32 v12, v12
; SI-NEXT: v_fma_f32 v11, -v12, v10, v11
@@ -12614,9 +13645,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v10, v10, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v10, s2, v10, v2
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
-; SI-NEXT: s_cbranch_vccz .LBB12_7
-; SI-NEXT: .LBB12_20: ; %frem.compute
+; SI-NEXT: .LBB12_27:
+; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
+; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT: s_cbranch_vccz .LBB12_29
+; SI-NEXT: ; %bb.28: ; %frem.else
+; SI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; SI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
+; SI-NEXT: s_mov_b64 s[2:3], 0
+; SI-NEXT: s_branch .LBB12_30
+; SI-NEXT: .LBB12_29:
+; SI-NEXT: s_mov_b64 s[2:3], -1
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: .LBB12_30: ; %Flow115
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cselect_b32 s2, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s2, 1
+; SI-NEXT: s_cbranch_scc1 .LBB12_36
+; SI-NEXT: ; %bb.31: ; %frem.compute
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v11, v3
@@ -12651,11 +13698,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v13, v13, v15, v16
; SI-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_23
-; SI-NEXT: ; %bb.21: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_35
+; SI-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_22: ; %frem.loop_body
+; SI-NEXT: .LBB12_33: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v14, v12
; SI-NEXT: v_mul_f32_e32 v12, v14, v13
@@ -12667,13 +13714,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v12, v12, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_22
-; SI-NEXT: s_branch .LBB12_24
-; SI-NEXT: .LBB12_23:
-; SI-NEXT: v_mov_b32_e32 v14, v12
-; SI-NEXT: .LBB12_24: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB12_33
+; SI-NEXT: ; %bb.34: ; %Flow
+; SI-NEXT: v_mov_b32_e32 v12, v14
+; SI-NEXT: .LBB12_35: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v12, v14, s3
+; SI-NEXT: v_ldexp_f32_e64 v12, v12, s3
; SI-NEXT: v_mul_f32_e32 v13, v12, v13
; SI-NEXT: v_rndne_f32_e32 v13, v13
; SI-NEXT: v_fma_f32 v12, -v13, v11, v12
@@ -12683,7 +13729,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v11, v11, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; SI-NEXT: .LBB12_25:
+; SI-NEXT: .LBB12_36: ; %Flow116
; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; SI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -12721,79 +13767,70 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; CI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:64
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v4|
-; CI-NEXT: s_cbranch_vccz .LBB12_4
-; CI-NEXT: ; %bb.1: ; %frem.compute77
+; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB12_2
+; CI-NEXT: ; %bb.1: ; %frem.else78
+; CI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; CI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: s_branch .LBB12_3
+; CI-NEXT: .LBB12_2:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr8
+; CI-NEXT: .LBB12_3: ; %Flow127
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB12_9
+; CI-NEXT: ; %bb.4: ; %frem.compute77
; CI-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; CI-NEXT: v_ldexp_f32_e64 v9, v9, 1
; CI-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v14, v4
-; CI-NEXT: v_ldexp_f32_e64 v12, v8, 12
+; CI-NEXT: v_ldexp_f32_e64 v11, v8, 12
; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v14
; CI-NEXT: v_frexp_exp_i32_f32_e32 v13, v0
; CI-NEXT: v_not_b32_e32 v10, v8
; CI-NEXT: v_add_i32_e32 v10, vcc, v10, v13
-; CI-NEXT: v_div_scale_f32 v11, vcc, 1.0, v9, 1.0
+; CI-NEXT: v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
; CI-NEXT: v_rcp_f32_e32 v16, v15
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v17, -v15, v16, 1.0
; CI-NEXT: v_fma_f32 v16, v17, v16, v16
-; CI-NEXT: v_mul_f32_e32 v17, v11, v16
-; CI-NEXT: v_fma_f32 v18, -v15, v17, v11
+; CI-NEXT: v_mul_f32_e32 v17, v12, v16
+; CI-NEXT: v_fma_f32 v18, -v15, v17, v12
; CI-NEXT: v_fma_f32 v17, v18, v16, v17
-; CI-NEXT: v_fma_f32 v11, -v15, v17, v11
+; CI-NEXT: v_fma_f32 v12, -v15, v17, v12
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v11, v11, v16, v17
+; CI-NEXT: v_div_fmas_f32 v12, v12, v16, v17
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v10
-; CI-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
+; CI-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
; CI-NEXT: s_cbranch_vccnz .LBB12_8
-; CI-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
+; CI-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
; CI-NEXT: v_sub_i32_e32 v10, vcc, v13, v14
; CI-NEXT: v_add_i32_e32 v10, vcc, 12, v10
-; CI-NEXT: .LBB12_3: ; %frem.loop_body85
+; CI-NEXT: .LBB12_6: ; %frem.loop_body85
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v13, v12
-; CI-NEXT: v_mul_f32_e32 v12, v13, v11
-; CI-NEXT: v_rndne_f32_e32 v12, v12
-; CI-NEXT: v_fma_f32 v12, -v12, v9, v13
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
-; CI-NEXT: v_add_f32_e32 v14, v12, v9
-; CI-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc
+; CI-NEXT: v_mov_b32_e32 v13, v11
+; CI-NEXT: v_mul_f32_e32 v11, v13, v12
+; CI-NEXT: v_rndne_f32_e32 v11, v11
+; CI-NEXT: v_fma_f32 v11, -v11, v9, v13
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
+; CI-NEXT: v_add_f32_e32 v14, v11, v9
+; CI-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
; CI-NEXT: v_add_i32_e32 v10, vcc, -12, v10
-; CI-NEXT: v_ldexp_f32_e64 v12, v12, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v10
-; CI-NEXT: s_cbranch_vccnz .LBB12_3
-; CI-NEXT: s_branch .LBB12_9
-; CI-NEXT: .LBB12_4: ; %frem.else78
-; CI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
-; CI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
-; CI-NEXT: s_cbranch_vccnz .LBB12_10
-; CI-NEXT: .LBB12_5: ; %frem.else47
-; CI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
-; CI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
-; CI-NEXT: s_cbranch_vccnz .LBB12_15
-; CI-NEXT: .LBB12_6: ; %frem.else16
-; CI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
-; CI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
-; CI-NEXT: s_cbranch_vccnz .LBB12_20
-; CI-NEXT: .LBB12_7: ; %frem.else
-; CI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
-; CI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
-; CI-NEXT: s_branch .LBB12_25
-; CI-NEXT: .LBB12_8:
-; CI-NEXT: v_mov_b32_e32 v13, v12
-; CI-NEXT: .LBB12_9: ; %frem.loop_exit86
+; CI-NEXT: v_ldexp_f32_e64 v11, v11, 12
+; CI-NEXT: s_cbranch_vccnz .LBB12_6
+; CI-NEXT: ; %bb.7: ; %Flow125
+; CI-NEXT: v_mov_b32_e32 v11, v13
+; CI-NEXT: .LBB12_8: ; %frem.loop_exit86
; CI-NEXT: v_add_i32_e32 v10, vcc, -11, v10
-; CI-NEXT: v_ldexp_f32_e32 v10, v13, v10
-; CI-NEXT: v_mul_f32_e32 v11, v10, v11
+; CI-NEXT: v_ldexp_f32_e32 v10, v11, v10
+; CI-NEXT: v_mul_f32_e32 v11, v10, v12
; CI-NEXT: v_rndne_f32_e32 v11, v11
; CI-NEXT: v_fma_f32 v10, -v11, v9, v10
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
@@ -12802,56 +13839,71 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v8, v9, v8
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v8, s2, v8, v0
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
-; CI-NEXT: s_cbranch_vccz .LBB12_5
-; CI-NEXT: .LBB12_10: ; %frem.compute46
+; CI-NEXT: .LBB12_9:
+; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB12_11
+; CI-NEXT: ; %bb.10: ; %frem.else47
+; CI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; CI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: s_branch .LBB12_12
+; CI-NEXT: .LBB12_11:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr9
+; CI-NEXT: .LBB12_12: ; %Flow123
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB12_18
+; CI-NEXT: ; %bb.13: ; %frem.compute46
; CI-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; CI-NEXT: v_ldexp_f32_e64 v10, v10, 1
; CI-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v9, |v1|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v15, v5
-; CI-NEXT: v_ldexp_f32_e64 v13, v9, 12
+; CI-NEXT: v_ldexp_f32_e64 v12, v9, 12
; CI-NEXT: v_add_i32_e32 v9, vcc, -1, v15
; CI-NEXT: v_frexp_exp_i32_f32_e32 v14, v1
; CI-NEXT: v_not_b32_e32 v11, v9
; CI-NEXT: v_add_i32_e32 v11, vcc, v11, v14
-; CI-NEXT: v_div_scale_f32 v12, vcc, 1.0, v10, 1.0
+; CI-NEXT: v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
; CI-NEXT: v_rcp_f32_e32 v17, v16
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; CI-NEXT: v_fma_f32 v17, v18, v17, v17
-; CI-NEXT: v_mul_f32_e32 v18, v12, v17
-; CI-NEXT: v_fma_f32 v19, -v16, v18, v12
+; CI-NEXT: v_mul_f32_e32 v18, v13, v17
+; CI-NEXT: v_fma_f32 v19, -v16, v18, v13
; CI-NEXT: v_fma_f32 v18, v19, v17, v18
-; CI-NEXT: v_fma_f32 v12, -v16, v18, v12
+; CI-NEXT: v_fma_f32 v13, -v16, v18, v13
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v12, v12, v17, v18
+; CI-NEXT: v_div_fmas_f32 v13, v13, v17, v18
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v11
-; CI-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_13
-; CI-NEXT: ; %bb.11: ; %frem.loop_body54.preheader
+; CI-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB12_17
+; CI-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
; CI-NEXT: v_sub_i32_e32 v11, vcc, v14, v15
; CI-NEXT: v_add_i32_e32 v11, vcc, 12, v11
-; CI-NEXT: .LBB12_12: ; %frem.loop_body54
+; CI-NEXT: .LBB12_15: ; %frem.loop_body54
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v14, v13
-; CI-NEXT: v_mul_f32_e32 v13, v14, v12
-; CI-NEXT: v_rndne_f32_e32 v13, v13
-; CI-NEXT: v_fma_f32 v13, -v13, v10, v14
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
-; CI-NEXT: v_add_f32_e32 v15, v13, v10
-; CI-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
+; CI-NEXT: v_mov_b32_e32 v14, v12
+; CI-NEXT: v_mul_f32_e32 v12, v14, v13
+; CI-NEXT: v_rndne_f32_e32 v12, v12
+; CI-NEXT: v_fma_f32 v12, -v12, v10, v14
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
+; CI-NEXT: v_add_f32_e32 v15, v12, v10
+; CI-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
; CI-NEXT: v_add_i32_e32 v11, vcc, -12, v11
-; CI-NEXT: v_ldexp_f32_e64 v13, v13, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v11
-; CI-NEXT: s_cbranch_vccnz .LBB12_12
-; CI-NEXT: s_branch .LBB12_14
-; CI-NEXT: .LBB12_13:
-; CI-NEXT: v_mov_b32_e32 v14, v13
-; CI-NEXT: .LBB12_14: ; %frem.loop_exit55
+; CI-NEXT: v_ldexp_f32_e64 v12, v12, 12
+; CI-NEXT: s_cbranch_vccnz .LBB12_15
+; CI-NEXT: ; %bb.16: ; %Flow121
+; CI-NEXT: v_mov_b32_e32 v12, v14
+; CI-NEXT: .LBB12_17: ; %frem.loop_exit55
; CI-NEXT: v_add_i32_e32 v11, vcc, -11, v11
-; CI-NEXT: v_ldexp_f32_e32 v11, v14, v11
-; CI-NEXT: v_mul_f32_e32 v12, v11, v12
+; CI-NEXT: v_ldexp_f32_e32 v11, v12, v11
+; CI-NEXT: v_mul_f32_e32 v12, v11, v13
; CI-NEXT: v_rndne_f32_e32 v12, v12
; CI-NEXT: v_fma_f32 v11, -v12, v10, v11
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
@@ -12860,56 +13912,71 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v9, v10, v9
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
-; CI-NEXT: s_cbranch_vccz .LBB12_6
-; CI-NEXT: .LBB12_15: ; %frem.compute15
+; CI-NEXT: .LBB12_18:
+; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB12_20
+; CI-NEXT: ; %bb.19: ; %frem.else16
+; CI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; CI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: s_branch .LBB12_21
+; CI-NEXT: .LBB12_20:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr10
+; CI-NEXT: .LBB12_21: ; %Flow119
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB12_27
+; CI-NEXT: ; %bb.22: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; CI-NEXT: v_ldexp_f32_e64 v11, v11, 1
; CI-NEXT: v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v16, v6
-; CI-NEXT: v_ldexp_f32_e64 v14, v10, 12
+; CI-NEXT: v_ldexp_f32_e64 v13, v10, 12
; CI-NEXT: v_add_i32_e32 v10, vcc, -1, v16
; CI-NEXT: v_frexp_exp_i32_f32_e32 v15, v2
; CI-NEXT: v_not_b32_e32 v12, v10
; CI-NEXT: v_add_i32_e32 v12, vcc, v12, v15
-; CI-NEXT: v_div_scale_f32 v13, vcc, 1.0, v11, 1.0
+; CI-NEXT: v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
; CI-NEXT: v_rcp_f32_e32 v18, v17
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v19, -v17, v18, 1.0
; CI-NEXT: v_fma_f32 v18, v19, v18, v18
-; CI-NEXT: v_mul_f32_e32 v19, v13, v18
-; CI-NEXT: v_fma_f32 v20, -v17, v19, v13
+; CI-NEXT: v_mul_f32_e32 v19, v14, v18
+; CI-NEXT: v_fma_f32 v20, -v17, v19, v14
; CI-NEXT: v_fma_f32 v19, v20, v18, v19
-; CI-NEXT: v_fma_f32 v13, -v17, v19, v13
+; CI-NEXT: v_fma_f32 v14, -v17, v19, v14
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v13, v13, v18, v19
+; CI-NEXT: v_div_fmas_f32 v14, v14, v18, v19
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v12
-; CI-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_18
-; CI-NEXT: ; %bb.16: ; %frem.loop_body23.preheader
+; CI-NEXT: v_div_fixup_f32 v14, v14, v11, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB12_26
+; CI-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
; CI-NEXT: v_sub_i32_e32 v12, vcc, v15, v16
; CI-NEXT: v_add_i32_e32 v12, vcc, 12, v12
-; CI-NEXT: .LBB12_17: ; %frem.loop_body23
+; CI-NEXT: .LBB12_24: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v15, v14
-; CI-NEXT: v_mul_f32_e32 v14, v15, v13
-; CI-NEXT: v_rndne_f32_e32 v14, v14
-; CI-NEXT: v_fma_f32 v14, -v14, v11, v15
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
-; CI-NEXT: v_add_f32_e32 v16, v14, v11
-; CI-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
+; CI-NEXT: v_mov_b32_e32 v15, v13
+; CI-NEXT: v_mul_f32_e32 v13, v15, v14
+; CI-NEXT: v_rndne_f32_e32 v13, v13
+; CI-NEXT: v_fma_f32 v13, -v13, v11, v15
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
+; CI-NEXT: v_add_f32_e32 v16, v13, v11
+; CI-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc
; CI-NEXT: v_add_i32_e32 v12, vcc, -12, v12
-; CI-NEXT: v_ldexp_f32_e64 v14, v14, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v12
-; CI-NEXT: s_cbranch_vccnz .LBB12_17
-; CI-NEXT: s_branch .LBB12_19
-; CI-NEXT: .LBB12_18:
-; CI-NEXT: v_mov_b32_e32 v15, v14
-; CI-NEXT: .LBB12_19: ; %frem.loop_exit24
+; CI-NEXT: v_ldexp_f32_e64 v13, v13, 12
+; CI-NEXT: s_cbranch_vccnz .LBB12_24
+; CI-NEXT: ; %bb.25: ; %Flow117
+; CI-NEXT: v_mov_b32_e32 v13, v15
+; CI-NEXT: .LBB12_26: ; %frem.loop_exit24
; CI-NEXT: v_add_i32_e32 v12, vcc, -11, v12
-; CI-NEXT: v_ldexp_f32_e32 v12, v15, v12
-; CI-NEXT: v_mul_f32_e32 v13, v12, v13
+; CI-NEXT: v_ldexp_f32_e32 v12, v13, v12
+; CI-NEXT: v_mul_f32_e32 v13, v12, v14
; CI-NEXT: v_rndne_f32_e32 v13, v13
; CI-NEXT: v_fma_f32 v12, -v13, v11, v12
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
@@ -12918,56 +13985,71 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v10, v11, v10
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v10, s2, v10, v2
-; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
-; CI-NEXT: s_cbranch_vccz .LBB12_7
-; CI-NEXT: .LBB12_20: ; %frem.compute
+; CI-NEXT: .LBB12_27:
+; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB12_29
+; CI-NEXT: ; %bb.28: ; %frem.else
+; CI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; CI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: s_branch .LBB12_30
+; CI-NEXT: .LBB12_29:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr11
+; CI-NEXT: .LBB12_30: ; %Flow115
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB12_36
+; CI-NEXT: ; %bb.31: ; %frem.compute
; CI-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; CI-NEXT: v_ldexp_f32_e64 v12, v12, 1
; CI-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v17, v7
-; CI-NEXT: v_ldexp_f32_e64 v15, v11, 12
+; CI-NEXT: v_ldexp_f32_e64 v14, v11, 12
; CI-NEXT: v_add_i32_e32 v11, vcc, -1, v17
; CI-NEXT: v_frexp_exp_i32_f32_e32 v16, v3
; CI-NEXT: v_not_b32_e32 v13, v11
; CI-NEXT: v_add_i32_e32 v13, vcc, v13, v16
-; CI-NEXT: v_div_scale_f32 v14, vcc, 1.0, v12, 1.0
+; CI-NEXT: v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; CI-NEXT: v_rcp_f32_e32 v19, v18
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v20, -v18, v19, 1.0
; CI-NEXT: v_fma_f32 v19, v20, v19, v19
-; CI-NEXT: v_mul_f32_e32 v20, v14, v19
-; CI-NEXT: v_fma_f32 v21, -v18, v20, v14
+; CI-NEXT: v_mul_f32_e32 v20, v15, v19
+; CI-NEXT: v_fma_f32 v21, -v18, v20, v15
; CI-NEXT: v_fma_f32 v20, v21, v19, v20
-; CI-NEXT: v_fma_f32 v14, -v18, v20, v14
+; CI-NEXT: v_fma_f32 v15, -v18, v20, v15
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v14, v14, v19, v20
+; CI-NEXT: v_div_fmas_f32 v15, v15, v19, v20
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v13
-; CI-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_23
-; CI-NEXT: ; %bb.21: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB12_35
+; CI-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v13, vcc, v16, v17
; CI-NEXT: v_add_i32_e32 v13, vcc, 12, v13
-; CI-NEXT: .LBB12_22: ; %frem.loop_body
+; CI-NEXT: .LBB12_33: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v16, v15
-; CI-NEXT: v_mul_f32_e32 v15, v16, v14
-; CI-NEXT: v_rndne_f32_e32 v15, v15
-; CI-NEXT: v_fma_f32 v15, -v15, v12, v16
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v15
-; CI-NEXT: v_add_f32_e32 v17, v15, v12
-; CI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; CI-NEXT: v_mov_b32_e32 v16, v14
+; CI-NEXT: v_mul_f32_e32 v14, v16, v15
+; CI-NEXT: v_rndne_f32_e32 v14, v14
+; CI-NEXT: v_fma_f32 v14, -v14, v12, v16
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
+; CI-NEXT: v_add_f32_e32 v17, v14, v12
+; CI-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
; CI-NEXT: v_add_i32_e32 v13, vcc, -12, v13
-; CI-NEXT: v_ldexp_f32_e64 v15, v15, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v13
-; CI-NEXT: s_cbranch_vccnz .LBB12_22
-; CI-NEXT: s_branch .LBB12_24
-; CI-NEXT: .LBB12_23:
-; CI-NEXT: v_mov_b32_e32 v16, v15
-; CI-NEXT: .LBB12_24: ; %frem.loop_exit
+; CI-NEXT: v_ldexp_f32_e64 v14, v14, 12
+; CI-NEXT: s_cbranch_vccnz .LBB12_33
+; CI-NEXT: ; %bb.34: ; %Flow
+; CI-NEXT: v_mov_b32_e32 v14, v16
+; CI-NEXT: .LBB12_35: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v13, vcc, -11, v13
-; CI-NEXT: v_ldexp_f32_e32 v13, v16, v13
-; CI-NEXT: v_mul_f32_e32 v14, v13, v14
+; CI-NEXT: v_ldexp_f32_e32 v13, v14, v13
+; CI-NEXT: v_mul_f32_e32 v14, v13, v15
; CI-NEXT: v_rndne_f32_e32 v14, v14
; CI-NEXT: v_fma_f32 v13, -v14, v12, v13
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
@@ -12976,7 +14058,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v11, v12, v11
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; CI-NEXT: .LBB12_25:
+; CI-NEXT: .LBB12_36: ; %Flow116
; CI-NEXT: s_mov_b32 s4, 0x7f800000
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -13014,79 +14096,70 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v4|
-; VI-NEXT: s_cbranch_vccz .LBB12_4
-; VI-NEXT: ; %bb.1: ; %frem.compute77
+; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB12_2
+; VI-NEXT: ; %bb.1: ; %frem.else78
+; VI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; VI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB12_3
+; VI-NEXT: .LBB12_2:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr8
+; VI-NEXT: .LBB12_3: ; %Flow127
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB12_9
+; VI-NEXT: ; %bb.4: ; %frem.compute77
; VI-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; VI-NEXT: v_ldexp_f32 v9, v9, 1
; VI-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v14, v4
-; VI-NEXT: v_ldexp_f32 v12, v8, 12
+; VI-NEXT: v_ldexp_f32 v11, v8, 12
; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v14
; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v0
; VI-NEXT: v_not_b32_e32 v10, v8
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v13
-; VI-NEXT: v_div_scale_f32 v11, vcc, 1.0, v9, 1.0
+; VI-NEXT: v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
; VI-NEXT: v_rcp_f32_e32 v16, v15
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v17, -v15, v16, 1.0
; VI-NEXT: v_fma_f32 v16, v17, v16, v16
-; VI-NEXT: v_mul_f32_e32 v17, v11, v16
-; VI-NEXT: v_fma_f32 v18, -v15, v17, v11
+; VI-NEXT: v_mul_f32_e32 v17, v12, v16
+; VI-NEXT: v_fma_f32 v18, -v15, v17, v12
; VI-NEXT: v_fma_f32 v17, v18, v16, v17
-; VI-NEXT: v_fma_f32 v11, -v15, v17, v11
+; VI-NEXT: v_fma_f32 v12, -v15, v17, v12
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v11, v11, v16, v17
+; VI-NEXT: v_div_fmas_f32 v12, v12, v16, v17
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v10
-; VI-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
+; VI-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
; VI-NEXT: s_cbranch_vccnz .LBB12_8
-; VI-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
+; VI-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
; VI-NEXT: v_sub_u32_e32 v10, vcc, v13, v14
; VI-NEXT: v_add_u32_e32 v10, vcc, 12, v10
-; VI-NEXT: .LBB12_3: ; %frem.loop_body85
+; VI-NEXT: .LBB12_6: ; %frem.loop_body85
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v13, v12
-; VI-NEXT: v_mul_f32_e32 v12, v13, v11
-; VI-NEXT: v_rndne_f32_e32 v12, v12
-; VI-NEXT: v_fma_f32 v12, -v12, v9, v13
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
-; VI-NEXT: v_add_f32_e32 v14, v12, v9
-; VI-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc
+; VI-NEXT: v_mov_b32_e32 v13, v11
+; VI-NEXT: v_mul_f32_e32 v11, v13, v12
+; VI-NEXT: v_rndne_f32_e32 v11, v11
+; VI-NEXT: v_fma_f32 v11, -v11, v9, v13
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
+; VI-NEXT: v_add_f32_e32 v14, v11, v9
+; VI-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, -12, v10
-; VI-NEXT: v_ldexp_f32 v12, v12, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v10
-; VI-NEXT: s_cbranch_vccnz .LBB12_3
-; VI-NEXT: s_branch .LBB12_9
-; VI-NEXT: .LBB12_4: ; %frem.else78
-; VI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
-; VI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
-; VI-NEXT: s_cbranch_vccnz .LBB12_10
-; VI-NEXT: .LBB12_5: ; %frem.else47
-; VI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
-; VI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
-; VI-NEXT: s_cbranch_vccnz .LBB12_15
-; VI-NEXT: .LBB12_6: ; %frem.else16
-; VI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
-; VI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
-; VI-NEXT: s_cbranch_vccnz .LBB12_20
-; VI-NEXT: .LBB12_7: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
-; VI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
-; VI-NEXT: s_branch .LBB12_25
-; VI-NEXT: .LBB12_8:
-; VI-NEXT: v_mov_b32_e32 v13, v12
-; VI-NEXT: .LBB12_9: ; %frem.loop_exit86
+; VI-NEXT: v_ldexp_f32 v11, v11, 12
+; VI-NEXT: s_cbranch_vccnz .LBB12_6
+; VI-NEXT: ; %bb.7: ; %Flow125
+; VI-NEXT: v_mov_b32_e32 v11, v13
+; VI-NEXT: .LBB12_8: ; %frem.loop_exit86
; VI-NEXT: v_add_u32_e32 v10, vcc, -11, v10
-; VI-NEXT: v_ldexp_f32 v10, v13, v10
-; VI-NEXT: v_mul_f32_e32 v11, v10, v11
+; VI-NEXT: v_ldexp_f32 v10, v11, v10
+; VI-NEXT: v_mul_f32_e32 v11, v10, v12
; VI-NEXT: v_rndne_f32_e32 v11, v11
; VI-NEXT: v_fma_f32 v10, -v11, v9, v10
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
@@ -13095,56 +14168,71 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v8, v9, v8
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v8, s2, v8, v0
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
-; VI-NEXT: s_cbranch_vccz .LBB12_5
-; VI-NEXT: .LBB12_10: ; %frem.compute46
+; VI-NEXT: .LBB12_9:
+; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB12_11
+; VI-NEXT: ; %bb.10: ; %frem.else47
+; VI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; VI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB12_12
+; VI-NEXT: .LBB12_11:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr9
+; VI-NEXT: .LBB12_12: ; %Flow123
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB12_18
+; VI-NEXT: ; %bb.13: ; %frem.compute46
; VI-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; VI-NEXT: v_ldexp_f32 v10, v10, 1
; VI-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v9, |v1|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v15, v5
-; VI-NEXT: v_ldexp_f32 v13, v9, 12
+; VI-NEXT: v_ldexp_f32 v12, v9, 12
; VI-NEXT: v_add_u32_e32 v9, vcc, -1, v15
; VI-NEXT: v_frexp_exp_i32_f32_e32 v14, v1
; VI-NEXT: v_not_b32_e32 v11, v9
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v14
-; VI-NEXT: v_div_scale_f32 v12, vcc, 1.0, v10, 1.0
+; VI-NEXT: v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
; VI-NEXT: v_rcp_f32_e32 v17, v16
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; VI-NEXT: v_fma_f32 v17, v18, v17, v17
-; VI-NEXT: v_mul_f32_e32 v18, v12, v17
-; VI-NEXT: v_fma_f32 v19, -v16, v18, v12
+; VI-NEXT: v_mul_f32_e32 v18, v13, v17
+; VI-NEXT: v_fma_f32 v19, -v16, v18, v13
; VI-NEXT: v_fma_f32 v18, v19, v17, v18
-; VI-NEXT: v_fma_f32 v12, -v16, v18, v12
+; VI-NEXT: v_fma_f32 v13, -v16, v18, v13
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v12, v12, v17, v18
+; VI-NEXT: v_div_fmas_f32 v13, v13, v17, v18
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v11
-; VI-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_13
-; VI-NEXT: ; %bb.11: ; %frem.loop_body54.preheader
+; VI-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB12_17
+; VI-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
; VI-NEXT: v_sub_u32_e32 v11, vcc, v14, v15
; VI-NEXT: v_add_u32_e32 v11, vcc, 12, v11
-; VI-NEXT: .LBB12_12: ; %frem.loop_body54
+; VI-NEXT: .LBB12_15: ; %frem.loop_body54
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v14, v13
-; VI-NEXT: v_mul_f32_e32 v13, v14, v12
-; VI-NEXT: v_rndne_f32_e32 v13, v13
-; VI-NEXT: v_fma_f32 v13, -v13, v10, v14
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
-; VI-NEXT: v_add_f32_e32 v15, v13, v10
-; VI-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
+; VI-NEXT: v_mov_b32_e32 v14, v12
+; VI-NEXT: v_mul_f32_e32 v12, v14, v13
+; VI-NEXT: v_rndne_f32_e32 v12, v12
+; VI-NEXT: v_fma_f32 v12, -v12, v10, v14
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
+; VI-NEXT: v_add_f32_e32 v15, v12, v10
+; VI-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
; VI-NEXT: v_add_u32_e32 v11, vcc, -12, v11
-; VI-NEXT: v_ldexp_f32 v13, v13, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v11
-; VI-NEXT: s_cbranch_vccnz .LBB12_12
-; VI-NEXT: s_branch .LBB12_14
-; VI-NEXT: .LBB12_13:
-; VI-NEXT: v_mov_b32_e32 v14, v13
-; VI-NEXT: .LBB12_14: ; %frem.loop_exit55
+; VI-NEXT: v_ldexp_f32 v12, v12, 12
+; VI-NEXT: s_cbranch_vccnz .LBB12_15
+; VI-NEXT: ; %bb.16: ; %Flow121
+; VI-NEXT: v_mov_b32_e32 v12, v14
+; VI-NEXT: .LBB12_17: ; %frem.loop_exit55
; VI-NEXT: v_add_u32_e32 v11, vcc, -11, v11
-; VI-NEXT: v_ldexp_f32 v11, v14, v11
-; VI-NEXT: v_mul_f32_e32 v12, v11, v12
+; VI-NEXT: v_ldexp_f32 v11, v12, v11
+; VI-NEXT: v_mul_f32_e32 v12, v11, v13
; VI-NEXT: v_rndne_f32_e32 v12, v12
; VI-NEXT: v_fma_f32 v11, -v12, v10, v11
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
@@ -13153,56 +14241,71 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v9, v10, v9
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
-; VI-NEXT: s_cbranch_vccz .LBB12_6
-; VI-NEXT: .LBB12_15: ; %frem.compute15
+; VI-NEXT: .LBB12_18:
+; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB12_20
+; VI-NEXT: ; %bb.19: ; %frem.else16
+; VI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; VI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB12_21
+; VI-NEXT: .LBB12_20:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr10
+; VI-NEXT: .LBB12_21: ; %Flow119
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB12_27
+; VI-NEXT: ; %bb.22: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; VI-NEXT: v_ldexp_f32 v11, v11, 1
; VI-NEXT: v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v16, v6
-; VI-NEXT: v_ldexp_f32 v14, v10, 12
+; VI-NEXT: v_ldexp_f32 v13, v10, 12
; VI-NEXT: v_add_u32_e32 v10, vcc, -1, v16
; VI-NEXT: v_frexp_exp_i32_f32_e32 v15, v2
; VI-NEXT: v_not_b32_e32 v12, v10
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v15
-; VI-NEXT: v_div_scale_f32 v13, vcc, 1.0, v11, 1.0
+; VI-NEXT: v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
; VI-NEXT: v_rcp_f32_e32 v18, v17
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v19, -v17, v18, 1.0
; VI-NEXT: v_fma_f32 v18, v19, v18, v18
-; VI-NEXT: v_mul_f32_e32 v19, v13, v18
-; VI-NEXT: v_fma_f32 v20, -v17, v19, v13
+; VI-NEXT: v_mul_f32_e32 v19, v14, v18
+; VI-NEXT: v_fma_f32 v20, -v17, v19, v14
; VI-NEXT: v_fma_f32 v19, v20, v18, v19
-; VI-NEXT: v_fma_f32 v13, -v17, v19, v13
+; VI-NEXT: v_fma_f32 v14, -v17, v19, v14
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v13, v13, v18, v19
+; VI-NEXT: v_div_fmas_f32 v14, v14, v18, v19
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v12
-; VI-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_18
-; VI-NEXT: ; %bb.16: ; %frem.loop_body23.preheader
+; VI-NEXT: v_div_fixup_f32 v14, v14, v11, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB12_26
+; VI-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
; VI-NEXT: v_sub_u32_e32 v12, vcc, v15, v16
; VI-NEXT: v_add_u32_e32 v12, vcc, 12, v12
-; VI-NEXT: .LBB12_17: ; %frem.loop_body23
+; VI-NEXT: .LBB12_24: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v15, v14
-; VI-NEXT: v_mul_f32_e32 v14, v15, v13
-; VI-NEXT: v_rndne_f32_e32 v14, v14
-; VI-NEXT: v_fma_f32 v14, -v14, v11, v15
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
-; VI-NEXT: v_add_f32_e32 v16, v14, v11
-; VI-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
+; VI-NEXT: v_mov_b32_e32 v15, v13
+; VI-NEXT: v_mul_f32_e32 v13, v15, v14
+; VI-NEXT: v_rndne_f32_e32 v13, v13
+; VI-NEXT: v_fma_f32 v13, -v13, v11, v15
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
+; VI-NEXT: v_add_f32_e32 v16, v13, v11
+; VI-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc
; VI-NEXT: v_add_u32_e32 v12, vcc, -12, v12
-; VI-NEXT: v_ldexp_f32 v14, v14, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v12
-; VI-NEXT: s_cbranch_vccnz .LBB12_17
-; VI-NEXT: s_branch .LBB12_19
-; VI-NEXT: .LBB12_18:
-; VI-NEXT: v_mov_b32_e32 v15, v14
-; VI-NEXT: .LBB12_19: ; %frem.loop_exit24
+; VI-NEXT: v_ldexp_f32 v13, v13, 12
+; VI-NEXT: s_cbranch_vccnz .LBB12_24
+; VI-NEXT: ; %bb.25: ; %Flow117
+; VI-NEXT: v_mov_b32_e32 v13, v15
+; VI-NEXT: .LBB12_26: ; %frem.loop_exit24
; VI-NEXT: v_add_u32_e32 v12, vcc, -11, v12
-; VI-NEXT: v_ldexp_f32 v12, v15, v12
-; VI-NEXT: v_mul_f32_e32 v13, v12, v13
+; VI-NEXT: v_ldexp_f32 v12, v13, v12
+; VI-NEXT: v_mul_f32_e32 v13, v12, v14
; VI-NEXT: v_rndne_f32_e32 v13, v13
; VI-NEXT: v_fma_f32 v12, -v13, v11, v12
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
@@ -13211,56 +14314,71 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v10, v11, v10
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v10, s2, v10, v2
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
-; VI-NEXT: s_cbranch_vccz .LBB12_7
-; VI-NEXT: .LBB12_20: ; %frem.compute
+; VI-NEXT: .LBB12_27:
+; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB12_29
+; VI-NEXT: ; %bb.28: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; VI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: s_branch .LBB12_30
+; VI-NEXT: .LBB12_29:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr11
+; VI-NEXT: .LBB12_30: ; %Flow115
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB12_36
+; VI-NEXT: ; %bb.31: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; VI-NEXT: v_ldexp_f32 v12, v12, 1
; VI-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v17, v7
-; VI-NEXT: v_ldexp_f32 v15, v11, 12
+; VI-NEXT: v_ldexp_f32 v14, v11, 12
; VI-NEXT: v_add_u32_e32 v11, vcc, -1, v17
; VI-NEXT: v_frexp_exp_i32_f32_e32 v16, v3
; VI-NEXT: v_not_b32_e32 v13, v11
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v16
-; VI-NEXT: v_div_scale_f32 v14, vcc, 1.0, v12, 1.0
+; VI-NEXT: v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; VI-NEXT: v_rcp_f32_e32 v19, v18
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v20, -v18, v19, 1.0
; VI-NEXT: v_fma_f32 v19, v20, v19, v19
-; VI-NEXT: v_mul_f32_e32 v20, v14, v19
-; VI-NEXT: v_fma_f32 v21, -v18, v20, v14
+; VI-NEXT: v_mul_f32_e32 v20, v15, v19
+; VI-NEXT: v_fma_f32 v21, -v18, v20, v15
; VI-NEXT: v_fma_f32 v20, v21, v19, v20
-; VI-NEXT: v_fma_f32 v14, -v18, v20, v14
+; VI-NEXT: v_fma_f32 v15, -v18, v20, v15
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v14, v14, v19, v20
+; VI-NEXT: v_div_fmas_f32 v15, v15, v19, v20
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v13
-; VI-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_23
-; VI-NEXT: ; %bb.21: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB12_35
+; VI-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v13, vcc, v16, v17
; VI-NEXT: v_add_u32_e32 v13, vcc, 12, v13
-; VI-NEXT: .LBB12_22: ; %frem.loop_body
+; VI-NEXT: .LBB12_33: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v16, v15
-; VI-NEXT: v_mul_f32_e32 v15, v16, v14
-; VI-NEXT: v_rndne_f32_e32 v15, v15
-; VI-NEXT: v_fma_f32 v15, -v15, v12, v16
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v15
-; VI-NEXT: v_add_f32_e32 v17, v15, v12
-; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; VI-NEXT: v_mov_b32_e32 v16, v14
+; VI-NEXT: v_mul_f32_e32 v14, v16, v15
+; VI-NEXT: v_rndne_f32_e32 v14, v14
+; VI-NEXT: v_fma_f32 v14, -v14, v12, v16
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
+; VI-NEXT: v_add_f32_e32 v17, v14, v12
+; VI-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
; VI-NEXT: v_add_u32_e32 v13, vcc, -12, v13
-; VI-NEXT: v_ldexp_f32 v15, v15, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v13
-; VI-NEXT: s_cbranch_vccnz .LBB12_22
-; VI-NEXT: s_branch .LBB12_24
-; VI-NEXT: .LBB12_23:
-; VI-NEXT: v_mov_b32_e32 v16, v15
-; VI-NEXT: .LBB12_24: ; %frem.loop_exit
+; VI-NEXT: v_ldexp_f32 v14, v14, 12
+; VI-NEXT: s_cbranch_vccnz .LBB12_33
+; VI-NEXT: ; %bb.34: ; %Flow
+; VI-NEXT: v_mov_b32_e32 v14, v16
+; VI-NEXT: .LBB12_35: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v13, vcc, -11, v13
-; VI-NEXT: v_ldexp_f32 v13, v16, v13
-; VI-NEXT: v_mul_f32_e32 v14, v13, v14
+; VI-NEXT: v_ldexp_f32 v13, v14, v13
+; VI-NEXT: v_mul_f32_e32 v14, v13, v15
; VI-NEXT: v_rndne_f32_e32 v14, v14
; VI-NEXT: v_fma_f32 v13, -v14, v12, v13
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
@@ -13269,7 +14387,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v11, v12, v11
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; VI-NEXT: .LBB12_25:
+; VI-NEXT: .LBB12_36: ; %Flow116
; VI-NEXT: s_mov_b32 s4, 0x7f800000
; VI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -13302,16 +14420,31 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3]
; GFX9-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v4|
-; GFX9-NEXT: s_cbranch_vccz .LBB12_4
-; GFX9-NEXT: ; %bb.1: ; %frem.compute77
+; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB12_2
+; GFX9-NEXT: ; %bb.1: ; %frem.else78
+; GFX9-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB12_3
+; GFX9-NEXT: .LBB12_2:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr8
+; GFX9-NEXT: .LBB12_3: ; %Flow127
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB12_9
+; GFX9-NEXT: ; %bb.4: ; %frem.compute77
; GFX9-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; GFX9-NEXT: v_ldexp_f32 v9, v9, 1
; GFX9-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
-; GFX9-NEXT: v_div_scale_f32 v11, vcc, 1.0, v9, 1.0
+; GFX9-NEXT: v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v13, v0
-; GFX9-NEXT: v_ldexp_f32 v12, v8, 12
+; GFX9-NEXT: v_ldexp_f32 v11, v8, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v14, v4
; GFX9-NEXT: v_add_u32_e32 v8, -1, v14
; GFX9-NEXT: v_not_b32_e32 v10, v8
@@ -13320,61 +14453,37 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v17, -v15, v16, 1.0
; GFX9-NEXT: v_fma_f32 v16, v17, v16, v16
-; GFX9-NEXT: v_mul_f32_e32 v17, v11, v16
-; GFX9-NEXT: v_fma_f32 v18, -v15, v17, v11
+; GFX9-NEXT: v_mul_f32_e32 v17, v12, v16
+; GFX9-NEXT: v_fma_f32 v18, -v15, v17, v12
; GFX9-NEXT: v_fma_f32 v17, v18, v16, v17
-; GFX9-NEXT: v_fma_f32 v11, -v15, v17, v11
+; GFX9-NEXT: v_fma_f32 v12, -v15, v17, v12
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v11, v11, v16, v17
+; GFX9-NEXT: v_div_fmas_f32 v12, v12, v16, v17
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v10
-; GFX9-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
+; GFX9-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
; GFX9-NEXT: s_cbranch_vccnz .LBB12_8
-; GFX9-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
+; GFX9-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
; GFX9-NEXT: v_sub_u32_e32 v10, v13, v14
; GFX9-NEXT: v_add_u32_e32 v10, 12, v10
-; GFX9-NEXT: .LBB12_3: ; %frem.loop_body85
+; GFX9-NEXT: .LBB12_6: ; %frem.loop_body85
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v13, v12
-; GFX9-NEXT: v_mul_f32_e32 v12, v13, v11
-; GFX9-NEXT: v_rndne_f32_e32 v12, v12
-; GFX9-NEXT: v_fma_f32 v12, -v12, v9, v13
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
-; GFX9-NEXT: v_add_f32_e32 v14, v12, v9
-; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc
+; GFX9-NEXT: v_mov_b32_e32 v13, v11
+; GFX9-NEXT: v_mul_f32_e32 v11, v13, v12
+; GFX9-NEXT: v_rndne_f32_e32 v11, v11
+; GFX9-NEXT: v_fma_f32 v11, -v11, v9, v13
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
+; GFX9-NEXT: v_add_f32_e32 v14, v11, v9
; GFX9-NEXT: v_add_u32_e32 v10, -12, v10
-; GFX9-NEXT: v_ldexp_f32 v12, v12, 12
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v10
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_3
-; GFX9-NEXT: s_branch .LBB12_9
-; GFX9-NEXT: .LBB12_4: ; %frem.else78
-; GFX9-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_10
-; GFX9-NEXT: .LBB12_5: ; %frem.else47
-; GFX9-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_15
-; GFX9-NEXT: .LBB12_6: ; %frem.else16
-; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
-; GFX9-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_20
-; GFX9-NEXT: .LBB12_7: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
-; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
-; GFX9-NEXT: s_branch .LBB12_25
-; GFX9-NEXT: .LBB12_8:
-; GFX9-NEXT: v_mov_b32_e32 v13, v12
-; GFX9-NEXT: .LBB12_9: ; %frem.loop_exit86
+; GFX9-NEXT: v_ldexp_f32 v11, v11, 12
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_6
+; GFX9-NEXT: ; %bb.7: ; %Flow125
+; GFX9-NEXT: v_mov_b32_e32 v11, v13
+; GFX9-NEXT: .LBB12_8: ; %frem.loop_exit86
; GFX9-NEXT: v_add_u32_e32 v10, -11, v10
-; GFX9-NEXT: v_ldexp_f32 v10, v13, v10
-; GFX9-NEXT: v_mul_f32_e32 v11, v10, v11
+; GFX9-NEXT: v_ldexp_f32 v10, v11, v10
+; GFX9-NEXT: v_mul_f32_e32 v11, v10, v12
; GFX9-NEXT: v_rndne_f32_e32 v11, v11
; GFX9-NEXT: v_fma_f32 v10, -v11, v9, v10
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
@@ -13383,16 +14492,32 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v8, v9, v8
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v8, s2, v8, v0
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
-; GFX9-NEXT: s_cbranch_vccz .LBB12_5
-; GFX9-NEXT: .LBB12_10: ; %frem.compute46
+; GFX9-NEXT: .LBB12_9:
+; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB12_11
+; GFX9-NEXT: ; %bb.10: ; %frem.else47
+; GFX9-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB12_12
+; GFX9-NEXT: .LBB12_11:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr9
+; GFX9-NEXT: .LBB12_12: ; %Flow123
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB12_18
+; GFX9-NEXT: ; %bb.13: ; %frem.compute46
; GFX9-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; GFX9-NEXT: v_ldexp_f32 v10, v10, 1
; GFX9-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
-; GFX9-NEXT: v_div_scale_f32 v12, vcc, 1.0, v10, 1.0
+; GFX9-NEXT: v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v9, |v1|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v14, v1
-; GFX9-NEXT: v_ldexp_f32 v13, v9, 12
+; GFX9-NEXT: v_ldexp_f32 v12, v9, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v15, v5
; GFX9-NEXT: v_add_u32_e32 v9, -1, v15
; GFX9-NEXT: v_not_b32_e32 v11, v9
@@ -13401,38 +14526,37 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; GFX9-NEXT: v_fma_f32 v17, v18, v17, v17
-; GFX9-NEXT: v_mul_f32_e32 v18, v12, v17
-; GFX9-NEXT: v_fma_f32 v19, -v16, v18, v12
+; GFX9-NEXT: v_mul_f32_e32 v18, v13, v17
+; GFX9-NEXT: v_fma_f32 v19, -v16, v18, v13
; GFX9-NEXT: v_fma_f32 v18, v19, v17, v18
-; GFX9-NEXT: v_fma_f32 v12, -v16, v18, v12
+; GFX9-NEXT: v_fma_f32 v13, -v16, v18, v13
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v12, v12, v17, v18
+; GFX9-NEXT: v_div_fmas_f32 v13, v13, v17, v18
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v11
-; GFX9-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_13
-; GFX9-NEXT: ; %bb.11: ; %frem.loop_body54.preheader
+; GFX9-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_17
+; GFX9-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
; GFX9-NEXT: v_sub_u32_e32 v11, v14, v15
; GFX9-NEXT: v_add_u32_e32 v11, 12, v11
-; GFX9-NEXT: .LBB12_12: ; %frem.loop_body54
+; GFX9-NEXT: .LBB12_15: ; %frem.loop_body54
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v14, v13
-; GFX9-NEXT: v_mul_f32_e32 v13, v14, v12
-; GFX9-NEXT: v_rndne_f32_e32 v13, v13
-; GFX9-NEXT: v_fma_f32 v13, -v13, v10, v14
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
-; GFX9-NEXT: v_add_f32_e32 v15, v13, v10
-; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
+; GFX9-NEXT: v_mov_b32_e32 v14, v12
+; GFX9-NEXT: v_mul_f32_e32 v12, v14, v13
+; GFX9-NEXT: v_rndne_f32_e32 v12, v12
+; GFX9-NEXT: v_fma_f32 v12, -v12, v10, v14
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
+; GFX9-NEXT: v_add_f32_e32 v15, v12, v10
; GFX9-NEXT: v_add_u32_e32 v11, -12, v11
-; GFX9-NEXT: v_ldexp_f32 v13, v13, 12
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v11
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_12
-; GFX9-NEXT: s_branch .LBB12_14
-; GFX9-NEXT: .LBB12_13:
-; GFX9-NEXT: v_mov_b32_e32 v14, v13
-; GFX9-NEXT: .LBB12_14: ; %frem.loop_exit55
+; GFX9-NEXT: v_ldexp_f32 v12, v12, 12
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_15
+; GFX9-NEXT: ; %bb.16: ; %Flow121
+; GFX9-NEXT: v_mov_b32_e32 v12, v14
+; GFX9-NEXT: .LBB12_17: ; %frem.loop_exit55
; GFX9-NEXT: v_add_u32_e32 v11, -11, v11
-; GFX9-NEXT: v_ldexp_f32 v11, v14, v11
-; GFX9-NEXT: v_mul_f32_e32 v12, v11, v12
+; GFX9-NEXT: v_ldexp_f32 v11, v12, v11
+; GFX9-NEXT: v_mul_f32_e32 v12, v11, v13
; GFX9-NEXT: v_rndne_f32_e32 v12, v12
; GFX9-NEXT: v_fma_f32 v11, -v12, v10, v11
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
@@ -13441,16 +14565,32 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v9, v10, v9
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v9, s2, v9, v1
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
-; GFX9-NEXT: s_cbranch_vccz .LBB12_6
-; GFX9-NEXT: .LBB12_15: ; %frem.compute15
+; GFX9-NEXT: .LBB12_18:
+; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB12_20
+; GFX9-NEXT: ; %bb.19: ; %frem.else16
+; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB12_21
+; GFX9-NEXT: .LBB12_20:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr10
+; GFX9-NEXT: .LBB12_21: ; %Flow119
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB12_27
+; GFX9-NEXT: ; %bb.22: ; %frem.compute15
; GFX9-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; GFX9-NEXT: v_ldexp_f32 v11, v11, 1
; GFX9-NEXT: v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
-; GFX9-NEXT: v_div_scale_f32 v13, vcc, 1.0, v11, 1.0
+; GFX9-NEXT: v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v15, v2
-; GFX9-NEXT: v_ldexp_f32 v14, v10, 12
+; GFX9-NEXT: v_ldexp_f32 v13, v10, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v16, v6
; GFX9-NEXT: v_add_u32_e32 v10, -1, v16
; GFX9-NEXT: v_not_b32_e32 v12, v10
@@ -13459,38 +14599,37 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v19, -v17, v18, 1.0
; GFX9-NEXT: v_fma_f32 v18, v19, v18, v18
-; GFX9-NEXT: v_mul_f32_e32 v19, v13, v18
-; GFX9-NEXT: v_fma_f32 v20, -v17, v19, v13
+; GFX9-NEXT: v_mul_f32_e32 v19, v14, v18
+; GFX9-NEXT: v_fma_f32 v20, -v17, v19, v14
; GFX9-NEXT: v_fma_f32 v19, v20, v18, v19
-; GFX9-NEXT: v_fma_f32 v13, -v17, v19, v13
+; GFX9-NEXT: v_fma_f32 v14, -v17, v19, v14
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v13, v13, v18, v19
+; GFX9-NEXT: v_div_fmas_f32 v14, v14, v18, v19
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v12
-; GFX9-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_18
-; GFX9-NEXT: ; %bb.16: ; %frem.loop_body23.preheader
+; GFX9-NEXT: v_div_fixup_f32 v14, v14, v11, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_26
+; GFX9-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
; GFX9-NEXT: v_sub_u32_e32 v12, v15, v16
; GFX9-NEXT: v_add_u32_e32 v12, 12, v12
-; GFX9-NEXT: .LBB12_17: ; %frem.loop_body23
+; GFX9-NEXT: .LBB12_24: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v15, v14
-; GFX9-NEXT: v_mul_f32_e32 v14, v15, v13
-; GFX9-NEXT: v_rndne_f32_e32 v14, v14
-; GFX9-NEXT: v_fma_f32 v14, -v14, v11, v15
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
-; GFX9-NEXT: v_add_f32_e32 v16, v14, v11
-; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
+; GFX9-NEXT: v_mov_b32_e32 v15, v13
+; GFX9-NEXT: v_mul_f32_e32 v13, v15, v14
+; GFX9-NEXT: v_rndne_f32_e32 v13, v13
+; GFX9-NEXT: v_fma_f32 v13, -v13, v11, v15
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
+; GFX9-NEXT: v_add_f32_e32 v16, v13, v11
; GFX9-NEXT: v_add_u32_e32 v12, -12, v12
-; GFX9-NEXT: v_ldexp_f32 v14, v14, 12
+; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v12
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_17
-; GFX9-NEXT: s_branch .LBB12_19
-; GFX9-NEXT: .LBB12_18:
-; GFX9-NEXT: v_mov_b32_e32 v15, v14
-; GFX9-NEXT: .LBB12_19: ; %frem.loop_exit24
+; GFX9-NEXT: v_ldexp_f32 v13, v13, 12
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_24
+; GFX9-NEXT: ; %bb.25: ; %Flow117
+; GFX9-NEXT: v_mov_b32_e32 v13, v15
+; GFX9-NEXT: .LBB12_26: ; %frem.loop_exit24
; GFX9-NEXT: v_add_u32_e32 v12, -11, v12
-; GFX9-NEXT: v_ldexp_f32 v12, v15, v12
-; GFX9-NEXT: v_mul_f32_e32 v13, v12, v13
+; GFX9-NEXT: v_ldexp_f32 v12, v13, v12
+; GFX9-NEXT: v_mul_f32_e32 v13, v12, v14
; GFX9-NEXT: v_rndne_f32_e32 v13, v13
; GFX9-NEXT: v_fma_f32 v12, -v13, v11, v12
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
@@ -13499,16 +14638,32 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v10, v11, v10
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v10, s2, v10, v2
-; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
-; GFX9-NEXT: s_cbranch_vccz .LBB12_7
-; GFX9-NEXT: .LBB12_20: ; %frem.compute
+; GFX9-NEXT: .LBB12_27:
+; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB12_29
+; GFX9-NEXT: ; %bb.28: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: s_branch .LBB12_30
+; GFX9-NEXT: .LBB12_29:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr11
+; GFX9-NEXT: .LBB12_30: ; %Flow115
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB12_36
+; GFX9-NEXT: ; %bb.31: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; GFX9-NEXT: v_ldexp_f32 v12, v12, 1
; GFX9-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
-; GFX9-NEXT: v_div_scale_f32 v14, vcc, 1.0, v12, 1.0
+; GFX9-NEXT: v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v16, v3
-; GFX9-NEXT: v_ldexp_f32 v15, v11, 12
+; GFX9-NEXT: v_ldexp_f32 v14, v11, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v17, v7
; GFX9-NEXT: v_add_u32_e32 v11, -1, v17
; GFX9-NEXT: v_not_b32_e32 v13, v11
@@ -13517,38 +14672,37 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v20, -v18, v19, 1.0
; GFX9-NEXT: v_fma_f32 v19, v20, v19, v19
-; GFX9-NEXT: v_mul_f32_e32 v20, v14, v19
-; GFX9-NEXT: v_fma_f32 v21, -v18, v20, v14
+; GFX9-NEXT: v_mul_f32_e32 v20, v15, v19
+; GFX9-NEXT: v_fma_f32 v21, -v18, v20, v15
; GFX9-NEXT: v_fma_f32 v20, v21, v19, v20
-; GFX9-NEXT: v_fma_f32 v14, -v18, v20, v14
+; GFX9-NEXT: v_fma_f32 v15, -v18, v20, v15
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v14, v14, v19, v20
+; GFX9-NEXT: v_div_fmas_f32 v15, v15, v19, v20
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v13
-; GFX9-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_23
-; GFX9-NEXT: ; %bb.21: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_35
+; GFX9-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v13, v16, v17
; GFX9-NEXT: v_add_u32_e32 v13, 12, v13
-; GFX9-NEXT: .LBB12_22: ; %frem.loop_body
+; GFX9-NEXT: .LBB12_33: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v16, v15
-; GFX9-NEXT: v_mul_f32_e32 v15, v16, v14
-; GFX9-NEXT: v_rndne_f32_e32 v15, v15
-; GFX9-NEXT: v_fma_f32 v15, -v15, v12, v16
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v15
-; GFX9-NEXT: v_add_f32_e32 v17, v15, v12
-; GFX9-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
+; GFX9-NEXT: v_mov_b32_e32 v16, v14
+; GFX9-NEXT: v_mul_f32_e32 v14, v16, v15
+; GFX9-NEXT: v_rndne_f32_e32 v14, v14
+; GFX9-NEXT: v_fma_f32 v14, -v14, v12, v16
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
+; GFX9-NEXT: v_add_f32_e32 v17, v14, v12
; GFX9-NEXT: v_add_u32_e32 v13, -12, v13
-; GFX9-NEXT: v_ldexp_f32 v15, v15, 12
+; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v13
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_22
-; GFX9-NEXT: s_branch .LBB12_24
-; GFX9-NEXT: .LBB12_23:
-; GFX9-NEXT: v_mov_b32_e32 v16, v15
-; GFX9-NEXT: .LBB12_24: ; %frem.loop_exit
+; GFX9-NEXT: v_ldexp_f32 v14, v14, 12
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_33
+; GFX9-NEXT: ; %bb.34: ; %Flow
+; GFX9-NEXT: v_mov_b32_e32 v14, v16
+; GFX9-NEXT: .LBB12_35: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v13, -11, v13
-; GFX9-NEXT: v_ldexp_f32 v13, v16, v13
-; GFX9-NEXT: v_mul_f32_e32 v14, v13, v14
+; GFX9-NEXT: v_ldexp_f32 v13, v14, v13
+; GFX9-NEXT: v_mul_f32_e32 v14, v13, v15
; GFX9-NEXT: v_rndne_f32_e32 v14, v14
; GFX9-NEXT: v_fma_f32 v13, -v14, v12, v13
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
@@ -13557,7 +14711,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v11, v12, v11
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v11, s2, v11, v3
-; GFX9-NEXT: .LBB12_25:
+; GFX9-NEXT: .LBB12_36: ; %Flow116
; GFX9-NEXT: s_mov_b32 s4, 0x7f800000
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; GFX9-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -13591,9 +14745,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3]
; GFX10-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v4|
-; GFX10-NEXT: s_cbranch_vccz .LBB12_5
-; GFX10-NEXT: ; %bb.1: ; %frem.compute77
+; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v4|
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB12_2
+; GFX10-NEXT: ; %bb.1: ; %frem.else78
+; GFX10-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc_lo
+; GFX10-NEXT: s_branch .LBB12_3
+; GFX10-NEXT: .LBB12_2:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr8
+; GFX10-NEXT: .LBB12_3: ; %Flow127
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_9
+; GFX10-NEXT: ; %bb.4: ; %frem.compute77
; GFX10-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; GFX10-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v11, v0
@@ -13619,11 +14788,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v11, v11, v14, v15
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v12
; GFX10-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_9
-; GFX10-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_8
+; GFX10-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_3: ; %frem.loop_body85
+; GFX10-NEXT: .LBB12_6: ; %frem.loop_body85
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v13, v10
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -13635,38 +14804,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v12, v10, v9
; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v10, v10, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_3
-; GFX10-NEXT: ; %bb.4:
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_6
+; GFX10-NEXT: ; %bb.7: ; %Flow125
; GFX10-NEXT: v_mov_b32_e32 v12, s2
-; GFX10-NEXT: s_branch .LBB12_10
-; GFX10-NEXT: .LBB12_5: ; %frem.else78
-; GFX10-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc_lo
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v5|
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_11
-; GFX10-NEXT: .LBB12_6: ; %frem.else47
-; GFX10-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc_lo
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v2|, |v6|
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_17
-; GFX10-NEXT: .LBB12_7: ; %frem.else16
-; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
-; GFX10-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc_lo
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v3|, |v7|
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_23
-; GFX10-NEXT: .LBB12_8: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc_lo
-; GFX10-NEXT: s_branch .LBB12_29
-; GFX10-NEXT: .LBB12_9:
-; GFX10-NEXT: v_mov_b32_e32 v13, v10
-; GFX10-NEXT: .LBB12_10: ; %frem.loop_exit86
-; GFX10-NEXT: v_add_nc_u32_e32 v10, -11, v12
-; GFX10-NEXT: v_ldexp_f32 v10, v13, v10
+; GFX10-NEXT: v_mov_b32_e32 v10, v13
+; GFX10-NEXT: .LBB12_8: ; %frem.loop_exit86
+; GFX10-NEXT: v_add_nc_u32_e32 v12, -11, v12
+; GFX10-NEXT: v_ldexp_f32 v10, v10, v12
; GFX10-NEXT: v_mul_f32_e32 v11, v10, v11
; GFX10-NEXT: v_rndne_f32_e32 v11, v11
; GFX10-NEXT: v_fma_f32 v10, -v11, v9, v10
@@ -13675,9 +14819,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v8, v9, v8
; GFX10-NEXT: v_bfi_b32 v8, 0x7fffffff, v8, v0
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v5|
-; GFX10-NEXT: s_cbranch_vccz .LBB12_6
-; GFX10-NEXT: .LBB12_11: ; %frem.compute46
+; GFX10-NEXT: .LBB12_9:
+; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v5|
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB12_11
+; GFX10-NEXT: ; %bb.10: ; %frem.else47
+; GFX10-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc_lo
+; GFX10-NEXT: s_branch .LBB12_12
+; GFX10-NEXT: .LBB12_11:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr9
+; GFX10-NEXT: .LBB12_12: ; %Flow123
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_18
+; GFX10-NEXT: ; %bb.13: ; %frem.compute46
; GFX10-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; GFX10-NEXT: v_frexp_mant_f32_e64 v9, |v1|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v12, v1
@@ -13703,11 +14863,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v12, v12, v15, v16
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v13
; GFX10-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_15
-; GFX10-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_17
+; GFX10-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_13: ; %frem.loop_body54
+; GFX10-NEXT: .LBB12_15: ; %frem.loop_body54
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v14, v11
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -13719,15 +14879,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v13, v11, v10
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v11, v11, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_13
-; GFX10-NEXT: ; %bb.14:
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_15
+; GFX10-NEXT: ; %bb.16: ; %Flow121
; GFX10-NEXT: v_mov_b32_e32 v13, s2
-; GFX10-NEXT: s_branch .LBB12_16
-; GFX10-NEXT: .LBB12_15:
-; GFX10-NEXT: v_mov_b32_e32 v14, v11
-; GFX10-NEXT: .LBB12_16: ; %frem.loop_exit55
-; GFX10-NEXT: v_add_nc_u32_e32 v11, -11, v13
-; GFX10-NEXT: v_ldexp_f32 v11, v14, v11
+; GFX10-NEXT: v_mov_b32_e32 v11, v14
+; GFX10-NEXT: .LBB12_17: ; %frem.loop_exit55
+; GFX10-NEXT: v_add_nc_u32_e32 v13, -11, v13
+; GFX10-NEXT: v_ldexp_f32 v11, v11, v13
; GFX10-NEXT: v_mul_f32_e32 v12, v11, v12
; GFX10-NEXT: v_rndne_f32_e32 v12, v12
; GFX10-NEXT: v_fma_f32 v11, -v12, v10, v11
@@ -13736,9 +14894,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v9, v10, v9
; GFX10-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v2|, |v6|
-; GFX10-NEXT: s_cbranch_vccz .LBB12_7
-; GFX10-NEXT: .LBB12_17: ; %frem.compute15
+; GFX10-NEXT: .LBB12_18:
+; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v2|, |v6|
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB12_20
+; GFX10-NEXT: ; %bb.19: ; %frem.else16
+; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc_lo
+; GFX10-NEXT: s_branch .LBB12_21
+; GFX10-NEXT: .LBB12_20:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr10
+; GFX10-NEXT: .LBB12_21: ; %Flow119
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_27
+; GFX10-NEXT: ; %bb.22: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; GFX10-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v13, v2
@@ -13764,11 +14938,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v13, v13, v16, v17
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v14
; GFX10-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_21
-; GFX10-NEXT: ; %bb.18: ; %frem.loop_body23.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_26
+; GFX10-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_19: ; %frem.loop_body23
+; GFX10-NEXT: .LBB12_24: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v15, v12
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -13780,15 +14954,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v14, v12, v11
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v12, v12, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_19
-; GFX10-NEXT: ; %bb.20:
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_24
+; GFX10-NEXT: ; %bb.25: ; %Flow117
; GFX10-NEXT: v_mov_b32_e32 v14, s2
-; GFX10-NEXT: s_branch .LBB12_22
-; GFX10-NEXT: .LBB12_21:
-; GFX10-NEXT: v_mov_b32_e32 v15, v12
-; GFX10-NEXT: .LBB12_22: ; %frem.loop_exit24
-; GFX10-NEXT: v_add_nc_u32_e32 v12, -11, v14
-; GFX10-NEXT: v_ldexp_f32 v12, v15, v12
+; GFX10-NEXT: v_mov_b32_e32 v12, v15
+; GFX10-NEXT: .LBB12_26: ; %frem.loop_exit24
+; GFX10-NEXT: v_add_nc_u32_e32 v14, -11, v14
+; GFX10-NEXT: v_ldexp_f32 v12, v12, v14
; GFX10-NEXT: v_mul_f32_e32 v13, v12, v13
; GFX10-NEXT: v_rndne_f32_e32 v13, v13
; GFX10-NEXT: v_fma_f32 v12, -v13, v11, v12
@@ -13797,9 +14969,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v11, v12, v11, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v10, v11, v10
; GFX10-NEXT: v_bfi_b32 v10, 0x7fffffff, v10, v2
-; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v3|, |v7|
-; GFX10-NEXT: s_cbranch_vccz .LBB12_8
-; GFX10-NEXT: .LBB12_23: ; %frem.compute
+; GFX10-NEXT: .LBB12_27:
+; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v3|, |v7|
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB12_29
+; GFX10-NEXT: ; %bb.28: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc_lo
+; GFX10-NEXT: s_branch .LBB12_30
+; GFX10-NEXT: .LBB12_29:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr11
+; GFX10-NEXT: .LBB12_30: ; %Flow115
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_36
+; GFX10-NEXT: ; %bb.31: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; GFX10-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v14, v3
@@ -13825,11 +15013,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v14, v14, v17, v18
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v15
; GFX10-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_27
-; GFX10-NEXT: ; %bb.24: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_35
+; GFX10-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_25: ; %frem.loop_body
+; GFX10-NEXT: .LBB12_33: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v16, v13
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -13841,15 +15029,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v15, v13, v12
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v13, v13, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_25
-; GFX10-NEXT: ; %bb.26:
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_33
+; GFX10-NEXT: ; %bb.34: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v15, s2
-; GFX10-NEXT: s_branch .LBB12_28
-; GFX10-NEXT: .LBB12_27:
-; GFX10-NEXT: v_mov_b32_e32 v16, v13
-; GFX10-NEXT: .LBB12_28: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v13, -11, v15
-; GFX10-NEXT: v_ldexp_f32 v13, v16, v13
+; GFX10-NEXT: v_mov_b32_e32 v13, v16
+; GFX10-NEXT: .LBB12_35: ; %frem.loop_exit
+; GFX10-NEXT: v_add_nc_u32_e32 v15, -11, v15
+; GFX10-NEXT: v_ldexp_f32 v13, v13, v15
; GFX10-NEXT: v_mul_f32_e32 v14, v13, v14
; GFX10-NEXT: v_rndne_f32_e32 v14, v14
; GFX10-NEXT: v_fma_f32 v13, -v14, v12, v13
@@ -13858,7 +15044,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v11, v12, v11
; GFX10-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX10-NEXT: .LBB12_29:
+; GFX10-NEXT: .LBB12_36: ; %Flow116
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX10-NEXT: v_mov_b32_e32 v4, 0
@@ -13890,9 +15076,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: global_load_b128 v[0:3], v4, s[2:3]
; GFX11-NEXT: global_load_b128 v[4:7], v4, s[4:5] offset:64
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v4|
-; GFX11-NEXT: s_cbranch_vccz .LBB12_5
-; GFX11-NEXT: ; %bb.1: ; %frem.compute77
+; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v4|
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB12_2
+; GFX11-NEXT: ; %bb.1: ; %frem.else78
+; GFX11-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc_lo
+; GFX11-NEXT: s_branch .LBB12_3
+; GFX11-NEXT: .LBB12_2:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr8
+; GFX11-NEXT: .LBB12_3: ; %Flow127
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_9
+; GFX11-NEXT: ; %bb.4: ; %frem.compute77
; GFX11-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; GFX11-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v11, v0
@@ -13927,12 +15129,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_9
-; GFX11-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_8
+; GFX11-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_3: ; %frem.loop_body85
+; GFX11-NEXT: .LBB12_6: ; %frem.loop_body85
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v13, v10
@@ -13948,43 +15150,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v10, v10, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_3
-; GFX11-NEXT: ; %bb.4:
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_6
+; GFX11-NEXT: ; %bb.7: ; %Flow125
; GFX11-NEXT: v_mov_b32_e32 v12, s2
-; GFX11-NEXT: s_branch .LBB12_10
-; GFX11-NEXT: .LBB12_5: ; %frem.else78
-; GFX11-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc_lo
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v5|
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_11
-; GFX11-NEXT: .LBB12_6: ; %frem.else47
-; GFX11-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc_lo
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v2|, |v6|
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_17
-; GFX11-NEXT: .LBB12_7: ; %frem.else16
-; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc_lo
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v3|, |v7|
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_23
-; GFX11-NEXT: .LBB12_8: ; %frem.else
-; GFX11-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc_lo
-; GFX11-NEXT: s_branch .LBB12_29
-; GFX11-NEXT: .LBB12_9:
-; GFX11-NEXT: v_mov_b32_e32 v13, v10
-; GFX11-NEXT: .LBB12_10: ; %frem.loop_exit86
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v10, -11, v12
-; GFX11-NEXT: v_ldexp_f32 v10, v13, v10
+; GFX11-NEXT: v_mov_b32_e32 v10, v13
+; GFX11-NEXT: .LBB12_8: ; %frem.loop_exit86
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v12, -11, v12
+; GFX11-NEXT: v_ldexp_f32 v10, v10, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v11, v10, v11
; GFX11-NEXT: v_rndne_f32_e32 v11, v11
@@ -13997,9 +15170,26 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v8, v9, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v8, 0x7fffffff, v8, v0
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v5|
-; GFX11-NEXT: s_cbranch_vccz .LBB12_6
-; GFX11-NEXT: .LBB12_11: ; %frem.compute46
+; GFX11-NEXT: .LBB12_9:
+; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v5|
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB12_11
+; GFX11-NEXT: ; %bb.10: ; %frem.else47
+; GFX11-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc_lo
+; GFX11-NEXT: s_branch .LBB12_12
+; GFX11-NEXT: .LBB12_11:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr9
+; GFX11-NEXT: .LBB12_12: ; %Flow123
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_18
+; GFX11-NEXT: ; %bb.13: ; %frem.compute46
; GFX11-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; GFX11-NEXT: v_frexp_mant_f32_e64 v9, |v1|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v12, v1
@@ -14034,12 +15224,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_15
-; GFX11-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_17
+; GFX11-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_13: ; %frem.loop_body54
+; GFX11-NEXT: .LBB12_15: ; %frem.loop_body54
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v14, v11
@@ -14055,16 +15245,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v11, v11, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_13
-; GFX11-NEXT: ; %bb.14:
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_15
+; GFX11-NEXT: ; %bb.16: ; %Flow121
; GFX11-NEXT: v_mov_b32_e32 v13, s2
-; GFX11-NEXT: s_branch .LBB12_16
-; GFX11-NEXT: .LBB12_15:
-; GFX11-NEXT: v_mov_b32_e32 v14, v11
-; GFX11-NEXT: .LBB12_16: ; %frem.loop_exit55
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v11, -11, v13
-; GFX11-NEXT: v_ldexp_f32 v11, v14, v11
+; GFX11-NEXT: v_mov_b32_e32 v11, v14
+; GFX11-NEXT: .LBB12_17: ; %frem.loop_exit55
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v13, -11, v13
+; GFX11-NEXT: v_ldexp_f32 v11, v11, v13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v12, v11, v12
; GFX11-NEXT: v_rndne_f32_e32 v12, v12
@@ -14077,9 +15265,26 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v9, v10, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v2|, |v6|
-; GFX11-NEXT: s_cbranch_vccz .LBB12_7
-; GFX11-NEXT: .LBB12_17: ; %frem.compute15
+; GFX11-NEXT: .LBB12_18:
+; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v2|, |v6|
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB12_20
+; GFX11-NEXT: ; %bb.19: ; %frem.else16
+; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc_lo
+; GFX11-NEXT: s_branch .LBB12_21
+; GFX11-NEXT: .LBB12_20:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr10
+; GFX11-NEXT: .LBB12_21: ; %Flow119
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_27
+; GFX11-NEXT: ; %bb.22: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; GFX11-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v13, v2
@@ -14114,12 +15319,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_21
-; GFX11-NEXT: ; %bb.18: ; %frem.loop_body23.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_26
+; GFX11-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_19: ; %frem.loop_body23
+; GFX11-NEXT: .LBB12_24: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v15, v12
@@ -14135,16 +15340,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v12, v12, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_19
-; GFX11-NEXT: ; %bb.20:
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_24
+; GFX11-NEXT: ; %bb.25: ; %Flow117
; GFX11-NEXT: v_mov_b32_e32 v14, s2
-; GFX11-NEXT: s_branch .LBB12_22
-; GFX11-NEXT: .LBB12_21:
-; GFX11-NEXT: v_mov_b32_e32 v15, v12
-; GFX11-NEXT: .LBB12_22: ; %frem.loop_exit24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v12, -11, v14
-; GFX11-NEXT: v_ldexp_f32 v12, v15, v12
+; GFX11-NEXT: v_mov_b32_e32 v12, v15
+; GFX11-NEXT: .LBB12_26: ; %frem.loop_exit24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v14, -11, v14
+; GFX11-NEXT: v_ldexp_f32 v12, v12, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v13, v12, v13
; GFX11-NEXT: v_rndne_f32_e32 v13, v13
@@ -14157,9 +15360,26 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v10, v11, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v10, 0x7fffffff, v10, v2
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v3|, |v7|
-; GFX11-NEXT: s_cbranch_vccz .LBB12_8
-; GFX11-NEXT: .LBB12_23: ; %frem.compute
+; GFX11-NEXT: .LBB12_27:
+; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v3|, |v7|
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB12_29
+; GFX11-NEXT: ; %bb.28: ; %frem.else
+; GFX11-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc_lo
+; GFX11-NEXT: s_branch .LBB12_30
+; GFX11-NEXT: .LBB12_29:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr11
+; GFX11-NEXT: .LBB12_30: ; %Flow115
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_36
+; GFX11-NEXT: ; %bb.31: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; GFX11-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v14, v3
@@ -14194,12 +15414,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v15
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_27
-; GFX11-NEXT: ; %bb.24: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_35
+; GFX11-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_25: ; %frem.loop_body
+; GFX11-NEXT: .LBB12_33: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v16, v13
@@ -14215,16 +15435,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v13, v13, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_25
-; GFX11-NEXT: ; %bb.26:
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_33
+; GFX11-NEXT: ; %bb.34: ; %Flow
; GFX11-NEXT: v_mov_b32_e32 v15, s2
-; GFX11-NEXT: s_branch .LBB12_28
-; GFX11-NEXT: .LBB12_27:
-; GFX11-NEXT: v_mov_b32_e32 v16, v13
-; GFX11-NEXT: .LBB12_28: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v13, -11, v15
-; GFX11-NEXT: v_ldexp_f32 v13, v16, v13
+; GFX11-NEXT: v_mov_b32_e32 v13, v16
+; GFX11-NEXT: .LBB12_35: ; %frem.loop_exit
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v15, -11, v15
+; GFX11-NEXT: v_ldexp_f32 v13, v13, v15
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v14, v13, v14
; GFX11-NEXT: v_rndne_f32_e32 v14, v14
@@ -14237,7 +15455,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v11, v12, v11
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX11-NEXT: .LBB12_29:
+; GFX11-NEXT: .LBB12_36: ; %Flow116
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX11-NEXT: v_mov_b32_e32 v4, 0
@@ -14280,9 +15498,27 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_readfirstlane_b32 s2, v4
; GFX1150-NEXT: s_and_b32 s11, s6, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_gt_f32 s5, s11
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_5
-; GFX1150-NEXT: ; %bb.1: ; %frem.compute77
+; GFX1150-NEXT: s_cmp_ngt_f32 s5, s11
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_2
+; GFX1150-NEXT: ; %bb.1: ; %frem.else78
+; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s8
+; GFX1150-NEXT: s_cmp_eq_f32 s5, s11
+; GFX1150-NEXT: v_mov_b32_e32 v0, s12
+; GFX1150-NEXT: s_mov_b32 s11, 0
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB12_3
+; GFX1150-NEXT: .LBB12_2:
+; GFX1150-NEXT: s_mov_b32 s11, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr0
+; GFX1150-NEXT: .LBB12_3: ; %Flow127
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_9
+; GFX1150-NEXT: ; %bb.4: ; %frem.compute77
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s6|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v0, |s8|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
@@ -14316,12 +15552,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1150-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_6
-; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_8
+; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_3: ; %frem.loop_body85
+; GFX1150-NEXT: .LBB12_6: ; %frem.loop_body85
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v5, v2
@@ -14339,24 +15575,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v2, v2, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_3
-; GFX1150-NEXT: ; %bb.4:
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_6
+; GFX1150-NEXT: ; %bb.7: ; %Flow125
; GFX1150-NEXT: v_mov_b32_e32 v4, s11
-; GFX1150-NEXT: s_branch .LBB12_7
-; GFX1150-NEXT: .LBB12_5: ; %frem.else78
-; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s8
-; GFX1150-NEXT: s_cmp_eq_f32 s5, s11
-; GFX1150-NEXT: v_mov_b32_e32 v0, s12
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB12_8
-; GFX1150-NEXT: .LBB12_6:
-; GFX1150-NEXT: v_mov_b32_e32 v5, v2
-; GFX1150-NEXT: .LBB12_7: ; %frem.loop_exit86
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v2, -11, v4
-; GFX1150-NEXT: v_ldexp_f32 v2, v5, v2
+; GFX1150-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-NEXT: .LBB12_8: ; %frem.loop_exit86
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v4, -11, v4
+; GFX1150-NEXT: v_ldexp_f32 v2, v2, v4
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-NEXT: v_rndne_f32_e32 v3, v3
@@ -14370,13 +15596,31 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1150-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s8
-; GFX1150-NEXT: .LBB12_8:
+; GFX1150-NEXT: .LBB12_9:
; GFX1150-NEXT: s_and_b32 s8, s10, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s11, s4, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_gt_f32 s8, s11
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_13
-; GFX1150-NEXT: ; %bb.9: ; %frem.compute46
+; GFX1150-NEXT: s_cmp_ngt_f32 s8, s11
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_11
+; GFX1150-NEXT: ; %bb.10: ; %frem.else47
+; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s10
+; GFX1150-NEXT: s_cmp_eq_f32 s8, s11
+; GFX1150-NEXT: v_mov_b32_e32 v1, s12
+; GFX1150-NEXT: s_mov_b32 s11, 0
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v1, s10, v1, vcc_lo
+; GFX1150-NEXT: s_branch .LBB12_12
+; GFX1150-NEXT: .LBB12_11:
+; GFX1150-NEXT: s_mov_b32 s11, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr1
+; GFX1150-NEXT: .LBB12_12: ; %Flow123
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_18
+; GFX1150-NEXT: ; %bb.13: ; %frem.compute46
; GFX1150-NEXT: v_frexp_mant_f32_e64 v2, |s4|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s10|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
@@ -14410,12 +15654,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1150-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_14
-; GFX1150-NEXT: ; %bb.10: ; %frem.loop_body54.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_17
+; GFX1150-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_11: ; %frem.loop_body54
+; GFX1150-NEXT: .LBB12_15: ; %frem.loop_body54
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v6, v3
@@ -14433,24 +15677,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_11
-; GFX1150-NEXT: ; %bb.12:
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_15
+; GFX1150-NEXT: ; %bb.16: ; %Flow121
; GFX1150-NEXT: v_mov_b32_e32 v5, s11
-; GFX1150-NEXT: s_branch .LBB12_15
-; GFX1150-NEXT: .LBB12_13: ; %frem.else47
-; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s10
-; GFX1150-NEXT: s_cmp_eq_f32 s8, s11
-; GFX1150-NEXT: v_mov_b32_e32 v1, s12
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v1, s10, v1, vcc_lo
-; GFX1150-NEXT: s_branch .LBB12_16
-; GFX1150-NEXT: .LBB12_14:
-; GFX1150-NEXT: v_mov_b32_e32 v6, v3
-; GFX1150-NEXT: .LBB12_15: ; %frem.loop_exit55
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v3, -11, v5
-; GFX1150-NEXT: v_ldexp_f32 v3, v6, v3
+; GFX1150-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-NEXT: .LBB12_17: ; %frem.loop_exit55
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v5, -11, v5
+; GFX1150-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-NEXT: v_rndne_f32_e32 v4, v4
@@ -14464,13 +15698,31 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1150-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s10
-; GFX1150-NEXT: .LBB12_16:
+; GFX1150-NEXT: .LBB12_18:
; GFX1150-NEXT: s_and_b32 s10, s9, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s11, s3, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_gt_f32 s10, s11
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_21
-; GFX1150-NEXT: ; %bb.17: ; %frem.compute15
+; GFX1150-NEXT: s_cmp_ngt_f32 s10, s11
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_20
+; GFX1150-NEXT: ; %bb.19: ; %frem.else16
+; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s9
+; GFX1150-NEXT: s_cmp_eq_f32 s10, s11
+; GFX1150-NEXT: v_mov_b32_e32 v2, s12
+; GFX1150-NEXT: s_mov_b32 s11, 0
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v2, s9, v2, vcc_lo
+; GFX1150-NEXT: s_branch .LBB12_21
+; GFX1150-NEXT: .LBB12_20:
+; GFX1150-NEXT: s_mov_b32 s11, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr2
+; GFX1150-NEXT: .LBB12_21: ; %Flow119
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_27
+; GFX1150-NEXT: ; %bb.22: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f32_e64 v3, |s3|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v2, |s9|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
@@ -14504,12 +15756,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX1150-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_22
-; GFX1150-NEXT: ; %bb.18: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_26
+; GFX1150-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_19: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB12_24: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v7, v4
@@ -14527,24 +15779,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_19
-; GFX1150-NEXT: ; %bb.20:
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_24
+; GFX1150-NEXT: ; %bb.25: ; %Flow117
; GFX1150-NEXT: v_mov_b32_e32 v6, s11
-; GFX1150-NEXT: s_branch .LBB12_23
-; GFX1150-NEXT: .LBB12_21: ; %frem.else16
-; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s9
-; GFX1150-NEXT: s_cmp_eq_f32 s10, s11
-; GFX1150-NEXT: v_mov_b32_e32 v2, s12
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v2, s9, v2, vcc_lo
-; GFX1150-NEXT: s_branch .LBB12_24
-; GFX1150-NEXT: .LBB12_22:
-; GFX1150-NEXT: v_mov_b32_e32 v7, v4
-; GFX1150-NEXT: .LBB12_23: ; %frem.loop_exit24
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v4, -11, v6
-; GFX1150-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX1150-NEXT: v_mov_b32_e32 v4, v7
+; GFX1150-NEXT: .LBB12_26: ; %frem.loop_exit24
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v6, -11, v6
+; GFX1150-NEXT: v_ldexp_f32 v4, v4, v6
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-NEXT: v_rndne_f32_e32 v5, v5
@@ -14558,13 +15800,31 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v2, v3, v2
; GFX1150-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s9
-; GFX1150-NEXT: .LBB12_24:
+; GFX1150-NEXT: .LBB12_27:
; GFX1150-NEXT: s_and_b32 s9, s7, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s11, s2, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_gt_f32 s9, s11
+; GFX1150-NEXT: s_cmp_ngt_f32 s9, s11
; GFX1150-NEXT: s_cbranch_scc0 .LBB12_29
-; GFX1150-NEXT: ; %bb.25: ; %frem.compute
+; GFX1150-NEXT: ; %bb.28: ; %frem.else
+; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s7
+; GFX1150-NEXT: s_cmp_eq_f32 s9, s11
+; GFX1150-NEXT: v_mov_b32_e32 v3, s12
+; GFX1150-NEXT: s_mov_b32 s11, 0
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v3, s7, v3, vcc_lo
+; GFX1150-NEXT: s_branch .LBB12_30
+; GFX1150-NEXT: .LBB12_29:
+; GFX1150-NEXT: s_mov_b32 s11, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr3
+; GFX1150-NEXT: .LBB12_30: ; %Flow115
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_36
+; GFX1150-NEXT: ; %bb.31: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f32_e64 v4, |s2|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v3, |s7|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v6, s7
@@ -14598,12 +15858,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1150-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_30
-; GFX1150-NEXT: ; %bb.26: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_35
+; GFX1150-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_27: ; %frem.loop_body
+; GFX1150-NEXT: .LBB12_33: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v8, v5
@@ -14621,24 +15881,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_27
-; GFX1150-NEXT: ; %bb.28:
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_33
+; GFX1150-NEXT: ; %bb.34: ; %Flow
; GFX1150-NEXT: v_mov_b32_e32 v7, s11
-; GFX1150-NEXT: s_branch .LBB12_31
-; GFX1150-NEXT: .LBB12_29: ; %frem.else
-; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s7
-; GFX1150-NEXT: s_cmp_eq_f32 s9, s11
-; GFX1150-NEXT: v_mov_b32_e32 v3, s12
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v3, s7, v3, vcc_lo
-; GFX1150-NEXT: s_branch .LBB12_32
-; GFX1150-NEXT: .LBB12_30:
-; GFX1150-NEXT: v_mov_b32_e32 v8, v5
-; GFX1150-NEXT: .LBB12_31: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v5, -11, v7
-; GFX1150-NEXT: v_ldexp_f32 v5, v8, v5
+; GFX1150-NEXT: v_mov_b32_e32 v5, v8
+; GFX1150-NEXT: .LBB12_35: ; %frem.loop_exit
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v7, -11, v7
+; GFX1150-NEXT: v_ldexp_f32 v5, v5, v7
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1150-NEXT: v_rndne_f32_e32 v6, v6
@@ -14652,7 +15902,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v4, v3
; GFX1150-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, s7
-; GFX1150-NEXT: .LBB12_32:
+; GFX1150-NEXT: .LBB12_36: ; %Flow116
; GFX1150-NEXT: s_cmp_lg_f32 s6, 0
; GFX1150-NEXT: v_mov_b32_e32 v4, 0
; GFX1150-NEXT: s_cselect_b32 s6, -1, 0
@@ -14707,9 +15957,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_readfirstlane_b32 s2, v4
; GFX1200-NEXT: s_and_b32 s11, s6, 0x7fffffff
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_cmp_gt_f32 s5, s11
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_5
-; GFX1200-NEXT: ; %bb.1: ; %frem.compute77
+; GFX1200-NEXT: s_cmp_ngt_f32 s5, s11
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_2
+; GFX1200-NEXT: ; %bb.1: ; %frem.else78
+; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s8
+; GFX1200-NEXT: s_cmp_eq_f32 s5, s11
+; GFX1200-NEXT: s_cselect_b32 s11, s12, s8
+; GFX1200-NEXT: s_mov_b32 s12, 0
+; GFX1200-NEXT: s_branch .LBB12_3
+; GFX1200-NEXT: .LBB12_2:
+; GFX1200-NEXT: s_mov_b32 s12, -1
+; GFX1200-NEXT: ; implicit-def: $sgpr11
+; GFX1200-NEXT: .LBB12_3: ; %Flow127
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s12, 1, 0
+; GFX1200-NEXT: s_cmp_lg_u32 s12, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_9
+; GFX1200-NEXT: ; %bb.4: ; %frem.compute77
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s6|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v0, |s8|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
@@ -14743,12 +16008,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1200-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_6
-; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_8
+; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_3: ; %frem.loop_body85
+; GFX1200-NEXT: .LBB12_6: ; %frem.loop_body85
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v2
@@ -14767,23 +16032,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v2, v2, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_3
-; GFX1200-NEXT: ; %bb.4:
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_6
+; GFX1200-NEXT: ; %bb.7: ; %Flow125
; GFX1200-NEXT: v_mov_b32_e32 v4, s11
-; GFX1200-NEXT: s_branch .LBB12_7
-; GFX1200-NEXT: .LBB12_5: ; %frem.else78
-; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s8
-; GFX1200-NEXT: s_cmp_eq_f32 s5, s11
-; GFX1200-NEXT: s_cselect_b32 s8, s12, s8
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: v_mov_b32_e32 v0, s8
-; GFX1200-NEXT: s_branch .LBB12_8
-; GFX1200-NEXT: .LBB12_6:
-; GFX1200-NEXT: v_mov_b32_e32 v5, v2
-; GFX1200-NEXT: .LBB12_7: ; %frem.loop_exit86
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v2, -11, v4
-; GFX1200-NEXT: v_ldexp_f32 v2, v5, v2
+; GFX1200-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-NEXT: .LBB12_8: ; %frem.loop_exit86
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v4, -11, v4
+; GFX1200-NEXT: v_ldexp_f32 v2, v2, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-NEXT: v_rndne_f32_e32 v3, v3
@@ -14798,13 +16054,31 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1200-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s8
-; GFX1200-NEXT: .LBB12_8:
+; GFX1200-NEXT: s_branch .LBB12_10
+; GFX1200-NEXT: .LBB12_9:
+; GFX1200-NEXT: v_mov_b32_e32 v0, s11
+; GFX1200-NEXT: .LBB12_10:
; GFX1200-NEXT: s_and_b32 s8, s10, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s11, s4, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cmp_gt_f32 s8, s11
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_13
-; GFX1200-NEXT: ; %bb.9: ; %frem.compute46
+; GFX1200-NEXT: s_cmp_ngt_f32 s8, s11
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_12
+; GFX1200-NEXT: ; %bb.11: ; %frem.else47
+; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s10
+; GFX1200-NEXT: s_cmp_eq_f32 s8, s11
+; GFX1200-NEXT: s_cselect_b32 s11, s12, s10
+; GFX1200-NEXT: s_mov_b32 s12, 0
+; GFX1200-NEXT: s_branch .LBB12_13
+; GFX1200-NEXT: .LBB12_12:
+; GFX1200-NEXT: s_mov_b32 s12, -1
+; GFX1200-NEXT: ; implicit-def: $sgpr11
+; GFX1200-NEXT: .LBB12_13: ; %Flow123
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s12, 1, 0
+; GFX1200-NEXT: s_cmp_lg_u32 s12, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_19
+; GFX1200-NEXT: ; %bb.14: ; %frem.compute46
; GFX1200-NEXT: v_frexp_mant_f32_e64 v2, |s4|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s10|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
@@ -14839,12 +16113,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1200-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_14
-; GFX1200-NEXT: ; %bb.10: ; %frem.loop_body54.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_18
+; GFX1200-NEXT: ; %bb.15: ; %frem.loop_body54.preheader
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_11: ; %frem.loop_body54
+; GFX1200-NEXT: .LBB12_16: ; %frem.loop_body54
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v6, v3
@@ -14864,23 +16139,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_11
-; GFX1200-NEXT: ; %bb.12:
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_16
+; GFX1200-NEXT: ; %bb.17: ; %Flow121
; GFX1200-NEXT: v_mov_b32_e32 v5, s11
-; GFX1200-NEXT: s_branch .LBB12_15
-; GFX1200-NEXT: .LBB12_13: ; %frem.else47
-; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s10
-; GFX1200-NEXT: s_cmp_eq_f32 s8, s11
-; GFX1200-NEXT: s_cselect_b32 s10, s12, s10
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v1, s10
-; GFX1200-NEXT: s_branch .LBB12_16
-; GFX1200-NEXT: .LBB12_14:
-; GFX1200-NEXT: v_mov_b32_e32 v6, v3
-; GFX1200-NEXT: .LBB12_15: ; %frem.loop_exit55
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v3, -11, v5
-; GFX1200-NEXT: v_ldexp_f32 v3, v6, v3
+; GFX1200-NEXT: v_mov_b32_e32 v3, v6
+; GFX1200-NEXT: .LBB12_18: ; %frem.loop_exit55
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v5, -11, v5
+; GFX1200-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-NEXT: v_rndne_f32_e32 v4, v4
@@ -14895,13 +16161,32 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1200-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s10
-; GFX1200-NEXT: .LBB12_16:
+; GFX1200-NEXT: s_branch .LBB12_20
+; GFX1200-NEXT: .LBB12_19:
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v1, s11
+; GFX1200-NEXT: .LBB12_20:
; GFX1200-NEXT: s_and_b32 s10, s9, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s11, s3, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cmp_gt_f32 s10, s11
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_21
-; GFX1200-NEXT: ; %bb.17: ; %frem.compute15
+; GFX1200-NEXT: s_cmp_ngt_f32 s10, s11
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_22
+; GFX1200-NEXT: ; %bb.21: ; %frem.else16
+; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s9
+; GFX1200-NEXT: s_cmp_eq_f32 s10, s11
+; GFX1200-NEXT: s_cselect_b32 s11, s12, s9
+; GFX1200-NEXT: s_mov_b32 s12, 0
+; GFX1200-NEXT: s_branch .LBB12_23
+; GFX1200-NEXT: .LBB12_22:
+; GFX1200-NEXT: s_mov_b32 s12, -1
+; GFX1200-NEXT: ; implicit-def: $sgpr11
+; GFX1200-NEXT: .LBB12_23: ; %Flow119
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s12, 1, 0
+; GFX1200-NEXT: s_cmp_lg_u32 s12, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_29
+; GFX1200-NEXT: ; %bb.24: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f32_e64 v3, |s3|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v2, |s9|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
@@ -14936,12 +16221,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX1200-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_22
-; GFX1200-NEXT: ; %bb.18: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_28
+; GFX1200-NEXT: ; %bb.25: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_19: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB12_26: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v7, v4
@@ -14961,23 +16247,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_19
-; GFX1200-NEXT: ; %bb.20:
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_26
+; GFX1200-NEXT: ; %bb.27: ; %Flow117
; GFX1200-NEXT: v_mov_b32_e32 v6, s11
-; GFX1200-NEXT: s_branch .LBB12_23
-; GFX1200-NEXT: .LBB12_21: ; %frem.else16
-; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s9
-; GFX1200-NEXT: s_cmp_eq_f32 s10, s11
-; GFX1200-NEXT: s_cselect_b32 s9, s12, s9
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v2, s9
-; GFX1200-NEXT: s_branch .LBB12_24
-; GFX1200-NEXT: .LBB12_22:
-; GFX1200-NEXT: v_mov_b32_e32 v7, v4
-; GFX1200-NEXT: .LBB12_23: ; %frem.loop_exit24
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v4, -11, v6
-; GFX1200-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX1200-NEXT: v_mov_b32_e32 v4, v7
+; GFX1200-NEXT: .LBB12_28: ; %frem.loop_exit24
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v6, -11, v6
+; GFX1200-NEXT: v_ldexp_f32 v4, v4, v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-NEXT: v_rndne_f32_e32 v5, v5
@@ -14992,13 +16269,32 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v2, v3, v2
; GFX1200-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s9
-; GFX1200-NEXT: .LBB12_24:
+; GFX1200-NEXT: s_branch .LBB12_30
+; GFX1200-NEXT: .LBB12_29:
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v2, s11
+; GFX1200-NEXT: .LBB12_30:
; GFX1200-NEXT: s_and_b32 s9, s7, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s11, s2, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cmp_gt_f32 s9, s11
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_29
-; GFX1200-NEXT: ; %bb.25: ; %frem.compute
+; GFX1200-NEXT: s_cmp_ngt_f32 s9, s11
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_32
+; GFX1200-NEXT: ; %bb.31: ; %frem.else
+; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s7
+; GFX1200-NEXT: s_cmp_eq_f32 s9, s11
+; GFX1200-NEXT: s_cselect_b32 s11, s12, s7
+; GFX1200-NEXT: s_mov_b32 s12, 0
+; GFX1200-NEXT: s_branch .LBB12_33
+; GFX1200-NEXT: .LBB12_32:
+; GFX1200-NEXT: s_mov_b32 s12, -1
+; GFX1200-NEXT: ; implicit-def: $sgpr11
+; GFX1200-NEXT: .LBB12_33: ; %Flow115
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s12, 1, 0
+; GFX1200-NEXT: s_cmp_lg_u32 s12, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_39
+; GFX1200-NEXT: ; %bb.34: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f32_e64 v4, |s2|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v3, |s7|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, s7
@@ -15033,12 +16329,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1200-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_30
-; GFX1200-NEXT: ; %bb.26: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_38
+; GFX1200-NEXT: ; %bb.35: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_27: ; %frem.loop_body
+; GFX1200-NEXT: .LBB12_36: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v8, v5
@@ -15058,23 +16355,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_27
-; GFX1200-NEXT: ; %bb.28:
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_36
+; GFX1200-NEXT: ; %bb.37: ; %Flow
; GFX1200-NEXT: v_mov_b32_e32 v7, s11
-; GFX1200-NEXT: s_branch .LBB12_31
-; GFX1200-NEXT: .LBB12_29: ; %frem.else
-; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s7
-; GFX1200-NEXT: s_cmp_eq_f32 s9, s11
-; GFX1200-NEXT: s_cselect_b32 s7, s12, s7
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v3, s7
-; GFX1200-NEXT: s_branch .LBB12_32
-; GFX1200-NEXT: .LBB12_30:
-; GFX1200-NEXT: v_mov_b32_e32 v8, v5
-; GFX1200-NEXT: .LBB12_31: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v5, -11, v7
-; GFX1200-NEXT: v_ldexp_f32 v5, v8, v5
+; GFX1200-NEXT: v_mov_b32_e32 v5, v8
+; GFX1200-NEXT: .LBB12_38: ; %frem.loop_exit
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v7, -11, v7
+; GFX1200-NEXT: v_ldexp_f32 v5, v5, v7
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1200-NEXT: v_rndne_f32_e32 v6, v6
@@ -15089,7 +16377,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v3, v4, v3
; GFX1200-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, s7
-; GFX1200-NEXT: .LBB12_32:
+; GFX1200-NEXT: s_branch .LBB12_40
+; GFX1200-NEXT: .LBB12_39:
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v3, s11
+; GFX1200-NEXT: .LBB12_40: ; %Flow116
; GFX1200-NEXT: s_cmp_lg_f32 s6, 0
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_cselect_b32 s6, -1, 0
@@ -15158,11 +16450,30 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_readfirstlane_b32 s10, v2
; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_mov_b32_e32 v1, s11
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[6:7]|, |v[0:1]|
+; SI-NEXT: v_cmp_ngt_f64_e64 s[0:1], |s[6:7]|, |v[0:1]|
; SI-NEXT: v_readfirstlane_b32 s4, v4
; SI-NEXT: v_readfirstlane_b32 s5, v5
-; SI-NEXT: s_cbranch_vccz .LBB13_4
-; SI-NEXT: ; %bb.1: ; %frem.compute15
+; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
+; SI-NEXT: s_cbranch_vccz .LBB13_2
+; SI-NEXT: ; %bb.1: ; %frem.else16
+; SI-NEXT: v_mov_b32_e32 v0, s10
+; SI-NEXT: v_mov_b32_e32 v1, s11
+; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[6:7]|, |v[0:1]|
+; SI-NEXT: s_and_b32 s12, s7, 0x80000000
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s1, s12, s7
+; SI-NEXT: s_cselect_b32 s0, 0, s6
+; SI-NEXT: s_mov_b64 s[12:13], 0
+; SI-NEXT: s_branch .LBB13_3
+; SI-NEXT: .LBB13_2:
+; SI-NEXT: s_mov_b64 s[12:13], -1
+; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
+; SI-NEXT: .LBB13_3: ; %Flow53
+; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
+; SI-NEXT: s_cselect_b32 s12, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s12, 1
+; SI-NEXT: s_cbranch_scc1 .LBB13_9
+; SI-NEXT: ; %bb.4: ; %frem.compute15
; SI-NEXT: s_and_b32 s0, s7, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[6:7]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -15174,7 +16485,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[6:7]
; SI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: s_cselect_b32 s15, s0, 0
+; SI-NEXT: s_cselect_b32 s13, s0, 0
; SI-NEXT: s_and_b32 s0, s11, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[10:11]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -15186,12 +16497,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[10:11]
; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1
; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: s_cselect_b32 s16, s0, 0
-; SI-NEXT: s_add_i32 s13, s16, -1
-; SI-NEXT: s_not_b32 s0, s13
-; SI-NEXT: s_add_i32 s14, s0, s15
+; SI-NEXT: s_cselect_b32 s17, s0, 0
+; SI-NEXT: s_add_i32 s14, s17, -1
+; SI-NEXT: s_not_b32 s0, s14
+; SI-NEXT: s_add_i32 s16, s0, s13
; SI-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], 1.0
-; SI-NEXT: s_brev_b32 s12, -2
+; SI-NEXT: s_brev_b32 s15, -2
+; SI-NEXT: s_mov_b32 s12, -1
; SI-NEXT: v_rcp_f64_e32 v[6:7], v[2:3]
; SI-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
; SI-NEXT: v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
@@ -15205,62 +16517,50 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], v[8:9]
; SI-NEXT: s_xor_b64 vcc, s[0:1], vcc
; SI-NEXT: v_div_fmas_f64 v[2:3], v[12:13], v[6:7], v[10:11]
-; SI-NEXT: s_cmp_lt_i32 s14, 27
+; SI-NEXT: s_cmp_lt_i32 s16, 27
; SI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
-; SI-NEXT: s_cbranch_scc1 .LBB13_5
-; SI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
-; SI-NEXT: s_sub_i32 s0, s15, s16
-; SI-NEXT: s_add_i32 s14, s0, 26
-; SI-NEXT: s_mov_b32 s0, -1
-; SI-NEXT: s_mov_b32 s1, 0x432fffff
+; SI-NEXT: s_cbranch_scc1 .LBB13_8
+; SI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; SI-NEXT: s_sub_i32 s0, s13, s17
+; SI-NEXT: s_add_i32 s16, s0, 26
+; SI-NEXT: s_mov_b32 s13, 0x432fffff
; SI-NEXT: v_mov_b32_e32 v10, 0x43300000
-; SI-NEXT: v_mov_b32_e32 v8, 0
-; SI-NEXT: .LBB13_3: ; %frem.loop_body23
+; SI-NEXT: v_mov_b32_e32 v6, 0
+; SI-NEXT: .LBB13_6: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v7, v5
-; SI-NEXT: v_mov_b32_e32 v6, v4
-; SI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3]
-; SI-NEXT: s_sub_i32 s14, s14, 26
-; SI-NEXT: v_bfi_b32 v9, s12, v10, v5
-; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[8:9]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[0:1]
-; SI-NEXT: v_add_f64 v[11:12], v[11:12], -v[8:9]
-; SI-NEXT: s_cmp_gt_i32 s14, 26
+; SI-NEXT: v_mov_b32_e32 v9, v5
+; SI-NEXT: v_mov_b32_e32 v8, v4
+; SI-NEXT: v_mul_f64 v[4:5], v[8:9], v[2:3]
+; SI-NEXT: s_sub_i32 s16, s16, 26
+; SI-NEXT: v_bfi_b32 v7, s15, v10, v5
+; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[6:7]
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[12:13]
+; SI-NEXT: v_add_f64 v[11:12], v[11:12], -v[6:7]
+; SI-NEXT: s_cmp_gt_i32 s16, 26
; SI-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v11, v4, vcc
-; SI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
+; SI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[0:1]
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc
; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; SI-NEXT: s_cbranch_scc1 .LBB13_3
-; SI-NEXT: s_branch .LBB13_6
-; SI-NEXT: .LBB13_4: ; %frem.else16
-; SI-NEXT: v_mov_b32_e32 v0, s10
-; SI-NEXT: v_mov_b32_e32 v1, s11
-; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[6:7]|, |v[0:1]|
-; SI-NEXT: s_and_b32 s12, s7, 0x80000000
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s1, s12, s7
-; SI-NEXT: s_cselect_b32 s0, 0, s6
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: s_branch .LBB13_7
-; SI-NEXT: .LBB13_5:
-; SI-NEXT: v_mov_b32_e32 v7, v5
-; SI-NEXT: v_mov_b32_e32 v6, v4
-; SI-NEXT: .LBB13_6: ; %frem.loop_exit24
-; SI-NEXT: s_sub_i32 s0, s14, 25
-; SI-NEXT: v_ldexp_f64 v[4:5], v[6:7], s0
-; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
-; SI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
+; SI-NEXT: s_cbranch_scc1 .LBB13_6
+; SI-NEXT: ; %bb.7: ; %Flow51
+; SI-NEXT: v_mov_b32_e32 v4, v8
+; SI-NEXT: v_mov_b32_e32 v5, v9
+; SI-NEXT: .LBB13_8: ; %frem.loop_exit24
+; SI-NEXT: s_sub_i32 s0, s16, 25
+; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], s0
; SI-NEXT: s_mov_b32 s0, -1
-; SI-NEXT: v_bfi_b32 v7, s12, v6, v3
-; SI-NEXT: v_mov_b32_e32 v6, 0
-; SI-NEXT: v_add_f64 v[8:9], v[2:3], v[6:7]
+; SI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
; SI-NEXT: s_mov_b32 s1, 0x432fffff
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[0:1]
+; SI-NEXT: s_brev_b32 s0, -2
+; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
+; SI-NEXT: v_bfi_b32 v7, s0, v6, v3
+; SI-NEXT: v_mov_b32_e32 v6, 0
+; SI-NEXT: v_add_f64 v[8:9], v[2:3], v[6:7]
; SI-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
; SI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
@@ -15269,15 +16569,38 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], s13
+; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], s14
; SI-NEXT: v_mov_b32_e32 v2, s7
-; SI-NEXT: v_bfi_b32 v1, s12, v1, v2
-; SI-NEXT: .LBB13_7:
+; SI-NEXT: v_bfi_b32 v1, s0, v1, v2
+; SI-NEXT: s_branch .LBB13_10
+; SI-NEXT: .LBB13_9:
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: .LBB13_10:
+; SI-NEXT: v_mov_b32_e32 v2, s4
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_cmp_ngt_f64_e64 s[0:1], |s[2:3]|, |v[2:3]|
+; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
+; SI-NEXT: s_cbranch_vccz .LBB13_12
+; SI-NEXT: ; %bb.11: ; %frem.else
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_mov_b32_e32 v3, s5
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, |v[2:3]|
-; SI-NEXT: s_cbranch_vccz .LBB13_11
-; SI-NEXT: ; %bb.8: ; %frem.compute
+; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[2:3]|, |v[2:3]|
+; SI-NEXT: s_and_b32 s12, s3, 0x80000000
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s1, s12, s3
+; SI-NEXT: s_cselect_b32 s0, 0, s2
+; SI-NEXT: s_mov_b64 s[12:13], 0
+; SI-NEXT: s_branch .LBB13_13
+; SI-NEXT: .LBB13_12:
+; SI-NEXT: s_mov_b64 s[12:13], -1
+; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
+; SI-NEXT: .LBB13_13: ; %Flow49
+; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
+; SI-NEXT: s_cselect_b32 s12, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s12, 1
+; SI-NEXT: s_cbranch_scc1 .LBB13_19
+; SI-NEXT: ; %bb.14: ; %frem.compute
; SI-NEXT: s_and_b32 s0, s3, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[2:3]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -15302,11 +16625,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f64 v[2:3], v[2:3], 1
; SI-NEXT: v_readfirstlane_b32 s0, v4
; SI-NEXT: s_cselect_b32 s17, s0, 0
-; SI-NEXT: s_add_i32 s15, s17, -1
-; SI-NEXT: s_not_b32 s0, s15
+; SI-NEXT: s_add_i32 s14, s17, -1
+; SI-NEXT: s_not_b32 s0, s14
; SI-NEXT: s_add_i32 s16, s0, s13
; SI-NEXT: v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], 1.0
-; SI-NEXT: s_brev_b32 s14, -2
+; SI-NEXT: s_brev_b32 s15, -2
; SI-NEXT: s_mov_b32 s12, -1
; SI-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; SI-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5
@@ -15323,58 +16646,48 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f64 v[4:5], v[14:15], v[8:9], v[12:13]
; SI-NEXT: s_cmp_lt_i32 s16, 27
; SI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
-; SI-NEXT: s_cbranch_scc1 .LBB13_12
-; SI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB13_18
+; SI-NEXT: ; %bb.15: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s0, s13, s17
; SI-NEXT: s_add_i32 s16, s0, 26
; SI-NEXT: s_mov_b32 s13, 0x432fffff
; SI-NEXT: v_mov_b32_e32 v12, 0x43300000
-; SI-NEXT: v_mov_b32_e32 v10, 0
-; SI-NEXT: .LBB13_10: ; %frem.loop_body
+; SI-NEXT: v_mov_b32_e32 v8, 0
+; SI-NEXT: .LBB13_16: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v9, v7
-; SI-NEXT: v_mov_b32_e32 v8, v6
-; SI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
+; SI-NEXT: v_mov_b32_e32 v11, v7
+; SI-NEXT: v_mov_b32_e32 v10, v6
+; SI-NEXT: v_mul_f64 v[6:7], v[10:11], v[4:5]
; SI-NEXT: s_sub_i32 s16, s16, 26
-; SI-NEXT: v_bfi_b32 v11, s14, v12, v7
-; SI-NEXT: v_add_f64 v[13:14], v[6:7], v[10:11]
+; SI-NEXT: v_bfi_b32 v9, s15, v12, v7
+; SI-NEXT: v_add_f64 v[13:14], v[6:7], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[6:7]|, s[12:13]
-; SI-NEXT: v_add_f64 v[13:14], v[13:14], -v[10:11]
+; SI-NEXT: v_add_f64 v[13:14], v[13:14], -v[8:9]
; SI-NEXT: s_cmp_gt_i32 s16, 26
; SI-NEXT: v_cndmask_b32_e32 v7, v14, v7, vcc
; SI-NEXT: v_cndmask_b32_e32 v6, v13, v6, vcc
-; SI-NEXT: v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
+; SI-NEXT: v_fma_f64 v[6:7], -v[6:7], v[2:3], v[10:11]
; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; SI-NEXT: v_add_f64 v[13:14], v[6:7], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v7, v7, v14, vcc
; SI-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc
; SI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; SI-NEXT: s_cbranch_scc1 .LBB13_10
-; SI-NEXT: s_branch .LBB13_13
-; SI-NEXT: .LBB13_11: ; %frem.else
-; SI-NEXT: v_mov_b32_e32 v2, s4
-; SI-NEXT: v_mov_b32_e32 v3, s5
-; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[2:3]|, |v[2:3]|
-; SI-NEXT: s_and_b32 s12, s3, 0x80000000
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s1, s12, s3
-; SI-NEXT: s_cselect_b32 s0, 0, s2
-; SI-NEXT: v_mov_b32_e32 v3, s1
-; SI-NEXT: v_mov_b32_e32 v2, s0
-; SI-NEXT: s_branch .LBB13_14
-; SI-NEXT: .LBB13_12:
-; SI-NEXT: v_mov_b32_e32 v9, v7
-; SI-NEXT: v_mov_b32_e32 v8, v6
-; SI-NEXT: .LBB13_13: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB13_16
+; SI-NEXT: ; %bb.17: ; %Flow
+; SI-NEXT: v_mov_b32_e32 v6, v10
+; SI-NEXT: v_mov_b32_e32 v7, v11
+; SI-NEXT: .LBB13_18: ; %frem.loop_exit
; SI-NEXT: s_sub_i32 s0, s16, 25
-; SI-NEXT: v_ldexp_f64 v[6:7], v[8:9], s0
-; SI-NEXT: v_mov_b32_e32 v8, 0x43300000
+; SI-NEXT: v_ldexp_f64 v[6:7], v[6:7], s0
+; SI-NEXT: s_mov_b32 s0, -1
; SI-NEXT: v_mul_f64 v[4:5], v[6:7], v[4:5]
-; SI-NEXT: s_mov_b32 s13, 0x432fffff
-; SI-NEXT: v_bfi_b32 v9, s14, v8, v5
+; SI-NEXT: s_mov_b32 s1, 0x432fffff
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[0:1]
+; SI-NEXT: s_brev_b32 s0, -2
+; SI-NEXT: v_mov_b32_e32 v8, 0x43300000
+; SI-NEXT: v_bfi_b32 v9, s0, v8, v5
; SI-NEXT: v_mov_b32_e32 v8, 0
; SI-NEXT: v_add_f64 v[10:11], v[4:5], v[8:9]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[12:13]
; SI-NEXT: v_add_f64 v[8:9], v[10:11], -v[8:9]
; SI-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
@@ -15383,10 +16696,14 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NEXT: v_ldexp_f64 v[2:3], v[2:3], s15
+; SI-NEXT: v_ldexp_f64 v[2:3], v[2:3], s14
; SI-NEXT: v_mov_b32_e32 v4, s3
-; SI-NEXT: v_bfi_b32 v3, s14, v3, v4
-; SI-NEXT: .LBB13_14:
+; SI-NEXT: v_bfi_b32 v3, s0, v3, v4
+; SI-NEXT: s_branch .LBB13_20
+; SI-NEXT: .LBB13_19:
+; SI-NEXT: v_mov_b32_e32 v3, s1
+; SI-NEXT: v_mov_b32_e32 v2, s0
+; SI-NEXT: .LBB13_20: ; %Flow50
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
; SI-NEXT: v_cmp_lg_f64_e64 s[0:1], s[10:11], 0
@@ -15419,9 +16736,25 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; CI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:64
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[4:5]|
-; CI-NEXT: s_cbranch_vccz .LBB13_4
-; CI-NEXT: ; %bb.1: ; %frem.compute15
+; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB13_2
+; CI-NEXT: ; %bb.1: ; %frem.else16
+; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; CI-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
+; CI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
+; CI-NEXT: s_branch .LBB13_3
+; CI-NEXT: .LBB13_2:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr8_vgpr9
+; CI-NEXT: .LBB13_3: ; %Flow53
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB13_9
+; CI-NEXT: ; %bb.4: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v15, v[4:5]
; CI-NEXT: v_frexp_exp_i32_f64_e32 v14, v[0:1]
@@ -15444,11 +16777,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v17
; CI-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB13_6
-; CI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB13_8
+; CI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; CI-NEXT: v_sub_i32_e32 v14, vcc, v14, v15
; CI-NEXT: v_add_i32_e32 v17, vcc, 26, v14
-; CI-NEXT: .LBB13_3: ; %frem.loop_body23
+; CI-NEXT: .LBB13_6: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v15, v13
; CI-NEXT: v_mov_b32_e32 v14, v12
@@ -15462,27 +16795,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
; CI-NEXT: v_subrev_i32_e32 v17, vcc, 26, v17
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v17
-; CI-NEXT: s_cbranch_vccnz .LBB13_3
-; CI-NEXT: s_branch .LBB13_7
-; CI-NEXT: .LBB13_4: ; %frem.else16
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
-; CI-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; CI-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
-; CI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; CI-NEXT: s_cbranch_vccnz .LBB13_8
-; CI-NEXT: .LBB13_5: ; %frem.else
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; CI-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; CI-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
-; CI-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
-; CI-NEXT: s_branch .LBB13_13
-; CI-NEXT: .LBB13_6:
-; CI-NEXT: v_mov_b32_e32 v15, v13
-; CI-NEXT: v_mov_b32_e32 v14, v12
-; CI-NEXT: .LBB13_7: ; %frem.loop_exit24
-; CI-NEXT: v_subrev_i32_e32 v12, vcc, 25, v17
-; CI-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
+; CI-NEXT: s_cbranch_vccnz .LBB13_6
+; CI-NEXT: ; %bb.7: ; %Flow51
+; CI-NEXT: v_mov_b32_e32 v12, v14
+; CI-NEXT: v_mov_b32_e32 v13, v15
+; CI-NEXT: .LBB13_8: ; %frem.loop_exit24
+; CI-NEXT: v_subrev_i32_e32 v14, vcc, 25, v17
+; CI-NEXT: v_ldexp_f64 v[12:13], v[12:13], v14
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
; CI-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
@@ -15493,9 +16812,26 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
; CI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; CI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; CI-NEXT: s_cbranch_vccz .LBB13_5
-; CI-NEXT: .LBB13_8: ; %frem.compute
+; CI-NEXT: .LBB13_9:
+; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB13_11
+; CI-NEXT: ; %bb.10: ; %frem.else
+; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; CI-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
+; CI-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
+; CI-NEXT: s_branch .LBB13_12
+; CI-NEXT: .LBB13_11:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr10_vgpr11
+; CI-NEXT: .LBB13_12: ; %Flow49
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB13_18
+; CI-NEXT: ; %bb.13: ; %frem.compute
; CI-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v17, v[6:7]
; CI-NEXT: v_frexp_exp_i32_f64_e32 v16, v[2:3]
@@ -15518,11 +16854,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v19
; CI-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB13_11
-; CI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB13_17
+; CI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v16, vcc, v16, v17
; CI-NEXT: v_add_i32_e32 v19, vcc, 26, v16
-; CI-NEXT: .LBB13_10: ; %frem.loop_body
+; CI-NEXT: .LBB13_15: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v17, v15
; CI-NEXT: v_mov_b32_e32 v16, v14
@@ -15536,14 +16872,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
; CI-NEXT: v_subrev_i32_e32 v19, vcc, 26, v19
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v19
-; CI-NEXT: s_cbranch_vccnz .LBB13_10
-; CI-NEXT: s_branch .LBB13_12
-; CI-NEXT: .LBB13_11:
-; CI-NEXT: v_mov_b32_e32 v17, v15
-; CI-NEXT: v_mov_b32_e32 v16, v14
-; CI-NEXT: .LBB13_12: ; %frem.loop_exit
-; CI-NEXT: v_subrev_i32_e32 v14, vcc, 25, v19
-; CI-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
+; CI-NEXT: s_cbranch_vccnz .LBB13_15
+; CI-NEXT: ; %bb.16: ; %Flow
+; CI-NEXT: v_mov_b32_e32 v14, v16
+; CI-NEXT: v_mov_b32_e32 v15, v17
+; CI-NEXT: .LBB13_17: ; %frem.loop_exit
+; CI-NEXT: v_subrev_i32_e32 v16, vcc, 25, v19
+; CI-NEXT: v_ldexp_f64 v[14:15], v[14:15], v16
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
; CI-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
@@ -15554,7 +16889,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc
; CI-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; CI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; CI-NEXT: .LBB13_13:
+; CI-NEXT: .LBB13_18: ; %Flow50
; CI-NEXT: s_mov_b32 s4, 0
; CI-NEXT: s_mov_b32 s5, 0x7ff00000
; CI-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[4:5]
@@ -15587,9 +16922,25 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[4:5]|
-; VI-NEXT: s_cbranch_vccz .LBB13_4
-; VI-NEXT: ; %bb.1: ; %frem.compute15
+; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB13_2
+; VI-NEXT: ; %bb.1: ; %frem.else16
+; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; VI-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
+; VI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
+; VI-NEXT: s_branch .LBB13_3
+; VI-NEXT: .LBB13_2:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr8_vgpr9
+; VI-NEXT: .LBB13_3: ; %Flow53
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB13_9
+; VI-NEXT: ; %bb.4: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v15, v[4:5]
; VI-NEXT: v_frexp_exp_i32_f64_e32 v14, v[0:1]
@@ -15612,11 +16963,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v17
; VI-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB13_6
-; VI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB13_8
+; VI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; VI-NEXT: v_sub_u32_e32 v14, vcc, v14, v15
; VI-NEXT: v_add_u32_e32 v17, vcc, 26, v14
-; VI-NEXT: .LBB13_3: ; %frem.loop_body23
+; VI-NEXT: .LBB13_6: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v15, v13
; VI-NEXT: v_mov_b32_e32 v14, v12
@@ -15630,27 +16981,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
; VI-NEXT: v_subrev_u32_e32 v17, vcc, 26, v17
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v17
-; VI-NEXT: s_cbranch_vccnz .LBB13_3
-; VI-NEXT: s_branch .LBB13_7
-; VI-NEXT: .LBB13_4: ; %frem.else16
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
-; VI-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; VI-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
-; VI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; VI-NEXT: s_cbranch_vccnz .LBB13_8
-; VI-NEXT: .LBB13_5: ; %frem.else
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; VI-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; VI-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
-; VI-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
-; VI-NEXT: s_branch .LBB13_13
-; VI-NEXT: .LBB13_6:
-; VI-NEXT: v_mov_b32_e32 v15, v13
-; VI-NEXT: v_mov_b32_e32 v14, v12
-; VI-NEXT: .LBB13_7: ; %frem.loop_exit24
-; VI-NEXT: v_subrev_u32_e32 v12, vcc, 25, v17
-; VI-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
+; VI-NEXT: s_cbranch_vccnz .LBB13_6
+; VI-NEXT: ; %bb.7: ; %Flow51
+; VI-NEXT: v_mov_b32_e32 v12, v14
+; VI-NEXT: v_mov_b32_e32 v13, v15
+; VI-NEXT: .LBB13_8: ; %frem.loop_exit24
+; VI-NEXT: v_subrev_u32_e32 v14, vcc, 25, v17
+; VI-NEXT: v_ldexp_f64 v[12:13], v[12:13], v14
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
; VI-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
@@ -15661,9 +16998,26 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
; VI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; VI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; VI-NEXT: s_cbranch_vccz .LBB13_5
-; VI-NEXT: .LBB13_8: ; %frem.compute
+; VI-NEXT: .LBB13_9:
+; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB13_11
+; VI-NEXT: ; %bb.10: ; %frem.else
+; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; VI-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
+; VI-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
+; VI-NEXT: s_branch .LBB13_12
+; VI-NEXT: .LBB13_11:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr10_vgpr11
+; VI-NEXT: .LBB13_12: ; %Flow49
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB13_18
+; VI-NEXT: ; %bb.13: ; %frem.compute
; VI-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v17, v[6:7]
; VI-NEXT: v_frexp_exp_i32_f64_e32 v16, v[2:3]
@@ -15686,11 +17040,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v19
; VI-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB13_11
-; VI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB13_17
+; VI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v16, vcc, v16, v17
; VI-NEXT: v_add_u32_e32 v19, vcc, 26, v16
-; VI-NEXT: .LBB13_10: ; %frem.loop_body
+; VI-NEXT: .LBB13_15: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v17, v15
; VI-NEXT: v_mov_b32_e32 v16, v14
@@ -15704,14 +17058,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
; VI-NEXT: v_subrev_u32_e32 v19, vcc, 26, v19
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v19
-; VI-NEXT: s_cbranch_vccnz .LBB13_10
-; VI-NEXT: s_branch .LBB13_12
-; VI-NEXT: .LBB13_11:
-; VI-NEXT: v_mov_b32_e32 v17, v15
-; VI-NEXT: v_mov_b32_e32 v16, v14
-; VI-NEXT: .LBB13_12: ; %frem.loop_exit
-; VI-NEXT: v_subrev_u32_e32 v14, vcc, 25, v19
-; VI-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
+; VI-NEXT: s_cbranch_vccnz .LBB13_15
+; VI-NEXT: ; %bb.16: ; %Flow
+; VI-NEXT: v_mov_b32_e32 v14, v16
+; VI-NEXT: v_mov_b32_e32 v15, v17
+; VI-NEXT: .LBB13_17: ; %frem.loop_exit
+; VI-NEXT: v_subrev_u32_e32 v16, vcc, 25, v19
+; VI-NEXT: v_ldexp_f64 v[14:15], v[14:15], v16
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
; VI-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
@@ -15722,7 +17075,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc
; VI-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; VI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; VI-NEXT: .LBB13_13:
+; VI-NEXT: .LBB13_18: ; %Flow50
; VI-NEXT: s_mov_b32 s2, 0
; VI-NEXT: s_mov_b32 s3, 0x7ff00000
; VI-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[4:5]
@@ -15750,9 +17103,25 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3]
; GFX9-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[4:5]|
-; GFX9-NEXT: s_cbranch_vccz .LBB13_4
-; GFX9-NEXT: ; %bb.1: ; %frem.compute15
+; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB13_2
+; GFX9-NEXT: ; %bb.1: ; %frem.else16
+; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; GFX9-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
+; GFX9-NEXT: s_branch .LBB13_3
+; GFX9-NEXT: .LBB13_2:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr8_vgpr9
+; GFX9-NEXT: .LBB13_3: ; %Flow53
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB13_9
+; GFX9-NEXT: ; %bb.4: ; %frem.compute15
; GFX9-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v15, v[4:5]
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v14, v[0:1]
@@ -15775,11 +17144,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v17
; GFX9-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_6
-; GFX9-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_8
+; GFX9-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX9-NEXT: v_sub_u32_e32 v14, v14, v15
; GFX9-NEXT: v_add_u32_e32 v17, 26, v14
-; GFX9-NEXT: .LBB13_3: ; %frem.loop_body23
+; GFX9-NEXT: .LBB13_6: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v15, v13
; GFX9-NEXT: v_mov_b32_e32 v14, v12
@@ -15793,27 +17162,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v18, vcc
; GFX9-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v17
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_3
-; GFX9-NEXT: s_branch .LBB13_7
-; GFX9-NEXT: .LBB13_4: ; %frem.else16
-; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
-; GFX9-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_8
-; GFX9-NEXT: .LBB13_5: ; %frem.else
-; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
-; GFX9-NEXT: s_branch .LBB13_13
-; GFX9-NEXT: .LBB13_6:
-; GFX9-NEXT: v_mov_b32_e32 v15, v13
-; GFX9-NEXT: v_mov_b32_e32 v14, v12
-; GFX9-NEXT: .LBB13_7: ; %frem.loop_exit24
-; GFX9-NEXT: v_subrev_u32_e32 v12, 25, v17
-; GFX9-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_6
+; GFX9-NEXT: ; %bb.7: ; %Flow51
+; GFX9-NEXT: v_mov_b32_e32 v12, v14
+; GFX9-NEXT: v_mov_b32_e32 v13, v15
+; GFX9-NEXT: .LBB13_8: ; %frem.loop_exit24
+; GFX9-NEXT: v_subrev_u32_e32 v14, 25, v17
+; GFX9-NEXT: v_ldexp_f64 v[12:13], v[12:13], v14
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
; GFX9-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
@@ -15824,9 +17179,26 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
; GFX9-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX9-NEXT: v_bfi_b32 v9, s2, v9, v1
-; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; GFX9-NEXT: s_cbranch_vccz .LBB13_5
-; GFX9-NEXT: .LBB13_8: ; %frem.compute
+; GFX9-NEXT: .LBB13_9:
+; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB13_11
+; GFX9-NEXT: ; %bb.10: ; %frem.else
+; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
+; GFX9-NEXT: s_branch .LBB13_12
+; GFX9-NEXT: .LBB13_11:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr10_vgpr11
+; GFX9-NEXT: .LBB13_12: ; %Flow49
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB13_18
+; GFX9-NEXT: ; %bb.13: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v17, v[6:7]
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v16, v[2:3]
@@ -15849,11 +17221,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v19
; GFX9-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_11
-; GFX9-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_17
+; GFX9-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v16, v16, v17
; GFX9-NEXT: v_add_u32_e32 v19, 26, v16
-; GFX9-NEXT: .LBB13_10: ; %frem.loop_body
+; GFX9-NEXT: .LBB13_15: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v17, v15
; GFX9-NEXT: v_mov_b32_e32 v16, v14
@@ -15867,14 +17239,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v20, vcc
; GFX9-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v19
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_10
-; GFX9-NEXT: s_branch .LBB13_12
-; GFX9-NEXT: .LBB13_11:
-; GFX9-NEXT: v_mov_b32_e32 v17, v15
-; GFX9-NEXT: v_mov_b32_e32 v16, v14
-; GFX9-NEXT: .LBB13_12: ; %frem.loop_exit
-; GFX9-NEXT: v_subrev_u32_e32 v14, 25, v19
-; GFX9-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_15
+; GFX9-NEXT: ; %bb.16: ; %Flow
+; GFX9-NEXT: v_mov_b32_e32 v14, v16
+; GFX9-NEXT: v_mov_b32_e32 v15, v17
+; GFX9-NEXT: .LBB13_17: ; %frem.loop_exit
+; GFX9-NEXT: v_subrev_u32_e32 v16, 25, v19
+; GFX9-NEXT: v_ldexp_f64 v[14:15], v[14:15], v16
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
; GFX9-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
@@ -15885,7 +17256,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc
; GFX9-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX9-NEXT: v_bfi_b32 v11, s2, v11, v3
-; GFX9-NEXT: .LBB13_13:
+; GFX9-NEXT: .LBB13_18: ; %Flow50
; GFX9-NEXT: s_mov_b32 s2, 0
; GFX9-NEXT: s_mov_b32 s3, 0x7ff00000
; GFX9-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[4:5]
@@ -15914,146 +17285,162 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3]
; GFX10-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX10-NEXT: s_cbranch_vccz .LBB13_5
-; GFX10-NEXT: ; %bb.1: ; %frem.compute15
+; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB13_2
+; GFX10-NEXT: ; %bb.1: ; %frem.else16
+; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX10-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX10-NEXT: s_branch .LBB13_3
+; GFX10-NEXT: .LBB13_2:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr8_vgpr9
+; GFX10-NEXT: .LBB13_3: ; %Flow53
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB13_9
+; GFX10-NEXT: ; %bb.4: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v11, v[4:5]
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
-; GFX10-NEXT: v_ldexp_f64 v[12:13], v[8:9], 26
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
+; GFX10-NEXT: v_ldexp_f64 v[10:11], v[8:9], 26
; GFX10-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
-; GFX10-NEXT: v_add_nc_u32_e32 v16, -1, v11
-; GFX10-NEXT: v_readfirstlane_b32 s3, v11
-; GFX10-NEXT: v_readfirstlane_b32 s2, v10
-; GFX10-NEXT: v_not_b32_e32 v11, v16
-; GFX10-NEXT: v_add_nc_u32_e32 v17, v11, v10
+; GFX10-NEXT: v_add_nc_u32_e32 v16, -1, v13
+; GFX10-NEXT: v_readfirstlane_b32 s3, v13
+; GFX10-NEXT: v_readfirstlane_b32 s2, v12
+; GFX10-NEXT: v_not_b32_e32 v13, v16
+; GFX10-NEXT: v_add_nc_u32_e32 v17, v13, v12
; GFX10-NEXT: v_ldexp_f64 v[8:9], v[8:9], 1
-; GFX10-NEXT: v_div_scale_f64 v[10:11], s4, v[8:9], v[8:9], 1.0
-; GFX10-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
-; GFX10-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX10-NEXT: v_div_scale_f64 v[12:13], s4, v[8:9], v[8:9], 1.0
+; GFX10-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX10-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX10-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX10-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX10-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX10-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX10-NEXT: v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
; GFX10-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15]
-; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
-; GFX10-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
+; GFX10-NEXT: v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
+; GFX10-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
-; GFX10-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB13_7
-; GFX10-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX10-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX10-NEXT: s_cbranch_vccnz .LBB13_8
+; GFX10-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 26
-; GFX10-NEXT: .LBB13_3: ; %frem.loop_body23
+; GFX10-NEXT: .LBB13_6: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v15, v13
-; GFX10-NEXT: v_mov_b32_e32 v14, v12
+; GFX10-NEXT: v_mov_b32_e32 v15, v11
+; GFX10-NEXT: v_mov_b32_e32 v14, v10
; GFX10-NEXT: s_sub_i32 s2, s2, 26
; GFX10-NEXT: s_cmp_gt_i32 s2, 26
-; GFX10-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11]
-; GFX10-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
-; GFX10-NEXT: v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
-; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
-; GFX10-NEXT: v_add_f64 v[17:18], v[12:13], v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v18, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v17, vcc_lo
-; GFX10-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB13_3
-; GFX10-NEXT: ; %bb.4:
+; GFX10-NEXT: v_mul_f64 v[10:11], v[14:15], v[12:13]
+; GFX10-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX10-NEXT: v_add_f64 v[17:18], v[10:11], v[8:9]
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
+; GFX10-NEXT: s_cbranch_scc1 .LBB13_6
+; GFX10-NEXT: ; %bb.7: ; %Flow51
; GFX10-NEXT: v_mov_b32_e32 v17, s2
-; GFX10-NEXT: s_branch .LBB13_8
-; GFX10-NEXT: .LBB13_5: ; %frem.else16
-; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX10-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX10-NEXT: s_cbranch_vccnz .LBB13_9
-; GFX10-NEXT: .LBB13_6: ; %frem.else
-; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX10-NEXT: s_branch .LBB13_15
-; GFX10-NEXT: .LBB13_7:
-; GFX10-NEXT: v_mov_b32_e32 v15, v13
-; GFX10-NEXT: v_mov_b32_e32 v14, v12
+; GFX10-NEXT: v_mov_b32_e32 v10, v14
+; GFX10-NEXT: v_mov_b32_e32 v11, v15
; GFX10-NEXT: .LBB13_8: ; %frem.loop_exit24
-; GFX10-NEXT: v_subrev_nc_u32_e32 v12, 25, v17
-; GFX10-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
-; GFX10-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
-; GFX10-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
-; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
+; GFX10-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
+; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
+; GFX10-NEXT: v_mul_f64 v[12:13], v[10:11], v[12:13]
+; GFX10-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX10-NEXT: v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_add_f64 v[8:9], v[10:11], v[8:9]
; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX10-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX10-NEXT: s_cbranch_vccz .LBB13_6
-; GFX10-NEXT: .LBB13_9: ; %frem.compute
+; GFX10-NEXT: .LBB13_9:
+; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB13_11
+; GFX10-NEXT: ; %bb.10: ; %frem.else
+; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX10-NEXT: s_branch .LBB13_12
+; GFX10-NEXT: .LBB13_11:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr10_vgpr11
+; GFX10-NEXT: .LBB13_12: ; %Flow49
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB13_18
+; GFX10-NEXT: ; %bb.13: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v13, v[6:7]
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v12, v[2:3]
-; GFX10-NEXT: v_ldexp_f64 v[14:15], v[10:11], 26
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
+; GFX10-NEXT: v_ldexp_f64 v[12:13], v[10:11], 26
; GFX10-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
-; GFX10-NEXT: v_add_nc_u32_e32 v18, -1, v13
-; GFX10-NEXT: v_readfirstlane_b32 s3, v13
-; GFX10-NEXT: v_readfirstlane_b32 s2, v12
-; GFX10-NEXT: v_not_b32_e32 v13, v18
-; GFX10-NEXT: v_add_nc_u32_e32 v19, v13, v12
+; GFX10-NEXT: v_add_nc_u32_e32 v18, -1, v15
+; GFX10-NEXT: v_readfirstlane_b32 s3, v15
+; GFX10-NEXT: v_readfirstlane_b32 s2, v14
+; GFX10-NEXT: v_not_b32_e32 v15, v18
+; GFX10-NEXT: v_add_nc_u32_e32 v19, v15, v14
; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], 1
-; GFX10-NEXT: v_div_scale_f64 v[12:13], s4, v[10:11], v[10:11], 1.0
-; GFX10-NEXT: v_rcp_f64_e32 v[16:17], v[12:13]
-; GFX10-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
+; GFX10-NEXT: v_div_scale_f64 v[14:15], s4, v[10:11], v[10:11], 1.0
+; GFX10-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
+; GFX10-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX10-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
-; GFX10-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
+; GFX10-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX10-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX10-NEXT: v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
; GFX10-NEXT: v_mul_f64 v[22:23], v[20:21], v[16:17]
-; GFX10-NEXT: v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
-; GFX10-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[22:23]
+; GFX10-NEXT: v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
+; GFX10-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
-; GFX10-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB13_13
-; GFX10-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX10-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; GFX10-NEXT: s_cbranch_vccnz .LBB13_17
+; GFX10-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 26
-; GFX10-NEXT: .LBB13_11: ; %frem.loop_body
+; GFX10-NEXT: .LBB13_15: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v17, v15
-; GFX10-NEXT: v_mov_b32_e32 v16, v14
+; GFX10-NEXT: v_mov_b32_e32 v17, v13
+; GFX10-NEXT: v_mov_b32_e32 v16, v12
; GFX10-NEXT: s_sub_i32 s2, s2, 26
; GFX10-NEXT: s_cmp_gt_i32 s2, 26
-; GFX10-NEXT: v_mul_f64 v[14:15], v[16:17], v[12:13]
-; GFX10-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
-; GFX10-NEXT: v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
-; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
-; GFX10-NEXT: v_add_f64 v[19:20], v[14:15], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v20, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v19, vcc_lo
-; GFX10-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB13_11
-; GFX10-NEXT: ; %bb.12:
-; GFX10-NEXT: v_mov_b32_e32 v19, s2
-; GFX10-NEXT: s_branch .LBB13_14
-; GFX10-NEXT: .LBB13_13:
-; GFX10-NEXT: v_mov_b32_e32 v17, v15
-; GFX10-NEXT: v_mov_b32_e32 v16, v14
-; GFX10-NEXT: .LBB13_14: ; %frem.loop_exit
-; GFX10-NEXT: v_subrev_nc_u32_e32 v14, 25, v19
-; GFX10-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
-; GFX10-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
+; GFX10-NEXT: v_mul_f64 v[12:13], v[16:17], v[14:15]
; GFX10-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
-; GFX10-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
+; GFX10-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX10-NEXT: v_add_f64 v[19:20], v[12:13], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v20, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v19, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX10-NEXT: s_cbranch_scc1 .LBB13_15
+; GFX10-NEXT: ; %bb.16: ; %Flow
+; GFX10-NEXT: v_mov_b32_e32 v19, s2
+; GFX10-NEXT: v_mov_b32_e32 v12, v16
+; GFX10-NEXT: v_mov_b32_e32 v13, v17
+; GFX10-NEXT: .LBB13_17: ; %frem.loop_exit
+; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
+; GFX10-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
+; GFX10-NEXT: v_mul_f64 v[14:15], v[12:13], v[14:15]
+; GFX10-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
+; GFX10-NEXT: v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX10-NEXT: v_add_f64 v[10:11], v[12:13], v[10:11]
; GFX10-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX10-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX10-NEXT: .LBB13_15:
+; GFX10-NEXT: .LBB13_18: ; %Flow50
; GFX10-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX10-NEXT: v_mov_b32_e32 v4, 0
@@ -16079,92 +17466,93 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: global_load_b128 v[0:3], v4, s[2:3]
; GFX11-NEXT: global_load_b128 v[4:7], v4, s[4:5] offset:64
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX11-NEXT: s_cbranch_vccz .LBB13_5
-; GFX11-NEXT: ; %bb.1: ; %frem.compute15
+; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB13_2
+; GFX11-NEXT: ; %bb.1: ; %frem.else16
+; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX11-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX11-NEXT: s_branch .LBB13_3
+; GFX11-NEXT: .LBB13_2:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr8_vgpr9
+; GFX11-NEXT: .LBB13_3: ; %Flow53
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB13_9
+; GFX11-NEXT: ; %bb.4: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v11, v[4:5]
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_ldexp_f64 v[12:13], v[8:9], 26
+; GFX11-NEXT: v_ldexp_f64 v[10:11], v[8:9], 26
; GFX11-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
-; GFX11-NEXT: v_add_nc_u32_e32 v16, -1, v11
-; GFX11-NEXT: v_readfirstlane_b32 s3, v11
-; GFX11-NEXT: v_readfirstlane_b32 s2, v10
+; GFX11-NEXT: v_add_nc_u32_e32 v16, -1, v13
+; GFX11-NEXT: v_readfirstlane_b32 s3, v13
+; GFX11-NEXT: v_readfirstlane_b32 s2, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_not_b32_e32 v11, v16
-; GFX11-NEXT: v_add_nc_u32_e32 v17, v11, v10
+; GFX11-NEXT: v_not_b32_e32 v13, v16
+; GFX11-NEXT: v_add_nc_u32_e32 v17, v13, v12
; GFX11-NEXT: v_ldexp_f64 v[8:9], v[8:9], 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
-; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
+; GFX11-NEXT: v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
+; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX11-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX11-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX11-NEXT: v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
; GFX11-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
-; GFX11-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
+; GFX11-NEXT: v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
+; GFX11-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB13_7
-; GFX11-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX11-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX11-NEXT: s_cbranch_vccnz .LBB13_8
+; GFX11-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 26
-; GFX11-NEXT: .p2align 6
-; GFX11-NEXT: .LBB13_3: ; %frem.loop_body23
-; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
-; GFX11-NEXT: s_sub_i32 s2, s2, 26
-; GFX11-NEXT: s_cmp_gt_i32 s2, 26
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11]
-; GFX11-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
-; GFX11-NEXT: v_add_f64 v[17:18], v[12:13], v[8:9]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v17
-; GFX11-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB13_3
-; GFX11-NEXT: ; %bb.4:
-; GFX11-NEXT: v_mov_b32_e32 v17, s2
-; GFX11-NEXT: s_branch .LBB13_8
-; GFX11-NEXT: .LBB13_5: ; %frem.else16
-; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX11-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX11-NEXT: s_cbranch_vccnz .LBB13_9
-; GFX11-NEXT: .LBB13_6: ; %frem.else
-; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX11-NEXT: s_branch .LBB13_15
-; GFX11-NEXT: .LBB13_7:
-; GFX11-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
-; GFX11-NEXT: .LBB13_8: ; %frem.loop_exit24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_nc_u32_e32 v12, 25, v17
-; GFX11-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
+; GFX11-NEXT: .p2align 6
+; GFX11-NEXT: .LBB13_6: ; %frem.loop_body23
+; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
+; GFX11-NEXT: s_sub_i32 s2, s2, 26
+; GFX11-NEXT: s_cmp_gt_i32 s2, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
+; GFX11-NEXT: v_mul_f64 v[10:11], v[14:15], v[12:13]
; GFX11-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
+; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT: v_add_f64 v[17:18], v[10:11], v[8:9]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
+; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
+; GFX11-NEXT: s_cbranch_scc1 .LBB13_6
+; GFX11-NEXT: ; %bb.7: ; %Flow51
+; GFX11-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
+; GFX11-NEXT: v_mov_b32_e32 v11, v15
+; GFX11-NEXT: .LBB13_8: ; %frem.loop_exit24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
+; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f64 v[12:13], v[10:11], v[12:13]
+; GFX11-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX11-NEXT: v_add_f64 v[8:9], v[10:11], v[8:9]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -16172,77 +17560,94 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX11-NEXT: s_cbranch_vccz .LBB13_6
-; GFX11-NEXT: .LBB13_9: ; %frem.compute
+; GFX11-NEXT: .LBB13_9:
+; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB13_11
+; GFX11-NEXT: ; %bb.10: ; %frem.else
+; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX11-NEXT: s_branch .LBB13_12
+; GFX11-NEXT: .LBB13_11:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr10_vgpr11
+; GFX11-NEXT: .LBB13_12: ; %Flow49
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB13_18
+; GFX11-NEXT: ; %bb.13: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v13, v[6:7]
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v12, v[2:3]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_ldexp_f64 v[14:15], v[10:11], 26
+; GFX11-NEXT: v_ldexp_f64 v[12:13], v[10:11], 26
; GFX11-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
-; GFX11-NEXT: v_add_nc_u32_e32 v18, -1, v13
-; GFX11-NEXT: v_readfirstlane_b32 s3, v13
-; GFX11-NEXT: v_readfirstlane_b32 s2, v12
+; GFX11-NEXT: v_add_nc_u32_e32 v18, -1, v15
+; GFX11-NEXT: v_readfirstlane_b32 s3, v15
+; GFX11-NEXT: v_readfirstlane_b32 s2, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_not_b32_e32 v13, v18
-; GFX11-NEXT: v_add_nc_u32_e32 v19, v13, v12
+; GFX11-NEXT: v_not_b32_e32 v15, v18
+; GFX11-NEXT: v_add_nc_u32_e32 v19, v15, v14
; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], 1.0
-; GFX11-NEXT: v_rcp_f64_e32 v[16:17], v[12:13]
+; GFX11-NEXT: v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
+; GFX11-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
+; GFX11-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
-; GFX11-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
+; GFX11-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX11-NEXT: v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
; GFX11-NEXT: v_mul_f64 v[22:23], v[20:21], v[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
-; GFX11-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[22:23]
+; GFX11-NEXT: v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
+; GFX11-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB13_13
-; GFX11-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX11-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; GFX11-NEXT: s_cbranch_vccnz .LBB13_17
+; GFX11-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 26
; GFX11-NEXT: .p2align 6
-; GFX11-NEXT: .LBB13_11: ; %frem.loop_body
+; GFX11-NEXT: .LBB13_15: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
+; GFX11-NEXT: v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
; GFX11-NEXT: s_sub_i32 s2, s2, 26
; GFX11-NEXT: s_cmp_gt_i32 s2, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[14:15], v[16:17], v[12:13]
-; GFX11-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
-; GFX11-NEXT: v_add_f64 v[19:20], v[14:15], v[10:11]
+; GFX11-NEXT: v_mul_f64 v[12:13], v[16:17], v[14:15]
+; GFX11-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_cndmask_b32 v14, v14, v19
-; GFX11-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB13_11
-; GFX11-NEXT: ; %bb.12:
-; GFX11-NEXT: v_mov_b32_e32 v19, s2
-; GFX11-NEXT: s_branch .LBB13_14
-; GFX11-NEXT: .LBB13_13:
-; GFX11-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
-; GFX11-NEXT: .LBB13_14: ; %frem.loop_exit
+; GFX11-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX11-NEXT: v_add_f64 v[19:20], v[12:13], v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_nc_u32_e32 v14, 25, v19
-; GFX11-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
+; GFX11-NEXT: v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
+; GFX11-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX11-NEXT: s_cbranch_scc1 .LBB13_15
+; GFX11-NEXT: ; %bb.16: ; %Flow
+; GFX11-NEXT: v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
+; GFX11-NEXT: v_mov_b32_e32 v13, v17
+; GFX11-NEXT: .LBB13_17: ; %frem.loop_exit
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
+; GFX11-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
-; GFX11-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX11-NEXT: v_mul_f64 v[14:15], v[12:13], v[14:15]
+; GFX11-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
+; GFX11-NEXT: v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX11-NEXT: v_add_f64 v[10:11], v[12:13], v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -16250,7 +17655,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX11-NEXT: .LBB13_15:
+; GFX11-NEXT: .LBB13_18: ; %Flow50
; GFX11-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -16274,91 +17679,92 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: global_load_b128 v[0:3], v4, s[2:3]
; GFX1150-NEXT: global_load_b128 v[4:7], v4, s[4:5] offset:64
; GFX1150-NEXT: s_waitcnt vmcnt(0)
-; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX1150-NEXT: s_cbranch_vccz .LBB13_5
-; GFX1150-NEXT: ; %bb.1: ; %frem.compute15
+; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
+; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX1150-NEXT: s_cbranch_vccz .LBB13_2
+; GFX1150-NEXT: ; %bb.1: ; %frem.else16
+; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX1150-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; GFX1150-NEXT: s_mov_b32 s2, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX1150-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB13_3
+; GFX1150-NEXT: .LBB13_2:
+; GFX1150-NEXT: s_mov_b32 s2, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr8_vgpr9
+; GFX1150-NEXT: .LBB13_3: ; %Flow53
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB13_9
+; GFX1150-NEXT: ; %bb.4: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v11, v[4:5]
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[8:9], 26
+; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[8:9], 26
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
-; GFX1150-NEXT: v_add_nc_u32_e32 v16, -1, v11
-; GFX1150-NEXT: v_readfirstlane_b32 s3, v11
-; GFX1150-NEXT: v_readfirstlane_b32 s2, v10
+; GFX1150-NEXT: v_add_nc_u32_e32 v16, -1, v13
+; GFX1150-NEXT: v_readfirstlane_b32 s3, v13
+; GFX1150-NEXT: v_readfirstlane_b32 s2, v12
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_not_b32_e32 v11, v16
-; GFX1150-NEXT: v_add_nc_u32_e32 v17, v11, v10
+; GFX1150-NEXT: v_not_b32_e32 v13, v16
+; GFX1150-NEXT: v_add_nc_u32_e32 v17, v13, v12
; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[8:9], 1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
-; GFX1150-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
+; GFX1150-NEXT: v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
+; GFX1150-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX1150-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX1150-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX1150-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX1150-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX1150-NEXT: v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15]
-; GFX1150-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX1150-NEXT: v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
+; GFX1150-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
-; GFX1150-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB13_7
-; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX1150-NEXT: s_cbranch_vccnz .LBB13_8
+; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_sub_i32 s2, s2, s3
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s2, s2, 26
; GFX1150-NEXT: .p2align 6
-; GFX1150-NEXT: .LBB13_3: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB13_6: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
+; GFX1150-NEXT: v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
; GFX1150-NEXT: s_sub_i32 s2, s2, 26
; GFX1150-NEXT: s_cmp_gt_i32 s2, 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11]
-; GFX1150-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1150-NEXT: v_mul_f64 v[10:11], v[14:15], v[12:13]
+; GFX1150-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
-; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
-; GFX1150-NEXT: v_add_f64 v[17:18], v[12:13], v[8:9]
+; GFX1150-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX1150-NEXT: v_add_f64 v[17:18], v[10:11], v[8:9]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v17
-; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB13_3
-; GFX1150-NEXT: ; %bb.4:
-; GFX1150-NEXT: v_mov_b32_e32 v17, s2
-; GFX1150-NEXT: s_branch .LBB13_8
-; GFX1150-NEXT: .LBB13_5: ; %frem.else16
-; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX1150-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX1150-NEXT: s_cbranch_vccnz .LBB13_9
-; GFX1150-NEXT: .LBB13_6: ; %frem.else
-; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX1150-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB13_15
-; GFX1150-NEXT: .LBB13_7:
-; GFX1150-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
+; GFX1150-NEXT: v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
+; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
+; GFX1150-NEXT: s_cbranch_scc1 .LBB13_6
+; GFX1150-NEXT: ; %bb.7: ; %Flow51
+; GFX1150-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
+; GFX1150-NEXT: v_mov_b32_e32 v11, v15
; GFX1150-NEXT: .LBB13_8: ; %frem.loop_exit24
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
+; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_subrev_nc_u32_e32 v12, 25, v17
-; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
-; GFX1150-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX1150-NEXT: v_mul_f64 v[12:13], v[10:11], v[12:13]
+; GFX1150-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
+; GFX1150-NEXT: v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX1150-NEXT: v_add_f64 v[8:9], v[10:11], v[8:9]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -16366,76 +17772,93 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX1150-NEXT: s_cbranch_vccz .LBB13_6
-; GFX1150-NEXT: .LBB13_9: ; %frem.compute
+; GFX1150-NEXT: .LBB13_9:
+; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
+; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX1150-NEXT: s_cbranch_vccz .LBB13_11
+; GFX1150-NEXT: ; %bb.10: ; %frem.else
+; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX1150-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; GFX1150-NEXT: s_mov_b32 s2, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX1150-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB13_12
+; GFX1150-NEXT: .LBB13_11:
+; GFX1150-NEXT: s_mov_b32 s2, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr10_vgpr11
+; GFX1150-NEXT: .LBB13_12: ; %Flow49
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB13_18
+; GFX1150-NEXT: ; %bb.13: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v13, v[6:7]
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v12, v[2:3]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1150-NEXT: v_ldexp_f64 v[14:15], v[10:11], 26
+; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[10:11], 26
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
-; GFX1150-NEXT: v_add_nc_u32_e32 v18, -1, v13
-; GFX1150-NEXT: v_readfirstlane_b32 s3, v13
-; GFX1150-NEXT: v_readfirstlane_b32 s2, v12
+; GFX1150-NEXT: v_add_nc_u32_e32 v18, -1, v15
+; GFX1150-NEXT: v_readfirstlane_b32 s3, v15
+; GFX1150-NEXT: v_readfirstlane_b32 s2, v14
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_not_b32_e32 v13, v18
-; GFX1150-NEXT: v_add_nc_u32_e32 v19, v13, v12
+; GFX1150-NEXT: v_not_b32_e32 v15, v18
+; GFX1150-NEXT: v_add_nc_u32_e32 v19, v15, v14
; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], 1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], 1.0
-; GFX1150-NEXT: v_rcp_f64_e32 v[16:17], v[12:13]
+; GFX1150-NEXT: v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
+; GFX1150-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
+; GFX1150-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX1150-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
+; GFX1150-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX1150-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX1150-NEXT: v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f64 v[22:23], v[20:21], v[16:17]
-; GFX1150-NEXT: v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
+; GFX1150-NEXT: v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[22:23]
+; GFX1150-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
-; GFX1150-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB13_13
-; GFX1150-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX1150-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; GFX1150-NEXT: s_cbranch_vccnz .LBB13_17
+; GFX1150-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s2, s2, s3
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s2, s2, 26
; GFX1150-NEXT: .p2align 6
-; GFX1150-NEXT: .LBB13_11: ; %frem.loop_body
+; GFX1150-NEXT: .LBB13_15: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
+; GFX1150-NEXT: v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
; GFX1150-NEXT: s_sub_i32 s2, s2, 26
; GFX1150-NEXT: s_cmp_gt_i32 s2, 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[14:15], v[16:17], v[12:13]
-; GFX1150-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
-; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
-; GFX1150-NEXT: v_add_f64 v[19:20], v[14:15], v[10:11]
+; GFX1150-NEXT: v_mul_f64 v[12:13], v[16:17], v[14:15]
+; GFX1150-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_cndmask_b32 v14, v14, v19
-; GFX1150-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB13_11
-; GFX1150-NEXT: ; %bb.12:
-; GFX1150-NEXT: v_mov_b32_e32 v19, s2
-; GFX1150-NEXT: s_branch .LBB13_14
-; GFX1150-NEXT: .LBB13_13:
-; GFX1150-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
-; GFX1150-NEXT: .LBB13_14: ; %frem.loop_exit
+; GFX1150-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX1150-NEXT: v_add_f64 v[19:20], v[12:13], v[10:11]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_subrev_nc_u32_e32 v14, 25, v19
-; GFX1150-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
+; GFX1150-NEXT: v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
+; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX1150-NEXT: s_cbranch_scc1 .LBB13_15
+; GFX1150-NEXT: ; %bb.16: ; %Flow
+; GFX1150-NEXT: v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
+; GFX1150-NEXT: v_mov_b32_e32 v13, v17
+; GFX1150-NEXT: .LBB13_17: ; %frem.loop_exit
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
+; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
-; GFX1150-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1150-NEXT: v_mul_f64 v[14:15], v[12:13], v[14:15]
+; GFX1150-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
+; GFX1150-NEXT: v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX1150-NEXT: v_add_f64 v[10:11], v[12:13], v[10:11]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -16443,7 +17866,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX1150-NEXT: .LBB13_15:
+; GFX1150-NEXT: .LBB13_18: ; %Flow50
; GFX1150-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1150-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -16467,92 +17890,93 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: global_load_b128 v[0:3], v4, s[2:3]
; GFX1200-NEXT: global_load_b128 v[4:7], v4, s[4:5] offset:64
; GFX1200-NEXT: s_wait_loadcnt 0x0
-; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX1200-NEXT: s_cbranch_vccz .LBB13_5
-; GFX1200-NEXT: ; %bb.1: ; %frem.compute15
+; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
+; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX1200-NEXT: s_cbranch_vccz .LBB13_2
+; GFX1200-NEXT: ; %bb.1: ; %frem.else16
+; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX1200-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; GFX1200-NEXT: s_mov_b32 s2, 0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX1200-NEXT: s_branch .LBB13_3
+; GFX1200-NEXT: .LBB13_2:
+; GFX1200-NEXT: s_mov_b32 s2, -1
+; GFX1200-NEXT: ; implicit-def: $vgpr8_vgpr9
+; GFX1200-NEXT: .LBB13_3: ; %Flow53
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1200-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB13_9
+; GFX1200-NEXT: ; %bb.4: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v11, v[4:5]
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[8:9], 26
+; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[8:9], 26
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
-; GFX1200-NEXT: v_add_nc_u32_e32 v16, -1, v11
-; GFX1200-NEXT: v_readfirstlane_b32 s3, v11
-; GFX1200-NEXT: v_readfirstlane_b32 s2, v10
+; GFX1200-NEXT: v_add_nc_u32_e32 v16, -1, v13
+; GFX1200-NEXT: v_readfirstlane_b32 s3, v13
+; GFX1200-NEXT: v_readfirstlane_b32 s2, v12
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_not_b32_e32 v11, v16
-; GFX1200-NEXT: v_add_nc_u32_e32 v17, v11, v10
+; GFX1200-NEXT: v_not_b32_e32 v13, v16
+; GFX1200-NEXT: v_add_nc_u32_e32 v17, v13, v12
; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[8:9], 1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
-; GFX1200-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
+; GFX1200-NEXT: v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
+; GFX1200-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX1200-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX1200-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX1200-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
; GFX1200-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX1200-NEXT: v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f64_e32 v[20:21], v[18:19], v[14:15]
-; GFX1200-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
+; GFX1200-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
-; GFX1200-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB13_7
-; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX1200-NEXT: s_cbranch_vccnz .LBB13_8
+; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_sub_co_i32 s2, s2, s3
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 26
-; GFX1200-NEXT: .LBB13_3: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB13_6: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
+; GFX1200-NEXT: v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_mul_f64_e32 v[12:13], v[14:15], v[10:11]
-; GFX1200-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1200-NEXT: v_mul_f64_e32 v[10:11], v[14:15], v[12:13]
+; GFX1200-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
-; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
-; GFX1200-NEXT: v_add_f64_e32 v[17:18], v[12:13], v[8:9]
+; GFX1200-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX1200-NEXT: v_add_f64_e32 v[17:18], v[10:11], v[8:9]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v17
-; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB13_3
-; GFX1200-NEXT: ; %bb.4:
-; GFX1200-NEXT: v_mov_b32_e32 v17, s2
-; GFX1200-NEXT: s_branch .LBB13_8
-; GFX1200-NEXT: .LBB13_5: ; %frem.else16
-; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX1200-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX1200-NEXT: s_cbranch_vccnz .LBB13_9
-; GFX1200-NEXT: .LBB13_6: ; %frem.else
-; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX1200-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX1200-NEXT: s_branch .LBB13_15
-; GFX1200-NEXT: .LBB13_7:
-; GFX1200-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
+; GFX1200-NEXT: v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
+; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
+; GFX1200-NEXT: s_cbranch_scc1 .LBB13_6
+; GFX1200-NEXT: ; %bb.7: ; %Flow51
+; GFX1200-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
+; GFX1200-NEXT: v_mov_b32_e32 v11, v15
; GFX1200-NEXT: .LBB13_8: ; %frem.loop_exit24
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
+; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_subrev_nc_u32_e32 v12, 25, v17
-; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_mul_f64_e32 v[10:11], v[12:13], v[10:11]
-; GFX1200-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX1200-NEXT: v_mul_f64_e32 v[12:13], v[10:11], v[12:13]
+; GFX1200-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
+; GFX1200-NEXT: v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX1200-NEXT: v_add_f64_e32 v[8:9], v[10:11], v[8:9]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -16561,79 +17985,99 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX1200-NEXT: s_cbranch_vccz .LBB13_6
-; GFX1200-NEXT: .LBB13_9: ; %frem.compute
+; GFX1200-NEXT: .LBB13_9:
+; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
+; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_cbranch_vccz .LBB13_11
+; GFX1200-NEXT: ; %bb.10: ; %frem.else
+; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX1200-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; GFX1200-NEXT: s_mov_b32 s2, 0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX1200-NEXT: s_branch .LBB13_12
+; GFX1200-NEXT: .LBB13_11:
+; GFX1200-NEXT: s_mov_b32 s2, -1
+; GFX1200-NEXT: ; implicit-def: $vgpr10_vgpr11
+; GFX1200-NEXT: .LBB13_12: ; %Flow49
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB13_18
+; GFX1200-NEXT: ; %bb.13: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v13, v[6:7]
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v12, v[2:3]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_ldexp_f64 v[14:15], v[10:11], 26
+; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[10:11], 26
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
-; GFX1200-NEXT: v_add_nc_u32_e32 v18, -1, v13
-; GFX1200-NEXT: v_readfirstlane_b32 s3, v13
-; GFX1200-NEXT: v_readfirstlane_b32 s2, v12
+; GFX1200-NEXT: v_add_nc_u32_e32 v18, -1, v15
+; GFX1200-NEXT: v_readfirstlane_b32 s3, v15
+; GFX1200-NEXT: v_readfirstlane_b32 s2, v14
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_not_b32_e32 v13, v18
-; GFX1200-NEXT: v_add_nc_u32_e32 v19, v13, v12
+; GFX1200-NEXT: v_not_b32_e32 v15, v18
+; GFX1200-NEXT: v_add_nc_u32_e32 v19, v15, v14
; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], 1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], 1.0
-; GFX1200-NEXT: v_rcp_f64_e32 v[16:17], v[12:13]
+; GFX1200-NEXT: v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
+; GFX1200-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
+; GFX1200-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX1200-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
+; GFX1200-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
; GFX1200-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX1200-NEXT: v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f64_e32 v[22:23], v[20:21], v[16:17]
-; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
+; GFX1200-NEXT: v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[22:23]
+; GFX1200-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
-; GFX1200-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB13_13
-; GFX1200-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX1200-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; GFX1200-NEXT: s_cbranch_vccnz .LBB13_17
+; GFX1200-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s2, s2, s3
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 26
-; GFX1200-NEXT: .LBB13_11: ; %frem.loop_body
+; GFX1200-NEXT: .LBB13_15: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
+; GFX1200-NEXT: v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
-; GFX1200-NEXT: v_mul_f64_e32 v[14:15], v[16:17], v[12:13]
+; GFX1200-NEXT: v_mul_f64_e32 v[12:13], v[16:17], v[14:15]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
-; GFX1200-NEXT: v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
+; GFX1200-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
-; GFX1200-NEXT: v_add_f64_e32 v[19:20], v[14:15], v[10:11]
+; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX1200-NEXT: v_add_f64_e32 v[19:20], v[12:13], v[10:11]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_cndmask_b32 v14, v14, v19
+; GFX1200-NEXT: v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB13_11
-; GFX1200-NEXT: ; %bb.12:
-; GFX1200-NEXT: v_mov_b32_e32 v19, s2
-; GFX1200-NEXT: s_branch .LBB13_14
-; GFX1200-NEXT: .LBB13_13:
-; GFX1200-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
-; GFX1200-NEXT: .LBB13_14: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_subrev_nc_u32_e32 v14, 25, v19
-; GFX1200-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
+; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX1200-NEXT: s_cbranch_scc1 .LBB13_15
+; GFX1200-NEXT: ; %bb.16: ; %Flow
+; GFX1200-NEXT: v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
+; GFX1200-NEXT: v_mov_b32_e32 v13, v17
+; GFX1200-NEXT: .LBB13_17: ; %frem.loop_exit
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
+; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_mul_f64_e32 v[12:13], v[14:15], v[12:13]
-; GFX1200-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1200-NEXT: v_mul_f64_e32 v[14:15], v[12:13], v[14:15]
+; GFX1200-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
+; GFX1200-NEXT: v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX1200-NEXT: v_add_f64_e32 v[10:11], v[12:13], v[10:11]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -16642,7 +18086,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX1200-NEXT: .LBB13_15:
+; GFX1200-NEXT: .LBB13_18: ; %Flow50
; GFX1200-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1200-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -16857,11 +18301,28 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s3, v1
; SI-NEXT: v_readfirstlane_b32 s2, v0
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, 1.0
+; SI-NEXT: v_cmp_ngt_f64_e64 s[6:7], |s[2:3]|, 1.0
; SI-NEXT: v_readfirstlane_b32 s4, v2
; SI-NEXT: v_readfirstlane_b32 s5, v3
-; SI-NEXT: s_cbranch_vccz .LBB15_4
-; SI-NEXT: ; %bb.1: ; %frem.compute15
+; SI-NEXT: s_and_b64 vcc, exec, s[6:7]
+; SI-NEXT: s_cbranch_vccz .LBB15_2
+; SI-NEXT: ; %bb.1: ; %frem.else16
+; SI-NEXT: v_cmp_eq_f64_e64 s[6:7], |s[2:3]|, 1.0
+; SI-NEXT: s_and_b32 s8, s3, 0x80000000
+; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; SI-NEXT: s_cselect_b32 s7, s8, s3
+; SI-NEXT: s_cselect_b32 s6, 0, s2
+; SI-NEXT: s_mov_b64 s[8:9], 0
+; SI-NEXT: s_branch .LBB15_3
+; SI-NEXT: .LBB15_2:
+; SI-NEXT: s_mov_b64 s[8:9], -1
+; SI-NEXT: ; implicit-def: $sgpr6_sgpr7
+; SI-NEXT: .LBB15_3: ; %Flow52
+; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; SI-NEXT: s_cselect_b32 s8, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s8, 1
+; SI-NEXT: s_cbranch_scc1 .LBB15_9
+; SI-NEXT: ; %bb.4: ; %frem.compute15
; SI-NEXT: s_and_b32 s6, s3, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
; SI-NEXT: s_cmp_lt_i32 s6, 0x7ff00000
@@ -16873,18 +18334,18 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[2:3]
; SI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
; SI-NEXT: v_readfirstlane_b32 s6, v2
-; SI-NEXT: s_cselect_b32 s6, s6, 0
-; SI-NEXT: s_add_i32 s9, s6, -1
+; SI-NEXT: s_cselect_b32 s7, s6, 0
+; SI-NEXT: s_add_i32 s9, s7, -1
; SI-NEXT: s_brev_b32 s8, -2
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_cmp_lt_i32 s9, 27
-; SI-NEXT: s_cbranch_scc1 .LBB15_6
-; SI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
-; SI-NEXT: s_add_i32 s9, s6, 25
+; SI-NEXT: s_cbranch_scc1 .LBB15_8
+; SI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; SI-NEXT: s_add_i32 s9, s7, 25
; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
; SI-NEXT: v_mov_b32_e32 v0, 0
-; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: .LBB15_3: ; %frem.loop_body23
+; SI-NEXT: .LBB15_6: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v3, v5
; SI-NEXT: v_mov_b32_e32 v2, v4
@@ -16902,40 +18363,21 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; SI-NEXT: s_cbranch_scc1 .LBB15_3
-; SI-NEXT: s_branch .LBB15_7
-; SI-NEXT: .LBB15_4: ; %frem.else16
-; SI-NEXT: v_cmp_eq_f64_e64 s[6:7], |s[2:3]|, 1.0
-; SI-NEXT: s_and_b32 s8, s3, 0x80000000
-; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
-; SI-NEXT: s_cselect_b32 s7, s8, s3
-; SI-NEXT: s_cselect_b32 s6, 0, s2
-; SI-NEXT: v_mov_b32_e32 v0, s6
-; SI-NEXT: v_mov_b32_e32 v1, s7
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[4:5]|, 1.0
-; SI-NEXT: s_cbranch_vccnz .LBB15_8
-; SI-NEXT: .LBB15_5: ; %frem.else
-; SI-NEXT: v_cmp_eq_f64_e64 s[6:7], |s[4:5]|, 1.0
-; SI-NEXT: s_and_b32 s8, s5, 0x80000000
-; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
-; SI-NEXT: s_cselect_b32 s7, s8, s5
-; SI-NEXT: s_cselect_b32 s6, 0, s4
-; SI-NEXT: v_mov_b32_e32 v2, s6
-; SI-NEXT: v_mov_b32_e32 v3, s7
-; SI-NEXT: s_branch .LBB15_13
-; SI-NEXT: .LBB15_6:
-; SI-NEXT: v_mov_b32_e32 v2, v4
-; SI-NEXT: v_mov_b32_e32 v3, v5
-; SI-NEXT: .LBB15_7: ; %frem.loop_exit24
+; SI-NEXT: s_cbranch_scc1 .LBB15_6
+; SI-NEXT: ; %bb.7: ; %Flow50
+; SI-NEXT: v_mov_b32_e32 v5, v3
+; SI-NEXT: v_mov_b32_e32 v4, v2
+; SI-NEXT: .LBB15_8: ; %frem.loop_exit24
; SI-NEXT: s_sub_i32 s6, s9, 25
-; SI-NEXT: v_ldexp_f64 v[0:1], v[2:3], s6
-; SI-NEXT: v_mov_b32_e32 v2, 0x43300000
-; SI-NEXT: v_bfi_b32 v3, s8, v2, v1
-; SI-NEXT: v_mov_b32_e32 v2, 0
-; SI-NEXT: v_add_f64 v[4:5], v[0:1], v[2:3]
+; SI-NEXT: v_ldexp_f64 v[0:1], v[4:5], s6
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s7, 0x432fffff
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[6:7]
+; SI-NEXT: s_brev_b32 s6, -2
+; SI-NEXT: v_mov_b32_e32 v2, 0x43300000
+; SI-NEXT: v_bfi_b32 v3, s6, v2, v1
+; SI-NEXT: v_mov_b32_e32 v2, 0
+; SI-NEXT: v_add_f64 v[4:5], v[0:1], v[2:3]
; SI-NEXT: v_add_f64 v[2:3], v[4:5], -v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
@@ -16945,10 +18387,32 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; SI-NEXT: v_mov_b32_e32 v2, s3
-; SI-NEXT: v_bfi_b32 v1, s8, v1, v2
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[4:5]|, 1.0
-; SI-NEXT: s_cbranch_vccz .LBB15_5
-; SI-NEXT: .LBB15_8: ; %frem.compute
+; SI-NEXT: v_bfi_b32 v1, s6, v1, v2
+; SI-NEXT: s_branch .LBB15_10
+; SI-NEXT: .LBB15_9:
+; SI-NEXT: v_mov_b32_e32 v0, s6
+; SI-NEXT: v_mov_b32_e32 v1, s7
+; SI-NEXT: .LBB15_10:
+; SI-NEXT: v_cmp_ngt_f64_e64 s[6:7], |s[4:5]|, 1.0
+; SI-NEXT: s_and_b64 vcc, exec, s[6:7]
+; SI-NEXT: s_cbranch_vccz .LBB15_12
+; SI-NEXT: ; %bb.11: ; %frem.else
+; SI-NEXT: v_cmp_eq_f64_e64 s[6:7], |s[4:5]|, 1.0
+; SI-NEXT: s_and_b32 s8, s5, 0x80000000
+; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; SI-NEXT: s_cselect_b32 s7, s8, s5
+; SI-NEXT: s_cselect_b32 s6, 0, s4
+; SI-NEXT: s_mov_b64 s[8:9], 0
+; SI-NEXT: s_branch .LBB15_13
+; SI-NEXT: .LBB15_12:
+; SI-NEXT: s_mov_b64 s[8:9], -1
+; SI-NEXT: ; implicit-def: $sgpr6_sgpr7
+; SI-NEXT: .LBB15_13: ; %Flow48
+; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; SI-NEXT: s_cselect_b32 s8, 1, 0
+; SI-NEXT: s_cmp_lg_u32 s8, 1
+; SI-NEXT: s_cbranch_scc1 .LBB15_19
+; SI-NEXT: ; %bb.14: ; %frem.compute
; SI-NEXT: s_and_b32 s6, s5, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[4:5]|
; SI-NEXT: s_cmp_lt_i32 s6, 0x7ff00000
@@ -16965,13 +18429,13 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: s_brev_b32 s8, -2
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_cmp_lt_i32 s9, 27
-; SI-NEXT: s_cbranch_scc1 .LBB15_11
-; SI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB15_18
+; SI-NEXT: ; %bb.15: ; %frem.loop_body.preheader
; SI-NEXT: s_add_i32 s9, s7, 25
; SI-NEXT: v_mov_b32_e32 v8, 0x43300000
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: .LBB15_10: ; %frem.loop_body
+; SI-NEXT: .LBB15_16: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v5, v7
; SI-NEXT: v_mov_b32_e32 v4, v6
@@ -16989,20 +18453,21 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; SI-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
; SI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; SI-NEXT: s_cbranch_scc1 .LBB15_10
-; SI-NEXT: s_branch .LBB15_12
-; SI-NEXT: .LBB15_11:
-; SI-NEXT: v_mov_b32_e32 v4, v6
-; SI-NEXT: v_mov_b32_e32 v5, v7
-; SI-NEXT: .LBB15_12: ; %frem.loop_exit
-; SI-NEXT: s_sub_i32 s7, s9, 25
-; SI-NEXT: v_ldexp_f64 v[2:3], v[4:5], s7
+; SI-NEXT: s_cbranch_scc1 .LBB15_16
+; SI-NEXT: ; %bb.17: ; %Flow
+; SI-NEXT: v_mov_b32_e32 v7, v5
+; SI-NEXT: v_mov_b32_e32 v6, v4
+; SI-NEXT: .LBB15_18: ; %frem.loop_exit
+; SI-NEXT: s_sub_i32 s6, s9, 25
+; SI-NEXT: v_ldexp_f64 v[2:3], v[6:7], s6
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s7, 0x432fffff
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
+; SI-NEXT: s_brev_b32 s6, -2
; SI-NEXT: v_mov_b32_e32 v4, 0x43300000
-; SI-NEXT: v_bfi_b32 v5, s8, v4, v3
+; SI-NEXT: v_bfi_b32 v5, s6, v4, v3
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: v_add_f64 v[6:7], v[2:3], v[4:5]
-; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
; SI-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
@@ -17012,8 +18477,12 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; SI-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; SI-NEXT: v_mov_b32_e32 v4, s5
-; SI-NEXT: v_bfi_b32 v3, s8, v3, v4
-; SI-NEXT: .LBB15_13:
+; SI-NEXT: v_bfi_b32 v3, s6, v3, v4
+; SI-NEXT: s_branch .LBB15_20
+; SI-NEXT: .LBB15_19:
+; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v3, s7
+; SI-NEXT: .LBB15_20: ; %Flow49
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
; SI-NEXT: v_cmp_nge_f64_e64 vcc, |s[2:3]|, v[4:5]
@@ -17038,49 +18507,51 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: s_mov_b32 s5, s3
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, 1.0
-; CI-NEXT: s_cbranch_vccz .LBB15_4
-; CI-NEXT: ; %bb.1: ; %frem.compute15
-; CI-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[0:1]|
-; CI-NEXT: v_frexp_exp_i32_f64_e32 v4, v[0:1]
-; CI-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
-; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v4
+; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, 1.0
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB15_2
+; CI-NEXT: ; %bb.1: ; %frem.else16
+; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
+; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
+; CI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
+; CI-NEXT: s_branch .LBB15_3
+; CI-NEXT: .LBB15_2:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr4_vgpr5
+; CI-NEXT: .LBB15_3: ; %Flow52
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB15_9
+; CI-NEXT: ; %bb.4: ; %frem.compute15
+; CI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; CI-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
+; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v6
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v8
-; CI-NEXT: s_cbranch_vccnz .LBB15_6
-; CI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
-; CI-NEXT: v_add_i32_e32 v8, vcc, 25, v4
-; CI-NEXT: .LBB15_3: ; %frem.loop_body23
+; CI-NEXT: s_cbranch_vccnz .LBB15_8
+; CI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; CI-NEXT: v_add_i32_e32 v8, vcc, 25, v6
+; CI-NEXT: .LBB15_6: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v4, v6
-; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; CI-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
-; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
-; CI-NEXT: v_add_f64 v[9:10], v[6:7], 1.0
-; CI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
-; CI-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
-; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; CI-NEXT: v_mov_b32_e32 v7, v5
+; CI-NEXT: v_mov_b32_e32 v6, v4
+; CI-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
+; CI-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
+; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
+; CI-NEXT: v_add_f64 v[9:10], v[4:5], 1.0
+; CI-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
+; CI-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
+; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; CI-NEXT: v_subrev_i32_e32 v8, vcc, 26, v8
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v8
-; CI-NEXT: s_cbranch_vccnz .LBB15_3
-; CI-NEXT: s_branch .LBB15_7
-; CI-NEXT: .LBB15_4: ; %frem.else16
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
-; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; CI-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc
-; CI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB15_8
-; CI-NEXT: .LBB15_5: ; %frem.else
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
-; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v3
-; CI-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc
-; CI-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc
-; CI-NEXT: s_branch .LBB15_13
-; CI-NEXT: .LBB15_6:
+; CI-NEXT: s_cbranch_vccnz .LBB15_6
+; CI-NEXT: ; %bb.7: ; %Flow50
; CI-NEXT: v_mov_b32_e32 v4, v6
; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: .LBB15_7: ; %frem.loop_exit24
+; CI-NEXT: .LBB15_8: ; %frem.loop_exit24
; CI-NEXT: v_subrev_i32_e32 v6, vcc, 25, v8
; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; CI-NEXT: s_brev_b32 s2, -2
@@ -17088,26 +18559,43 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; CI-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; CI-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc
-; CI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
-; CI-NEXT: v_bfi_b32 v9, s2, v4, v1
-; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
-; CI-NEXT: s_cbranch_vccz .LBB15_5
-; CI-NEXT: .LBB15_8: ; %frem.compute
-; CI-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[2:3]|
-; CI-NEXT: v_frexp_exp_i32_f64_e32 v4, v[2:3]
-; CI-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
-; CI-NEXT: v_add_i32_e32 v10, vcc, -1, v4
+; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; CI-NEXT: v_bfi_b32 v5, s2, v5, v1
+; CI-NEXT: .LBB15_9:
+; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, 1.0
+; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT: s_cbranch_vccz .LBB15_11
+; CI-NEXT: ; %bb.10: ; %frem.else
+; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
+; CI-NEXT: v_and_b32_e32 v6, 0x80000000, v3
+; CI-NEXT: s_mov_b64 s[2:3], 0
+; CI-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc
+; CI-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc
+; CI-NEXT: s_branch .LBB15_12
+; CI-NEXT: .LBB15_11:
+; CI-NEXT: s_mov_b64 s[2:3], -1
+; CI-NEXT: ; implicit-def: $vgpr6_vgpr7
+; CI-NEXT: .LBB15_12: ; %Flow48
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cselect_b32 s2, 1, 0
+; CI-NEXT: s_cmp_lg_u32 s2, 1
+; CI-NEXT: s_cbranch_scc1 .LBB15_18
+; CI-NEXT: ; %bb.13: ; %frem.compute
+; CI-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
+; CI-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
+; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; CI-NEXT: v_add_i32_e32 v10, vcc, -1, v8
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v10
-; CI-NEXT: s_cbranch_vccnz .LBB15_11
-; CI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v10, vcc, 25, v4
-; CI-NEXT: .LBB15_10: ; %frem.loop_body
+; CI-NEXT: s_cbranch_vccnz .LBB15_17
+; CI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; CI-NEXT: v_add_i32_e32 v10, vcc, 25, v8
+; CI-NEXT: .LBB15_15: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v4, v6
-; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; CI-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; CI-NEXT: v_mov_b32_e32 v9, v7
+; CI-NEXT: v_mov_b32_e32 v8, v6
+; CI-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
+; CI-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; CI-NEXT: v_add_f64 v[11:12], v[6:7], 1.0
; CI-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
@@ -17115,34 +18603,33 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; CI-NEXT: v_subrev_i32_e32 v10, vcc, 26, v10
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v10
-; CI-NEXT: s_cbranch_vccnz .LBB15_10
-; CI-NEXT: s_branch .LBB15_12
-; CI-NEXT: .LBB15_11:
-; CI-NEXT: v_mov_b32_e32 v4, v6
-; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: .LBB15_12: ; %frem.loop_exit
-; CI-NEXT: v_subrev_i32_e32 v6, vcc, 25, v10
-; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; CI-NEXT: s_cbranch_vccnz .LBB15_15
+; CI-NEXT: ; %bb.16: ; %Flow
+; CI-NEXT: v_mov_b32_e32 v6, v8
+; CI-NEXT: v_mov_b32_e32 v7, v9
+; CI-NEXT: .LBB15_17: ; %frem.loop_exit
+; CI-NEXT: v_subrev_i32_e32 v8, vcc, 25, v10
+; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; CI-NEXT: s_brev_b32 s2, -2
-; CI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; CI-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
-; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; CI-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CI-NEXT: v_bfi_b32 v5, s2, v5, v3
-; CI-NEXT: .LBB15_13:
+; CI-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
+; CI-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
+; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; CI-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
+; CI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; CI-NEXT: v_bfi_b32 v7, s2, v7, v3
+; CI-NEXT: .LBB15_18: ; %Flow49
; CI-NEXT: s_mov_b32 s4, 0
; CI-NEXT: s_mov_b32 s5, 0x7ff00000
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[4:5]
-; CI-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; CI-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, -1
-; CI-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; CI-NEXT: v_cndmask_b32_e32 v1, v8, v5, vcc
+; CI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[4:5]
-; CI-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc
-; CI-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; CI-NEXT: v_cndmask_b32_e32 v3, v8, v7, vcc
+; CI-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; CI-NEXT: s_endpgm
;
@@ -17154,49 +18641,51 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, 1.0
-; VI-NEXT: s_cbranch_vccz .LBB15_4
-; VI-NEXT: ; %bb.1: ; %frem.compute15
-; VI-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[0:1]|
-; VI-NEXT: v_frexp_exp_i32_f64_e32 v4, v[0:1]
-; VI-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
-; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v4
+; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, 1.0
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB15_2
+; VI-NEXT: ; %bb.1: ; %frem.else16
+; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
+; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
+; VI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
+; VI-NEXT: s_branch .LBB15_3
+; VI-NEXT: .LBB15_2:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr4_vgpr5
+; VI-NEXT: .LBB15_3: ; %Flow52
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB15_9
+; VI-NEXT: ; %bb.4: ; %frem.compute15
+; VI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; VI-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
+; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v6
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v8
-; VI-NEXT: s_cbranch_vccnz .LBB15_6
-; VI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
-; VI-NEXT: v_add_u32_e32 v8, vcc, 25, v4
-; VI-NEXT: .LBB15_3: ; %frem.loop_body23
+; VI-NEXT: s_cbranch_vccnz .LBB15_8
+; VI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; VI-NEXT: v_add_u32_e32 v8, vcc, 25, v6
+; VI-NEXT: .LBB15_6: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v4, v6
-; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; VI-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
-; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
-; VI-NEXT: v_add_f64 v[9:10], v[6:7], 1.0
-; VI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
-; VI-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
-; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; VI-NEXT: v_mov_b32_e32 v7, v5
+; VI-NEXT: v_mov_b32_e32 v6, v4
+; VI-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
+; VI-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
+; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
+; VI-NEXT: v_add_f64 v[9:10], v[4:5], 1.0
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
+; VI-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
+; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; VI-NEXT: v_subrev_u32_e32 v8, vcc, 26, v8
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v8
-; VI-NEXT: s_cbranch_vccnz .LBB15_3
-; VI-NEXT: s_branch .LBB15_7
-; VI-NEXT: .LBB15_4: ; %frem.else16
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
-; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; VI-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc
-; VI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB15_8
-; VI-NEXT: .LBB15_5: ; %frem.else
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
-; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v3
-; VI-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc
-; VI-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc
-; VI-NEXT: s_branch .LBB15_13
-; VI-NEXT: .LBB15_6:
+; VI-NEXT: s_cbranch_vccnz .LBB15_6
+; VI-NEXT: ; %bb.7: ; %Flow50
; VI-NEXT: v_mov_b32_e32 v4, v6
; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: .LBB15_7: ; %frem.loop_exit24
+; VI-NEXT: .LBB15_8: ; %frem.loop_exit24
; VI-NEXT: v_subrev_u32_e32 v6, vcc, 25, v8
; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; VI-NEXT: s_brev_b32 s2, -2
@@ -17204,62 +18693,78 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; VI-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; VI-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; VI-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc
-; VI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
-; VI-NEXT: v_bfi_b32 v9, s2, v4, v1
-; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
-; VI-NEXT: s_cbranch_vccz .LBB15_5
-; VI-NEXT: .LBB15_8: ; %frem.compute
-; VI-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[2:3]|
-; VI-NEXT: v_frexp_exp_i32_f64_e32 v4, v[2:3]
-; VI-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
-; VI-NEXT: v_add_u32_e32 v10, vcc, -1, v4
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; VI-NEXT: v_bfi_b32 v5, s2, v5, v1
+; VI-NEXT: .LBB15_9:
+; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, 1.0
+; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT: s_cbranch_vccz .LBB15_11
+; VI-NEXT: ; %bb.10: ; %frem.else
+; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
+; VI-NEXT: v_and_b32_e32 v6, 0x80000000, v3
+; VI-NEXT: s_mov_b64 s[2:3], 0
+; VI-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc
+; VI-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc
+; VI-NEXT: s_branch .LBB15_12
+; VI-NEXT: .LBB15_11:
+; VI-NEXT: s_mov_b64 s[2:3], -1
+; VI-NEXT: ; implicit-def: $vgpr6_vgpr7
+; VI-NEXT: .LBB15_12: ; %Flow48
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cselect_b32 s2, 1, 0
+; VI-NEXT: s_cmp_lg_u32 s2, 1
+; VI-NEXT: s_cbranch_scc1 .LBB15_18
+; VI-NEXT: ; %bb.13: ; %frem.compute
+; VI-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
+; VI-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
+; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; VI-NEXT: v_add_u32_e32 v10, vcc, -1, v8
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v10
-; VI-NEXT: s_cbranch_vccnz .LBB15_11
-; VI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v10, vcc, 25, v4
-; VI-NEXT: .LBB15_10: ; %frem.loop_body
+; VI-NEXT: s_cbranch_vccnz .LBB15_17
+; VI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; VI-NEXT: v_add_u32_e32 v10, vcc, 25, v8
+; VI-NEXT: .LBB15_15: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v4, v6
-; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; VI-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; VI-NEXT: v_mov_b32_e32 v9, v7
+; VI-NEXT: v_mov_b32_e32 v8, v6
+; VI-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
+; VI-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; VI-NEXT: v_add_f64 v[11:12], v[6:7], 1.0
; VI-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
; VI-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc
; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; VI-NEXT: v_subrev_u32_e32 v10, vcc, 26, v10
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v10
-; VI-NEXT: s_cbranch_vccnz .LBB15_10
-; VI-NEXT: s_branch .LBB15_12
-; VI-NEXT: .LBB15_11:
-; VI-NEXT: v_mov_b32_e32 v4, v6
-; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: .LBB15_12: ; %frem.loop_exit
-; VI-NEXT: v_subrev_u32_e32 v6, vcc, 25, v10
-; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; VI-NEXT: v_subrev_u32_e32 v10, vcc, 26, v10
+; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v10
+; VI-NEXT: s_cbranch_vccnz .LBB15_15
+; VI-NEXT: ; %bb.16: ; %Flow
+; VI-NEXT: v_mov_b32_e32 v6, v8
+; VI-NEXT: v_mov_b32_e32 v7, v9
+; VI-NEXT: .LBB15_17: ; %frem.loop_exit
+; VI-NEXT: v_subrev_u32_e32 v8, vcc, 25, v10
+; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; VI-NEXT: s_brev_b32 s2, -2
-; VI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; VI-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
-; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; VI-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; VI-NEXT: v_bfi_b32 v5, s2, v5, v3
-; VI-NEXT: .LBB15_13:
+; VI-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
+; VI-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
+; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; VI-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
+; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; VI-NEXT: v_bfi_b32 v7, s2, v7, v3
+; VI-NEXT: .LBB15_18: ; %Flow49
; VI-NEXT: s_mov_b32 s2, 0
; VI-NEXT: s_mov_b32 s3, 0x7ff00000
; VI-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[2:3]
-; VI-NEXT: v_mov_b32_e32 v10, 0x7ff80000
-; VI-NEXT: v_mov_b32_e32 v6, s0
-; VI-NEXT: v_mov_b32_e32 v7, s1
-; VI-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; VI-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; VI-NEXT: v_cndmask_b32_e32 v1, v8, v5, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; VI-NEXT: v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[2:3]
-; VI-NEXT: v_cndmask_b32_e32 v3, v10, v5, vcc
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; VI-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; VI-NEXT: v_mov_b32_e32 v4, s0
+; VI-NEXT: v_mov_b32_e32 v5, s1
+; VI-NEXT: v_cndmask_b32_e32 v3, v8, v7, vcc
+; VI-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: frem_v2f64_const_one_denum:
@@ -17269,49 +18774,51 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, 1.0
-; GFX9-NEXT: s_cbranch_vccz .LBB15_4
-; GFX9-NEXT: ; %bb.1: ; %frem.compute15
-; GFX9-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[0:1]|
-; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v4, v[0:1]
-; GFX9-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
-; GFX9-NEXT: v_add_u32_e32 v8, -1, v4
+; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, 1.0
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB15_2
+; GFX9-NEXT: ; %bb.1: ; %frem.else16
+; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
+; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
+; GFX9-NEXT: s_branch .LBB15_3
+; GFX9-NEXT: .LBB15_2:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX9-NEXT: .LBB15_3: ; %Flow52
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB15_9
+; GFX9-NEXT: ; %bb.4: ; %frem.compute15
+; GFX9-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
+; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; GFX9-NEXT: v_add_u32_e32 v8, -1, v6
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v8
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_6
-; GFX9-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
-; GFX9-NEXT: v_add_u32_e32 v8, 25, v4
-; GFX9-NEXT: .LBB15_3: ; %frem.loop_body23
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_8
+; GFX9-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX9-NEXT: v_add_u32_e32 v8, 25, v6
+; GFX9-NEXT: .LBB15_6: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v4, v6
-; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v7, v5
+; GFX9-NEXT: v_mov_b32_e32 v6, v4
+; GFX9-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
; GFX9-NEXT: v_subrev_u32_e32 v8, 26, v8
-; GFX9-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
-; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
-; GFX9-NEXT: v_add_f64 v[9:10], v[6:7], 1.0
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
-; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX9-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
+; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT: v_add_f64 v[9:10], v[4:5], 1.0
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
+; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v8
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_3
-; GFX9-NEXT: s_branch .LBB15_7
-; GFX9-NEXT: .LBB15_4: ; %frem.else16
-; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
-; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_8
-; GFX9-NEXT: .LBB15_5: ; %frem.else
-; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
-; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc
-; GFX9-NEXT: s_branch .LBB15_13
-; GFX9-NEXT: .LBB15_6:
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_6
+; GFX9-NEXT: ; %bb.7: ; %Flow50
; GFX9-NEXT: v_mov_b32_e32 v4, v6
; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: .LBB15_7: ; %frem.loop_exit24
+; GFX9-NEXT: .LBB15_8: ; %frem.loop_exit24
; GFX9-NEXT: v_subrev_u32_e32 v6, 25, v8
; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX9-NEXT: s_brev_b32 s2, -2
@@ -17319,61 +18826,77 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
-; GFX9-NEXT: v_bfi_b32 v9, s2, v4, v1
-; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
-; GFX9-NEXT: s_cbranch_vccz .LBB15_5
-; GFX9-NEXT: .LBB15_8: ; %frem.compute
-; GFX9-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[2:3]|
-; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v4, v[2:3]
-; GFX9-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
-; GFX9-NEXT: v_add_u32_e32 v10, -1, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v1
+; GFX9-NEXT: .LBB15_9:
+; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, 1.0
+; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT: s_cbranch_vccz .LBB15_11
+; GFX9-NEXT: ; %bb.10: ; %frem.else
+; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
+; GFX9-NEXT: v_and_b32_e32 v6, 0x80000000, v3
+; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc
+; GFX9-NEXT: s_branch .LBB15_12
+; GFX9-NEXT: .LBB15_11:
+; GFX9-NEXT: s_mov_b64 s[2:3], -1
+; GFX9-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX9-NEXT: .LBB15_12: ; %Flow48
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 1
+; GFX9-NEXT: s_cbranch_scc1 .LBB15_18
+; GFX9-NEXT: ; %bb.13: ; %frem.compute
+; GFX9-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
+; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
+; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX9-NEXT: v_add_u32_e32 v10, -1, v8
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v10
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_11
-; GFX9-NEXT: ; %bb.9: ; %frem.loop_body.preheader
-; GFX9-NEXT: v_add_u32_e32 v10, 25, v4
-; GFX9-NEXT: .LBB15_10: ; %frem.loop_body
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_17
+; GFX9-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_add_u32_e32 v10, 25, v8
+; GFX9-NEXT: .LBB15_15: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v4, v6
-; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v9, v7
+; GFX9-NEXT: v_mov_b32_e32 v8, v6
+; GFX9-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
; GFX9-NEXT: v_subrev_u32_e32 v10, 26, v10
-; GFX9-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; GFX9-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; GFX9-NEXT: v_add_f64 v[11:12], v[6:7], 1.0
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc
; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v10
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_10
-; GFX9-NEXT: s_branch .LBB15_12
-; GFX9-NEXT: .LBB15_11:
-; GFX9-NEXT: v_mov_b32_e32 v4, v6
-; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: .LBB15_12: ; %frem.loop_exit
-; GFX9-NEXT: v_subrev_u32_e32 v6, 25, v10
-; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_15
+; GFX9-NEXT: ; %bb.16: ; %Flow
+; GFX9-NEXT: v_mov_b32_e32 v6, v8
+; GFX9-NEXT: v_mov_b32_e32 v7, v9
+; GFX9-NEXT: .LBB15_17: ; %frem.loop_exit
+; GFX9-NEXT: v_subrev_u32_e32 v8, 25, v10
+; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; GFX9-NEXT: s_brev_b32 s2, -2
-; GFX9-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
-; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; GFX9-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v3
-; GFX9-NEXT: .LBB15_13:
+; GFX9-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
+; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
+; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; GFX9-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GFX9-NEXT: v_bfi_b32 v7, s2, v7, v3
+; GFX9-NEXT: .LBB15_18: ; %Flow49
; GFX9-NEXT: s_mov_b32 s2, 0
; GFX9-NEXT: s_mov_b32 s3, 0x7ff00000
; GFX9-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000
-; GFX9-NEXT: v_mov_b32_e32 v7, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX9-NEXT: v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[2:3]
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
-; GFX9-NEXT: global_store_dwordx4 v7, v[0:3], s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: frem_v2f64_const_one_denum:
@@ -17383,49 +18906,50 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX10-NEXT: s_cbranch_vccz .LBB15_5
-; GFX10-NEXT: ; %bb.1: ; %frem.compute15
+; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, 1.0
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB15_2
+; GFX10-NEXT: ; %bb.1: ; %frem.else16
+; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX10-NEXT: s_branch .LBB15_3
+; GFX10-NEXT: .LBB15_2:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX10-NEXT: .LBB15_3: ; %Flow52
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB15_9
+; GFX10-NEXT: ; %bb.4: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; GFX10-NEXT: v_readfirstlane_b32 s2, v6
+; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX10-NEXT: v_add_nc_u32_e32 v8, -1, v6
-; GFX10-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX10-NEXT: v_readfirstlane_b32 s2, v6
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
-; GFX10-NEXT: s_cbranch_vccnz .LBB15_7
-; GFX10-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB15_8
+; GFX10-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_add_i32 s2, s2, 25
-; GFX10-NEXT: .LBB15_3: ; %frem.loop_body23
+; GFX10-NEXT: .LBB15_6: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v4, v6
-; GFX10-NEXT: v_mov_b32_e32 v5, v7
+; GFX10-NEXT: v_mov_b32_e32 v7, v5
+; GFX10-NEXT: v_mov_b32_e32 v6, v4
; GFX10-NEXT: s_sub_i32 s2, s2, 26
; GFX10-NEXT: s_cmp_gt_i32 s2, 26
-; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX10-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
-; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX10-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
-; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB15_3
-; GFX10-NEXT: ; %bb.4:
+; GFX10-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
+; GFX10-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
+; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
+; GFX10-NEXT: v_add_f64 v[8:9], v[4:5], 1.0
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; GFX10-NEXT: s_cbranch_scc1 .LBB15_6
+; GFX10-NEXT: ; %bb.7: ; %Flow50
; GFX10-NEXT: v_mov_b32_e32 v8, s2
-; GFX10-NEXT: s_branch .LBB15_8
-; GFX10-NEXT: .LBB15_5: ; %frem.else16
-; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB15_9
-; GFX10-NEXT: .LBB15_6: ; %frem.else
-; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc_lo
-; GFX10-NEXT: s_branch .LBB15_15
-; GFX10-NEXT: .LBB15_7:
; GFX10-NEXT: v_mov_b32_e32 v4, v6
; GFX10-NEXT: v_mov_b32_e32 v5, v7
; GFX10-NEXT: .LBB15_8: ; %frem.loop_exit24
@@ -17435,60 +18959,75 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX10-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX10-NEXT: v_bfi_b32 v9, 0x7fffffff, v4, v1
-; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX10-NEXT: s_cbranch_vccz .LBB15_6
-; GFX10-NEXT: .LBB15_9: ; %frem.compute
-; GFX10-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v6, v[2:3]
-; GFX10-NEXT: v_readfirstlane_b32 s2, v6
-; GFX10-NEXT: v_add_nc_u32_e32 v10, -1, v6
-; GFX10-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
+; GFX10-NEXT: .LBB15_9:
+; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
+; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT: s_cbranch_vccz .LBB15_11
+; GFX10-NEXT: ; %bb.10: ; %frem.else
+; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX10-NEXT: v_and_b32_e32 v6, 0x80000000, v3
+; GFX10-NEXT: s_mov_b32 s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
+; GFX10-NEXT: s_branch .LBB15_12
+; GFX10-NEXT: .LBB15_11:
+; GFX10-NEXT: s_mov_b32 s2, -1
+; GFX10-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX10-NEXT: .LBB15_12: ; %Flow48
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 1
+; GFX10-NEXT: s_cbranch_scc1 .LBB15_18
+; GFX10-NEXT: ; %bb.13: ; %frem.compute
+; GFX10-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
+; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX10-NEXT: v_add_nc_u32_e32 v10, -1, v8
+; GFX10-NEXT: v_readfirstlane_b32 s2, v8
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX10-NEXT: s_cbranch_vccnz .LBB15_13
-; GFX10-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB15_17
+; GFX10-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX10-NEXT: s_add_i32 s2, s2, 25
-; GFX10-NEXT: .LBB15_11: ; %frem.loop_body
+; GFX10-NEXT: .LBB15_15: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v4, v6
-; GFX10-NEXT: v_mov_b32_e32 v5, v7
+; GFX10-NEXT: v_mov_b32_e32 v9, v7
+; GFX10-NEXT: v_mov_b32_e32 v8, v6
; GFX10-NEXT: s_sub_i32 s2, s2, 26
; GFX10-NEXT: s_cmp_gt_i32 s2, 26
-; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX10-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
+; GFX10-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX10-NEXT: v_add_f64 v[10:11], v[6:7], 1.0
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB15_11
-; GFX10-NEXT: ; %bb.12:
+; GFX10-NEXT: s_cbranch_scc1 .LBB15_15
+; GFX10-NEXT: ; %bb.16: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v10, s2
-; GFX10-NEXT: s_branch .LBB15_14
-; GFX10-NEXT: .LBB15_13:
-; GFX10-NEXT: v_mov_b32_e32 v4, v6
-; GFX10-NEXT: v_mov_b32_e32 v5, v7
-; GFX10-NEXT: .LBB15_14: ; %frem.loop_exit
-; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 25, v10
-; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
-; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX10-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
-; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
-; GFX10-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v3
-; GFX10-NEXT: .LBB15_15:
+; GFX10-NEXT: v_mov_b32_e32 v6, v8
+; GFX10-NEXT: v_mov_b32_e32 v7, v9
+; GFX10-NEXT: .LBB15_17: ; %frem.loop_exit
+; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
+; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; GFX10-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
+; GFX10-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
+; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX10-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
+; GFX10-NEXT: .LBB15_18: ; %Flow49
; GFX10-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
-; GFX10-NEXT: v_mov_b32_e32 v6, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX10-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
-; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7ff80000, v5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
-; GFX10-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7ff80000, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc_lo
+; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: frem_v2f64_const_one_denum:
@@ -17498,59 +19037,59 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX11-NEXT: s_cbranch_vccz .LBB15_5
-; GFX11-NEXT: ; %bb.1: ; %frem.compute15
+; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, 1.0
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB15_2
+; GFX11-NEXT: ; %bb.1: ; %frem.else16
+; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX11-NEXT: s_branch .LBB15_3
+; GFX11-NEXT: .LBB15_2:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT: .LBB15_3: ; %Flow52
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB15_9
+; GFX11-NEXT: ; %bb.4: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_readfirstlane_b32 s2, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX11-NEXT: v_add_nc_u32_e32 v8, -1, v6
-; GFX11-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX11-NEXT: v_readfirstlane_b32 s2, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
-; GFX11-NEXT: s_cbranch_vccnz .LBB15_7
-; GFX11-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB15_8
+; GFX11-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_add_i32 s2, s2, 25
-; GFX11-NEXT: .LBB15_3: ; %frem.loop_body23
+; GFX11-NEXT: .LBB15_6: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX11-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX11-NEXT: s_sub_i32 s2, s2, 26
; GFX11-NEXT: s_cmp_gt_i32 s2, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX11-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; GFX11-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
+; GFX11-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX11-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
-; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
+; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT: v_add_f64 v[8:9], v[4:5], 1.0
+; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB15_3
-; GFX11-NEXT: ; %bb.4:
-; GFX11-NEXT: v_mov_b32_e32 v8, s2
-; GFX11-NEXT: s_branch .LBB15_8
-; GFX11-NEXT: .LBB15_5: ; %frem.else16
-; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB15_9
-; GFX11-NEXT: .LBB15_6: ; %frem.else
-; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc_lo
-; GFX11-NEXT: s_branch .LBB15_15
-; GFX11-NEXT: .LBB15_7:
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; GFX11-NEXT: s_cbranch_scc1 .LBB15_6
+; GFX11-NEXT: ; %bb.7: ; %Flow50
+; GFX11-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
+; GFX11-NEXT: v_mov_b32_e32 v4, v6
; GFX11-NEXT: .LBB15_8: ; %frem.loop_exit24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17559,67 +19098,82 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX11-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11-NEXT: v_bfi_b32 v9, 0x7fffffff, v4, v1
-; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX11-NEXT: s_cbranch_vccz .LBB15_6
-; GFX11-NEXT: .LBB15_9: ; %frem.compute
-; GFX11-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v6, v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_readfirstlane_b32 s2, v6
-; GFX11-NEXT: v_add_nc_u32_e32 v10, -1, v6
-; GFX11-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
+; GFX11-NEXT: .LBB15_9:
+; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT: s_cbranch_vccz .LBB15_11
+; GFX11-NEXT: ; %bb.10: ; %frem.else
+; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX11-NEXT: v_and_b32_e32 v6, 0x80000000, v3
+; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
+; GFX11-NEXT: s_branch .LBB15_12
+; GFX11-NEXT: .LBB15_11:
+; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX11-NEXT: .LBB15_12: ; %Flow48
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 1
+; GFX11-NEXT: s_cbranch_scc1 .LBB15_18
+; GFX11-NEXT: ; %bb.13: ; %frem.compute
+; GFX11-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX11-NEXT: v_add_nc_u32_e32 v10, -1, v8
+; GFX11-NEXT: v_readfirstlane_b32 s2, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX11-NEXT: s_cbranch_vccnz .LBB15_13
-; GFX11-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB15_17
+; GFX11-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX11-NEXT: s_add_i32 s2, s2, 25
-; GFX11-NEXT: .LBB15_11: ; %frem.loop_body
+; GFX11-NEXT: .LBB15_15: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX11-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX11-NEXT: s_sub_i32 s2, s2, 26
; GFX11-NEXT: s_cmp_gt_i32 s2, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX11-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
+; GFX11-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX11-NEXT: v_add_f64 v[10:11], v[6:7], 1.0
; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB15_11
-; GFX11-NEXT: ; %bb.12:
-; GFX11-NEXT: v_mov_b32_e32 v10, s2
-; GFX11-NEXT: s_branch .LBB15_14
-; GFX11-NEXT: .LBB15_13:
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
-; GFX11-NEXT: .LBB15_14: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_nc_u32_e32 v6, 25, v10
-; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; GFX11-NEXT: s_cbranch_scc1 .LBB15_15
+; GFX11-NEXT: ; %bb.16: ; %Flow
+; GFX11-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
+; GFX11-NEXT: v_mov_b32_e32 v6, v8
+; GFX11-NEXT: .LBB15_17: ; %frem.loop_exit
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
+; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
+; GFX11-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
+; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
-; GFX11-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
+; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX11-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v3
-; GFX11-NEXT: .LBB15_15:
+; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
+; GFX11-NEXT: .LBB15_18: ; %Flow49
; GFX11-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
-; GFX11-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v9 :: v_dual_cndmask_b32 v0, 0, v8
+; GFX11-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v5 :: v_dual_cndmask_b32 v0, 0, v4
; GFX11-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v5
-; GFX11-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
-; GFX11-NEXT: global_store_b128 v6, v[0:3], s[0:1]
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc_lo
+; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-NEXT: s_endpgm
;
; GFX1150-LABEL: frem_v2f64_const_one_denum:
@@ -17629,59 +19183,59 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: s_waitcnt lgkmcnt(0)
; GFX1150-NEXT: global_load_b128 v[0:3], v0, s[2:3]
; GFX1150-NEXT: s_waitcnt vmcnt(0)
-; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX1150-NEXT: s_cbranch_vccz .LBB15_5
-; GFX1150-NEXT: ; %bb.1: ; %frem.compute15
+; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, 1.0
+; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX1150-NEXT: s_cbranch_vccz .LBB15_2
+; GFX1150-NEXT: ; %bb.1: ; %frem.else16
+; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX1150-NEXT: s_mov_b32 s2, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX1150-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB15_3
+; GFX1150-NEXT: .LBB15_2:
+; GFX1150-NEXT: s_mov_b32 s2, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1150-NEXT: .LBB15_3: ; %Flow52
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB15_9
+; GFX1150-NEXT: ; %bb.4: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1150-NEXT: v_readfirstlane_b32 s2, v6
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1150-NEXT: v_add_nc_u32_e32 v8, -1, v6
-; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX1150-NEXT: v_readfirstlane_b32 s2, v6
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
-; GFX1150-NEXT: s_cbranch_vccnz .LBB15_7
-; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB15_8
+; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_add_i32 s2, s2, 25
-; GFX1150-NEXT: .LBB15_3: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB15_6: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX1150-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1150-NEXT: s_sub_i32 s2, s2, 26
; GFX1150-NEXT: s_cmp_gt_i32 s2, 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX1150-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; GFX1150-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
+; GFX1150-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX1150-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
-; GFX1150-NEXT: v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
+; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
+; GFX1150-NEXT: v_add_f64 v[8:9], v[4:5], 1.0
+; GFX1150-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB15_3
-; GFX1150-NEXT: ; %bb.4:
-; GFX1150-NEXT: v_mov_b32_e32 v8, s2
-; GFX1150-NEXT: s_branch .LBB15_8
-; GFX1150-NEXT: .LBB15_5: ; %frem.else16
-; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB15_9
-; GFX1150-NEXT: .LBB15_6: ; %frem.else
-; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v3
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB15_15
-; GFX1150-NEXT: .LBB15_7:
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; GFX1150-NEXT: s_cbranch_scc1 .LBB15_6
+; GFX1150-NEXT: ; %bb.7: ; %Flow50
+; GFX1150-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
+; GFX1150-NEXT: v_mov_b32_e32 v4, v6
; GFX1150-NEXT: .LBB15_8: ; %frem.loop_exit24
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17690,67 +19244,82 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX1150-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc_lo
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX1150-NEXT: v_bfi_b32 v9, 0x7fffffff, v4, v1
-; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX1150-NEXT: s_cbranch_vccz .LBB15_6
-; GFX1150-NEXT: .LBB15_9: ; %frem.compute
-; GFX1150-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v6, v[2:3]
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1150-NEXT: v_readfirstlane_b32 s2, v6
-; GFX1150-NEXT: v_add_nc_u32_e32 v10, -1, v6
-; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX1150-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
+; GFX1150-NEXT: .LBB15_9:
+; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
+; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX1150-NEXT: s_cbranch_vccz .LBB15_11
+; GFX1150-NEXT: ; %bb.10: ; %frem.else
+; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX1150-NEXT: v_and_b32_e32 v6, 0x80000000, v3
+; GFX1150-NEXT: s_mov_b32 s2, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
+; GFX1150-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB15_12
+; GFX1150-NEXT: .LBB15_11:
+; GFX1150-NEXT: s_mov_b32 s2, -1
+; GFX1150-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1150-NEXT: .LBB15_12: ; %Flow48
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1150-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1150-NEXT: s_cbranch_scc1 .LBB15_18
+; GFX1150-NEXT: ; %bb.13: ; %frem.compute
+; GFX1150-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX1150-NEXT: v_add_nc_u32_e32 v10, -1, v8
+; GFX1150-NEXT: v_readfirstlane_b32 s2, v8
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX1150-NEXT: s_cbranch_vccnz .LBB15_13
-; GFX1150-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB15_17
+; GFX1150-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_add_i32 s2, s2, 25
-; GFX1150-NEXT: .LBB15_11: ; %frem.loop_body
+; GFX1150-NEXT: .LBB15_15: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX1150-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX1150-NEXT: s_sub_i32 s2, s2, 26
; GFX1150-NEXT: s_cmp_gt_i32 s2, 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX1150-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
+; GFX1150-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1150-NEXT: v_add_f64 v[10:11], v[6:7], 1.0
; GFX1150-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB15_11
-; GFX1150-NEXT: ; %bb.12:
-; GFX1150-NEXT: v_mov_b32_e32 v10, s2
-; GFX1150-NEXT: s_branch .LBB15_14
-; GFX1150-NEXT: .LBB15_13:
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
-; GFX1150-NEXT: .LBB15_14: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_subrev_nc_u32_e32 v6, 25, v10
-; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; GFX1150-NEXT: s_cbranch_scc1 .LBB15_15
+; GFX1150-NEXT: ; %bb.16: ; %Flow
+; GFX1150-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
+; GFX1150-NEXT: v_mov_b32_e32 v6, v8
+; GFX1150-NEXT: .LBB15_17: ; %frem.loop_exit
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
+; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX1150-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
+; GFX1150-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
+; GFX1150-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
-; GFX1150-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX1150-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
+; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1150-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
+; GFX1150-NEXT: v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v3
-; GFX1150-NEXT: .LBB15_15:
+; GFX1150-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
+; GFX1150-NEXT: .LBB15_18: ; %Flow49
; GFX1150-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
-; GFX1150-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v9 :: v_dual_cndmask_b32 v0, 0, v8
+; GFX1150-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v5 :: v_dual_cndmask_b32 v0, 0, v4
; GFX1150-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1150-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v5
-; GFX1150-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
-; GFX1150-NEXT: global_store_b128 v6, v[0:3], s[0:1]
+; GFX1150-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v7
+; GFX1150-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc_lo
+; GFX1150-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1150-NEXT: s_endpgm
;
; GFX1200-LABEL: frem_v2f64_const_one_denum:
@@ -17760,61 +19329,60 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: global_load_b128 v[0:3], v0, s[2:3]
; GFX1200-NEXT: s_wait_loadcnt 0x0
-; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX1200-NEXT: s_cbranch_vccz .LBB15_5
-; GFX1200-NEXT: ; %bb.1: ; %frem.compute15
+; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, 1.0
+; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX1200-NEXT: s_cbranch_vccz .LBB15_2
+; GFX1200-NEXT: ; %bb.1: ; %frem.else16
+; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX1200-NEXT: s_mov_b32 s2, 0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX1200-NEXT: s_branch .LBB15_3
+; GFX1200-NEXT: .LBB15_2:
+; GFX1200-NEXT: s_mov_b32 s2, -1
+; GFX1200-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX1200-NEXT: .LBB15_3: ; %Flow52
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1200-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB15_9
+; GFX1200-NEXT: ; %bb.4: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_readfirstlane_b32 s2, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX1200-NEXT: v_add_nc_u32_e32 v8, -1, v6
-; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX1200-NEXT: v_readfirstlane_b32 s2, v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
-; GFX1200-NEXT: s_cbranch_vccnz .LBB15_7
-; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB15_8
+; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_add_co_i32 s2, s2, 25
-; GFX1200-NEXT: .LBB15_3: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB15_6: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX1200-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX1200-NEXT: v_add_f64_e64 v[6:7], v[4:5], -v[6:7]
+; GFX1200-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
+; GFX1200-NEXT: v_add_f64_e64 v[4:5], v[6:7], -v[4:5]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX1200-NEXT: v_add_f64_e32 v[8:9], 1.0, v[6:7]
+; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
+; GFX1200-NEXT: v_add_f64_e32 v[8:9], 1.0, v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
+; GFX1200-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB15_3
-; GFX1200-NEXT: ; %bb.4:
-; GFX1200-NEXT: v_mov_b32_e32 v8, s2
-; GFX1200-NEXT: s_branch .LBB15_8
-; GFX1200-NEXT: .LBB15_5: ; %frem.else16
-; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB15_9
-; GFX1200-NEXT: .LBB15_6: ; %frem.else
-; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v3
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc_lo
-; GFX1200-NEXT: s_branch .LBB15_15
-; GFX1200-NEXT: .LBB15_7:
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; GFX1200-NEXT: s_cbranch_scc1 .LBB15_6
+; GFX1200-NEXT: ; %bb.7: ; %Flow50
+; GFX1200-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
+; GFX1200-NEXT: v_mov_b32_e32 v4, v6
; GFX1200-NEXT: .LBB15_8: ; %frem.loop_exit24
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17824,71 +19392,89 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT: v_add_f64_e32 v[6:7], 1.0, v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX1200-NEXT: v_bfi_b32 v9, 0x7fffffff, v4, v1
-; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX1200-NEXT: s_cbranch_vccz .LBB15_6
-; GFX1200-NEXT: .LBB15_9: ; %frem.compute
-; GFX1200-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v6, v[2:3]
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_readfirstlane_b32 s2, v6
-; GFX1200-NEXT: v_add_nc_u32_e32 v10, -1, v6
-; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX1200-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
+; GFX1200-NEXT: .LBB15_9:
+; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
+; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_cbranch_vccz .LBB15_11
+; GFX1200-NEXT: ; %bb.10: ; %frem.else
+; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX1200-NEXT: v_and_b32_e32 v6, 0x80000000, v3
+; GFX1200-NEXT: s_mov_b32 s2, 0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
+; GFX1200-NEXT: s_branch .LBB15_12
+; GFX1200-NEXT: .LBB15_11:
+; GFX1200-NEXT: s_mov_b32 s2, -1
+; GFX1200-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1200-NEXT: .LBB15_12: ; %Flow48
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1200-NEXT: s_cbranch_scc1 .LBB15_18
+; GFX1200-NEXT: ; %bb.13: ; %frem.compute
+; GFX1200-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX1200-NEXT: v_add_nc_u32_e32 v10, -1, v8
+; GFX1200-NEXT: v_readfirstlane_b32 s2, v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX1200-NEXT: s_cbranch_vccnz .LBB15_13
-; GFX1200-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB15_17
+; GFX1200-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_add_co_i32 s2, s2, 25
-; GFX1200-NEXT: .LBB15_11: ; %frem.loop_body
+; GFX1200-NEXT: .LBB15_15: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX1200-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
-; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_f64_e64 v[6:7], v[4:5], -v[6:7]
+; GFX1200-NEXT: v_add_f64_e64 v[6:7], v[8:9], -v[6:7]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT: v_add_f64_e32 v[10:11], 1.0, v[6:7]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB15_11
-; GFX1200-NEXT: ; %bb.12:
-; GFX1200-NEXT: v_mov_b32_e32 v10, s2
-; GFX1200-NEXT: s_branch .LBB15_14
-; GFX1200-NEXT: .LBB15_13:
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
-; GFX1200-NEXT: .LBB15_14: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_subrev_nc_u32_e32 v6, 25, v10
-; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; GFX1200-NEXT: s_cbranch_scc1 .LBB15_15
+; GFX1200-NEXT: ; %bb.16: ; %Flow
+; GFX1200-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
+; GFX1200-NEXT: v_mov_b32_e32 v6, v8
+; GFX1200-NEXT: .LBB15_17: ; %frem.loop_exit
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
+; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
-; GFX1200-NEXT: v_add_f64_e64 v[4:5], v[4:5], -v[6:7]
+; GFX1200-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
+; GFX1200-NEXT: v_add_f64_e64 v[6:7], v[6:7], -v[8:9]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
-; GFX1200-NEXT: v_add_f64_e32 v[6:7], 1.0, v[4:5]
+; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1200-NEXT: v_add_f64_e32 v[8:9], 1.0, v[6:7]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
+; GFX1200-NEXT: v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v3
-; GFX1200-NEXT: .LBB15_15:
+; GFX1200-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
+; GFX1200-NEXT: .LBB15_18: ; %Flow49
; GFX1200-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v9 :: v_dual_cndmask_b32 v0, 0, v8
+; GFX1200-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v5 :: v_dual_cndmask_b32 v0, 0, v4
; GFX1200-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v5
-; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
-; GFX1200-NEXT: global_store_b128 v6, v[0:3], s[0:1]
+; GFX1200-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v7
+; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc_lo
+; GFX1200-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1200-NEXT: s_endpgm
%r0 = load <2 x double>, ptr addrspace(1) %in, align 16
%r1 = frem <2 x double> %r0, <double 1.0, double 1.0>
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
index 9a569fd127d73a..14886857fa2f08 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
@@ -102,7 +102,7 @@ define amdgpu_kernel void @cos_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0.15915494, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
index ad690fe234bc79..1c035c4709babe 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
@@ -96,7 +96,7 @@ define amdgpu_kernel void @rint_f16(
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_rndne_f16_e32 v0.l, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
index d8f53af61b3431..0a5df29922f452 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
@@ -102,7 +102,7 @@ define amdgpu_kernel void @sin_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0.15915494, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
index 30d966eb1b7c2f..14945be58876a2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
@@ -23,7 +23,7 @@ define amdgpu_kernel void @sqrt_bf16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s4, s0
-; GFX12-TRUE16-SDAG-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null
+; GFX12-TRUE16-SDAG-NEXT: buffer_load_u16 v0, off, s[8:11], null
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-SDAG-NEXT: v_sqrt_bf16_e32 v0.l, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
index bcaba060b812fa..c9f4e1993cd736 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
@@ -129,7 +129,7 @@ define amdgpu_kernel void @sqrt_f16(
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s4, s0
-; GFX12-TRUE16-SDAG-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null
+; GFX12-TRUE16-SDAG-NEXT: buffer_load_u16 v0, off, s[8:11], null
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-SDAG-NEXT: v_sqrt_f16_e32 v0.l, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
index 4664a4475d22ac..9715cb0e3ee5b8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
@@ -95,7 +95,7 @@ define amdgpu_kernel void @trunc_f16(
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
-; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index 633c54f06a3621..e95e1763ce30a6 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -534,55 +534,29 @@ define amdgpu_kernel void @constant_load_v16i1(ptr addrspace(1) %out, ptr addrsp
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_load_v16i1:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: s_load_u16 s2, s[2:3], 0x0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_load_v16i1:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_load_u16 s2, s[2:3], 0x0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX12-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
-;
-; GFX1250-TRUE16-LABEL: constant_load_v16i1:
-; GFX1250-TRUE16: ; %bb.0:
-; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-TRUE16-NEXT: v_nop
-; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: s_load_u16 s2, s[2:3], 0x0 nv
-; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1250-TRUE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_load_v16i1:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX12-NEXT: s_endpgm
;
-; GFX1250-FAKE16-LABEL: constant_load_v16i1:
-; GFX1250-FAKE16: ; %bb.0:
-; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-FAKE16-NEXT: v_nop
-; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: s_load_u16 s2, s[2:3], 0x0 nv
-; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX1250-FAKE16-NEXT: s_endpgm
+; GFX1250-LABEL: constant_load_v16i1:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_load_u16 s2, s[2:3], 0x0 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX1250-NEXT: s_endpgm
%load = load <16 x i1>, ptr addrspace(4) %in
store <16 x i1> %load, ptr addrspace(1) %out
ret void
@@ -2240,32 +2214,31 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_and_b32 s6, 0xffff, s2
; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10003
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10001
; GFX12-NEXT: s_bfe_u32 s5, s2, 0x10007
-; GFX12-NEXT: s_bfe_u32 s7, s2, 0x10009
-; GFX12-NEXT: s_bfe_u32 s8, s2, 0x1000d
-; GFX12-NEXT: s_and_b32 s9, s2, 1
-; GFX12-NEXT: s_bfe_u32 s10, s2, 0x1000a
-; GFX12-NEXT: s_bfe_u32 s2, s2, 0x1000c
-; GFX12-NEXT: s_bfe_u32 s11, s6, 0x10005
-; GFX12-NEXT: s_bfe_u32 s12, s6, 0x1000b
-; GFX12-NEXT: s_lshr_b32 s13, s6, 15
-; GFX12-NEXT: s_bfe_u32 s14, s6, 0x10002
-; GFX12-NEXT: s_bfe_u32 s15, s6, 0x10006
-; GFX12-NEXT: s_bfe_u32 s16, s6, 0x10004
-; GFX12-NEXT: s_bfe_u32 s17, s6, 0x10008
-; GFX12-NEXT: s_bfe_u32 s6, s6, 0x1000e
-; GFX12-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s8
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s7
-; GFX12-NEXT: v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v2, s6
-; GFX12-NEXT: v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, s17
-; GFX12-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v11, s5
-; GFX12-NEXT: v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, s16
-; GFX12-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s15
-; GFX12-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v13, s4
-; GFX12-NEXT: v_mov_b32_e32 v14, s14
+; GFX12-NEXT: s_bfe_u32 s6, s2, 0x10005
+; GFX12-NEXT: s_bfe_u32 s7, s2, 0x1000b
+; GFX12-NEXT: s_bfe_u32 s8, s2, 0x10009
+; GFX12-NEXT: s_lshr_b32 s9, s2, 15
+; GFX12-NEXT: s_bfe_u32 s10, s2, 0x1000d
+; GFX12-NEXT: s_and_b32 s11, s2, 1
+; GFX12-NEXT: s_bfe_u32 s12, s2, 0x10002
+; GFX12-NEXT: s_bfe_u32 s13, s2, 0x10006
+; GFX12-NEXT: s_bfe_u32 s14, s2, 0x10004
+; GFX12-NEXT: s_bfe_u32 s15, s2, 0x1000a
+; GFX12-NEXT: s_bfe_u32 s16, s2, 0x10008
+; GFX12-NEXT: s_bfe_u32 s17, s2, 0x1000c
+; GFX12-NEXT: s_bfe_u32 s2, s2, 0x1000e
+; GFX12-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v1, s10
+; GFX12-NEXT: v_dual_mov_b32 v0, s17 :: v_dual_mov_b32 v3, s9
+; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s8
+; GFX12-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v7, s7
+; GFX12-NEXT: v_dual_mov_b32 v6, s15 :: v_dual_mov_b32 v9, s6
+; GFX12-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v11, s5
+; GFX12-NEXT: v_dual_mov_b32 v10, s13 :: v_dual_mov_b32 v13, s4
+; GFX12-NEXT: v_dual_mov_b32 v12, s11 :: v_dual_mov_b32 v15, s3
+; GFX12-NEXT: v_mov_b32_e32 v14, s12
; GFX12-NEXT: s_clause 0x3
; GFX12-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
; GFX12-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
@@ -2283,32 +2256,31 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u16 s2, s[2:3], 0x0 nv
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_and_b32 s6, 0xffff, s2
; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x10003
; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10001
; GFX1250-NEXT: s_bfe_u32 s5, s2, 0x10007
-; GFX1250-NEXT: s_bfe_u32 s7, s2, 0x10009
-; GFX1250-NEXT: s_bfe_u32 s8, s2, 0x1000d
-; GFX1250-NEXT: s_and_b32 s9, s2, 1
-; GFX1250-NEXT: s_bfe_u32 s10, s2, 0x1000a
-; GFX1250-NEXT: s_bfe_u32 s2, s2, 0x1000c
-; GFX1250-NEXT: s_bfe_u32 s11, s6, 0x10005
-; GFX1250-NEXT: s_bfe_u32 s12, s6, 0x1000b
-; GFX1250-NEXT: s_lshr_b32 s13, s6, 15
-; GFX1250-NEXT: s_bfe_u32 s14, s6, 0x10002
-; GFX1250-NEXT: s_bfe_u32 s15, s6, 0x10006
-; GFX1250-NEXT: s_bfe_u32 s16, s6, 0x10004
-; GFX1250-NEXT: s_bfe_u32 s17, s6, 0x10008
-; GFX1250-NEXT: s_bfe_u32 s6, s6, 0x1000e
-; GFX1250-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v0, s2
-; GFX1250-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v5, s7
-; GFX1250-NEXT: v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v2, s6
-; GFX1250-NEXT: v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, s17
-; GFX1250-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v11, s5
-; GFX1250-NEXT: v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, s16
-; GFX1250-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s15
-; GFX1250-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v13, s4
-; GFX1250-NEXT: v_mov_b32_e32 v14, s14
+; GFX1250-NEXT: s_bfe_u32 s6, s2, 0x10005
+; GFX1250-NEXT: s_bfe_u32 s7, s2, 0x1000b
+; GFX1250-NEXT: s_bfe_u32 s8, s2, 0x10009
+; GFX1250-NEXT: s_lshr_b32 s9, s2, 15
+; GFX1250-NEXT: s_bfe_u32 s10, s2, 0x1000d
+; GFX1250-NEXT: s_and_b32 s11, s2, 1
+; GFX1250-NEXT: s_bfe_u32 s12, s2, 0x10002
+; GFX1250-NEXT: s_bfe_u32 s13, s2, 0x10006
+; GFX1250-NEXT: s_bfe_u32 s14, s2, 0x10004
+; GFX1250-NEXT: s_bfe_u32 s15, s2, 0x1000a
+; GFX1250-NEXT: s_bfe_u32 s16, s2, 0x10008
+; GFX1250-NEXT: s_bfe_u32 s17, s2, 0x1000c
+; GFX1250-NEXT: s_bfe_u32 s2, s2, 0x1000e
+; GFX1250-NEXT: v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v0, s17
+; GFX1250-NEXT: v_dual_mov_b32 v1, s10 :: v_dual_mov_b32 v2, s2
+; GFX1250-NEXT: v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s16
+; GFX1250-NEXT: v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s15
+; GFX1250-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v8, s14
+; GFX1250-NEXT: v_dual_mov_b32 v9, s6 :: v_dual_mov_b32 v10, s13
+; GFX1250-NEXT: v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v12, s11
+; GFX1250-NEXT: v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v14, s12
+; GFX1250-NEXT: v_mov_b32_e32 v15, s3
; GFX1250-NEXT: s_clause 0x3
; GFX1250-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
; GFX1250-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
@@ -7294,38 +7266,36 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000a
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s4
-; GFX12-NEXT: s_and_b32 s3, 0xffff, s2
-; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10009
-; GFX12-NEXT: s_bfe_u32 s5, s3, 0x1000b
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, s5
-; GFX12-NEXT: s_bfe_u32 s5, s3, 0x10008
+; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000a
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s3
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000b
+; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10009
+; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, v1
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10008
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:80
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v0, s5
-; GFX12-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-NEXT: s_lshr_b32 s4, s3, 15
-; GFX12-NEXT: s_bfe_u32 s5, s3, 0x1000e
-; GFX12-NEXT: s_bfe_u32 s3, s3, 0x10005
+; GFX12-NEXT: v_mov_b32_e32 v0, s4
+; GFX12-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-NEXT: s_lshr_b32 s3, s2, 15
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000e
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:64
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v0, s5
-; GFX12-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000d
-; GFX12-NEXT: s_bfe_u32 s5, s2, 0x1000c
+; GFX12-NEXT: v_mov_b32_e32 v0, s4
+; GFX12-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000d
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000c
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:112
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v0, s5
-; GFX12-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10007
-; GFX12-NEXT: s_bfe_u32 s5, s2, 0x10006
+; GFX12-NEXT: v_mov_b32_e32 v0, s4
+; GFX12-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10007
+; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10006
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:96
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v0, s5
-; GFX12-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-NEXT: v_mov_b32_e32 v0, s4
+; GFX12-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10005
; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10004
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7356,51 +7326,47 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_u16 s2, s[2:3], 0x0 nv
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x1000a
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s4
-; GFX1250-NEXT: s_and_b32 s3, 0xffff, s2
-; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10009
-; GFX1250-NEXT: s_bfe_u32 s5, s3, 0x1000b
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, s5
-; GFX1250-NEXT: s_bfe_u32 s5, s3, 0x10008
-; GFX1250-NEXT: v_mov_b32_e32 v1, v3
-; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:80
+; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x1000a
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s3
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x1000b
+; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x10009
+; GFX1250-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, v1
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10008
+; GFX1250-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:80
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
-; GFX1250-NEXT: s_lshr_b32 s4, s3, 15
-; GFX1250-NEXT: s_bfe_u32 s5, s3, 0x1000e
-; GFX1250-NEXT: s_bfe_u32 s3, s3, 0x10005
-; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:64
+; GFX1250-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v2, s3
+; GFX1250-NEXT: s_lshr_b32 s3, s2, 15
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x1000e
+; GFX1250-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:64
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
-; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x1000d
-; GFX1250-NEXT: s_bfe_u32 s5, s2, 0x1000c
-; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:112
+; GFX1250-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v2, s3
+; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x1000d
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x1000c
+; GFX1250-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:112
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
-; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10007
-; GFX1250-NEXT: s_bfe_u32 s5, s2, 0x10006
-; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:96
+; GFX1250-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v2, s3
+; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x10007
+; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10006
+; GFX1250-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:96
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v4, s4
+; GFX1250-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v2, s3
+; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x10005
; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10004
-; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:48
+; GFX1250-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v4, s3
+; GFX1250-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v2, s3
; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x10003
; GFX1250-NEXT: s_bfe_u32 s4, s2, 0x10002
-; GFX1250-NEXT: v_mov_b32_e32 v0, s2
-; GFX1250-NEXT: s_bfe_u32 s2, s2, 0x10001
-; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:32
+; GFX1250-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:32
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v4, s3
-; GFX1250-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX1250-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:16
+; GFX1250-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v2, s3
+; GFX1250-NEXT: s_bfe_u32 s3, s2, 0x10001
+; GFX1250-NEXT: s_and_b32 s2, s2, 1
+; GFX1250-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_mov_b32_e32 v2, s2
-; GFX1250-NEXT: global_store_b128 v3, v[0:3], s[0:1]
+; GFX1250-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v2, s3
+; GFX1250-NEXT: global_store_b128 v1, v[0:3], s[0:1]
; GFX1250-NEXT: s_endpgm
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = zext <16 x i1> %load to <16 x i64>
@@ -7754,7 +7720,7 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-TRUE16-NEXT: global_store_b128 v32, v[24:27], s[0:1] offset:16
; GFX12-TRUE16-NEXT: global_store_b128 v32, v[28:31], s[0:1]
; GFX12-TRUE16-NEXT: s_endpgm
-;
+
; GFX12-FAKE16-LABEL: constant_sextload_v16i1_to_v16i64:
; GFX12-FAKE16: ; %bb.0:
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
@@ -7826,6 +7792,7 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-FAKE16-NEXT: global_store_b128 v32, v[28:31], s[0:1]
; GFX12-FAKE16-NEXT: s_endpgm
+
; GFX1250-LABEL: constant_sextload_v16i1_to_v16i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
index 895dedfff038ec..9189fdbadd2c94 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
@@ -79,26 +79,15 @@ define amdgpu_kernel void @constant_load_i16(ptr addrspace(1) %out, ptr addrspac
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_load_i16:
-; GFX12-TRUE16: ; %bb.0: ; %entry
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: s_load_u16 s2, s[2:3], 0x0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_load_i16:
-; GFX12-FAKE16: ; %bb.0: ; %entry
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_load_u16 s2, s[2:3], 0x0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX12-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_load_i16:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX12-NEXT: s_endpgm
entry:
%ld = load i16, ptr addrspace(4) %in
store i16 %ld, ptr addrspace(1) %out
@@ -760,77 +749,47 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; EG-NEXT: MOV * T2.X, literal.x,
; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_load_v16i16_align2:
-; GFX12-TRUE16: ; %bb.0: ; %entry
-; GFX12-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v8, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: s_clause 0x7
-; GFX12-TRUE16-NEXT: s_load_u16 s2, s[0:1], 0xc
-; GFX12-TRUE16-NEXT: s_load_u16 s3, s[0:1], 0x8
-; GFX12-TRUE16-NEXT: s_load_u16 s4, s[0:1], 0x4
-; GFX12-TRUE16-NEXT: s_load_u16 s5, s[0:1], 0x0
-; GFX12-TRUE16-NEXT: s_load_u16 s6, s[0:1], 0x1c
-; GFX12-TRUE16-NEXT: s_load_u16 s7, s[0:1], 0x18
-; GFX12-TRUE16-NEXT: s_load_u16 s8, s[0:1], 0x14
-; GFX12-TRUE16-NEXT: s_load_u16 s9, s[0:1], 0x10
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, s3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, s6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, s7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, s8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, s9
-; GFX12-TRUE16-NEXT: s_clause 0x7
-; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v3, v8, s[0:1] offset:14
-; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v7, v8, s[0:1] offset:30
-; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v6, v8, s[0:1] offset:26
-; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v5, v8, s[0:1] offset:22
-; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v4, v8, s[0:1] offset:18
-; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v2, v8, s[0:1] offset:10
-; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v1, v8, s[0:1] offset:6
-; GFX12-TRUE16-NEXT: global_load_d16_hi_b16 v0, v8, s[0:1] offset:2
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: global_store_b128 v[0:1], v[4:7], off
-; GFX12-TRUE16-NEXT: global_store_b128 v[0:1], v[0:3], off
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_load_v16i16_align2:
-; GFX12-FAKE16: ; %bb.0: ; %entry
-; GFX12-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_clause 0x7
-; GFX12-FAKE16-NEXT: s_load_u16 s2, s[0:1], 0xc
-; GFX12-FAKE16-NEXT: s_load_u16 s3, s[0:1], 0x8
-; GFX12-FAKE16-NEXT: s_load_u16 s4, s[0:1], 0x4
-; GFX12-FAKE16-NEXT: s_load_u16 s5, s[0:1], 0x0
-; GFX12-FAKE16-NEXT: s_load_u16 s6, s[0:1], 0x1c
-; GFX12-FAKE16-NEXT: s_load_u16 s7, s[0:1], 0x18
-; GFX12-FAKE16-NEXT: s_load_u16 s8, s[0:1], 0x14
-; GFX12-FAKE16-NEXT: s_load_u16 s9, s[0:1], 0x10
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v3, s2
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v1, s4
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v7, s6
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v6, s7 :: v_dual_mov_b32 v5, s8
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, s9
-; GFX12-FAKE16-NEXT: s_clause 0x7
-; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v3, v8, s[0:1] offset:14
-; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v7, v8, s[0:1] offset:30
-; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v6, v8, s[0:1] offset:26
-; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v5, v8, s[0:1] offset:22
-; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v4, v8, s[0:1] offset:18
-; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v2, v8, s[0:1] offset:10
-; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v1, v8, s[0:1] offset:6
-; GFX12-FAKE16-NEXT: global_load_d16_hi_b16 v0, v8, s[0:1] offset:2
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: s_clause 0x1
-; GFX12-FAKE16-NEXT: global_store_b128 v[0:1], v[4:7], off
-; GFX12-FAKE16-NEXT: global_store_b128 v[0:1], v[0:3], off
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_load_v16i16_align2:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_clause 0xf
+; GFX12-NEXT: s_load_u16 s2, s[0:1], 0x0
+; GFX12-NEXT: s_load_u16 s3, s[0:1], 0x2
+; GFX12-NEXT: s_load_u16 s4, s[0:1], 0x4
+; GFX12-NEXT: s_load_u16 s5, s[0:1], 0x6
+; GFX12-NEXT: s_load_u16 s6, s[0:1], 0x8
+; GFX12-NEXT: s_load_u16 s7, s[0:1], 0xa
+; GFX12-NEXT: s_load_u16 s8, s[0:1], 0xc
+; GFX12-NEXT: s_load_u16 s9, s[0:1], 0xe
+; GFX12-NEXT: s_load_u16 s10, s[0:1], 0x10
+; GFX12-NEXT: s_load_u16 s11, s[0:1], 0x18
+; GFX12-NEXT: s_load_u16 s12, s[0:1], 0x1a
+; GFX12-NEXT: s_load_u16 s13, s[0:1], 0x1c
+; GFX12-NEXT: s_load_u16 s14, s[0:1], 0x1e
+; GFX12-NEXT: s_load_u16 s15, s[0:1], 0x12
+; GFX12-NEXT: s_load_u16 s16, s[0:1], 0x14
+; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x16
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX12-NEXT: s_pack_ll_b32_b16 s4, s4, s5
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s4
+; GFX12-NEXT: s_pack_ll_b32_b16 s6, s6, s7
+; GFX12-NEXT: s_pack_ll_b32_b16 s1, s8, s9
+; GFX12-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s1
+; GFX12-NEXT: s_pack_ll_b32_b16 s5, s11, s12
+; GFX12-NEXT: s_pack_ll_b32_b16 s3, s13, s14
+; GFX12-NEXT: s_pack_ll_b32_b16 s7, s10, s15
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v3, s3
+; GFX12-NEXT: s_pack_ll_b32_b16 s0, s16, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: v_dual_mov_b32 v0, s7 :: v_dual_mov_b32 v1, s0
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: global_store_b128 v[0:1], v[0:3], off
+; GFX12-NEXT: global_store_b128 v[0:1], v[4:7], off
+; GFX12-NEXT: s_endpgm
entry:
%ld = load <16 x i16>, ptr addrspace(4) %ptr0, align 2
store <16 x i16> %ld, ptr addrspace(1) poison, align 32
@@ -5429,8 +5388,6 @@ define amdgpu_kernel void @constant_zextload_i16_to_i64(ptr addrspace(1) %out, p
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-NEXT: global_store_b64 v1, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
@@ -5521,9 +5478,8 @@ define amdgpu_kernel void @constant_sextload_i16_to_i64(ptr addrspace(1) %out, p
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_sext_i32_i16 s2, s2
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_ashr_i32 s3, s2, 31
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
@@ -5608,8 +5564,6 @@ define amdgpu_kernel void @constant_zextload_v1i16_to_v1i64(ptr addrspace(1) %ou
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-NEXT: global_store_b64 v1, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
@@ -5695,9 +5649,8 @@ define amdgpu_kernel void @constant_sextload_v1i16_to_v1i64(ptr addrspace(1) %ou
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_sext_i32_i16 s2, s2
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_ashr_i32 s3, s2, 31
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
@@ -9012,3 +8965,6 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; }
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX12-FAKE16: {{.*}}
+; GFX12-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index ec1444d983dbc7..fba7b61f960cc4 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -178,26 +178,15 @@ define amdgpu_kernel void @constant_load_v2i8(ptr addrspace(1) %out, ptr addrspa
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
-; GFX12-TRUE16-LABEL: constant_load_v2i8:
-; GFX12-TRUE16: ; %bb.0: ; %entry
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: s_load_u16 s2, s[2:3], 0x0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-;
-; GFX12-FAKE16-LABEL: constant_load_v2i8:
-; GFX12-FAKE16: ; %bb.0: ; %entry
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_load_u16 s2, s[2:3], 0x0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX12-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
+; GFX12-LABEL: constant_load_v2i8:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX12-NEXT: s_endpgm
entry:
%ld = load <2 x i8>, ptr addrspace(4) %in
store <2 x i8> %ld, ptr addrspace(1) %out
@@ -951,12 +940,11 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i32(ptr addrspace(1) %out
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_and_b32 s3, 0xffff, s2
-; GFX12-NEXT: s_and_b32 s2, s2, 0xff
-; GFX12-NEXT: s_lshr_b32 s3, s3, 8
+; GFX12-NEXT: s_and_b32 s3, s2, 0xff
+; GFX12-NEXT: s_lshr_b32 s2, s2, 8
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
-; GFX12-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX12-NEXT: v_mov_b32_e32 v0, s3
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX12-NEXT: s_endpgm
%load = load <2 x i8>, ptr addrspace(4) %in
@@ -5627,13 +5615,12 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i64(ptr addrspace(1) %out
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_and_b32 s3, 0xffff, s2
-; GFX12-NEXT: s_and_b32 s2, s2, 0xff
+; GFX12-NEXT: s_and_b32 s3, s2, 0xff
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
-; GFX12-NEXT: s_lshr_b32 s3, s3, 8
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s3
+; GFX12-NEXT: s_lshr_b32 s2, s2, 8
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v3, v1
+; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, v1
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
%load = load <2 x i8>, ptr addrspace(4) %in
@@ -5738,20 +5725,15 @@ define amdgpu_kernel void @constant_sextload_v2i8_to_v2i64(ptr addrspace(1) %out
; GFX12-LABEL: constant_sextload_v2i8_to_v2i64:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b32_e32 v0, s2
-; GFX12-NEXT: s_lshr_b32 s2, s2, 8
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_lshr_b32 s4, s2, 8
; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v3, s3
-; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-NEXT: v_mov_b32_e32 v2, s2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GFX12-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, s5
+; GFX12-NEXT: v_mov_b32_e32 v2, s4
; GFX12-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
%load = load <2 x i8>, ptr addrspace(4) %in
@@ -9477,9 +9459,8 @@ define amdgpu_kernel void @constant_zextload_v2i8_to_v2i16(ptr addrspace(1) %out
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_and_b32 s3, 0xffff, s2
+; GFX12-NEXT: s_lshr_b32 s3, s2, 8
; GFX12-NEXT: s_and_b32 s2, s2, 0xff
-; GFX12-NEXT: s_lshr_b32 s3, s3, 8
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-NEXT: s_pack_ll_b32_b16 s2, s2, s3
; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll
index b403c6f3419b48..b6ca816550cc7c 100644
--- a/llvm/test/CodeGen/AMDGPU/min.ll
+++ b/llvm/test/CodeGen/AMDGPU/min.ll
@@ -3324,14 +3324,11 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x0 nv
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_load_u16 s0, s[14:15], 0x0
-; GFX1250-NEXT: s_load_u16 s1, s[12:13], 0x0
+; GFX1250-NEXT: s_load_u16 s0, s[12:13], 0x0
+; GFX1250-NEXT: s_load_u16 s1, s[14:15], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_and_b32 s2, 0xffff, s0
-; GFX1250-NEXT: s_and_b32 s3, 0xffff, s1
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_lt_u32 s3, s2
-; GFX1250-NEXT: s_cselect_b32 s0, s1, s0
+; GFX1250-NEXT: s_cmp_lt_u32 s0, s1
+; GFX1250-NEXT: s_cselect_b32 s0, s0, s1
; GFX1250-NEXT: s_cselect_b32 s1, 1, 0
; GFX1250-NEXT: v_mov_b32_e32 v1, s0
; GFX1250-NEXT: v_mov_b32_e32 v2, s1
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
index 99b77b1517bd2b..b1184b56f4b79e 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
@@ -9,13 +9,11 @@ define amdgpu_kernel void @exp_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[GLOBAL_LOAD_USHORT_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[V_EXP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_EXP_F16_t16_e64 0, [[GLOBAL_LOAD_USHORT_SADDR]].lo16, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[V_EXP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_EXP_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_EXP_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_EXP_F16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE]]
; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
@@ -32,13 +30,11 @@ define amdgpu_kernel void @log_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[GLOBAL_LOAD_USHORT_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[V_LOG_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_LOG_F16_t16_e64 0, [[GLOBAL_LOAD_USHORT_SADDR]].lo16, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[V_LOG_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_LOG_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_LOG_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_LOG_F16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE]]
; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
@@ -55,13 +51,11 @@ define amdgpu_kernel void @rcp_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[GLOBAL_LOAD_USHORT_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[V_RCP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RCP_F16_t16_e64 0, [[GLOBAL_LOAD_USHORT_SADDR]].lo16, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[V_RCP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RCP_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RCP_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RCP_F16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE]]
; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
@@ -78,13 +72,11 @@ define amdgpu_kernel void @rsq_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[GLOBAL_LOAD_USHORT_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[V_RSQ_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RSQ_F16_t16_e64 0, [[GLOBAL_LOAD_USHORT_SADDR]].lo16, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[V_RSQ_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RSQ_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RSQ_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RSQ_F16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE]]
; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
@@ -101,13 +93,11 @@ define amdgpu_kernel void @sqrt_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[GLOBAL_LOAD_USHORT_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[V_SQRT_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_SQRT_F16_t16_e64 0, [[GLOBAL_LOAD_USHORT_SADDR]].lo16, 0, 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[V_SQRT_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_SQRT_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_SQRT_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_SQRT_F16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE]]
; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
index d8ce9f1726965a..bb9dd7fce9c5e1 100644
--- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgpu9.42--amdhsa < %s | FileCheck -check-prefixes=GFX942 %s
; RUN: llc -mtriple=amdgpu9.0a--amdhsa < %s | FileCheck -check-prefixes=GFX90a %s
-; RUN: llc -mtriple=amdgpu12.50--amdhsa -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
-; RUN: llc -mtriple=amdgpu12.50--amdhsa -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
+; RUN: llc -mtriple=amdgpu12.50--amdhsa -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250 %s
+; RUN: llc -mtriple=amdgpu12.50--amdhsa -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250 %s
define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg %out) #0 {
; GFX942-LABEL: preload_block_count_x:
@@ -298,30 +298,17 @@ define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inr
; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
-; GFX1250-FAKE16-LABEL: incorrect_type_i16_block_count_x:
-; GFX1250-FAKE16: ; %bb.0:
-; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-FAKE16-NEXT: v_nop
-; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-FAKE16-NEXT: s_load_u16 s0, s[0:1], 0x8 nv
-; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-FAKE16-NEXT: global_store_b16 v0, v1, s[2:3]
-; GFX1250-FAKE16-NEXT: s_endpgm
-;
-; GFX1250-REAL16-LABEL: incorrect_type_i16_block_count_x:
-; GFX1250-REAL16: ; %bb.0:
-; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-REAL16-NEXT: v_nop
-; GFX1250-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-REAL16-NEXT: s_load_u16 s0, s[0:1], 0x8 nv
-; GFX1250-REAL16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX1250-REAL16-NEXT: global_store_b16 v1, v0, s[2:3]
-; GFX1250-REAL16-NEXT: s_endpgm
+; GFX1250-LABEL: incorrect_type_i16_block_count_x:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_load_u16 s0, s[0:1], 0x8 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]
+; GFX1250-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i16, ptr addrspace(4) %imp_arg_ptr
store i16 %load, ptr addrspace(1) %out
>From f6e3d99cc7f21aa7eb1f90af0ef979a52babf4db Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Mon, 28 Sep 2026 09:36:36 -0500
Subject: [PATCH 3/7] Remove tablegen patterns
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/lib/Target/AMDGPU/SMInstructions.td | 21 +++++++--------------
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 0f155fd898e981..19aeafe9b30ccc 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -980,7 +980,7 @@ multiclass SMLoad_Pattern <string Instr, ValueType vt, bit immci = true> {
}
}
-multiclass ScalarSubwordLoadPat <string Instr, SDPatternOperator node, ValueType vt> {
+multiclass ScalarLoadWithExtensionPat <string Instr, SDPatternOperator node, ValueType vt> {
// 1. IMM offset
def : GCNPat <
(node (SMRDImm i64:$sbase, i32:$offset)),
@@ -1041,19 +1041,12 @@ multiclass ScalarBufferLoadIntrinsicPat <SDPatternOperator name, string Instr> {
// selector to prefer those.
let AddedComplexity = 100 in {
-// Extending subword loads
-defm : ScalarSubwordLoadPat <"S_LOAD_U8", smrd_extloadi8, i32>;
-defm : ScalarSubwordLoadPat <"S_LOAD_U8", smrd_zextloadi8, i32>;
-defm : ScalarSubwordLoadPat <"S_LOAD_I8", smrd_sextloadi8, i32>;
-defm : ScalarSubwordLoadPat <"S_LOAD_U16", smrd_extloadi16, i32>;
-defm : ScalarSubwordLoadPat <"S_LOAD_U16", smrd_zextloadi16, i32>;
-defm : ScalarSubwordLoadPat <"S_LOAD_I16", smrd_sextloadi16, i32>;
-
-// Non-extending subword loads
-foreach vt = Reg16Types.types in {
- defm : ScalarSubwordLoadPat <"S_LOAD_U16", smrd_load, vt>;
-}
-
+defm : ScalarLoadWithExtensionPat <"S_LOAD_U8", smrd_extloadi8, i32>;
+defm : ScalarLoadWithExtensionPat <"S_LOAD_U8", smrd_zextloadi8, i32>;
+defm : ScalarLoadWithExtensionPat <"S_LOAD_I8", smrd_sextloadi8, i32>;
+defm : ScalarLoadWithExtensionPat <"S_LOAD_U16", smrd_extloadi16, i32>;
+defm : ScalarLoadWithExtensionPat <"S_LOAD_U16", smrd_zextloadi16, i32>;
+defm : ScalarLoadWithExtensionPat <"S_LOAD_I16", smrd_sextloadi16, i32>;
defm : ScalarBufferLoadIntrinsicPat <SIsbuffer_load_byte, "S_BUFFER_LOAD_I8">;
defm : ScalarBufferLoadIntrinsicPat <SIsbuffer_load_ubyte, "S_BUFFER_LOAD_U8">;
defm : ScalarBufferLoadIntrinsicPat <SIsbuffer_load_short, "S_BUFFER_LOAD_I16">;
>From 2ae8ea612a782199fc358a2c4e5fe385cfac7302 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Mon, 28 Sep 2026 11:12:31 -0500
Subject: [PATCH 4/7] Unify opc and node parameters
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/include/llvm/CodeGen/TargetLowering.h | 7 +++----
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 +--
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 9 ++++-----
llvm/lib/Target/AMDGPU/SIISelLowering.h | 2 +-
4 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index a53b4fdd9f91f7..91221f31b49a39 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4845,10 +4845,9 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
return isTypeLegal(VT);
}
- /// Overload that provides context about the specific node being optimized.
- /// By default, calls the version without the node parameter.
- virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT, SDNode *N) const {
- return isTypeDesirableForOp(Opc, VT);
+ /// Overload that takes the specific node being optimized.
+ virtual bool isTypeDesirableForOp(SDNode *N, EVT VT) const {
+ return isTypeDesirableForOp(N->getOpcode(), VT);
}
/// Return true if it is profitable for dag combiner to transform a floating
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c43f6990fb18c5..ea2955050332ec 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17970,8 +17970,7 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
// fold (truncate (load x)) -> (smaller load x)
// fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
- if (!LegalTypes ||
- TLI.isTypeDesirableForOp(N0.getOpcode(), VT, N0.getNode())) {
+ if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getNode(), VT)) {
if (SDValue Reduced = reduceLoadWidth(N))
return Reduced;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 3ebd668d32b421..f5b405ea02efd2 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2505,14 +2505,13 @@ bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
return TargetLowering::isTypeDesirableForOp(Op, VT);
}
-bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT,
- SDNode *N) const {
+bool SITargetLowering::isTypeDesirableForOp(SDNode *N, EVT VT) const {
// Do not convert uniform i32 loads to 16-bit.
// Uniform 16-bit loads are legalized to i16 = trunc (zextload i16->i32)
// to match subword load patterns. Allowing conversion back to a 16-bit
// load would create an infinite loop.
- if (Subtarget->hasScalarSubwordLoads() && Op == ISD::LOAD && !VT.isVector() &&
- VT.getSizeInBits() == 16) {
+ if (Subtarget->hasScalarSubwordLoads() && N->getOpcode() == ISD::LOAD &&
+ !VT.isVector() && VT.getSizeInBits() == 16) {
auto *Load = dyn_cast<LoadSDNode>(N);
if (Load && Load->getValueType(0) == MVT::i32 && !Load->isDivergent() &&
AMDGPU::isUniformMMO(Load->getMemOperand())) {
@@ -2520,7 +2519,7 @@ bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT,
}
}
- return isTypeDesirableForOp(Op, VT);
+ return isTypeDesirableForOp(N->getOpcode(), VT);
}
MachinePointerInfo
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index c55ecce8a28fe6..140b6c0a810c6f 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -417,7 +417,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override;
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
- bool isTypeDesirableForOp(unsigned Op, EVT VT, SDNode *N) const override;
+ bool isTypeDesirableForOp(SDNode *N, EVT VT) const override;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
>From 4605d55678c89e6efe3da56e3bcc45f656bf4d56 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Mon, 28 Sep 2026 14:45:51 -0500
Subject: [PATCH 5/7] Use isUniformLoad to guard legalization
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 27 --
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h | 1 -
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 27 +-
llvm/lib/Target/AMDGPU/SIISelLowering.h | 2 +
llvm/lib/Target/AMDGPU/SMInstructions.td | 5 +-
llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fcmp.f16.ll | 88 ++---
llvm/test/CodeGen/AMDGPU/fmax3.ll | 48 +--
llvm/test/CodeGen/AMDGPU/fmaximum.ll | 6 +-
llvm/test/CodeGen/AMDGPU/fmin3.ll | 48 +--
llvm/test/CodeGen/AMDGPU/fminimum.ll | 6 +-
llvm/test/CodeGen/AMDGPU/frem.ll | 351 +++++++++---------
llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll | 2 +-
...-to-valu-pseudo-scalar-trans-f16-true16.ll | 50 ++-
19 files changed, 340 insertions(+), 335 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index ff58f560314ab7..86cb52485ee97e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -4755,33 +4755,6 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
return !AllUsesAcceptSReg && (Limit < 10);
}
-bool AMDGPUDAGToDAGISel::isUniformLoad(const SDNode *N) const {
- const auto *Ld = cast<LoadSDNode>(N);
- const MachineMemOperand *MMO = Ld->getMemOperand();
-
- // FIXME: We ought to able able to take the direct isDivergent result. We
- // cannot rely on the MMO for a uniformity check, and should stop using
- // it. This is a hack for 2 ways that the IR divergence analysis is superior
- // to the DAG divergence: Recognizing shift-of-workitem-id as always
- // uniform, and isSingleLaneExecution. These should be handled in the DAG
- // version, and then this can be dropped.
- if (Ld->isDivergent() && !AMDGPU::isUniformMMO(MMO))
- return false;
-
- return MMO->getSize().hasValue() &&
- Ld->getAlign() >=
- Align(std::min(MMO->getSize().getValue().getKnownMinValue(),
- uint64_t(4))) &&
- (MMO->isInvariant() ||
- (Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
- Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ||
- (Subtarget->getScalarizeGlobalBehavior() &&
- Ld->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
- Ld->isSimple() &&
- static_cast<const SITargetLowering *>(getTargetLowering())
- ->isMemOpHasNoClobberedMemOperand(N)));
-}
-
void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
const AMDGPUTargetLowering& Lowering =
*static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index 2bcfe530b39473..a0e6b547b90af0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -90,7 +90,6 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
}
bool isVGPRImm(const SDNode *N) const;
- bool isUniformLoad(const SDNode *N) const;
bool isUniformBr(const SDNode *N) const;
MachineSDNode *buildRegSequence16(SmallVectorImpl<SDValue> &Elts,
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index f5b405ea02efd2..4012992d3f1d6a 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2522,6 +2522,30 @@ bool SITargetLowering::isTypeDesirableForOp(SDNode *N, EVT VT) const {
return isTypeDesirableForOp(N->getOpcode(), VT);
}
+bool SITargetLowering::isUniformLoad(const LoadSDNode *Load) const {
+ const MachineMemOperand *MMO = Load->getMemOperand();
+
+ // FIXME: We ought to able able to take the direct isDivergent result. We
+ // cannot rely on the MMO for a uniformity check, and should stop using
+ // it. This is a hack for 2 ways that the IR divergence analysis is superior
+ // to the DAG divergence: Recognizing shift-of-workitem-id as always
+ // uniform, and isSingleLaneExecution. These should be handled in the DAG
+ // version, and then this can be dropped.
+ if (Load->isDivergent() && !AMDGPU::isUniformMMO(MMO))
+ return false;
+
+ return MMO->getSize().hasValue() &&
+ Load->getAlign() >=
+ Align(std::min(MMO->getSize().getValue().getKnownMinValue(),
+ uint64_t(4))) &&
+ (MMO->isInvariant() ||
+ (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
+ Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ||
+ (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
+ Load->isSimple() && Subtarget->getScalarizeGlobalBehavior() &&
+ isMemOpHasNoClobberedMemOperand(Load)));
+}
+
MachinePointerInfo
SITargetLowering::getKernargSegmentPtrInfo(MachineFunction &MF) const {
// This isn't really a constant pool but close enough.
@@ -13624,9 +13648,10 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) {
// Legalize uniform 16-bit loads to i16 = trunc (zextload i16->i32)
// to match subword load patterns.
+ // Only do this for loads that can use scalar subword load instructions.
if (!MemVT.isVector() && MemVT.getSizeInBits() == 16 &&
isTypeLegal(MemVT) && Subtarget->hasScalarSubwordLoads() &&
- !Load->isDivergent() && AMDGPU::isUniformMMO(MMO)) {
+ isUniformLoad(Load)) {
SDValue Chain = Load->getChain();
SDValue BasePtr = Load->getBasePtr();
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index 140b6c0a810c6f..d1200ca7ce8252 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -54,6 +54,8 @@ class SITargetLowering final : public AMDGPUTargetLowering {
MachinePointerInfo getKernargSegmentPtrInfo(MachineFunction &MF) const;
+ bool isUniformLoad(const LoadSDNode *Load) const;
+
private:
SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
SDValue Chain, uint64_t Offset) const;
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 19aeafe9b30ccc..a4ef127a9029dd 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -828,7 +828,10 @@ def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>;
// Scalar Memory Patterns
//===----------------------------------------------------------------------===//
-class SMRDLoadPat<PatFrag Op> : PatFrag <(ops node:$ptr), (Op node:$ptr), [{ return isUniformLoad(N);}]> {
+class SMRDLoadPat<PatFrag Op> : PatFrag <(ops node:$ptr), (Op node:$ptr), [{
+ return static_cast<const SITargetLowering *>(getTargetLowering())
+ ->isUniformLoad(cast<LoadSDNode>(N));
+}]> {
let GISelPredicateCode = [{
if (!MI.hasOneMemOperand())
return false;
diff --git a/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll b/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
index 25a488f2b795fb..7fe521102be992 100644
--- a/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
+++ b/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
@@ -126,9 +126,9 @@ define amdgpu_kernel void @d16_two_order_group(ptr addrspace(3) %in1, ptr %in2)
; GFX12-NEXT: flat_load_d16_b16 v0, v[1:2]
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v3, s0
-; GFX12-NEXT: ds_load_u16 v3, v3
+; GFX12-NEXT: ds_load_u16_d16_hi v0, v3
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: v_or_b16 v0.l, v3.l, v0.l
+; GFX12-NEXT: v_or_b16 v0.l, v0.h, v0.l
; GFX12-NEXT: flat_store_b16 v[1:2], v0
; GFX12-NEXT: s_endpgm
%i16a = load i16, ptr addrspace(3) %in1, align 2
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
index 3685fb0d5d18fb..1720f242fcc96d 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
@@ -131,13 +131,13 @@ define amdgpu_kernel void @fcmp_f16_lt(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -303,9 +303,9 @@ define amdgpu_kernel void @fcmp_f16_lt_abs(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
@@ -483,13 +483,13 @@ define amdgpu_kernel void @fcmp_f16_eq(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -655,13 +655,13 @@ define amdgpu_kernel void @fcmp_f16_le(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -827,13 +827,13 @@ define amdgpu_kernel void @fcmp_f16_gt(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -999,13 +999,13 @@ define amdgpu_kernel void @fcmp_f16_lg(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -1171,13 +1171,13 @@ define amdgpu_kernel void @fcmp_f16_ge(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -1343,13 +1343,13 @@ define amdgpu_kernel void @fcmp_f16_o(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -1515,13 +1515,13 @@ define amdgpu_kernel void @fcmp_f16_u(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -1687,13 +1687,13 @@ define amdgpu_kernel void @fcmp_f16_nge(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -1859,13 +1859,13 @@ define amdgpu_kernel void @fcmp_f16_nlg(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -2031,13 +2031,13 @@ define amdgpu_kernel void @fcmp_f16_ngt(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -2203,13 +2203,13 @@ define amdgpu_kernel void @fcmp_f16_nle(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -2375,13 +2375,13 @@ define amdgpu_kernel void @fcmp_f16_neq(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
@@ -2547,13 +2547,13 @@ define amdgpu_kernel void @fcmp_f16_nlt(
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fmax3.ll b/llvm/test/CodeGen/AMDGPU/fmax3.ll
index 6618966a8e1ce4..f34efb4f4af2ba 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax3.ll
@@ -696,15 +696,15 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5
; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6
; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v1.l, v2.l, v0.l
+; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
;
@@ -760,15 +760,15 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13
; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14
; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8
; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9
-; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v1.l, v2.l, v0.l
+; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-TRUE16-NEXT: s_endpgm
;
@@ -1044,24 +1044,24 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
; GFX12-TRUE16-NEXT: s_mov_b32 s15, s11
; GFX12-TRUE16-NEXT: s_mov_b32 s18, s10
; GFX12-TRUE16-NEXT: s_mov_b32 s19, s11
+; GFX12-TRUE16-NEXT: s_mov_b32 s22, s10
+; GFX12-TRUE16-NEXT: s_mov_b32 s23, s11
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s16, s4
; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5
-; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6
-; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7
-; GFX12-TRUE16-NEXT: s_mov_b32 s6, s10
-; GFX12-TRUE16-NEXT: s_mov_b32 s7, s11
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6
+; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v2.l, v1.l, v0.l
+; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v1.l, v0.l, v0.h
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
;
@@ -1108,24 +1108,24 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
; GFX1250-TRUE16-NEXT: s_mov_b32 s7, s3
; GFX1250-TRUE16-NEXT: s_mov_b32 s18, s2
; GFX1250-TRUE16-NEXT: s_mov_b32 s19, s3
+; GFX1250-TRUE16-NEXT: s_mov_b32 s22, s2
+; GFX1250-TRUE16-NEXT: s_mov_b32 s23, s3
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s4, s10
; GFX1250-TRUE16-NEXT: s_mov_b32 s5, s11
; GFX1250-TRUE16-NEXT: s_mov_b32 s16, s12
; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13
-; GFX1250-TRUE16-NEXT: s_mov_b32 s12, s14
-; GFX1250-TRUE16-NEXT: s_mov_b32 s13, s15
-; GFX1250-TRUE16-NEXT: s_mov_b32 s14, s2
-; GFX1250-TRUE16-NEXT: s_mov_b32 s15, s3
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14
+; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15
+; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[12:15], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8
; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9
-; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v2.l, v1.l, v0.l
+; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v1.l, v0.l, v0.h
; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
index dffa28a5c52fd2..213d6ffeb9f00e 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
@@ -1492,11 +1492,11 @@ define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: global_load_u16 v2, v1, s[4:5] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-SDAG-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3.ll b/llvm/test/CodeGen/AMDGPU/fmin3.ll
index bcd50ee8f47fd6..c03e81e6b71299 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3.ll
@@ -696,15 +696,15 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5
; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6
; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v1.l, v2.l, v0.l
+; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
;
@@ -760,15 +760,15 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs
; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13
; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14
; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8
; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9
-; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v1.l, v2.l, v0.l
+; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l
; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-TRUE16-NEXT: s_endpgm
;
@@ -1044,24 +1044,24 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
; GFX12-TRUE16-NEXT: s_mov_b32 s15, s11
; GFX12-TRUE16-NEXT: s_mov_b32 s18, s10
; GFX12-TRUE16-NEXT: s_mov_b32 s19, s11
+; GFX12-TRUE16-NEXT: s_mov_b32 s22, s10
+; GFX12-TRUE16-NEXT: s_mov_b32 s23, s11
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s16, s4
; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5
-; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6
-; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7
-; GFX12-TRUE16-NEXT: s_mov_b32 s6, s10
-; GFX12-TRUE16-NEXT: s_mov_b32 s7, s11
-; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6
+; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[4:7], null scope:SCOPE_SYS
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1
-; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v2.l, v1.l, v0.l
+; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v1.l, v0.l, v0.h
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_endpgm
;
@@ -1108,24 +1108,24 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs
; GFX1250-TRUE16-NEXT: s_mov_b32 s7, s3
; GFX1250-TRUE16-NEXT: s_mov_b32 s18, s2
; GFX1250-TRUE16-NEXT: s_mov_b32 s19, s3
+; GFX1250-TRUE16-NEXT: s_mov_b32 s22, s2
+; GFX1250-TRUE16-NEXT: s_mov_b32 s23, s3
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s4, s10
; GFX1250-TRUE16-NEXT: s_mov_b32 s5, s11
; GFX1250-TRUE16-NEXT: s_mov_b32 s16, s12
; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13
-; GFX1250-TRUE16-NEXT: s_mov_b32 s12, s14
-; GFX1250-TRUE16-NEXT: s_mov_b32 s13, s15
-; GFX1250-TRUE16-NEXT: s_mov_b32 s14, s2
-; GFX1250-TRUE16-NEXT: s_mov_b32 s15, s3
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14
+; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15
+; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[16:19], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[12:15], null scope:SCOPE_SYS
+; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS
; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8
; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9
-; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v2.l, v1.l, v0.l
+; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v1.l, v0.l, v0.h
; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll
index 11acac09aa30f4..094dd76e0f945b 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll
@@ -1492,11 +1492,11 @@ define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-SDAG-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: global_load_u16 v2, v1, s[4:5] scope:SCOPE_SYS
+; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] scope:SCOPE_SYS
; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-SDAG-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index e2ea47c6b27fb0..f202227662c402 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -978,249 +978,244 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-LABEL: frem_f16:
; GFX1200-TRUE16: ; %bb.0:
; GFX1200-TRUE16-NEXT: s_clause 0x1
-; GFX1200-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1200-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v0, 0
+; GFX1200-TRUE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1200-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX1200-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT: s_clause 0x1
-; GFX1200-TRUE16-NEXT: global_load_u16 v1, v0, s[2:3]
-; GFX1200-TRUE16-NEXT: global_load_u16 v0, v0, s[4:5] offset:8
+; GFX1200-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[10:11]
+; GFX1200-TRUE16-NEXT: global_load_d16_b16 v1, v1, s[0:1] offset:8
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
-; GFX1200-TRUE16-NEXT: s_and_b32 s2, s6, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s4, s3, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s5, s2
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s4, s4
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1200-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s2, s1, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s1, s0
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s0, s2
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s5, s4
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s1, s0
; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB0_2
; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s5, s4
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s6
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s6, v0.l, s7
-; GFX1200-TRUE16-NEXT: s_mov_b32 s6, 0
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s1, s0
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v0.l
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s2
+; GFX1200-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX1200-TRUE16-NEXT: s_branch .LBB0_3
; GFX1200-TRUE16-NEXT: .LBB0_2:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s6, -1
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
; GFX1200-TRUE16-NEXT: .LBB0_3: ; %Flow18
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s6, 1
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s4
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s4
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s5
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s5
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s4, v3
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v2
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v3, v3
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v5
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s4, s5, s4
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s0, s1, s0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s4, s4, 11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, 11
; GFX1200-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s4, s4, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s4, 11
-; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
; GFX1200-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
; GFX1200-TRUE16-NEXT: .LBB0_8: ; %Flow19
-; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s2, 0x7c00
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: s_and_b32 s2, s2, s3
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
-; GFX1200-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1200-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
+; GFX1200-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, 0x7c00, v0.l
+; GFX1200-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
+; GFX1200-TRUE16-NEXT: global_store_b16 v3, v0, s[8:9]
; GFX1200-TRUE16-NEXT: s_endpgm
;
; GFX1200-FAKE16-LABEL: frem_f16:
; GFX1200-FAKE16: ; %bb.0:
; GFX1200-FAKE16-NEXT: s_clause 0x1
-; GFX1200-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1200-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, 0
+; GFX1200-FAKE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1200-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GFX1200-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-FAKE16-NEXT: s_clause 0x1
-; GFX1200-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3]
-; GFX1200-FAKE16-NEXT: global_load_u16 v0, v0, s[6:7] offset:8
+; GFX1200-FAKE16-NEXT: global_load_u16 v0, v1, s[10:11]
+; GFX1200-FAKE16-NEXT: global_load_u16 v1, v1, s[0:1] offset:8
; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x1
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s3, v0
-; GFX1200-FAKE16-NEXT: s_and_b32 s2, s4, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s5, s3, 0x7fff
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s6, s2
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s5, s5
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s1, v1
+; GFX1200-FAKE16-NEXT: s_and_b32 s0, s0, 0x7fff
+; GFX1200-FAKE16-NEXT: s_and_b32 s2, s1, 0x7fff
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s1, s0
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s0, s2
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s6, s5
+; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s1, s0
; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB0_2
; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.else
-; GFX1200-FAKE16-NEXT: s_and_b32 s7, 0x8000, s4
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s6, s5
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, s7
-; GFX1200-FAKE16-NEXT: s_mov_b32 s7, 0
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s1, s0
+; GFX1200-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; GFX1200-FAKE16-NEXT: s_mov_b32 s2, 0
; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX1200-FAKE16-NEXT: s_branch .LBB0_3
; GFX1200-FAKE16-NEXT: .LBB0_2:
-; GFX1200-FAKE16-NEXT: s_mov_b32 s7, -1
-; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1200-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr2
; GFX1200-FAKE16-NEXT: .LBB0_3: ; %Flow18
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1200-FAKE16-NEXT: s_cselect_b32 s7, 1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s7, 1
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_9
; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.compute
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s5
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s0
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s1
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
-; GFX1200-FAKE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1200-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s5, v0
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
-; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_not_b32_e32 v4, v0
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1200-FAKE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1200-FAKE16-NEXT: v_not_b32_e32 v6, v2
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-FAKE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1200-FAKE16-NEXT: s_denorm_mode 15
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
-; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX1200-FAKE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v8, v9, v8
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v7, v3, v6
-; GFX1200-FAKE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1200-FAKE16-NEXT: v_fma_f32 v10, -v7, v9, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1200-FAKE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1200-FAKE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB0_8
; GFX1200-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s5, s6, s5
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s0, s1, s0
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_add_co_i32 s5, s5, 11
+; GFX1200-FAKE16-NEXT: s_add_co_i32 s0, s0, 11
; GFX1200-FAKE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_add_co_i32 s5, s5, -11
+; GFX1200-FAKE16-NEXT: s_add_co_i32 s0, s0, -11
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s5, 11
-; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v2, v5, v3
+; GFX1200-FAKE16-NEXT: s_cmp_gt_i32 s0, 11
+; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v4, v7, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v2, v2
-; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_fma_f32 v2, v2, v1, v5
-; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-FAKE16-NEXT: v_add_f32_e32 v4, v2, v1
+; GFX1200-FAKE16-NEXT: v_fma_f32 v4, v4, v3, v7
+; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-FAKE16-NEXT: v_add_f32_e32 v6, v4, v3
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_6
; GFX1200-FAKE16-NEXT: ; %bb.7: ; %Flow
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, s5
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, s0
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, v7
; GFX1200-FAKE16-NEXT: .LBB0_8: ; %frem.loop_exit
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v2, v3
-; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v2, v3, v1
+; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v4, v5, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-FAKE16-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX1200-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v4, v3
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v0, v1, v0
-; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s4
+; GFX1200-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
; GFX1200-FAKE16-NEXT: .LBB0_9: ; %Flow19
-; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s3, 0
-; GFX1200-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1200-FAKE16-NEXT: s_cmp_nge_f16 s2, 0x7c00
-; GFX1200-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s2, s3
+; GFX1200-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
+; GFX1200-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-FAKE16-NEXT: v_cmp_nle_f16_e64 s0, 0x7c00, v0
+; GFX1200-FAKE16-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_cndmask_b32 v0, 0x7e00, v0
-; GFX1200-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX1200-FAKE16-NEXT: global_store_b16 v3, v0, s[8:9]
; GFX1200-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %in2) #0 {
%gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4
@@ -1641,35 +1636,34 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1200-TRUE16-NEXT: s_clause 0x1
; GFX1200-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1200-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX1200-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT: s_clause 0x1
-; GFX1200-TRUE16-NEXT: global_load_u16 v3, v2, s[2:3]
-; GFX1200-TRUE16-NEXT: global_load_u16 v4, v2, s[4:5] offset:8
+; GFX1200-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[2:3]
+; GFX1200-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] offset:8
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v4.l
+; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v1, v3, v0, neg(0) op_sel_hi:[1,0,0]
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0]
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v4, v1, v3 op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v1, v5, v0
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v4, v1, v3 op_sel_hi:[1,0,1]
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v4.l, v1.l
+; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v0.l, v4.l
-; GFX1200-TRUE16-NEXT: global_store_b16 v2, v3, s[0:1]
+; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
+; GFX1200-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
;
; GFX1200-FAKE16-LABEL: fast_frem_f16:
@@ -2125,35 +2119,34 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1200-TRUE16-NEXT: s_clause 0x1
; GFX1200-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1200-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX1200-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT: s_clause 0x1
-; GFX1200-TRUE16-NEXT: global_load_u16 v3, v2, s[2:3]
-; GFX1200-TRUE16-NEXT: global_load_u16 v4, v2, s[4:5] offset:8
+; GFX1200-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[2:3]
+; GFX1200-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] offset:8
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v4.l
+; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v0, v0
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v1, v3, v0, neg(0) op_sel_hi:[1,0,0]
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0]
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v4, v1, v3 op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v1, v5, v0
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v4, v1, v3 op_sel_hi:[1,0,1]
+; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1]
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v4.l, v1.l
+; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v0.l, v4.l
-; GFX1200-TRUE16-NEXT: global_store_b16 v2, v3, s[0:1]
+; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
+; GFX1200-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
;
; GFX1200-FAKE16-LABEL: unsafe_frem_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
index 14886857fa2f08..9a569fd127d73a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
@@ -102,7 +102,7 @@ define amdgpu_kernel void @cos_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0.15915494, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
index 1c035c4709babe..ad690fe234bc79 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
@@ -96,7 +96,7 @@ define amdgpu_kernel void @rint_f16(
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_rndne_f16_e32 v0.l, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
index 0a5df29922f452..d8f53af61b3431 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
@@ -102,7 +102,7 @@ define amdgpu_kernel void @sin_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3]
+; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0.15915494, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
index 14945be58876a2..30d966eb1b7c2f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll
@@ -23,7 +23,7 @@ define amdgpu_kernel void @sqrt_bf16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s4, s0
-; GFX12-TRUE16-SDAG-NEXT: buffer_load_u16 v0, off, s[8:11], null
+; GFX12-TRUE16-SDAG-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-SDAG-NEXT: v_sqrt_bf16_e32 v0.l, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
index c9f4e1993cd736..bcaba060b812fa 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
@@ -129,7 +129,7 @@ define amdgpu_kernel void @sqrt_f16(
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s4, s0
-; GFX12-TRUE16-SDAG-NEXT: buffer_load_u16 v0, off, s[8:11], null
+; GFX12-TRUE16-SDAG-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null
; GFX12-TRUE16-SDAG-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-SDAG-NEXT: v_sqrt_f16_e32 v0.l, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
index 9715cb0e3ee5b8..4664a4475d22ac 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
@@ -95,7 +95,7 @@ define amdgpu_kernel void @trunc_f16(
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
-; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
+; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
index b1184b56f4b79e..99b77b1517bd2b 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
@@ -9,11 +9,13 @@ define amdgpu_kernel void @exp_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[GLOBAL_LOAD_USHORT_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
- ; CHECK-NEXT: [[V_EXP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_EXP_F16_t16_e64 0, [[GLOBAL_LOAD_USHORT_SADDR]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_EXP_F16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[V_EXP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_EXP_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_EXP_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
@@ -30,11 +32,13 @@ define amdgpu_kernel void @log_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[GLOBAL_LOAD_USHORT_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
- ; CHECK-NEXT: [[V_LOG_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_LOG_F16_t16_e64 0, [[GLOBAL_LOAD_USHORT_SADDR]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_LOG_F16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[V_LOG_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_LOG_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_LOG_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
@@ -51,11 +55,13 @@ define amdgpu_kernel void @rcp_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[GLOBAL_LOAD_USHORT_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
- ; CHECK-NEXT: [[V_RCP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RCP_F16_t16_e64 0, [[GLOBAL_LOAD_USHORT_SADDR]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RCP_F16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[V_RCP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RCP_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RCP_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
@@ -72,11 +78,13 @@ define amdgpu_kernel void @rsq_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[GLOBAL_LOAD_USHORT_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
- ; CHECK-NEXT: [[V_RSQ_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RSQ_F16_t16_e64 0, [[GLOBAL_LOAD_USHORT_SADDR]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RSQ_F16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[V_RSQ_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RSQ_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RSQ_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
@@ -93,11 +101,13 @@ define amdgpu_kernel void @sqrt_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; CHECK-NEXT: [[GLOBAL_LOAD_USHORT_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT_SADDR [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
- ; CHECK-NEXT: [[V_SQRT_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_SQRT_F16_t16_e64 0, [[GLOBAL_LOAD_USHORT_SADDR]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_SQRT_F16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[V_SQRT_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_SQRT_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_SQRT_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
>From 4563085a7cdcabc227a80a24fa8c182626a9edd8 Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Mon, 28 Sep 2026 22:00:15 -0500
Subject: [PATCH 6/7] Remove TODO
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 9 +-
llvm/test/CodeGen/AMDGPU/frem.ll | 5267 ++++++++---------
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 327 +-
3 files changed, 2667 insertions(+), 2936 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 40e87a701c5f32..30d899f2cc4942 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -846,7 +846,14 @@ bool AMDGPUTargetLowering::shouldReduceLoadWidth(
unsigned AS = MN->getAddressSpace();
// Do not shrink an aligned scalar load to sub-dword.
// Scalar engine cannot do sub-dword loads.
- // TODO: Update this for GFX12 which does have scalar sub-dword loads.
+ // Do not enable for gfx1250+ even though it has sub-dword loads because
+ // this will convert:
+ // i16 = trunc (zextload i16->i32)
+ // to:
+ // i16 = (load i16)
+ // This transformation will be reversed by LowerLOAD resulting in an infinite
+ // loop. Also, tablegen already has a pattern to match zextload i16->i32, but
+ // load i16 will not be matched since there is no instruction that does it.
if (OldSize >= 32 && NewSize < 32 && MN->getAlign() >= Align(4) &&
(AS == AMDGPUAS::CONSTANT_ADDRESS ||
AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index f202227662c402..267e722b406193 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -36,16 +36,15 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v4
; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_branch .LBB0_3
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cbranch_scc1 .LBB0_3
+; SI-NEXT: s_branch .LBB0_8
; SI-NEXT: .LBB0_2:
; SI-NEXT: s_mov_b64 s[0:1], -1
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: .LBB0_3: ; %Flow18
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s0, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s0, 1
-; SI-NEXT: s_cbranch_scc1 .LBB0_9
-; SI-NEXT: ; %bb.4: ; %frem.compute
+; SI-NEXT: s_cbranch_scc0 .LBB0_8
+; SI-NEXT: .LBB0_3: ; %frem.compute
; SI-NEXT: s_mov_b32 s3, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
@@ -80,11 +79,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB0_8
-; SI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB0_7
+; SI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s1, s2, s3
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB0_6: ; %frem.loop_body
+; SI-NEXT: .LBB0_5: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v5, v3
; SI-NEXT: v_mul_f32_e32 v3, v5, v4
@@ -96,10 +95,10 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB0_6
-; SI-NEXT: ; %bb.7: ; %Flow
+; SI-NEXT: s_cbranch_scc1 .LBB0_5
+; SI-NEXT: ; %bb.6: ; %Flow
; SI-NEXT: v_mov_b32_e32 v3, v5
-; SI-NEXT: .LBB0_8: ; %frem.loop_exit
+; SI-NEXT: .LBB0_7: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s1, s1, -10
; SI-NEXT: v_ldexp_f32_e64 v3, v3, s1
; SI-NEXT: v_mul_f32_e32 v4, v3, v4
@@ -113,7 +112,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_and_b32_e32 v3, 0x8000, v0
; SI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: .LBB0_9: ; %Flow19
+; SI-NEXT: .LBB0_8: ; %Flow19
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; SI-NEXT: s_mov_b32 s0, 0x7f800000
@@ -151,16 +150,15 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_branch .LBB0_3
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cbranch_scc1 .LBB0_3
+; CI-NEXT: s_branch .LBB0_8
; CI-NEXT: .LBB0_2:
; CI-NEXT: s_mov_b64 s[0:1], -1
; CI-NEXT: ; implicit-def: $vgpr2
-; CI-NEXT: .LBB0_3: ; %Flow18
; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cselect_b32 s0, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s0, 1
-; CI-NEXT: s_cbranch_scc1 .LBB0_9
-; CI-NEXT: ; %bb.4: ; %frem.compute
+; CI-NEXT: s_cbranch_scc0 .LBB0_8
+; CI-NEXT: .LBB0_3: ; %frem.compute
; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
; CI-NEXT: v_frexp_mant_f32_e32 v2, v4
; CI-NEXT: v_frexp_mant_f32_e32 v4, v3
@@ -184,11 +182,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB0_8
-; CI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB0_7
+; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT: v_add_i32_e32 v4, vcc, 11, v4
-; CI-NEXT: .LBB0_6: ; %frem.loop_body
+; CI-NEXT: .LBB0_5: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v7, v5
; CI-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -200,10 +198,10 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11
-; CI-NEXT: s_cbranch_vccnz .LBB0_6
-; CI-NEXT: ; %bb.7: ; %Flow
+; CI-NEXT: s_cbranch_vccnz .LBB0_5
+; CI-NEXT: ; %bb.6: ; %Flow
; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: .LBB0_8: ; %frem.loop_exit
+; CI-NEXT: .LBB0_7: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v4, vcc, -10, v4
; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT: v_mul_f32_e32 v5, v4, v6
@@ -217,7 +215,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_and_b32_e32 v3, 0x8000, v0
; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; CI-NEXT: v_or_b32_e32 v2, v2, v3
-; CI-NEXT: .LBB0_9: ; %Flow19
+; CI-NEXT: .LBB0_8: ; %Flow19
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; CI-NEXT: s_mov_b32 s0, 0x7f800000
@@ -255,16 +253,15 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB0_3
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB0_3
+; VI-NEXT: s_branch .LBB0_8
; VI-NEXT: .LBB0_2:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr2
-; VI-NEXT: .LBB0_3: ; %Flow18
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB0_9
-; VI-NEXT: ; %bb.4: ; %frem.compute
+; VI-NEXT: s_cbranch_scc0 .LBB0_8
+; VI-NEXT: .LBB0_3: ; %frem.compute
; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
; VI-NEXT: v_frexp_mant_f32_e32 v2, v4
; VI-NEXT: v_frexp_mant_f32_e32 v4, v3
@@ -288,11 +285,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
; VI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB0_8
-; VI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB0_7
+; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT: v_add_u32_e32 v4, vcc, 11, v4
-; VI-NEXT: .LBB0_6: ; %frem.loop_body
+; VI-NEXT: .LBB0_5: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v7, v5
; VI-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -304,10 +301,10 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
; VI-NEXT: v_ldexp_f32 v5, v5, 11
-; VI-NEXT: s_cbranch_vccnz .LBB0_6
-; VI-NEXT: ; %bb.7: ; %Flow
+; VI-NEXT: s_cbranch_vccnz .LBB0_5
+; VI-NEXT: ; %bb.6: ; %Flow
; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: .LBB0_8: ; %frem.loop_exit
+; VI-NEXT: .LBB0_7: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v4, vcc, -10, v4
; VI-NEXT: v_ldexp_f32 v4, v5, v4
; VI-NEXT: v_mul_f32_e32 v5, v4, v6
@@ -320,7 +317,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_cvt_f16_f32_e32 v2, v2
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; VI-NEXT: .LBB0_9: ; %Flow19
+; VI-NEXT: .LBB0_8: ; %Flow19
; VI-NEXT: v_mov_b32_e32 v3, s0
; VI-NEXT: s_movk_i32 s0, 0x7c00
; VI-NEXT: v_mov_b32_e32 v4, s1
@@ -351,16 +348,15 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB0_3
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX9-NEXT: s_branch .LBB0_8
; GFX9-NEXT: .LBB0_2:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr2
-; GFX9-NEXT: .LBB0_3: ; %Flow18
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB0_9
-; GFX9-NEXT: ; %bb.4: ; %frem.compute
+; GFX9-NEXT: s_cbranch_scc0 .LBB0_8
+; GFX9-NEXT: .LBB0_3: ; %frem.compute
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
; GFX9-NEXT: v_frexp_mant_f32_e32 v2, v4
; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v3
@@ -384,11 +380,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
; GFX9-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB0_8
-; GFX9-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX9-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT: v_add_u32_e32 v4, 11, v4
-; GFX9-NEXT: .LBB0_6: ; %frem.loop_body
+; GFX9-NEXT: .LBB0_5: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -400,10 +396,10 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
; GFX9-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB0_6
-; GFX9-NEXT: ; %bb.7: ; %Flow
+; GFX9-NEXT: s_cbranch_vccnz .LBB0_5
+; GFX9-NEXT: ; %bb.6: ; %Flow
; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX9-NEXT: .LBB0_7: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v4, -10, v4
; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
; GFX9-NEXT: v_mul_f32_e32 v5, v4, v6
@@ -416,7 +412,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v2, s2, v2, v0
-; GFX9-NEXT: .LBB0_9: ; %Flow19
+; GFX9-NEXT: .LBB0_8: ; %Flow19
; GFX9-NEXT: s_movk_i32 s2, 0x7c00
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v1
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v0|, s2
@@ -440,36 +436,35 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_cvt_f32_f16_e64 v4, |v0|
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v2, |v1|
-; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v2
+; GFX10-NEXT: v_cvt_f32_f16_e64 v3, |v1|
+; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v3
; GFX10-NEXT: s_cbranch_vccz .LBB0_2
; GFX10-NEXT: ; %bb.1: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v3, 0x8000, v0
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v2
+; GFX10-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc_lo
-; GFX10-NEXT: s_branch .LBB0_3
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX10-NEXT: s_branch .LBB0_8
; GFX10-NEXT: .LBB0_2:
; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr3
-; GFX10-NEXT: .LBB0_3: ; %Flow18
+; GFX10-NEXT: ; implicit-def: $vgpr2
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB0_9
-; GFX10-NEXT: ; %bb.4: ; %frem.compute
-; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v4
+; GFX10-NEXT: s_cbranch_scc0 .LBB0_8
+; GFX10-NEXT: .LBB0_3: ; %frem.compute
+; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v4
+; GFX10-NEXT: v_frexp_mant_f32_e32 v6, v3
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; GFX10-NEXT: v_ldexp_f32 v4, v3, 11
-; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v2
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
+; GFX10-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
+; GFX10-NEXT: v_ldexp_f32 v3, v6, 1
; GFX10-NEXT: v_readfirstlane_b32 s2, v5
-; GFX10-NEXT: v_ldexp_f32 v3, v3, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v2
-; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX10-NEXT: v_div_scale_f32 v7, s4, v3, v3, 1.0
-; GFX10-NEXT: v_not_b32_e32 v6, v2
+; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX10-NEXT: v_rcp_f32_e32 v8, v7
+; GFX10-NEXT: v_not_b32_e32 v6, v2
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -483,11 +478,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX10-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB0_8
-; GFX10-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX10-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB0_6: ; %frem.loop_body
+; GFX10-NEXT: .LBB0_5: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -499,11 +494,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_add_f32_e32 v6, v4, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX10-NEXT: ; %bb.7: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB0_5
+; GFX10-NEXT: ; %bb.6: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v6, s2
; GFX10-NEXT: v_mov_b32_e32 v4, v7
-; GFX10-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX10-NEXT: .LBB0_7: ; %frem.loop_exit
; GFX10-NEXT: v_add_nc_u32_e32 v6, -10, v6
; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v5
@@ -514,14 +509,14 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v2, v3, v2
; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX10-NEXT: v_bfi_b32 v3, 0x7fff, v2, v0
-; GFX10-NEXT: .LBB0_9: ; %Flow19
+; GFX10-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
+; GFX10-NEXT: .LBB0_8: ; %Flow19
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
-; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
-; GFX10-NEXT: global_store_short v2, v0, s[0:1]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX10-NEXT: global_store_short v3, v0, s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-TRUE16-LABEL: frem_f16:
@@ -546,17 +541,16 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB0_3
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX11-TRUE16-NEXT: s_branch .LBB0_7
; GFX11-TRUE16-NEXT: .LBB0_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX11-TRUE16-NEXT: .LBB0_3: ; %Flow18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
-; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB0_7
+; GFX11-TRUE16-NEXT: .LBB0_3: ; %frem.compute
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v3
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, v3
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v2
@@ -590,12 +584,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
-; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_6
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB0_5: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -610,10 +604,10 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX11-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_5
+; GFX11-TRUE16-NEXT: .LBB0_6: ; %frem.loop_exit
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX11-TRUE16-NEXT: .LBB0_8: ; %Flow19
+; GFX11-TRUE16-NEXT: .LBB0_7: ; %Flow19
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.h
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
@@ -636,43 +630,42 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v4, |v0|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v2, |v1|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, |v1|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v2
+; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v3
; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB0_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.else
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0x8000, v0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB0_3
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX11-FAKE16-NEXT: s_branch .LBB0_8
; GFX11-FAKE16-NEXT: .LBB0_2:
; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3
-; GFX11-FAKE16-NEXT: .LBB0_3: ; %Flow18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB0_9
-; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.compute
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v4
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB0_8
+; GFX11-FAKE16-NEXT: .LBB0_3: ; %frem.compute
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, v4
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v6, v3
; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v3, 11
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v2
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v6, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX11-FAKE16-NEXT: v_not_b32_e32 v6, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_not_b32_e32 v6, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-FAKE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -691,12 +684,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB0_8
-; GFX11-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB0_6: ; %frem.loop_body
+; GFX11-FAKE16-NEXT: .LBB0_5: ; %frem.loop_body
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -712,11 +705,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX11-FAKE16-NEXT: ; %bb.7: ; %Flow
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB0_5
+; GFX11-FAKE16-NEXT: ; %bb.6: ; %Flow
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, s2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-FAKE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX11-FAKE16-NEXT: .LBB0_7: ; %frem.loop_exit
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
@@ -732,14 +725,13 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: v_ldexp_f32 v2, v3, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_bfi_b32 v3, 0x7fff, v2, v0
-; GFX11-FAKE16-NEXT: .LBB0_9: ; %Flow19
+; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
+; GFX11-FAKE16-NEXT: .LBB0_8: ; %Flow19
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7e00, v3, vcc_lo
-; GFX11-FAKE16-NEXT: global_store_b16 v2, v0, s[0:1]
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, 0x7e00, v2
+; GFX11-FAKE16-NEXT: global_store_b16 v3, v0, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX1150-TRUE16-LABEL: frem_f16:
@@ -770,17 +762,17 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s2
; GFX1150-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB0_3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX1150-TRUE16-NEXT: s_branch .LBB0_7
; GFX1150-TRUE16-NEXT: .LBB0_2:
; GFX1150-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB0_3: ; %Flow18
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
-; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB0_7
+; GFX1150-TRUE16-NEXT: .LBB0_3: ; %frem.compute
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
@@ -813,12 +805,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
-; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_6
+; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s0, s1, s0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s0, s0, 11
-; GFX1150-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: .LBB0_5: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -834,10 +826,10 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1150-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_5
+; GFX1150-TRUE16-NEXT: .LBB0_6: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB0_8: ; %Flow19
+; GFX1150-TRUE16-NEXT: .LBB0_7: ; %Flow19
; GFX1150-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1150-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
@@ -875,17 +867,16 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB0_3
+; GFX1150-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX1150-FAKE16-NEXT: s_branch .LBB0_8
; GFX1150-FAKE16-NEXT: .LBB0_2:
; GFX1150-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-FAKE16-NEXT: .LBB0_3: ; %Flow18
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB0_9
-; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB0_8
+; GFX1150-FAKE16-NEXT: .LBB0_3: ; %frem.compute
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s0
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s1
; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
@@ -919,12 +910,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB0_8
-; GFX1150-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX1150-FAKE16-NEXT: s_sub_i32 s0, s1, s0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s0, s0, 11
-; GFX1150-FAKE16-NEXT: .LBB0_6: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT: .LBB0_5: ; %frem.loop_body
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -942,11 +933,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1150-FAKE16-NEXT: ; %bb.7: ; %Flow
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB0_5
+; GFX1150-FAKE16-NEXT: ; %bb.6: ; %Flow
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, s0
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX1150-FAKE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX1150-FAKE16-NEXT: .LBB0_7: ; %frem.loop_exit
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
@@ -965,7 +956,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX1150-FAKE16-NEXT: .LBB0_9: ; %Flow19
+; GFX1150-FAKE16-NEXT: .LBB0_8: ; %Flow19
; GFX1150-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1150-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -1003,18 +994,17 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s2
; GFX1200-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB0_3
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX1200-TRUE16-NEXT: s_branch .LBB0_7
; GFX1200-TRUE16-NEXT: .LBB0_2:
; GFX1200-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB0_3: ; %Flow18
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
-; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB0_7
+; GFX1200-TRUE16-NEXT: .LBB0_3: ; %frem.compute
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
@@ -1047,12 +1037,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
-; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_6
+; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s0, s1, s0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, 11
-; GFX1200-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: .LBB0_5: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -1071,10 +1061,10 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1200-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_5
+; GFX1200-TRUE16-NEXT: .LBB0_6: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB0_8: ; %Flow19
+; GFX1200-TRUE16-NEXT: .LBB0_7: ; %Flow19
; GFX1200-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1200-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -1113,17 +1103,16 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB0_3
+; GFX1200-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX1200-FAKE16-NEXT: s_branch .LBB0_8
; GFX1200-FAKE16-NEXT: .LBB0_2:
; GFX1200-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-FAKE16-NEXT: .LBB0_3: ; %Flow18
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_9
-; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.compute
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB0_8
+; GFX1200-FAKE16-NEXT: .LBB0_3: ; %frem.compute
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s0
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s1
; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
@@ -1158,12 +1147,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB0_8
-; GFX1200-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s0, s1, s0
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s0, s0, 11
-; GFX1200-FAKE16-NEXT: .LBB0_6: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT: .LBB0_5: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -1183,11 +1172,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1200-FAKE16-NEXT: ; %bb.7: ; %Flow
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_5
+; GFX1200-FAKE16-NEXT: ; %bb.6: ; %Flow
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, s0
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX1200-FAKE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX1200-FAKE16-NEXT: .LBB0_7: ; %frem.loop_exit
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
@@ -1207,7 +1196,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX1200-FAKE16-NEXT: .LBB0_9: ; %Flow19
+; GFX1200-FAKE16-NEXT: .LBB0_8: ; %Flow19
; GFX1200-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1200-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -1485,8 +1474,7 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX10-NEXT: v_mad_f32 v3, -v3, v5, v6
; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4
; GFX10-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX10-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v5 op_sel_hi:[0,1,0]
; GFX10-NEXT: v_div_fixup_f16 v3, v3, v2, v1
; GFX10-NEXT: v_trunc_f16_e32 v3, v3
; GFX10-NEXT: v_fma_f16 v1, -v3, v2, v1
@@ -1517,12 +1505,10 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
; GFX11-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_f16 v0.l, -v0.l, v3.l, v2.l
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -1551,12 +1537,10 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
; GFX11-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fma_f16 v1, -v3, v2, v1
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -1584,14 +1568,12 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX1150-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1150-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
; GFX1150-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
; GFX1150-TRUE16-NEXT: s_endpgm
@@ -1619,14 +1601,12 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX1150-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX1150-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_xor_b32_e32 v3, 0x8000, v3
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_fmac_f16_e32 v1, v3, v2
; GFX1150-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1150-FAKE16-NEXT: s_endpgm
@@ -1654,14 +1634,12 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX1200-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
; GFX1200-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
@@ -1689,14 +1667,12 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX1200-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v3, 0x8000, v3
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_fmac_f16_e32 v1, v3, v2
; GFX1200-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1200-FAKE16-NEXT: s_endpgm
@@ -1968,8 +1944,7 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX10-NEXT: v_mad_f32 v3, -v3, v5, v6
; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4
; GFX10-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX10-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v5 op_sel_hi:[0,1,0]
; GFX10-NEXT: v_div_fixup_f16 v3, v3, v2, v1
; GFX10-NEXT: v_trunc_f16_e32 v3, v3
; GFX10-NEXT: v_fma_f16 v1, -v3, v2, v1
@@ -2000,12 +1975,10 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
; GFX11-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_f16 v0.l, -v0.l, v3.l, v2.l
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
@@ -2034,12 +2007,10 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
; GFX11-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_fma_f16 v1, -v3, v2, v1
; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
@@ -2067,14 +2038,12 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX1150-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1150-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
; GFX1150-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
; GFX1150-TRUE16-NEXT: s_endpgm
@@ -2102,14 +2071,12 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX1150-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX1150-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_xor_b32_e32 v3, 0x8000, v3
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_fmac_f16_e32 v1, v3, v2
; GFX1150-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1150-FAKE16-NEXT: s_endpgm
@@ -2137,14 +2104,12 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX1200-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, 1.0, v4 op_sel_hi:[0,1,0]
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
; GFX1200-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
@@ -2172,14 +2137,12 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX1200-FAKE16-NEXT: v_fma_mixlo_f16 v3, v3, 1.0, v4 op_sel_hi:[0,1,0]
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_trunc_f16_e32 v3, v3
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_xor_b32_e32 v3, 0x8000, v3
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_fmac_f16_e32 v1, v3, v2
; GFX1200-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1200-FAKE16-NEXT: s_endpgm
@@ -2215,16 +2178,15 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_branch .LBB3_3
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cbranch_scc1 .LBB3_3
+; SI-NEXT: s_branch .LBB3_8
; SI-NEXT: .LBB3_2:
; SI-NEXT: s_mov_b64 s[2:3], -1
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: .LBB3_3: ; %Flow16
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cselect_b32 s2, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s2, 1
-; SI-NEXT: s_cbranch_scc1 .LBB3_9
-; SI-NEXT: ; %bb.4: ; %frem.compute
+; SI-NEXT: s_cbranch_scc0 .LBB3_8
+; SI-NEXT: .LBB3_3: ; %frem.compute
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
@@ -2259,11 +2221,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB3_8
-; SI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB3_7
+; SI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB3_6: ; %frem.loop_body
+; SI-NEXT: .LBB3_5: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v5, v3
; SI-NEXT: v_mul_f32_e32 v3, v5, v4
@@ -2275,10 +2237,10 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v3, v3, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB3_6
-; SI-NEXT: ; %bb.7: ; %Flow
+; SI-NEXT: s_cbranch_scc1 .LBB3_5
+; SI-NEXT: ; %bb.6: ; %Flow
; SI-NEXT: v_mov_b32_e32 v3, v5
-; SI-NEXT: .LBB3_8: ; %frem.loop_exit
+; SI-NEXT: .LBB3_7: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s3, s3, -11
; SI-NEXT: v_ldexp_f32_e64 v3, v3, s3
; SI-NEXT: v_mul_f32_e32 v4, v3, v4
@@ -2290,7 +2252,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_ldexp_f32_e64 v2, v2, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; SI-NEXT: .LBB3_9: ; %Flow17
+; SI-NEXT: .LBB3_8: ; %Flow17
; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT: v_cmp_nge_f32_e64 s[4:5], |v0|, s4
@@ -2324,16 +2286,15 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_branch .LBB3_3
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB3_3
+; CI-NEXT: s_branch .LBB3_8
; CI-NEXT: .LBB3_2:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr2
-; CI-NEXT: .LBB3_3: ; %Flow16
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB3_9
-; CI-NEXT: ; %bb.4: ; %frem.compute
+; CI-NEXT: s_cbranch_scc0 .LBB3_8
+; CI-NEXT: .LBB3_3: ; %frem.compute
; CI-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; CI-NEXT: v_ldexp_f32_e64 v3, v3, 1
; CI-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
@@ -2357,11 +2318,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB3_8
-; CI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB3_7
+; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT: v_add_i32_e32 v4, vcc, 12, v4
-; CI-NEXT: .LBB3_6: ; %frem.loop_body
+; CI-NEXT: .LBB3_5: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v7, v5
; CI-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -2373,10 +2334,10 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_add_i32_e32 v4, vcc, -12, v4
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
; CI-NEXT: v_ldexp_f32_e64 v5, v5, 12
-; CI-NEXT: s_cbranch_vccnz .LBB3_6
-; CI-NEXT: ; %bb.7: ; %Flow
+; CI-NEXT: s_cbranch_vccnz .LBB3_5
+; CI-NEXT: ; %bb.6: ; %Flow
; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: .LBB3_8: ; %frem.loop_exit
+; CI-NEXT: .LBB3_7: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT: v_mul_f32_e32 v5, v4, v6
@@ -2388,7 +2349,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; CI-NEXT: .LBB3_9: ; %Flow17
+; CI-NEXT: .LBB3_8: ; %Flow17
; CI-NEXT: s_mov_b32 s4, 0x7f800000
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT: v_cmp_nge_f32_e64 s[4:5], |v0|, s4
@@ -2422,16 +2383,15 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB3_3
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB3_3
+; VI-NEXT: s_branch .LBB3_8
; VI-NEXT: .LBB3_2:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr2
-; VI-NEXT: .LBB3_3: ; %Flow16
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB3_9
-; VI-NEXT: ; %bb.4: ; %frem.compute
+; VI-NEXT: s_cbranch_scc0 .LBB3_8
+; VI-NEXT: .LBB3_3: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; VI-NEXT: v_ldexp_f32 v3, v3, 1
; VI-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
@@ -2455,11 +2415,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
; VI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB3_8
-; VI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB3_7
+; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v4
-; VI-NEXT: .LBB3_6: ; %frem.loop_body
+; VI-NEXT: .LBB3_5: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v7, v5
; VI-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -2471,10 +2431,10 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_add_u32_e32 v4, vcc, -12, v4
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
; VI-NEXT: v_ldexp_f32 v5, v5, 12
-; VI-NEXT: s_cbranch_vccnz .LBB3_6
-; VI-NEXT: ; %bb.7: ; %Flow
+; VI-NEXT: s_cbranch_vccnz .LBB3_5
+; VI-NEXT: ; %bb.6: ; %Flow
; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: .LBB3_8: ; %frem.loop_exit
+; VI-NEXT: .LBB3_7: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
; VI-NEXT: v_ldexp_f32 v4, v5, v4
; VI-NEXT: v_mul_f32_e32 v5, v4, v6
@@ -2486,7 +2446,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_ldexp_f32 v2, v3, v2
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; VI-NEXT: .LBB3_9: ; %Flow17
+; VI-NEXT: .LBB3_8: ; %Flow17
; VI-NEXT: v_mov_b32_e32 v3, s0
; VI-NEXT: s_mov_b32 s0, 0x7f800000
; VI-NEXT: v_mov_b32_e32 v4, s1
@@ -2515,16 +2475,15 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB3_3
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB3_3
+; GFX9-NEXT: s_branch .LBB3_8
; GFX9-NEXT: .LBB3_2:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr2
-; GFX9-NEXT: .LBB3_3: ; %Flow16
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB3_9
-; GFX9-NEXT: ; %bb.4: ; %frem.compute
+; GFX9-NEXT: s_cbranch_scc0 .LBB3_8
+; GFX9-NEXT: .LBB3_3: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; GFX9-NEXT: v_ldexp_f32 v3, v3, 1
; GFX9-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
@@ -2548,11 +2507,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
; GFX9-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB3_8
-; GFX9-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB3_7
+; GFX9-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT: v_add_u32_e32 v4, 12, v4
-; GFX9-NEXT: .LBB3_6: ; %frem.loop_body
+; GFX9-NEXT: .LBB3_5: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -2564,10 +2523,10 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
; GFX9-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB3_6
-; GFX9-NEXT: ; %bb.7: ; %Flow
+; GFX9-NEXT: s_cbranch_vccnz .LBB3_5
+; GFX9-NEXT: ; %bb.6: ; %Flow
; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: .LBB3_8: ; %frem.loop_exit
+; GFX9-NEXT: .LBB3_7: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v4, -11, v4
; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
; GFX9-NEXT: v_mul_f32_e32 v5, v4, v6
@@ -2579,7 +2538,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_ldexp_f32 v2, v3, v2
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v2, s2, v2, v0
-; GFX9-NEXT: .LBB3_9: ; %Flow17
+; GFX9-NEXT: .LBB3_8: ; %Flow17
; GFX9-NEXT: s_mov_b32 s2, 0x7f800000
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; GFX9-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s2
@@ -2609,16 +2568,15 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX10-NEXT: s_branch .LBB3_3
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB3_3
+; GFX10-NEXT: s_branch .LBB3_8
; GFX10-NEXT: .LBB3_2:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr2
-; GFX10-NEXT: .LBB3_3: ; %Flow16
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB3_9
-; GFX10-NEXT: ; %bb.4: ; %frem.compute
+; GFX10-NEXT: s_cbranch_scc0 .LBB3_8
+; GFX10-NEXT: .LBB3_3: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; GFX10-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
@@ -2644,11 +2602,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX10-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB3_8
-; GFX10-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB3_7
+; GFX10-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB3_6: ; %frem.loop_body
+; GFX10-NEXT: .LBB3_5: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -2660,11 +2618,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_add_f32_e32 v6, v4, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB3_6
-; GFX10-NEXT: ; %bb.7: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB3_5
+; GFX10-NEXT: ; %bb.6: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v6, s2
; GFX10-NEXT: v_mov_b32_e32 v4, v7
-; GFX10-NEXT: .LBB3_8: ; %frem.loop_exit
+; GFX10-NEXT: .LBB3_7: ; %frem.loop_exit
; GFX10-NEXT: v_add_nc_u32_e32 v6, -11, v6
; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v5
@@ -2675,7 +2633,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v2, v3, v2
; GFX10-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v0
-; GFX10-NEXT: .LBB3_9: ; %Flow17
+; GFX10-NEXT: .LBB3_8: ; %Flow17
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v1
; GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX10-NEXT: v_mov_b32_e32 v3, 0
@@ -2703,17 +2661,16 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX11-NEXT: s_branch .LBB3_3
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB3_3
+; GFX11-NEXT: s_branch .LBB3_8
; GFX11-NEXT: .LBB3_2:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr2
-; GFX11-NEXT: .LBB3_3: ; %Flow16
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB3_9
-; GFX11-NEXT: ; %bb.4: ; %frem.compute
+; GFX11-NEXT: s_cbranch_scc0 .LBB3_8
+; GFX11-NEXT: .LBB3_3: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; GFX11-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
@@ -2748,12 +2705,12 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB3_8
-; GFX11-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB3_7
+; GFX11-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB3_6: ; %frem.loop_body
+; GFX11-NEXT: .LBB3_5: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v7, v4
@@ -2769,11 +2726,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB3_6
-; GFX11-NEXT: ; %bb.7: ; %Flow
+; GFX11-NEXT: s_cbranch_scc1 .LBB3_5
+; GFX11-NEXT: ; %bb.6: ; %Flow
; GFX11-NEXT: v_mov_b32_e32 v6, s2
; GFX11-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-NEXT: .LBB3_8: ; %frem.loop_exit
+; GFX11-NEXT: .LBB3_7: ; %frem.loop_exit
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_nc_u32_e32 v6, -11, v6
; GFX11-NEXT: v_ldexp_f32 v4, v4, v6
@@ -2789,7 +2746,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_ldexp_f32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v0
-; GFX11-NEXT: .LBB3_9: ; %Flow17
+; GFX11-NEXT: .LBB3_8: ; %Flow17
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -2820,17 +2777,16 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: s_mov_b32 s0, 0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT: v_cndmask_b32_e32 v3, v2, v4, vcc_lo
-; GFX1150-NEXT: s_branch .LBB3_3
+; GFX1150-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB3_3
+; GFX1150-NEXT: s_branch .LBB3_8
; GFX1150-NEXT: .LBB3_2:
; GFX1150-NEXT: s_mov_b32 s0, -1
; GFX1150-NEXT: ; implicit-def: $vgpr3
-; GFX1150-NEXT: .LBB3_3: ; %Flow16
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s0, s0, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s0, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s0, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB3_9
-; GFX1150-NEXT: ; %bb.4: ; %frem.compute
+; GFX1150-NEXT: s_cbranch_scc0 .LBB3_8
+; GFX1150-NEXT: .LBB3_3: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v3, |v2|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v6, v2
@@ -2864,12 +2820,12 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1150-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB3_8
-; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB3_7
+; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s0, s0, s1
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s0, s0, 12
-; GFX1150-NEXT: .LBB3_6: ; %frem.loop_body
+; GFX1150-NEXT: .LBB3_5: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v8, v5
@@ -2887,11 +2843,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB3_6
-; GFX1150-NEXT: ; %bb.7: ; %Flow
+; GFX1150-NEXT: s_cbranch_scc1 .LBB3_5
+; GFX1150-NEXT: ; %bb.6: ; %Flow
; GFX1150-NEXT: v_mov_b32_e32 v7, s0
; GFX1150-NEXT: v_mov_b32_e32 v5, v8
-; GFX1150-NEXT: .LBB3_8: ; %frem.loop_exit
+; GFX1150-NEXT: .LBB3_7: ; %frem.loop_exit
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_add_nc_u32_e32 v7, -11, v7
; GFX1150-NEXT: v_ldexp_f32 v5, v5, v7
@@ -2908,7 +2864,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v4, v3
; GFX1150-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v2
-; GFX1150-NEXT: .LBB3_9: ; %Flow17
+; GFX1150-NEXT: .LBB3_8: ; %Flow17
; GFX1150-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v0
; GFX1150-NEXT: v_cmp_nle_f32_e64 s0, 0x7f800000, v1
; GFX1150-NEXT: v_mov_b32_e32 v2, 0
@@ -2940,17 +2896,16 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: s_mov_b32 s0, 0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v2, v4, vcc_lo
-; GFX1200-NEXT: s_branch .LBB3_3
+; GFX1200-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB3_3
+; GFX1200-NEXT: s_branch .LBB3_8
; GFX1200-NEXT: .LBB3_2:
; GFX1200-NEXT: s_mov_b32 s0, -1
; GFX1200-NEXT: ; implicit-def: $vgpr3
-; GFX1200-NEXT: .LBB3_3: ; %Flow16
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_and_b32 s0, s0, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s0, 1, 0
-; GFX1200-NEXT: s_cmp_lg_u32 s0, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB3_9
-; GFX1200-NEXT: ; %bb.4: ; %frem.compute
+; GFX1200-NEXT: s_cbranch_scc0 .LBB3_8
+; GFX1200-NEXT: .LBB3_3: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v3, |v2|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, v2
@@ -2985,12 +2940,12 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1200-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB3_8
-; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB3_7
+; GFX1200-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s0, s0, s1
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s0, s0, 12
-; GFX1200-NEXT: .LBB3_6: ; %frem.loop_body
+; GFX1200-NEXT: .LBB3_5: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1200-NEXT: v_mov_b32_e32 v8, v5
@@ -3009,11 +2964,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB3_6
-; GFX1200-NEXT: ; %bb.7: ; %Flow
+; GFX1200-NEXT: s_cbranch_scc1 .LBB3_5
+; GFX1200-NEXT: ; %bb.6: ; %Flow
; GFX1200-NEXT: v_mov_b32_e32 v7, s0
; GFX1200-NEXT: v_mov_b32_e32 v5, v8
-; GFX1200-NEXT: .LBB3_8: ; %frem.loop_exit
+; GFX1200-NEXT: .LBB3_7: ; %frem.loop_exit
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_add_nc_u32_e32 v7, -11, v7
; GFX1200-NEXT: v_ldexp_f32 v5, v5, v7
@@ -3031,7 +2986,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v3, v4, v3
; GFX1200-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v2
-; GFX1200-NEXT: .LBB3_9: ; %Flow17
+; GFX1200-NEXT: .LBB3_8: ; %Flow17
; GFX1200-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: v_cmp_nle_f32_e64 s0, 0x7f800000, v1
; GFX1200-NEXT: v_mov_b32_e32 v2, 0
@@ -3627,7 +3582,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_readfirstlane_b32 s4, v2
; SI-NEXT: v_readfirstlane_b32 s5, v3
; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
-; SI-NEXT: s_cbranch_vccz .LBB6_2
+; SI-NEXT: s_cbranch_vccz .LBB6_3
; SI-NEXT: ; %bb.1: ; %frem.else
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
@@ -3637,16 +3592,18 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_cselect_b32 s1, s6, s3
; SI-NEXT: s_cselect_b32 s0, 0, s2
; SI-NEXT: s_mov_b64 s[6:7], 0
-; SI-NEXT: s_branch .LBB6_3
+; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; SI-NEXT: s_cbranch_scc1 .LBB6_4
; SI-NEXT: .LBB6_2:
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: s_branch .LBB6_9
+; SI-NEXT: .LBB6_3:
; SI-NEXT: s_mov_b64 s[6:7], -1
; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
-; SI-NEXT: .LBB6_3: ; %Flow16
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
-; SI-NEXT: s_cselect_b32 s6, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s6, 1
-; SI-NEXT: s_cbranch_scc1 .LBB6_9
-; SI-NEXT: ; %bb.4: ; %frem.compute
+; SI-NEXT: s_cbranch_scc0 .LBB6_2
+; SI-NEXT: .LBB6_4: ; %frem.compute
; SI-NEXT: s_and_b32 s0, s3, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -3745,11 +3702,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], s10
; SI-NEXT: v_mov_b32_e32 v2, s3
; SI-NEXT: v_bfi_b32 v1, s0, v1, v2
-; SI-NEXT: s_branch .LBB6_10
-; SI-NEXT: .LBB6_9:
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: .LBB6_10: ; %Flow17
+; SI-NEXT: .LBB6_9: ; %Flow17
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: v_mov_b32_e32 v3, 0x7ff00000
; SI-NEXT: v_cmp_lg_f64_e64 s[0:1], s[4:5], 0
@@ -3786,16 +3739,15 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: s_mov_b64 s[2:3], 0
; CI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
; CI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; CI-NEXT: s_branch .LBB6_3
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB6_3
+; CI-NEXT: s_branch .LBB6_8
; CI-NEXT: .LBB6_2:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr4_vgpr5
-; CI-NEXT: .LBB6_3: ; %Flow16
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB6_9
-; CI-NEXT: ; %bb.4: ; %frem.compute
+; CI-NEXT: s_cbranch_scc0 .LBB6_8
+; CI-NEXT: .LBB6_3: ; %frem.compute
; CI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v11, v[2:3]
; CI-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
@@ -3818,11 +3770,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v13
; CI-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB6_8
-; CI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB6_7
+; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v10, vcc, v10, v11
; CI-NEXT: v_add_i32_e32 v13, vcc, 26, v10
-; CI-NEXT: .LBB6_6: ; %frem.loop_body
+; CI-NEXT: .LBB6_5: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v11, v9
; CI-NEXT: v_mov_b32_e32 v10, v8
@@ -3836,11 +3788,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
; CI-NEXT: v_subrev_i32_e32 v13, vcc, 26, v13
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v13
-; CI-NEXT: s_cbranch_vccnz .LBB6_6
-; CI-NEXT: ; %bb.7: ; %Flow
+; CI-NEXT: s_cbranch_vccnz .LBB6_5
+; CI-NEXT: ; %bb.6: ; %Flow
; CI-NEXT: v_mov_b32_e32 v8, v10
; CI-NEXT: v_mov_b32_e32 v9, v11
-; CI-NEXT: .LBB6_8: ; %frem.loop_exit
+; CI-NEXT: .LBB6_7: ; %frem.loop_exit
; CI-NEXT: v_subrev_i32_e32 v10, vcc, 25, v13
; CI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
; CI-NEXT: s_brev_b32 s2, -2
@@ -3853,7 +3805,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; CI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; CI-NEXT: .LBB6_9: ; %Flow17
+; CI-NEXT: .LBB6_8: ; %Flow17
; CI-NEXT: s_mov_b32 s4, 0
; CI-NEXT: s_mov_b32 s5, 0x7ff00000
; CI-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[2:3]
@@ -3888,16 +3840,15 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: s_mov_b64 s[2:3], 0
; VI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
; VI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; VI-NEXT: s_branch .LBB6_3
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB6_3
+; VI-NEXT: s_branch .LBB6_8
; VI-NEXT: .LBB6_2:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr4_vgpr5
-; VI-NEXT: .LBB6_3: ; %Flow16
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB6_9
-; VI-NEXT: ; %bb.4: ; %frem.compute
+; VI-NEXT: s_cbranch_scc0 .LBB6_8
+; VI-NEXT: .LBB6_3: ; %frem.compute
; VI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v11, v[2:3]
; VI-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
@@ -3920,11 +3871,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v13
; VI-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB6_8
-; VI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB6_7
+; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v10, vcc, v10, v11
; VI-NEXT: v_add_u32_e32 v13, vcc, 26, v10
-; VI-NEXT: .LBB6_6: ; %frem.loop_body
+; VI-NEXT: .LBB6_5: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v11, v9
; VI-NEXT: v_mov_b32_e32 v10, v8
@@ -3938,11 +3889,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
; VI-NEXT: v_subrev_u32_e32 v13, vcc, 26, v13
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v13
-; VI-NEXT: s_cbranch_vccnz .LBB6_6
-; VI-NEXT: ; %bb.7: ; %Flow
+; VI-NEXT: s_cbranch_vccnz .LBB6_5
+; VI-NEXT: ; %bb.6: ; %Flow
; VI-NEXT: v_mov_b32_e32 v8, v10
; VI-NEXT: v_mov_b32_e32 v9, v11
-; VI-NEXT: .LBB6_8: ; %frem.loop_exit
+; VI-NEXT: .LBB6_7: ; %frem.loop_exit
; VI-NEXT: v_subrev_u32_e32 v10, vcc, 25, v13
; VI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
; VI-NEXT: s_brev_b32 s2, -2
@@ -3955,7 +3906,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; VI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; VI-NEXT: .LBB6_9: ; %Flow17
+; VI-NEXT: .LBB6_8: ; %Flow17
; VI-NEXT: v_mov_b32_e32 v6, s0
; VI-NEXT: v_mov_b32_e32 v7, s1
; VI-NEXT: s_mov_b32 s0, 0
@@ -3987,16 +3938,15 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; GFX9-NEXT: s_branch .LBB6_3
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB6_3
+; GFX9-NEXT: s_branch .LBB6_8
; GFX9-NEXT: .LBB6_2:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX9-NEXT: .LBB6_3: ; %Flow16
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB6_9
-; GFX9-NEXT: ; %bb.4: ; %frem.compute
+; GFX9-NEXT: s_cbranch_scc0 .LBB6_8
+; GFX9-NEXT: .LBB6_3: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v11, v[2:3]
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
@@ -4019,11 +3969,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v13
; GFX9-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB6_8
-; GFX9-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB6_7
+; GFX9-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v10, v10, v11
; GFX9-NEXT: v_add_u32_e32 v13, 26, v10
-; GFX9-NEXT: .LBB6_6: ; %frem.loop_body
+; GFX9-NEXT: .LBB6_5: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v11, v9
; GFX9-NEXT: v_mov_b32_e32 v10, v8
@@ -4037,11 +3987,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc
; GFX9-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v13
-; GFX9-NEXT: s_cbranch_vccnz .LBB6_6
-; GFX9-NEXT: ; %bb.7: ; %Flow
+; GFX9-NEXT: s_cbranch_vccnz .LBB6_5
+; GFX9-NEXT: ; %bb.6: ; %Flow
; GFX9-NEXT: v_mov_b32_e32 v8, v10
; GFX9-NEXT: v_mov_b32_e32 v9, v11
-; GFX9-NEXT: .LBB6_8: ; %frem.loop_exit
+; GFX9-NEXT: .LBB6_7: ; %frem.loop_exit
; GFX9-NEXT: v_subrev_u32_e32 v10, 25, v13
; GFX9-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
; GFX9-NEXT: s_brev_b32 s2, -2
@@ -4054,7 +4004,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v1
-; GFX9-NEXT: .LBB6_9: ; %Flow17
+; GFX9-NEXT: .LBB6_8: ; %Flow17
; GFX9-NEXT: s_mov_b32 s2, 0
; GFX9-NEXT: s_mov_b32 s3, 0x7ff00000
; GFX9-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[2:3]
@@ -4087,16 +4037,15 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX10-NEXT: s_branch .LBB6_3
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB6_3
+; GFX10-NEXT: s_branch .LBB6_8
; GFX10-NEXT: .LBB6_2:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX10-NEXT: .LBB6_3: ; %Flow16
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB6_9
-; GFX10-NEXT: ; %bb.4: ; %frem.compute
+; GFX10-NEXT: s_cbranch_scc0 .LBB6_8
+; GFX10-NEXT: .LBB6_3: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
@@ -4120,11 +4069,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
; GFX10-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB6_8
-; GFX10-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB6_7
+; GFX10-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 26
-; GFX10-NEXT: .LBB6_6: ; %frem.loop_body
+; GFX10-NEXT: .LBB6_5: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v11, v7
; GFX10-NEXT: v_mov_b32_e32 v10, v6
@@ -4138,12 +4087,12 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB6_6
-; GFX10-NEXT: ; %bb.7: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB6_5
+; GFX10-NEXT: ; %bb.6: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v13, s2
; GFX10-NEXT: v_mov_b32_e32 v6, v10
; GFX10-NEXT: v_mov_b32_e32 v7, v11
-; GFX10-NEXT: .LBB6_8: ; %frem.loop_exit
+; GFX10-NEXT: .LBB6_7: ; %frem.loop_exit
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
; GFX10-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
@@ -4155,7 +4104,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX10-NEXT: .LBB6_9: ; %Flow17
+; GFX10-NEXT: .LBB6_8: ; %Flow17
; GFX10-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX10-NEXT: v_mov_b32_e32 v6, 0
@@ -4186,17 +4135,16 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX11-NEXT: s_branch .LBB6_3
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB6_3
+; GFX11-NEXT: s_branch .LBB6_8
; GFX11-NEXT: .LBB6_2:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX11-NEXT: .LBB6_3: ; %Flow16
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB6_9
-; GFX11-NEXT: ; %bb.4: ; %frem.compute
+; GFX11-NEXT: s_cbranch_scc0 .LBB6_8
+; GFX11-NEXT: .LBB6_3: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
@@ -4228,13 +4176,13 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB6_8
-; GFX11-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB6_7
+; GFX11-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 26
; GFX11-NEXT: .p2align 6
-; GFX11-NEXT: .LBB6_6: ; %frem.loop_body
+; GFX11-NEXT: .LBB6_5: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
@@ -4250,11 +4198,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB6_6
-; GFX11-NEXT: ; %bb.7: ; %Flow
+; GFX11-NEXT: s_cbranch_scc1 .LBB6_5
+; GFX11-NEXT: ; %bb.6: ; %Flow
; GFX11-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
; GFX11-NEXT: v_mov_b32_e32 v7, v11
-; GFX11-NEXT: .LBB6_8: ; %frem.loop_exit
+; GFX11-NEXT: .LBB6_7: ; %frem.loop_exit
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
@@ -4270,7 +4218,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX11-NEXT: .LBB6_9: ; %Flow17
+; GFX11-NEXT: .LBB6_8: ; %Flow17
; GFX11-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX11-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -4300,17 +4248,16 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX1150-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB6_3
+; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB6_3
+; GFX1150-NEXT: s_branch .LBB6_8
; GFX1150-NEXT: .LBB6_2:
; GFX1150-NEXT: s_mov_b32 s2, -1
; GFX1150-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX1150-NEXT: .LBB6_3: ; %Flow16
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB6_9
-; GFX1150-NEXT: ; %bb.4: ; %frem.compute
+; GFX1150-NEXT: s_cbranch_scc0 .LBB6_8
+; GFX1150-NEXT: .LBB6_3: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
@@ -4341,13 +4288,13 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
; GFX1150-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB6_8
-; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB6_7
+; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s2, s2, s3
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s2, s2, 26
; GFX1150-NEXT: .p2align 6
-; GFX1150-NEXT: .LBB6_6: ; %frem.loop_body
+; GFX1150-NEXT: .LBB6_5: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
@@ -4363,11 +4310,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB6_6
-; GFX1150-NEXT: ; %bb.7: ; %Flow
+; GFX1150-NEXT: s_cbranch_scc1 .LBB6_5
+; GFX1150-NEXT: ; %bb.6: ; %Flow
; GFX1150-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
; GFX1150-NEXT: v_mov_b32_e32 v7, v11
-; GFX1150-NEXT: .LBB6_8: ; %frem.loop_exit
+; GFX1150-NEXT: .LBB6_7: ; %frem.loop_exit
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
@@ -4383,7 +4330,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX1150-NEXT: .LBB6_9: ; %Flow17
+; GFX1150-NEXT: .LBB6_8: ; %Flow17
; GFX1150-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1150-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1150-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -4413,17 +4360,16 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX1200-NEXT: s_branch .LBB6_3
+; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB6_3
+; GFX1200-NEXT: s_branch .LBB6_8
; GFX1200-NEXT: .LBB6_2:
; GFX1200-NEXT: s_mov_b32 s2, -1
; GFX1200-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX1200-NEXT: .LBB6_3: ; %Flow16
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1200-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB6_9
-; GFX1200-NEXT: ; %bb.4: ; %frem.compute
+; GFX1200-NEXT: s_cbranch_scc0 .LBB6_8
+; GFX1200-NEXT: .LBB6_3: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
@@ -4455,12 +4401,12 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
; GFX1200-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB6_8
-; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB6_7
+; GFX1200-NEXT: ; %bb.4: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s2, s2, s3
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 26
-; GFX1200-NEXT: .LBB6_6: ; %frem.loop_body
+; GFX1200-NEXT: .LBB6_5: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1200-NEXT: v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
@@ -4477,11 +4423,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB6_6
-; GFX1200-NEXT: ; %bb.7: ; %Flow
+; GFX1200-NEXT: s_cbranch_scc1 .LBB6_5
+; GFX1200-NEXT: ; %bb.6: ; %Flow
; GFX1200-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
; GFX1200-NEXT: v_mov_b32_e32 v7, v11
-; GFX1200-NEXT: .LBB6_8: ; %frem.loop_exit
+; GFX1200-NEXT: .LBB6_7: ; %frem.loop_exit
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
@@ -4498,7 +4444,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX1200-NEXT: .LBB6_9: ; %Flow17
+; GFX1200-NEXT: .LBB6_8: ; %Flow17
; GFX1200-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1200-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -5094,16 +5040,15 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v4
; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_branch .LBB9_3
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cbranch_scc1 .LBB9_3
+; SI-NEXT: s_branch .LBB9_8
; SI-NEXT: .LBB9_2:
; SI-NEXT: s_mov_b64 s[0:1], -1
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: .LBB9_3: ; %Flow57
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s0, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s0, 1
-; SI-NEXT: s_cbranch_scc1 .LBB9_9
-; SI-NEXT: ; %bb.4: ; %frem.compute19
+; SI-NEXT: s_cbranch_scc0 .LBB9_8
+; SI-NEXT: .LBB9_3: ; %frem.compute19
; SI-NEXT: s_mov_b32 s3, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
@@ -5138,11 +5083,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB9_8
-; SI-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB9_7
+; SI-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; SI-NEXT: s_sub_i32 s1, s2, s3
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB9_6: ; %frem.loop_body27
+; SI-NEXT: .LBB9_5: ; %frem.loop_body27
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v5, v3
; SI-NEXT: v_mul_f32_e32 v3, v5, v4
@@ -5154,10 +5099,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB9_6
-; SI-NEXT: ; %bb.7: ; %Flow55
+; SI-NEXT: s_cbranch_scc1 .LBB9_5
+; SI-NEXT: ; %bb.6: ; %Flow55
; SI-NEXT: v_mov_b32_e32 v3, v5
-; SI-NEXT: .LBB9_8: ; %frem.loop_exit28
+; SI-NEXT: .LBB9_7: ; %frem.loop_exit28
; SI-NEXT: s_add_i32 s1, s1, -10
; SI-NEXT: v_ldexp_f32_e64 v3, v3, s1
; SI-NEXT: v_mul_f32_e32 v4, v3, v4
@@ -5171,28 +5116,27 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_and_b32_e32 v3, 0xffff8000, v0
; SI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: .LBB9_9: ; %Flow58
+; SI-NEXT: .LBB9_8: ; %Flow58
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; SI-NEXT: v_cvt_f32_f16_e64 v6, |v3|
; SI-NEXT: v_cvt_f32_f16_e64 v7, |v4|
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v7
-; SI-NEXT: s_cbranch_vccz .LBB9_11
-; SI-NEXT: ; %bb.10: ; %frem.else
+; SI-NEXT: s_cbranch_vccz .LBB9_10
+; SI-NEXT: ; %bb.9: ; %frem.else
; SI-NEXT: v_and_b32_e32 v5, 0x8000, v3
; SI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v7
; SI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_branch .LBB9_12
-; SI-NEXT: .LBB9_11:
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cbranch_scc1 .LBB9_11
+; SI-NEXT: s_branch .LBB9_16
+; SI-NEXT: .LBB9_10:
; SI-NEXT: s_mov_b64 s[0:1], -1
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: .LBB9_12: ; %Flow53
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s0, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s0, 1
-; SI-NEXT: s_cbranch_scc1 .LBB9_18
-; SI-NEXT: ; %bb.13: ; %frem.compute
+; SI-NEXT: s_cbranch_scc0 .LBB9_16
+; SI-NEXT: .LBB9_11: ; %frem.compute
; SI-NEXT: s_mov_b32 s3, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s3
; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v6
@@ -5227,11 +5171,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v7, v7, v9, v10
; SI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB9_17
-; SI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB9_15
+; SI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s1, s2, s3
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB9_15: ; %frem.loop_body
+; SI-NEXT: .LBB9_13: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v8, v6
; SI-NEXT: v_mul_f32_e32 v6, v8, v7
@@ -5243,10 +5187,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v6, v6, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB9_15
-; SI-NEXT: ; %bb.16: ; %Flow
+; SI-NEXT: s_cbranch_scc1 .LBB9_13
+; SI-NEXT: ; %bb.14: ; %Flow
; SI-NEXT: v_mov_b32_e32 v6, v8
-; SI-NEXT: .LBB9_17: ; %frem.loop_exit
+; SI-NEXT: .LBB9_15: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s1, s1, -10
; SI-NEXT: v_ldexp_f32_e64 v6, v6, s1
; SI-NEXT: v_mul_f32_e32 v7, v6, v7
@@ -5260,7 +5204,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_and_b32_e32 v6, 0x8000, v3
; SI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: .LBB9_18: ; %Flow54
+; SI-NEXT: .LBB9_16: ; %Flow54
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; SI-NEXT: s_mov_b32 s2, 0x7f800000
@@ -5307,16 +5251,15 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_branch .LBB9_3
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cbranch_scc1 .LBB9_3
+; CI-NEXT: s_branch .LBB9_8
; CI-NEXT: .LBB9_2:
; CI-NEXT: s_mov_b64 s[0:1], -1
; CI-NEXT: ; implicit-def: $vgpr2
-; CI-NEXT: .LBB9_3: ; %Flow57
; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cselect_b32 s0, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s0, 1
-; CI-NEXT: s_cbranch_scc1 .LBB9_9
-; CI-NEXT: ; %bb.4: ; %frem.compute19
+; CI-NEXT: s_cbranch_scc0 .LBB9_8
+; CI-NEXT: .LBB9_3: ; %frem.compute19
; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
; CI-NEXT: v_frexp_mant_f32_e32 v2, v4
; CI-NEXT: v_frexp_mant_f32_e32 v4, v3
@@ -5340,11 +5283,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB9_8
-; CI-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB9_7
+; CI-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT: v_add_i32_e32 v4, vcc, 11, v4
-; CI-NEXT: .LBB9_6: ; %frem.loop_body27
+; CI-NEXT: .LBB9_5: ; %frem.loop_body27
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v7, v5
; CI-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -5356,10 +5299,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11
-; CI-NEXT: s_cbranch_vccnz .LBB9_6
-; CI-NEXT: ; %bb.7: ; %Flow55
+; CI-NEXT: s_cbranch_vccnz .LBB9_5
+; CI-NEXT: ; %bb.6: ; %Flow55
; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: .LBB9_8: ; %frem.loop_exit28
+; CI-NEXT: .LBB9_7: ; %frem.loop_exit28
; CI-NEXT: v_add_i32_e32 v4, vcc, -10, v4
; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT: v_mul_f32_e32 v5, v4, v6
@@ -5373,28 +5316,27 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_and_b32_e32 v3, 0xffff8000, v0
; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; CI-NEXT: v_or_b32_e32 v2, v2, v3
-; CI-NEXT: .LBB9_9: ; %Flow58
+; CI-NEXT: .LBB9_8: ; %Flow58
; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; CI-NEXT: v_cvt_f32_f16_e64 v7, |v3|
; CI-NEXT: v_cvt_f32_f16_e64 v6, |v4|
; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
-; CI-NEXT: s_cbranch_vccz .LBB9_11
-; CI-NEXT: ; %bb.10: ; %frem.else
+; CI-NEXT: s_cbranch_vccz .LBB9_10
+; CI-NEXT: ; %bb.9: ; %frem.else
; CI-NEXT: v_and_b32_e32 v5, 0x8000, v3
; CI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
; CI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_branch .LBB9_12
-; CI-NEXT: .LBB9_11:
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cbranch_scc1 .LBB9_11
+; CI-NEXT: s_branch .LBB9_16
+; CI-NEXT: .LBB9_10:
; CI-NEXT: s_mov_b64 s[0:1], -1
; CI-NEXT: ; implicit-def: $vgpr5
-; CI-NEXT: .LBB9_12: ; %Flow53
; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cselect_b32 s0, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s0, 1
-; CI-NEXT: s_cbranch_scc1 .LBB9_18
-; CI-NEXT: ; %bb.13: ; %frem.compute
+; CI-NEXT: s_cbranch_scc0 .LBB9_16
+; CI-NEXT: .LBB9_11: ; %frem.compute
; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v7
; CI-NEXT: v_frexp_mant_f32_e32 v5, v7
; CI-NEXT: v_frexp_mant_f32_e32 v7, v6
@@ -5418,11 +5360,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v7
; CI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB9_17
-; CI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB9_15
+; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v7, vcc, v10, v11
; CI-NEXT: v_add_i32_e32 v7, vcc, 11, v7
-; CI-NEXT: .LBB9_15: ; %frem.loop_body
+; CI-NEXT: .LBB9_13: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v10, v8
; CI-NEXT: v_mul_f32_e32 v8, v10, v9
@@ -5434,10 +5376,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v7, vcc, -11, v7
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v7
; CI-NEXT: v_ldexp_f32_e64 v8, v8, 11
-; CI-NEXT: s_cbranch_vccnz .LBB9_15
-; CI-NEXT: ; %bb.16: ; %Flow
+; CI-NEXT: s_cbranch_vccnz .LBB9_13
+; CI-NEXT: ; %bb.14: ; %Flow
; CI-NEXT: v_mov_b32_e32 v8, v10
-; CI-NEXT: .LBB9_17: ; %frem.loop_exit
+; CI-NEXT: .LBB9_15: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v7, vcc, -10, v7
; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
; CI-NEXT: v_mul_f32_e32 v8, v7, v9
@@ -5451,7 +5393,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_and_b32_e32 v6, 0x8000, v3
; CI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
; CI-NEXT: v_or_b32_e32 v5, v5, v6
-; CI-NEXT: .LBB9_18: ; %Flow54
+; CI-NEXT: .LBB9_16: ; %Flow54
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; CI-NEXT: s_mov_b32 s2, 0x7f800000
@@ -5498,16 +5440,15 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB9_3
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB9_3
+; VI-NEXT: s_branch .LBB9_8
; VI-NEXT: .LBB9_2:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr2
-; VI-NEXT: .LBB9_3: ; %Flow57
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB9_9
-; VI-NEXT: ; %bb.4: ; %frem.compute19
+; VI-NEXT: s_cbranch_scc0 .LBB9_8
+; VI-NEXT: .LBB9_3: ; %frem.compute19
; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
; VI-NEXT: v_frexp_mant_f32_e32 v2, v4
; VI-NEXT: v_frexp_mant_f32_e32 v4, v3
@@ -5531,11 +5472,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
; VI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB9_8
-; VI-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB9_7
+; VI-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; VI-NEXT: v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT: v_add_u32_e32 v4, vcc, 11, v4
-; VI-NEXT: .LBB9_6: ; %frem.loop_body27
+; VI-NEXT: .LBB9_5: ; %frem.loop_body27
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v7, v5
; VI-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -5547,10 +5488,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
; VI-NEXT: v_ldexp_f32 v5, v5, 11
-; VI-NEXT: s_cbranch_vccnz .LBB9_6
-; VI-NEXT: ; %bb.7: ; %Flow55
+; VI-NEXT: s_cbranch_vccnz .LBB9_5
+; VI-NEXT: ; %bb.6: ; %Flow55
; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: .LBB9_8: ; %frem.loop_exit28
+; VI-NEXT: .LBB9_7: ; %frem.loop_exit28
; VI-NEXT: v_add_u32_e32 v4, vcc, -10, v4
; VI-NEXT: v_ldexp_f32 v4, v5, v4
; VI-NEXT: v_mul_f32_e32 v5, v4, v6
@@ -5563,28 +5504,27 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cvt_f16_f32_e32 v2, v2
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; VI-NEXT: .LBB9_9:
+; VI-NEXT: .LBB9_8:
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; VI-NEXT: v_cvt_f32_f16_e64 v7, |v3|
; VI-NEXT: v_cvt_f32_f16_e64 v6, |v4|
; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
-; VI-NEXT: s_cbranch_vccz .LBB9_11
-; VI-NEXT: ; %bb.10: ; %frem.else
+; VI-NEXT: s_cbranch_vccz .LBB9_10
+; VI-NEXT: ; %bb.9: ; %frem.else
; VI-NEXT: v_and_b32_e32 v5, 0x8000, v3
; VI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
; VI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB9_12
-; VI-NEXT: .LBB9_11:
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB9_11
+; VI-NEXT: s_branch .LBB9_16
+; VI-NEXT: .LBB9_10:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr5
-; VI-NEXT: .LBB9_12: ; %Flow53
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB9_18
-; VI-NEXT: ; %bb.13: ; %frem.compute
+; VI-NEXT: s_cbranch_scc0 .LBB9_16
+; VI-NEXT: .LBB9_11: ; %frem.compute
; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v7
; VI-NEXT: v_frexp_mant_f32_e32 v5, v7
; VI-NEXT: v_frexp_mant_f32_e32 v7, v6
@@ -5608,11 +5548,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v7
; VI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB9_17
-; VI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB9_15
+; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v7, vcc, v10, v11
; VI-NEXT: v_add_u32_e32 v7, vcc, 11, v7
-; VI-NEXT: .LBB9_15: ; %frem.loop_body
+; VI-NEXT: .LBB9_13: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v10, v8
; VI-NEXT: v_mul_f32_e32 v8, v10, v9
@@ -5624,10 +5564,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v7, vcc, -11, v7
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v7
; VI-NEXT: v_ldexp_f32 v8, v8, 11
-; VI-NEXT: s_cbranch_vccnz .LBB9_15
-; VI-NEXT: ; %bb.16: ; %Flow
+; VI-NEXT: s_cbranch_vccnz .LBB9_13
+; VI-NEXT: ; %bb.14: ; %Flow
; VI-NEXT: v_mov_b32_e32 v8, v10
-; VI-NEXT: .LBB9_17: ; %frem.loop_exit
+; VI-NEXT: .LBB9_15: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v7, vcc, -10, v7
; VI-NEXT: v_ldexp_f32 v7, v8, v7
; VI-NEXT: v_mul_f32_e32 v8, v7, v9
@@ -5640,7 +5580,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cvt_f16_f32_e32 v5, v5
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v5, s2, v5, v3
-; VI-NEXT: .LBB9_18: ; %Flow54
+; VI-NEXT: .LBB9_16: ; %Flow54
; VI-NEXT: s_movk_i32 s4, 0x7c00
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v1
; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |v0|, s4
@@ -5676,16 +5616,15 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB9_3
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX9-NEXT: s_branch .LBB9_8
; GFX9-NEXT: .LBB9_2:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr2
-; GFX9-NEXT: .LBB9_3: ; %Flow57
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB9_9
-; GFX9-NEXT: ; %bb.4: ; %frem.compute19
+; GFX9-NEXT: s_cbranch_scc0 .LBB9_8
+; GFX9-NEXT: .LBB9_3: ; %frem.compute19
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
; GFX9-NEXT: v_frexp_mant_f32_e32 v2, v4
; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v3
@@ -5709,11 +5648,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v6, v6, v10, v11
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
; GFX9-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_8
-; GFX9-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX9-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; GFX9-NEXT: v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT: v_add_u32_e32 v4, 11, v4
-; GFX9-NEXT: .LBB9_6: ; %frem.loop_body27
+; GFX9-NEXT: .LBB9_5: ; %frem.loop_body27
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -5725,10 +5664,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
; GFX9-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_6
-; GFX9-NEXT: ; %bb.7: ; %Flow55
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_5
+; GFX9-NEXT: ; %bb.6: ; %Flow55
; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX9-NEXT: .LBB9_7: ; %frem.loop_exit28
; GFX9-NEXT: v_add_u32_e32 v4, -10, v4
; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
; GFX9-NEXT: v_mul_f32_e32 v5, v4, v6
@@ -5741,27 +5680,26 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v2, s2, v2, v1
-; GFX9-NEXT: .LBB9_9:
+; GFX9-NEXT: .LBB9_8:
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-NEXT: v_cvt_f32_f16_e64 v6, |v3|
; GFX9-NEXT: v_cvt_f32_f16_sdwa v5, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
-; GFX9-NEXT: s_cbranch_vccz .LBB9_11
-; GFX9-NEXT: ; %bb.10: ; %frem.else
+; GFX9-NEXT: s_cbranch_vccz .LBB9_10
+; GFX9-NEXT: ; %bb.9: ; %frem.else
; GFX9-NEXT: v_and_b32_e32 v4, 0x8000, v3
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB9_12
-; GFX9-NEXT: .LBB9_11:
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB9_11
+; GFX9-NEXT: s_branch .LBB9_16
+; GFX9-NEXT: .LBB9_10:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr4
-; GFX9-NEXT: .LBB9_12: ; %Flow53
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB9_18
-; GFX9-NEXT: ; %bb.13: ; %frem.compute
+; GFX9-NEXT: s_cbranch_scc0 .LBB9_16
+; GFX9-NEXT: .LBB9_11: ; %frem.compute
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v6
; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v6
; GFX9-NEXT: v_frexp_mant_f32_e32 v6, v5
@@ -5785,11 +5723,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
; GFX9-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_17
-; GFX9-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX9-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT: v_add_u32_e32 v6, 11, v6
-; GFX9-NEXT: .LBB9_15: ; %frem.loop_body
+; GFX9-NEXT: .LBB9_13: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v9, v7
; GFX9-NEXT: v_mul_f32_e32 v7, v9, v8
@@ -5801,10 +5739,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
; GFX9-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX9-NEXT: ; %bb.16: ; %Flow
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_13
+; GFX9-NEXT: ; %bb.14: ; %Flow
; GFX9-NEXT: v_mov_b32_e32 v7, v9
-; GFX9-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX9-NEXT: .LBB9_15: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v6, -10, v6
; GFX9-NEXT: v_ldexp_f32 v6, v7, v6
; GFX9-NEXT: v_mul_f32_e32 v7, v6, v8
@@ -5817,7 +5755,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v3
-; GFX9-NEXT: .LBB9_18: ; %Flow54
+; GFX9-NEXT: .LBB9_16: ; %Flow54
; GFX9-NEXT: s_movk_i32 s4, 0x7c00
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v0
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v1|, s4
@@ -5854,16 +5792,15 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc_lo
-; GFX10-NEXT: s_branch .LBB9_3
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX10-NEXT: s_branch .LBB9_8
; GFX10-NEXT: .LBB9_2:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr2
-; GFX10-NEXT: .LBB9_3: ; %Flow57
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB9_9
-; GFX10-NEXT: ; %bb.4: ; %frem.compute19
+; GFX10-NEXT: s_cbranch_scc0 .LBB9_8
+; GFX10-NEXT: .LBB9_3: ; %frem.compute19
; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v4
; GFX10-NEXT: v_frexp_mant_f32_e32 v6, v3
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
@@ -5889,11 +5826,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX10-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB9_8
-; GFX10-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX10-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB9_6: ; %frem.loop_body27
+; GFX10-NEXT: .LBB9_5: ; %frem.loop_body27
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -5905,11 +5842,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v6, v4, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX10-NEXT: ; %bb.7: ; %Flow55
+; GFX10-NEXT: s_cbranch_scc1 .LBB9_5
+; GFX10-NEXT: ; %bb.6: ; %Flow55
; GFX10-NEXT: v_mov_b32_e32 v6, s2
; GFX10-NEXT: v_mov_b32_e32 v4, v7
-; GFX10-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX10-NEXT: .LBB9_7: ; %frem.loop_exit28
; GFX10-NEXT: v_add_nc_u32_e32 v6, -10, v6
; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v5
@@ -5921,27 +5858,26 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v2, v3, v2
; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT: v_bfi_b32 v2, 0x7fff, v2, v1
-; GFX10-NEXT: .LBB9_9:
+; GFX10-NEXT: .LBB9_8:
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e64 v6, |v3|
; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v6, v5
-; GFX10-NEXT: s_cbranch_vccz .LBB9_11
-; GFX10-NEXT: ; %bb.10: ; %frem.else
+; GFX10-NEXT: s_cbranch_vccz .LBB9_10
+; GFX10-NEXT: ; %bb.9: ; %frem.else
; GFX10-NEXT: v_and_b32_e32 v4, 0x8000, v3
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc_lo
-; GFX10-NEXT: s_branch .LBB9_12
-; GFX10-NEXT: .LBB9_11:
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB9_11
+; GFX10-NEXT: s_branch .LBB9_16
+; GFX10-NEXT: .LBB9_10:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: .LBB9_12: ; %Flow53
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB9_18
-; GFX10-NEXT: ; %bb.13: ; %frem.compute
+; GFX10-NEXT: s_cbranch_scc0 .LBB9_16
+; GFX10-NEXT: .LBB9_11: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e32 v4, v6
; GFX10-NEXT: v_frexp_mant_f32_e32 v8, v5
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
@@ -5967,11 +5903,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX10-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB9_17
-; GFX10-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX10-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB9_15: ; %frem.loop_body
+; GFX10-NEXT: .LBB9_13: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -5983,11 +5919,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v8, v6, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v6, v6, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB9_15
-; GFX10-NEXT: ; %bb.16: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB9_13
+; GFX10-NEXT: ; %bb.14: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v8, s2
; GFX10-NEXT: v_mov_b32_e32 v6, v9
-; GFX10-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX10-NEXT: .LBB9_15: ; %frem.loop_exit
; GFX10-NEXT: v_add_nc_u32_e32 v8, -10, v8
; GFX10-NEXT: v_ldexp_f32 v6, v6, v8
; GFX10-NEXT: v_mul_f32_e32 v7, v6, v7
@@ -5999,7 +5935,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v4, v5, v4
; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX10-NEXT: v_bfi_b32 v4, 0x7fff, v4, v3
-; GFX10-NEXT: .LBB9_18: ; %Flow54
+; GFX10-NEXT: .LBB9_16: ; %Flow54
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v1|
; GFX10-NEXT: v_cmp_nle_f16_e64 s3, 0x7c00, |v3|
@@ -6037,17 +5973,16 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB9_3
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX11-TRUE16-NEXT: s_branch .LBB9_7
; GFX11-TRUE16-NEXT: .LBB9_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX11-TRUE16-NEXT: .LBB9_3: ; %Flow57
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
-; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB9_7
+; GFX11-TRUE16-NEXT: .LBB9_3: ; %frem.compute19
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v4
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v3
@@ -6081,12 +6016,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
-; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_6
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT: .LBB9_5: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -6101,10 +6036,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX11-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_5
+; GFX11-TRUE16-NEXT: .LBB9_6: ; %frem.loop_exit28
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX11-TRUE16-NEXT: .LBB9_8:
+; GFX11-TRUE16-NEXT: .LBB9_7:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6112,24 +6047,23 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, |v4.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v6
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_10
-; GFX11-TRUE16-NEXT: ; %bb.9: ; %frem.else
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_9
+; GFX11-TRUE16-NEXT: ; %bb.8: ; %frem.else
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB9_11
-; GFX11-TRUE16-NEXT: .LBB9_10:
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_10
+; GFX11-TRUE16-NEXT: s_branch .LBB9_14
+; GFX11-TRUE16-NEXT: .LBB9_9:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-TRUE16-NEXT: .LBB9_11: ; %Flow53
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
-; GFX11-TRUE16-NEXT: ; %bb.12: ; %frem.compute
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB9_14
+; GFX11-TRUE16-NEXT: .LBB9_10: ; %frem.compute
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v7
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v6
@@ -6163,12 +6097,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v7, v7, v6, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_13
+; GFX11-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB9_12: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v5, v7
@@ -6183,10 +6117,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
-; GFX11-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_12
+; GFX11-TRUE16-NEXT: .LBB9_13: ; %frem.loop_exit
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-TRUE16-NEXT: .LBB9_16: ; %Flow54
+; GFX11-TRUE16-NEXT: .LBB9_14: ; %Flow54
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
@@ -6223,17 +6157,16 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB9_3
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX11-FAKE16-NEXT: s_branch .LBB9_8
; GFX11-FAKE16-NEXT: .LBB9_2:
; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX11-FAKE16-NEXT: .LBB9_3: ; %Flow57
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_9
-; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB9_8
+; GFX11-FAKE16-NEXT: .LBB9_3: ; %frem.compute19
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, v4
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v6, v3
; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
@@ -6268,12 +6201,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_8
-; GFX11-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB9_6: ; %frem.loop_body27
+; GFX11-FAKE16-NEXT: .LBB9_5: ; %frem.loop_body27
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -6289,11 +6222,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX11-FAKE16-NEXT: ; %bb.7: ; %Flow55
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_5
+; GFX11-FAKE16-NEXT: ; %bb.6: ; %Flow55
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, s2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-FAKE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX11-FAKE16-NEXT: .LBB9_7: ; %frem.loop_exit28
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
@@ -6310,7 +6243,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX11-FAKE16-NEXT: .LBB9_9:
+; GFX11-FAKE16-NEXT: .LBB9_8:
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6318,24 +6251,23 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, |v4|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v6
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB9_11
-; GFX11-FAKE16-NEXT: ; %bb.10: ; %frem.else
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB9_10
+; GFX11-FAKE16-NEXT: ; %bb.9: ; %frem.else
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x8000, v3
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB9_12
-; GFX11-FAKE16-NEXT: .LBB9_11:
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
+; GFX11-FAKE16-NEXT: s_branch .LBB9_16
+; GFX11-FAKE16-NEXT: .LBB9_10:
; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-FAKE16-NEXT: .LBB9_12: ; %Flow53
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_18
-; GFX11-FAKE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB9_16
+; GFX11-FAKE16-NEXT: .LBB9_11: ; %frem.compute
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v5, v7
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v9, v6
; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
@@ -6370,12 +6302,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_17
-; GFX11-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX11-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB9_15: ; %frem.loop_body
+; GFX11-FAKE16-NEXT: .LBB9_13: ; %frem.loop_body
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, v7
@@ -6391,11 +6323,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_15
-; GFX11-FAKE16-NEXT: ; %bb.16: ; %Flow
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_13
+; GFX11-FAKE16-NEXT: ; %bb.14: ; %Flow
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, s2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v10
-; GFX11-FAKE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX11-FAKE16-NEXT: .LBB9_15: ; %frem.loop_exit
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, -10, v9
; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v7, v9
@@ -6412,7 +6344,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX11-FAKE16-NEXT: v_bfi_b32 v5, 0x7fff, v5, v3
-; GFX11-FAKE16-NEXT: .LBB9_18: ; %Flow54
+; GFX11-FAKE16-NEXT: .LBB9_16: ; %Flow54
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@@ -6456,17 +6388,17 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s7
; GFX1150-TRUE16-NEXT: s_mov_b32 s7, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB9_3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX1150-TRUE16-NEXT: s_branch .LBB9_7
; GFX1150-TRUE16-NEXT: .LBB9_2:
; GFX1150-TRUE16-NEXT: s_mov_b32 s7, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: .LBB9_3: ; %Flow57
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
-; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_7
+; GFX1150-TRUE16-NEXT: .LBB9_3: ; %frem.compute19
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
@@ -6499,12 +6431,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
-; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_6
+; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s5, s6, s5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s5, s5, 11
-; GFX1150-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT: .LBB9_5: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -6520,10 +6452,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX1150-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_5
+; GFX1150-TRUE16-NEXT: .LBB9_6: ; %frem.loop_exit28
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: .LBB9_8:
+; GFX1150-TRUE16-NEXT: .LBB9_7:
; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
; GFX1150-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
@@ -6532,25 +6464,25 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
-; GFX1150-TRUE16-NEXT: ; %bb.9: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_9
+; GFX1150-TRUE16-NEXT: ; %bb.8: ; %frem.else
; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
; GFX1150-TRUE16-NEXT: s_mov_b32 s8, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB9_11
-; GFX1150-TRUE16-NEXT: .LBB9_10:
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_10
+; GFX1150-TRUE16-NEXT: s_branch .LBB9_14
+; GFX1150-TRUE16-NEXT: .LBB9_9:
; GFX1150-TRUE16-NEXT: s_mov_b32 s8, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB9_11: ; %Flow53
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s8, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
-; GFX1150-TRUE16-NEXT: ; %bb.12: ; %frem.compute
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_14
+; GFX1150-TRUE16-NEXT: .LBB9_10: ; %frem.compute
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
@@ -6583,12 +6515,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_13
+; GFX1150-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s7, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: .LBB9_12: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -6604,10 +6536,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
-; GFX1150-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_12
+; GFX1150-TRUE16-NEXT: .LBB9_13: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB9_16: ; %Flow54
+; GFX1150-TRUE16-NEXT: .LBB9_14: ; %Flow54
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -6655,17 +6587,16 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB9_3
+; GFX1150-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX1150-FAKE16-NEXT: s_branch .LBB9_8
; GFX1150-FAKE16-NEXT: .LBB9_2:
; GFX1150-FAKE16-NEXT: s_mov_b32 s7, -1
; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-FAKE16-NEXT: .LBB9_3: ; %Flow57
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-FAKE16-NEXT: s_cselect_b32 s7, 1, 0
-; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_9
-; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_8
+; GFX1150-FAKE16-NEXT: .LBB9_3: ; %frem.compute19
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s5
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
@@ -6699,12 +6630,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_8
-; GFX1150-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; GFX1150-FAKE16-NEXT: s_sub_i32 s5, s6, s5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s5, s5, 11
-; GFX1150-FAKE16-NEXT: .LBB9_6: ; %frem.loop_body27
+; GFX1150-FAKE16-NEXT: .LBB9_5: ; %frem.loop_body27
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -6722,11 +6653,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX1150-FAKE16-NEXT: ; %bb.7: ; %Flow55
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_5
+; GFX1150-FAKE16-NEXT: ; %bb.6: ; %Flow55
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, s5
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, v5
-; GFX1150-FAKE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX1150-FAKE16-NEXT: .LBB9_7: ; %frem.loop_exit28
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
@@ -6745,7 +6676,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s4
-; GFX1150-FAKE16-NEXT: .LBB9_9:
+; GFX1150-FAKE16-NEXT: .LBB9_8:
; GFX1150-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1150-FAKE16-NEXT: s_lshr_b32 s5, s3, 16
; GFX1150-FAKE16-NEXT: s_and_b32 s4, s6, 0x7fff
@@ -6754,8 +6685,8 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s7, s7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s8, s7
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_11
-; GFX1150-FAKE16-NEXT: ; %bb.10: ; %frem.else
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_10
+; GFX1150-FAKE16-NEXT: ; %bb.9: ; %frem.else
; GFX1150-FAKE16-NEXT: s_and_b32 s9, 0x8000, s6
; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s8, s7
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v1, s9
@@ -6763,17 +6694,16 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB9_12
-; GFX1150-FAKE16-NEXT: .LBB9_11:
+; GFX1150-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
+; GFX1150-FAKE16-NEXT: s_branch .LBB9_16
+; GFX1150-FAKE16-NEXT: .LBB9_10:
; GFX1150-FAKE16-NEXT: s_mov_b32 s9, -1
; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-FAKE16-NEXT: .LBB9_12: ; %Flow53
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1150-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
-; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_18
-; GFX1150-FAKE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_16
+; GFX1150-FAKE16-NEXT: .LBB9_11: ; %frem.compute
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s7
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s8
; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
@@ -6807,12 +6737,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_17
-; GFX1150-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX1150-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX1150-FAKE16-NEXT: s_sub_i32 s7, s8, s7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s7, s7, 11
-; GFX1150-FAKE16-NEXT: .LBB9_15: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT: .LBB9_13: ; %frem.loop_body
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -6830,11 +6760,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_15
-; GFX1150-FAKE16-NEXT: ; %bb.16: ; %Flow
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_13
+; GFX1150-FAKE16-NEXT: ; %bb.14: ; %Flow
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, s7
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, v6
-; GFX1150-FAKE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX1150-FAKE16-NEXT: .LBB9_15: ; %frem.loop_exit
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
@@ -6853,7 +6783,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s6
-; GFX1150-FAKE16-NEXT: .LBB9_18: ; %Flow54
+; GFX1150-FAKE16-NEXT: .LBB9_16: ; %Flow54
; GFX1150-FAKE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -6902,18 +6832,17 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s7
; GFX1200-TRUE16-NEXT: s_mov_b32 s7, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB9_3
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX1200-TRUE16-NEXT: s_branch .LBB9_7
; GFX1200-TRUE16-NEXT: .LBB9_2:
; GFX1200-TRUE16-NEXT: s_mov_b32 s7, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: .LBB9_3: ; %Flow57
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
-; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_7
+; GFX1200-TRUE16-NEXT: .LBB9_3: ; %frem.compute19
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
@@ -6946,12 +6875,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
-; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_6
+; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s5, s6, s5
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s5, s5, 11
-; GFX1200-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT: .LBB9_5: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -6970,10 +6899,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX1200-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_5
+; GFX1200-TRUE16-NEXT: .LBB9_6: ; %frem.loop_exit28
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: .LBB9_8:
+; GFX1200-TRUE16-NEXT: .LBB9_7:
; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
; GFX1200-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
@@ -6985,8 +6914,8 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
-; GFX1200-TRUE16-NEXT: ; %bb.9: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_9
+; GFX1200-TRUE16-NEXT: ; %bb.8: ; %frem.else
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
@@ -6994,18 +6923,17 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
; GFX1200-TRUE16-NEXT: s_mov_b32 s8, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB9_11
-; GFX1200-TRUE16-NEXT: .LBB9_10:
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_10
+; GFX1200-TRUE16-NEXT: s_branch .LBB9_14
+; GFX1200-TRUE16-NEXT: .LBB9_9:
; GFX1200-TRUE16-NEXT: s_mov_b32 s8, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB9_11: ; %Flow53
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s8, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
-; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.compute
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_14
+; GFX1200-TRUE16-NEXT: .LBB9_10: ; %frem.compute
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
@@ -7039,12 +6967,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_13
+; GFX1200-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s7, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: .LBB9_12: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -7063,10 +6991,10 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
-; GFX1200-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_12
+; GFX1200-TRUE16-NEXT: .LBB9_13: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB9_16: ; %Flow54
+; GFX1200-TRUE16-NEXT: .LBB9_14: ; %Flow54
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -7115,18 +7043,17 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB9_3
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX1200-FAKE16-NEXT: s_branch .LBB9_8
; GFX1200-FAKE16-NEXT: .LBB9_2:
; GFX1200-FAKE16-NEXT: s_mov_b32 s7, -1
; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-FAKE16-NEXT: .LBB9_3: ; %Flow57
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1200-FAKE16-NEXT: s_cselect_b32 s7, 1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_9
-; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.compute19
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_8
+; GFX1200-FAKE16-NEXT: .LBB9_3: ; %frem.compute19
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s5
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
@@ -7161,12 +7088,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_8
-; GFX1200-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s5, s6, s5
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s5, s5, 11
-; GFX1200-FAKE16-NEXT: .LBB9_6: ; %frem.loop_body27
+; GFX1200-FAKE16-NEXT: .LBB9_5: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -7186,11 +7113,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX1200-FAKE16-NEXT: ; %bb.7: ; %Flow55
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_5
+; GFX1200-FAKE16-NEXT: ; %bb.6: ; %Flow55
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, s5
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, v5
-; GFX1200-FAKE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX1200-FAKE16-NEXT: .LBB9_7: ; %frem.loop_exit28
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
@@ -7210,7 +7137,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s4
-; GFX1200-FAKE16-NEXT: .LBB9_9:
+; GFX1200-FAKE16-NEXT: .LBB9_8:
; GFX1200-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-FAKE16-NEXT: s_lshr_b32 s5, s3, 16
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -7222,8 +7149,8 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s8, s7
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_11
-; GFX1200-FAKE16-NEXT: ; %bb.10: ; %frem.else
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_10
+; GFX1200-FAKE16-NEXT: ; %bb.9: ; %frem.else
; GFX1200-FAKE16-NEXT: s_and_b32 s9, 0x8000, s6
; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s8, s7
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, s9
@@ -7232,18 +7159,16 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB9_12
-; GFX1200-FAKE16-NEXT: .LBB9_11:
+; GFX1200-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
+; GFX1200-FAKE16-NEXT: s_branch .LBB9_16
+; GFX1200-FAKE16-NEXT: .LBB9_10:
; GFX1200-FAKE16-NEXT: s_mov_b32 s9, -1
; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-FAKE16-NEXT: .LBB9_12: ; %Flow53
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1200-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_18
-; GFX1200-FAKE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_16
+; GFX1200-FAKE16-NEXT: .LBB9_11: ; %frem.compute
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s7
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s8
; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
@@ -7278,12 +7203,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_17
-; GFX1200-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_15
+; GFX1200-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s7, s8, s7
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s7, s7, 11
-; GFX1200-FAKE16-NEXT: .LBB9_15: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT: .LBB9_13: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -7303,11 +7228,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_15
-; GFX1200-FAKE16-NEXT: ; %bb.16: ; %Flow
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_13
+; GFX1200-FAKE16-NEXT: ; %bb.14: ; %Flow
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, s7
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, v6
-; GFX1200-FAKE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX1200-FAKE16-NEXT: .LBB9_15: ; %frem.loop_exit
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
@@ -7327,7 +7252,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s6
-; GFX1200-FAKE16-NEXT: .LBB9_18: ; %Flow54
+; GFX1200-FAKE16-NEXT: .LBB9_16: ; %Flow54
; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -7379,23 +7304,24 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e64 v2, |v0|
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2
-; SI-NEXT: s_cbranch_vccz .LBB10_2
+; SI-NEXT: s_cbranch_vccz .LBB10_3
; SI-NEXT: ; %bb.1: ; %frem.else86
; SI-NEXT: s_and_b32 s4, s3, 0xffff8000
; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: s_cselect_b32 s4, s4, s3
; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_branch .LBB10_3
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cbranch_scc1 .LBB10_4
; SI-NEXT: .LBB10_2:
+; SI-NEXT: v_mov_b32_e32 v3, s4
+; SI-NEXT: s_branch .LBB10_9
+; SI-NEXT: .LBB10_3:
; SI-NEXT: s_mov_b64 s[0:1], -1
; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: .LBB10_3: ; %Flow135
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s0, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s0, 1
-; SI-NEXT: s_cbranch_scc1 .LBB10_9
-; SI-NEXT: ; %bb.4: ; %frem.compute85
+; SI-NEXT: s_cbranch_scc0 .LBB10_2
+; SI-NEXT: .LBB10_4: ; %frem.compute85
; SI-NEXT: s_mov_b32 s5, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s5
; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v3
@@ -7463,35 +7389,33 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_and_b32 s0, s3, 0xffff8000
; SI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; SI-NEXT: v_or_b32_e32 v3, s0, v2
-; SI-NEXT: s_branch .LBB10_10
-; SI-NEXT: .LBB10_9:
-; SI-NEXT: v_mov_b32_e32 v3, s4
-; SI-NEXT: .LBB10_10: ; %Flow136
+; SI-NEXT: .LBB10_9: ; %Flow136
; SI-NEXT: s_lshr_b32 s4, s2, 16
; SI-NEXT: s_lshr_b32 s5, s3, 16
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; SI-NEXT: ; %bb.11:
+; SI-NEXT: ; %bb.10:
; SI-NEXT: v_cvt_f32_f16_e64 v6, |s5|
; SI-NEXT: v_cvt_f32_f16_e64 v5, |v4|
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
; SI-NEXT: s_cbranch_vccz .LBB10_13
-; SI-NEXT: ; %bb.12: ; %frem.else53
+; SI-NEXT: ; %bb.11: ; %frem.else53
; SI-NEXT: s_and_b32 s6, s5, 0x8000
; SI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: s_cselect_b32 s6, s6, s5
; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_branch .LBB10_14
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cbranch_scc1 .LBB10_14
+; SI-NEXT: .LBB10_12:
+; SI-NEXT: v_mov_b32_e32 v5, s6
+; SI-NEXT: s_branch .LBB10_19
; SI-NEXT: .LBB10_13:
; SI-NEXT: s_mov_b64 s[0:1], -1
; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: .LBB10_14: ; %Flow131
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s0, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s0, 1
-; SI-NEXT: s_cbranch_scc1 .LBB10_20
-; SI-NEXT: ; %bb.15: ; %frem.compute52
+; SI-NEXT: s_cbranch_scc0 .LBB10_12
+; SI-NEXT: .LBB10_14: ; %frem.compute52
; SI-NEXT: s_mov_b32 s7, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
; SI-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
@@ -7526,11 +7450,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v7, v7, v9, v10
; SI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_19
-; SI-NEXT: ; %bb.16: ; %frem.loop_body60.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB10_18
+; SI-NEXT: ; %bb.15: ; %frem.loop_body60.preheader
; SI-NEXT: s_sub_i32 s1, s6, s7
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB10_17: ; %frem.loop_body60
+; SI-NEXT: .LBB10_16: ; %frem.loop_body60
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v8, v6
; SI-NEXT: v_mul_f32_e32 v6, v8, v7
@@ -7542,10 +7466,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v6, v6, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_17
-; SI-NEXT: ; %bb.18: ; %Flow129
+; SI-NEXT: s_cbranch_scc1 .LBB10_16
+; SI-NEXT: ; %bb.17: ; %Flow129
; SI-NEXT: v_mov_b32_e32 v6, v8
-; SI-NEXT: .LBB10_19: ; %frem.loop_exit61
+; SI-NEXT: .LBB10_18: ; %frem.loop_exit61
; SI-NEXT: s_add_i32 s1, s1, -10
; SI-NEXT: v_ldexp_f32_e64 v6, v6, s1
; SI-NEXT: v_mul_f32_e32 v7, v6, v7
@@ -7559,30 +7483,28 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_and_b32 s0, s5, 0x8000
; SI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
; SI-NEXT: v_or_b32_e32 v5, s0, v5
-; SI-NEXT: s_branch .LBB10_21
-; SI-NEXT: .LBB10_20:
-; SI-NEXT: v_mov_b32_e32 v5, s6
-; SI-NEXT: .LBB10_21:
+; SI-NEXT: .LBB10_19:
; SI-NEXT: v_cvt_f32_f16_e64 v7, |s2|
; SI-NEXT: v_cvt_f32_f16_e64 v6, |v1|
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
-; SI-NEXT: s_cbranch_vccz .LBB10_23
-; SI-NEXT: ; %bb.22: ; %frem.else20
+; SI-NEXT: s_cbranch_vccz .LBB10_22
+; SI-NEXT: ; %bb.20: ; %frem.else20
; SI-NEXT: s_and_b32 s6, s2, 0xffff8000
; SI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: s_cselect_b32 s6, s6, s2
; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_branch .LBB10_24
-; SI-NEXT: .LBB10_23:
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cbranch_scc1 .LBB10_23
+; SI-NEXT: .LBB10_21:
+; SI-NEXT: v_mov_b32_e32 v6, s6
+; SI-NEXT: s_branch .LBB10_28
+; SI-NEXT: .LBB10_22:
; SI-NEXT: s_mov_b64 s[0:1], -1
; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: .LBB10_24: ; %Flow127
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s0, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s0, 1
-; SI-NEXT: s_cbranch_scc1 .LBB10_30
-; SI-NEXT: ; %bb.25: ; %frem.compute19
+; SI-NEXT: s_cbranch_scc0 .LBB10_21
+; SI-NEXT: .LBB10_23: ; %frem.compute19
; SI-NEXT: s_mov_b32 s7, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s7
; SI-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
@@ -7617,11 +7539,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v8, v8, v10, v11
; SI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_29
-; SI-NEXT: ; %bb.26: ; %frem.loop_body27.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB10_27
+; SI-NEXT: ; %bb.24: ; %frem.loop_body27.preheader
; SI-NEXT: s_sub_i32 s1, s6, s7
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB10_27: ; %frem.loop_body27
+; SI-NEXT: .LBB10_25: ; %frem.loop_body27
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v9, v7
; SI-NEXT: v_mul_f32_e32 v7, v9, v8
@@ -7633,10 +7555,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v7, v7, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_27
-; SI-NEXT: ; %bb.28: ; %Flow125
+; SI-NEXT: s_cbranch_scc1 .LBB10_25
+; SI-NEXT: ; %bb.26: ; %Flow125
; SI-NEXT: v_mov_b32_e32 v7, v9
-; SI-NEXT: .LBB10_29: ; %frem.loop_exit28
+; SI-NEXT: .LBB10_27: ; %frem.loop_exit28
; SI-NEXT: s_add_i32 s1, s1, -10
; SI-NEXT: v_ldexp_f32_e64 v7, v7, s1
; SI-NEXT: v_mul_f32_e32 v8, v7, v8
@@ -7650,30 +7572,28 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_and_b32 s0, s2, 0xffff8000
; SI-NEXT: v_and_b32_e32 v6, 0x7fff, v6
; SI-NEXT: v_or_b32_e32 v6, s0, v6
-; SI-NEXT: s_branch .LBB10_31
-; SI-NEXT: .LBB10_30:
-; SI-NEXT: v_mov_b32_e32 v6, s6
-; SI-NEXT: .LBB10_31:
+; SI-NEXT: .LBB10_28:
; SI-NEXT: v_cvt_f32_f16_e64 v8, |s4|
; SI-NEXT: v_cvt_f32_f16_e64 v7, |v2|
; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v8, v7
-; SI-NEXT: s_cbranch_vccz .LBB10_33
-; SI-NEXT: ; %bb.32: ; %frem.else
+; SI-NEXT: s_cbranch_vccz .LBB10_31
+; SI-NEXT: ; %bb.29: ; %frem.else
; SI-NEXT: s_and_b32 s6, s4, 0x8000
; SI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: s_cselect_b32 s6, s6, s4
; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_branch .LBB10_34
-; SI-NEXT: .LBB10_33:
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cbranch_scc1 .LBB10_32
+; SI-NEXT: .LBB10_30:
+; SI-NEXT: v_mov_b32_e32 v7, s6
+; SI-NEXT: s_branch .LBB10_37
+; SI-NEXT: .LBB10_31:
; SI-NEXT: s_mov_b64 s[0:1], -1
; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: .LBB10_34: ; %Flow123
; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s0, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s0, 1
-; SI-NEXT: s_cbranch_scc1 .LBB10_40
-; SI-NEXT: ; %bb.35: ; %frem.compute
+; SI-NEXT: s_cbranch_scc0 .LBB10_30
+; SI-NEXT: .LBB10_32: ; %frem.compute
; SI-NEXT: s_mov_b32 s7, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s7
; SI-NEXT: v_frexp_exp_i32_f32_e32 v9, v8
@@ -7708,11 +7628,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v9, v9, v11, v12
; SI-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_39
-; SI-NEXT: ; %bb.36: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB10_36
+; SI-NEXT: ; %bb.33: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s1, s6, s7
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB10_37: ; %frem.loop_body
+; SI-NEXT: .LBB10_34: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v10, v8
; SI-NEXT: v_mul_f32_e32 v8, v10, v9
@@ -7724,10 +7644,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v8, v8, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_37
-; SI-NEXT: ; %bb.38: ; %Flow
+; SI-NEXT: s_cbranch_scc1 .LBB10_34
+; SI-NEXT: ; %bb.35: ; %Flow
; SI-NEXT: v_mov_b32_e32 v8, v10
-; SI-NEXT: .LBB10_39: ; %frem.loop_exit
+; SI-NEXT: .LBB10_36: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s1, s1, -10
; SI-NEXT: v_ldexp_f32_e64 v8, v8, s1
; SI-NEXT: v_mul_f32_e32 v9, v8, v9
@@ -7741,10 +7661,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_and_b32 s0, s4, 0x8000
; SI-NEXT: v_and_b32_e32 v7, 0x7fff, v7
; SI-NEXT: v_or_b32_e32 v7, s0, v7
-; SI-NEXT: s_branch .LBB10_41
-; SI-NEXT: .LBB10_40:
-; SI-NEXT: v_mov_b32_e32 v7, s6
-; SI-NEXT: .LBB10_41: ; %Flow124
+; SI-NEXT: .LBB10_37: ; %Flow124
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
@@ -7802,23 +7719,24 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_cvt_f32_f16_e64 v2, |v0|
; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2
-; CI-NEXT: s_cbranch_vccz .LBB10_2
+; CI-NEXT: s_cbranch_vccz .LBB10_3
; CI-NEXT: ; %bb.1: ; %frem.else86
; CI-NEXT: s_and_b32 s4, s3, 0xffff8000
; CI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
; CI-NEXT: s_and_b64 s[0:1], vcc, exec
; CI-NEXT: s_cselect_b32 s4, s4, s3
; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_branch .LBB10_3
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cbranch_scc1 .LBB10_4
; CI-NEXT: .LBB10_2:
+; CI-NEXT: v_mov_b32_e32 v3, s4
+; CI-NEXT: s_branch .LBB10_9
+; CI-NEXT: .LBB10_3:
; CI-NEXT: s_mov_b64 s[0:1], -1
; CI-NEXT: ; implicit-def: $sgpr4
-; CI-NEXT: .LBB10_3: ; %Flow135
; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cselect_b32 s0, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s0, 1
-; CI-NEXT: s_cbranch_scc1 .LBB10_9
-; CI-NEXT: ; %bb.4: ; %frem.compute85
+; CI-NEXT: s_cbranch_scc0 .LBB10_2
+; CI-NEXT: .LBB10_4: ; %frem.compute85
; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
; CI-NEXT: v_frexp_mant_f32_e32 v3, v3
; CI-NEXT: v_ldexp_f32_e64 v5, v3, 11
@@ -7875,35 +7793,33 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_and_b32 s0, s3, 0xffff8000
; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; CI-NEXT: v_or_b32_e32 v3, s0, v2
-; CI-NEXT: s_branch .LBB10_10
-; CI-NEXT: .LBB10_9:
-; CI-NEXT: v_mov_b32_e32 v3, s4
-; CI-NEXT: .LBB10_10: ; %Flow136
+; CI-NEXT: .LBB10_9: ; %Flow136
; CI-NEXT: s_lshr_b32 s4, s2, 16
; CI-NEXT: s_lshr_b32 s5, s3, 16
; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; CI-NEXT: ; %bb.11:
+; CI-NEXT: ; %bb.10:
; CI-NEXT: v_cvt_f32_f16_e64 v6, |s5|
; CI-NEXT: v_cvt_f32_f16_e64 v5, |v4|
; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
; CI-NEXT: s_cbranch_vccz .LBB10_13
-; CI-NEXT: ; %bb.12: ; %frem.else53
+; CI-NEXT: ; %bb.11: ; %frem.else53
; CI-NEXT: s_and_b32 s6, s5, 0x8000
; CI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
; CI-NEXT: s_and_b64 s[0:1], vcc, exec
; CI-NEXT: s_cselect_b32 s6, s6, s5
; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_branch .LBB10_14
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cbranch_scc1 .LBB10_14
+; CI-NEXT: .LBB10_12:
+; CI-NEXT: v_mov_b32_e32 v5, s6
+; CI-NEXT: s_branch .LBB10_19
; CI-NEXT: .LBB10_13:
; CI-NEXT: s_mov_b64 s[0:1], -1
; CI-NEXT: ; implicit-def: $sgpr6
-; CI-NEXT: .LBB10_14: ; %Flow131
; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cselect_b32 s0, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s0, 1
-; CI-NEXT: s_cbranch_scc1 .LBB10_20
-; CI-NEXT: ; %bb.15: ; %frem.compute52
+; CI-NEXT: s_cbranch_scc0 .LBB10_12
+; CI-NEXT: .LBB10_14: ; %frem.compute52
; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v6
; CI-NEXT: v_frexp_mant_f32_e32 v6, v6
; CI-NEXT: v_ldexp_f32_e64 v8, v6, 11
@@ -7927,11 +7843,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v7
; CI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_19
-; CI-NEXT: ; %bb.16: ; %frem.loop_body60.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB10_18
+; CI-NEXT: ; %bb.15: ; %frem.loop_body60.preheader
; CI-NEXT: v_sub_i32_e32 v7, vcc, v10, v11
; CI-NEXT: v_add_i32_e32 v7, vcc, 11, v7
-; CI-NEXT: .LBB10_17: ; %frem.loop_body60
+; CI-NEXT: .LBB10_16: ; %frem.loop_body60
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v10, v8
; CI-NEXT: v_mul_f32_e32 v8, v10, v9
@@ -7943,10 +7859,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v7, vcc, -11, v7
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v7
; CI-NEXT: v_ldexp_f32_e64 v8, v8, 11
-; CI-NEXT: s_cbranch_vccnz .LBB10_17
-; CI-NEXT: ; %bb.18: ; %Flow129
+; CI-NEXT: s_cbranch_vccnz .LBB10_16
+; CI-NEXT: ; %bb.17: ; %Flow129
; CI-NEXT: v_mov_b32_e32 v8, v10
-; CI-NEXT: .LBB10_19: ; %frem.loop_exit61
+; CI-NEXT: .LBB10_18: ; %frem.loop_exit61
; CI-NEXT: v_add_i32_e32 v7, vcc, -10, v7
; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
; CI-NEXT: v_mul_f32_e32 v8, v7, v9
@@ -7960,30 +7876,28 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_and_b32 s0, s5, 0x8000
; CI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
; CI-NEXT: v_or_b32_e32 v5, s0, v5
-; CI-NEXT: s_branch .LBB10_21
-; CI-NEXT: .LBB10_20:
-; CI-NEXT: v_mov_b32_e32 v5, s6
-; CI-NEXT: .LBB10_21:
+; CI-NEXT: .LBB10_19:
; CI-NEXT: v_cvt_f32_f16_e64 v7, |s2|
; CI-NEXT: v_cvt_f32_f16_e64 v6, |v1|
; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
-; CI-NEXT: s_cbranch_vccz .LBB10_23
-; CI-NEXT: ; %bb.22: ; %frem.else20
+; CI-NEXT: s_cbranch_vccz .LBB10_22
+; CI-NEXT: ; %bb.20: ; %frem.else20
; CI-NEXT: s_and_b32 s6, s2, 0xffff8000
; CI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
; CI-NEXT: s_and_b64 s[0:1], vcc, exec
; CI-NEXT: s_cselect_b32 s6, s6, s2
; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_branch .LBB10_24
-; CI-NEXT: .LBB10_23:
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cbranch_scc1 .LBB10_23
+; CI-NEXT: .LBB10_21:
+; CI-NEXT: v_mov_b32_e32 v6, s6
+; CI-NEXT: s_branch .LBB10_28
+; CI-NEXT: .LBB10_22:
; CI-NEXT: s_mov_b64 s[0:1], -1
; CI-NEXT: ; implicit-def: $sgpr6
-; CI-NEXT: .LBB10_24: ; %Flow127
; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cselect_b32 s0, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s0, 1
-; CI-NEXT: s_cbranch_scc1 .LBB10_30
-; CI-NEXT: ; %bb.25: ; %frem.compute19
+; CI-NEXT: s_cbranch_scc0 .LBB10_21
+; CI-NEXT: .LBB10_23: ; %frem.compute19
; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v7
; CI-NEXT: v_frexp_mant_f32_e32 v7, v7
; CI-NEXT: v_ldexp_f32_e64 v9, v7, 11
@@ -8007,11 +7921,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v10, v10, v14, v15
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v8
; CI-NEXT: v_div_fixup_f32 v10, v10, v7, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_29
-; CI-NEXT: ; %bb.26: ; %frem.loop_body27.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB10_27
+; CI-NEXT: ; %bb.24: ; %frem.loop_body27.preheader
; CI-NEXT: v_sub_i32_e32 v8, vcc, v11, v12
; CI-NEXT: v_add_i32_e32 v8, vcc, 11, v8
-; CI-NEXT: .LBB10_27: ; %frem.loop_body27
+; CI-NEXT: .LBB10_25: ; %frem.loop_body27
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v11, v9
; CI-NEXT: v_mul_f32_e32 v9, v11, v10
@@ -8023,10 +7937,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v8, vcc, -11, v8
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v8
; CI-NEXT: v_ldexp_f32_e64 v9, v9, 11
-; CI-NEXT: s_cbranch_vccnz .LBB10_27
-; CI-NEXT: ; %bb.28: ; %Flow125
+; CI-NEXT: s_cbranch_vccnz .LBB10_25
+; CI-NEXT: ; %bb.26: ; %Flow125
; CI-NEXT: v_mov_b32_e32 v9, v11
-; CI-NEXT: .LBB10_29: ; %frem.loop_exit28
+; CI-NEXT: .LBB10_27: ; %frem.loop_exit28
; CI-NEXT: v_add_i32_e32 v8, vcc, -10, v8
; CI-NEXT: v_ldexp_f32_e32 v8, v9, v8
; CI-NEXT: v_mul_f32_e32 v9, v8, v10
@@ -8040,30 +7954,28 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_and_b32 s0, s2, 0xffff8000
; CI-NEXT: v_and_b32_e32 v6, 0x7fff, v6
; CI-NEXT: v_or_b32_e32 v6, s0, v6
-; CI-NEXT: s_branch .LBB10_31
-; CI-NEXT: .LBB10_30:
-; CI-NEXT: v_mov_b32_e32 v6, s6
-; CI-NEXT: .LBB10_31:
+; CI-NEXT: .LBB10_28:
; CI-NEXT: v_cvt_f32_f16_e64 v8, |s4|
; CI-NEXT: v_cvt_f32_f16_e64 v7, |v2|
; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v8, v7
-; CI-NEXT: s_cbranch_vccz .LBB10_33
-; CI-NEXT: ; %bb.32: ; %frem.else
+; CI-NEXT: s_cbranch_vccz .LBB10_31
+; CI-NEXT: ; %bb.29: ; %frem.else
; CI-NEXT: s_and_b32 s6, s4, 0x8000
; CI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
; CI-NEXT: s_and_b64 s[0:1], vcc, exec
; CI-NEXT: s_cselect_b32 s6, s6, s4
; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_branch .LBB10_34
-; CI-NEXT: .LBB10_33:
+; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; CI-NEXT: s_cbranch_scc1 .LBB10_32
+; CI-NEXT: .LBB10_30:
+; CI-NEXT: v_mov_b32_e32 v7, s6
+; CI-NEXT: s_branch .LBB10_37
+; CI-NEXT: .LBB10_31:
; CI-NEXT: s_mov_b64 s[0:1], -1
; CI-NEXT: ; implicit-def: $sgpr6
-; CI-NEXT: .LBB10_34: ; %Flow123
; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cselect_b32 s0, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s0, 1
-; CI-NEXT: s_cbranch_scc1 .LBB10_40
-; CI-NEXT: ; %bb.35: ; %frem.compute
+; CI-NEXT: s_cbranch_scc0 .LBB10_30
+; CI-NEXT: .LBB10_32: ; %frem.compute
; CI-NEXT: v_frexp_exp_i32_f32_e32 v12, v8
; CI-NEXT: v_frexp_mant_f32_e32 v8, v8
; CI-NEXT: v_ldexp_f32_e64 v10, v8, 11
@@ -8087,11 +7999,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v11, v11, v15, v16
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v9
; CI-NEXT: v_div_fixup_f32 v11, v11, v8, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_39
-; CI-NEXT: ; %bb.36: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB10_36
+; CI-NEXT: ; %bb.33: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v9, vcc, v12, v13
; CI-NEXT: v_add_i32_e32 v9, vcc, 11, v9
-; CI-NEXT: .LBB10_37: ; %frem.loop_body
+; CI-NEXT: .LBB10_34: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v12, v10
; CI-NEXT: v_mul_f32_e32 v10, v12, v11
@@ -8103,10 +8015,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v9, vcc, -11, v9
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v9
; CI-NEXT: v_ldexp_f32_e64 v10, v10, 11
-; CI-NEXT: s_cbranch_vccnz .LBB10_37
-; CI-NEXT: ; %bb.38: ; %Flow
+; CI-NEXT: s_cbranch_vccnz .LBB10_34
+; CI-NEXT: ; %bb.35: ; %Flow
; CI-NEXT: v_mov_b32_e32 v10, v12
-; CI-NEXT: .LBB10_39: ; %frem.loop_exit
+; CI-NEXT: .LBB10_36: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v9, vcc, -10, v9
; CI-NEXT: v_ldexp_f32_e32 v9, v10, v9
; CI-NEXT: v_mul_f32_e32 v10, v9, v11
@@ -8120,10 +8032,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_and_b32 s0, s4, 0x8000
; CI-NEXT: v_and_b32_e32 v7, 0x7fff, v7
; CI-NEXT: v_or_b32_e32 v7, s0, v7
-; CI-NEXT: s_branch .LBB10_41
-; CI-NEXT: .LBB10_40:
-; CI-NEXT: v_mov_b32_e32 v7, s6
-; CI-NEXT: .LBB10_41: ; %Flow124
+; CI-NEXT: .LBB10_37: ; %Flow124
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
@@ -8185,16 +8094,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
; VI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB10_3
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB10_3
+; VI-NEXT: s_branch .LBB10_8
; VI-NEXT: .LBB10_2:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr4
-; VI-NEXT: .LBB10_3: ; %Flow135
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB10_9
-; VI-NEXT: ; %bb.4: ; %frem.compute85
+; VI-NEXT: s_cbranch_scc0 .LBB10_8
+; VI-NEXT: .LBB10_3: ; %frem.compute85
; VI-NEXT: v_frexp_exp_i32_f32_e32 v9, v6
; VI-NEXT: v_frexp_mant_f32_e32 v4, v6
; VI-NEXT: v_frexp_mant_f32_e32 v6, v5
@@ -8218,11 +8126,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
; VI-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_8
-; VI-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB10_7
+; VI-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; VI-NEXT: v_sub_u32_e32 v6, vcc, v9, v10
; VI-NEXT: v_add_u32_e32 v6, vcc, 11, v6
-; VI-NEXT: .LBB10_6: ; %frem.loop_body93
+; VI-NEXT: .LBB10_5: ; %frem.loop_body93
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v9, v7
; VI-NEXT: v_mul_f32_e32 v7, v9, v8
@@ -8234,10 +8142,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v6, vcc, -11, v6
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
; VI-NEXT: v_ldexp_f32 v7, v7, 11
-; VI-NEXT: s_cbranch_vccnz .LBB10_6
-; VI-NEXT: ; %bb.7: ; %Flow133
+; VI-NEXT: s_cbranch_vccnz .LBB10_5
+; VI-NEXT: ; %bb.6: ; %Flow133
; VI-NEXT: v_mov_b32_e32 v7, v9
-; VI-NEXT: .LBB10_8: ; %frem.loop_exit94
+; VI-NEXT: .LBB10_7: ; %frem.loop_exit94
; VI-NEXT: v_add_u32_e32 v6, vcc, -10, v6
; VI-NEXT: v_ldexp_f32 v6, v7, v6
; VI-NEXT: v_mul_f32_e32 v7, v6, v8
@@ -8250,28 +8158,27 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cvt_f16_f32_e32 v4, v4
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; VI-NEXT: .LBB10_9:
+; VI-NEXT: .LBB10_8:
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; VI-NEXT: v_cvt_f32_f16_e64 v9, |v5|
; VI-NEXT: v_cvt_f32_f16_e64 v8, |v6|
; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v9, v8
-; VI-NEXT: s_cbranch_vccz .LBB10_11
-; VI-NEXT: ; %bb.10: ; %frem.else53
+; VI-NEXT: s_cbranch_vccz .LBB10_10
+; VI-NEXT: ; %bb.9: ; %frem.else53
; VI-NEXT: v_and_b32_e32 v7, 0x8000, v5
; VI-NEXT: v_cmp_eq_f32_e32 vcc, v9, v8
; VI-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB10_12
-; VI-NEXT: .LBB10_11:
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB10_11
+; VI-NEXT: s_branch .LBB10_16
+; VI-NEXT: .LBB10_10:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr7
-; VI-NEXT: .LBB10_12: ; %Flow131
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB10_18
-; VI-NEXT: ; %bb.13: ; %frem.compute52
+; VI-NEXT: s_cbranch_scc0 .LBB10_16
+; VI-NEXT: .LBB10_11: ; %frem.compute52
; VI-NEXT: v_frexp_exp_i32_f32_e32 v12, v9
; VI-NEXT: v_frexp_mant_f32_e32 v7, v9
; VI-NEXT: v_frexp_mant_f32_e32 v9, v8
@@ -8295,11 +8202,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v11, v11, v15, v16
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v9
; VI-NEXT: v_div_fixup_f32 v11, v11, v8, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_17
-; VI-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB10_15
+; VI-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
; VI-NEXT: v_sub_u32_e32 v9, vcc, v12, v13
; VI-NEXT: v_add_u32_e32 v9, vcc, 11, v9
-; VI-NEXT: .LBB10_15: ; %frem.loop_body60
+; VI-NEXT: .LBB10_13: ; %frem.loop_body60
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v12, v10
; VI-NEXT: v_mul_f32_e32 v10, v12, v11
@@ -8311,10 +8218,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v9, vcc, -11, v9
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v9
; VI-NEXT: v_ldexp_f32 v10, v10, 11
-; VI-NEXT: s_cbranch_vccnz .LBB10_15
-; VI-NEXT: ; %bb.16: ; %Flow129
+; VI-NEXT: s_cbranch_vccnz .LBB10_13
+; VI-NEXT: ; %bb.14: ; %Flow129
; VI-NEXT: v_mov_b32_e32 v10, v12
-; VI-NEXT: .LBB10_17: ; %frem.loop_exit61
+; VI-NEXT: .LBB10_15: ; %frem.loop_exit61
; VI-NEXT: v_add_u32_e32 v9, vcc, -10, v9
; VI-NEXT: v_ldexp_f32 v9, v10, v9
; VI-NEXT: v_mul_f32_e32 v10, v9, v11
@@ -8327,26 +8234,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cvt_f16_f32_e32 v7, v7
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v7, s2, v7, v5
-; VI-NEXT: .LBB10_18:
+; VI-NEXT: .LBB10_16:
; VI-NEXT: v_cvt_f32_f16_e64 v10, |v1|
; VI-NEXT: v_cvt_f32_f16_e64 v9, |v3|
; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v10, v9
-; VI-NEXT: s_cbranch_vccz .LBB10_20
-; VI-NEXT: ; %bb.19: ; %frem.else20
+; VI-NEXT: s_cbranch_vccz .LBB10_18
+; VI-NEXT: ; %bb.17: ; %frem.else20
; VI-NEXT: v_and_b32_e32 v8, 0x8000, v1
; VI-NEXT: v_cmp_eq_f32_e32 vcc, v10, v9
; VI-NEXT: v_cndmask_b32_e32 v8, v1, v8, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB10_21
-; VI-NEXT: .LBB10_20:
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB10_19
+; VI-NEXT: s_branch .LBB10_24
+; VI-NEXT: .LBB10_18:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr8
-; VI-NEXT: .LBB10_21: ; %Flow127
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB10_27
-; VI-NEXT: ; %bb.22: ; %frem.compute19
+; VI-NEXT: s_cbranch_scc0 .LBB10_24
+; VI-NEXT: .LBB10_19: ; %frem.compute19
; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v10
; VI-NEXT: v_frexp_mant_f32_e32 v8, v10
; VI-NEXT: v_frexp_mant_f32_e32 v10, v9
@@ -8370,11 +8276,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v12, v12, v16, v17
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v10
; VI-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_26
-; VI-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB10_23
+; VI-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
; VI-NEXT: v_sub_u32_e32 v10, vcc, v13, v14
; VI-NEXT: v_add_u32_e32 v10, vcc, 11, v10
-; VI-NEXT: .LBB10_24: ; %frem.loop_body27
+; VI-NEXT: .LBB10_21: ; %frem.loop_body27
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v13, v11
; VI-NEXT: v_mul_f32_e32 v11, v13, v12
@@ -8386,10 +8292,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v10, vcc, -11, v10
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v10
; VI-NEXT: v_ldexp_f32 v11, v11, 11
-; VI-NEXT: s_cbranch_vccnz .LBB10_24
-; VI-NEXT: ; %bb.25: ; %Flow125
+; VI-NEXT: s_cbranch_vccnz .LBB10_21
+; VI-NEXT: ; %bb.22: ; %Flow125
; VI-NEXT: v_mov_b32_e32 v11, v13
-; VI-NEXT: .LBB10_26: ; %frem.loop_exit28
+; VI-NEXT: .LBB10_23: ; %frem.loop_exit28
; VI-NEXT: v_add_u32_e32 v10, vcc, -10, v10
; VI-NEXT: v_ldexp_f32 v10, v11, v10
; VI-NEXT: v_mul_f32_e32 v11, v10, v12
@@ -8402,28 +8308,27 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cvt_f16_f32_e32 v8, v8
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v8, s2, v8, v1
-; VI-NEXT: .LBB10_27:
+; VI-NEXT: .LBB10_24:
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v3
; VI-NEXT: v_cvt_f32_f16_e64 v13, |v9|
; VI-NEXT: v_cvt_f32_f16_e64 v12, |v10|
; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v13, v12
-; VI-NEXT: s_cbranch_vccz .LBB10_29
-; VI-NEXT: ; %bb.28: ; %frem.else
+; VI-NEXT: s_cbranch_vccz .LBB10_26
+; VI-NEXT: ; %bb.25: ; %frem.else
; VI-NEXT: v_and_b32_e32 v11, 0x8000, v9
; VI-NEXT: v_cmp_eq_f32_e32 vcc, v13, v12
; VI-NEXT: v_cndmask_b32_e32 v11, v9, v11, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB10_30
-; VI-NEXT: .LBB10_29:
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB10_27
+; VI-NEXT: s_branch .LBB10_32
+; VI-NEXT: .LBB10_26:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr11
-; VI-NEXT: .LBB10_30: ; %Flow123
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB10_36
-; VI-NEXT: ; %bb.31: ; %frem.compute
+; VI-NEXT: s_cbranch_scc0 .LBB10_32
+; VI-NEXT: .LBB10_27: ; %frem.compute
; VI-NEXT: v_frexp_exp_i32_f32_e32 v16, v13
; VI-NEXT: v_frexp_mant_f32_e32 v11, v13
; VI-NEXT: v_frexp_mant_f32_e32 v13, v12
@@ -8447,11 +8352,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v15, v15, v19, v20
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v13
; VI-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_35
-; VI-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB10_31
+; VI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v13, vcc, v16, v17
; VI-NEXT: v_add_u32_e32 v13, vcc, 11, v13
-; VI-NEXT: .LBB10_33: ; %frem.loop_body
+; VI-NEXT: .LBB10_29: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v16, v14
; VI-NEXT: v_mul_f32_e32 v14, v16, v15
@@ -8463,10 +8368,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v13, vcc, -11, v13
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v13
; VI-NEXT: v_ldexp_f32 v14, v14, 11
-; VI-NEXT: s_cbranch_vccnz .LBB10_33
-; VI-NEXT: ; %bb.34: ; %Flow
+; VI-NEXT: s_cbranch_vccnz .LBB10_29
+; VI-NEXT: ; %bb.30: ; %Flow
; VI-NEXT: v_mov_b32_e32 v14, v16
-; VI-NEXT: .LBB10_35: ; %frem.loop_exit
+; VI-NEXT: .LBB10_31: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v13, vcc, -10, v13
; VI-NEXT: v_ldexp_f32 v13, v14, v13
; VI-NEXT: v_mul_f32_e32 v14, v13, v15
@@ -8479,7 +8384,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cvt_f16_f32_e32 v11, v11
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v11, s2, v11, v9
-; VI-NEXT: .LBB10_36: ; %Flow124
+; VI-NEXT: .LBB10_32: ; %Flow124
; VI-NEXT: s_movk_i32 s4, 0x7c00
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v2
; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |v0|, s4
@@ -8524,16 +8429,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB10_3
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX9-NEXT: s_branch .LBB10_8
; GFX9-NEXT: .LBB10_2:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr4
-; GFX9-NEXT: .LBB10_3: ; %Flow135
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB10_9
-; GFX9-NEXT: ; %bb.4: ; %frem.compute85
+; GFX9-NEXT: s_cbranch_scc0 .LBB10_8
+; GFX9-NEXT: .LBB10_3: ; %frem.compute85
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v6
; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v6
; GFX9-NEXT: v_frexp_mant_f32_e32 v6, v5
@@ -8557,11 +8461,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
; GFX9-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_8
-; GFX9-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX9-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; GFX9-NEXT: v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT: v_add_u32_e32 v6, 11, v6
-; GFX9-NEXT: .LBB10_6: ; %frem.loop_body93
+; GFX9-NEXT: .LBB10_5: ; %frem.loop_body93
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v9, v7
; GFX9-NEXT: v_mul_f32_e32 v7, v9, v8
@@ -8573,10 +8477,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
; GFX9-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_6
-; GFX9-NEXT: ; %bb.7: ; %Flow133
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_5
+; GFX9-NEXT: ; %bb.6: ; %Flow133
; GFX9-NEXT: v_mov_b32_e32 v7, v9
-; GFX9-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX9-NEXT: .LBB10_7: ; %frem.loop_exit94
; GFX9-NEXT: v_add_u32_e32 v6, -10, v6
; GFX9-NEXT: v_ldexp_f32 v6, v7, v6
; GFX9-NEXT: v_mul_f32_e32 v7, v6, v8
@@ -8589,27 +8493,26 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v2
-; GFX9-NEXT: .LBB10_9:
+; GFX9-NEXT: .LBB10_8:
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX9-NEXT: v_cvt_f32_f16_e64 v8, |v5|
; GFX9-NEXT: v_cvt_f32_f16_sdwa v7, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v8, v7
-; GFX9-NEXT: s_cbranch_vccz .LBB10_11
-; GFX9-NEXT: ; %bb.10: ; %frem.else53
+; GFX9-NEXT: s_cbranch_vccz .LBB10_10
+; GFX9-NEXT: ; %bb.9: ; %frem.else53
; GFX9-NEXT: v_and_b32_e32 v6, 0x8000, v5
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB10_12
-; GFX9-NEXT: .LBB10_11:
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB10_11
+; GFX9-NEXT: s_branch .LBB10_16
+; GFX9-NEXT: .LBB10_10:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr6
-; GFX9-NEXT: .LBB10_12: ; %Flow131
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB10_18
-; GFX9-NEXT: ; %bb.13: ; %frem.compute52
+; GFX9-NEXT: s_cbranch_scc0 .LBB10_16
+; GFX9-NEXT: .LBB10_11: ; %frem.compute52
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v11, v8
; GFX9-NEXT: v_frexp_mant_f32_e32 v6, v8
; GFX9-NEXT: v_frexp_mant_f32_e32 v8, v7
@@ -8633,11 +8536,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v10, v10, v14, v15
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v8
; GFX9-NEXT: v_div_fixup_f32 v10, v10, v7, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_17
-; GFX9-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX9-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
; GFX9-NEXT: v_sub_u32_e32 v8, v11, v12
; GFX9-NEXT: v_add_u32_e32 v8, 11, v8
-; GFX9-NEXT: .LBB10_15: ; %frem.loop_body60
+; GFX9-NEXT: .LBB10_13: ; %frem.loop_body60
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v11, v9
; GFX9-NEXT: v_mul_f32_e32 v9, v11, v10
@@ -8649,10 +8552,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v8
; GFX9-NEXT: v_ldexp_f32 v9, v9, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX9-NEXT: ; %bb.16: ; %Flow129
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_13
+; GFX9-NEXT: ; %bb.14: ; %Flow129
; GFX9-NEXT: v_mov_b32_e32 v9, v11
-; GFX9-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX9-NEXT: .LBB10_15: ; %frem.loop_exit61
; GFX9-NEXT: v_add_u32_e32 v8, -10, v8
; GFX9-NEXT: v_ldexp_f32 v8, v9, v8
; GFX9-NEXT: v_mul_f32_e32 v9, v8, v10
@@ -8665,26 +8568,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v6, s2, v6, v5
-; GFX9-NEXT: .LBB10_18:
+; GFX9-NEXT: .LBB10_16:
; GFX9-NEXT: v_cvt_f32_f16_e64 v9, |v3|
; GFX9-NEXT: v_cvt_f32_f16_e64 v8, |v1|
; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v9, v8
-; GFX9-NEXT: s_cbranch_vccz .LBB10_20
-; GFX9-NEXT: ; %bb.19: ; %frem.else20
+; GFX9-NEXT: s_cbranch_vccz .LBB10_18
+; GFX9-NEXT: ; %bb.17: ; %frem.else20
; GFX9-NEXT: v_and_b32_e32 v7, 0x8000, v3
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v9, v8
; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v7, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB10_21
-; GFX9-NEXT: .LBB10_20:
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX9-NEXT: s_branch .LBB10_24
+; GFX9-NEXT: .LBB10_18:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr7
-; GFX9-NEXT: .LBB10_21: ; %Flow127
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX9-NEXT: ; %bb.22: ; %frem.compute19
+; GFX9-NEXT: s_cbranch_scc0 .LBB10_24
+; GFX9-NEXT: .LBB10_19: ; %frem.compute19
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v12, v9
; GFX9-NEXT: v_frexp_mant_f32_e32 v7, v9
; GFX9-NEXT: v_frexp_mant_f32_e32 v9, v8
@@ -8708,11 +8610,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v11, v11, v15, v16
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v9
; GFX9-NEXT: v_div_fixup_f32 v11, v11, v8, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_26
-; GFX9-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX9-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
; GFX9-NEXT: v_sub_u32_e32 v9, v12, v13
; GFX9-NEXT: v_add_u32_e32 v9, 11, v9
-; GFX9-NEXT: .LBB10_24: ; %frem.loop_body27
+; GFX9-NEXT: .LBB10_21: ; %frem.loop_body27
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v12, v10
; GFX9-NEXT: v_mul_f32_e32 v10, v12, v11
@@ -8724,10 +8626,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v9
; GFX9-NEXT: v_ldexp_f32 v10, v10, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_24
-; GFX9-NEXT: ; %bb.25: ; %Flow125
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_21
+; GFX9-NEXT: ; %bb.22: ; %Flow125
; GFX9-NEXT: v_mov_b32_e32 v10, v12
-; GFX9-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX9-NEXT: .LBB10_23: ; %frem.loop_exit28
; GFX9-NEXT: v_add_u32_e32 v9, -10, v9
; GFX9-NEXT: v_ldexp_f32 v9, v10, v9
; GFX9-NEXT: v_mul_f32_e32 v10, v9, v11
@@ -8740,27 +8642,26 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v7, v7
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v7, s2, v7, v3
-; GFX9-NEXT: .LBB10_27:
+; GFX9-NEXT: .LBB10_24:
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v3
; GFX9-NEXT: v_cvt_f32_f16_e64 v11, |v8|
; GFX9-NEXT: v_cvt_f32_f16_sdwa v10, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v11, v10
-; GFX9-NEXT: s_cbranch_vccz .LBB10_29
-; GFX9-NEXT: ; %bb.28: ; %frem.else
+; GFX9-NEXT: s_cbranch_vccz .LBB10_26
+; GFX9-NEXT: ; %bb.25: ; %frem.else
; GFX9-NEXT: v_and_b32_e32 v9, 0x8000, v8
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v11, v10
; GFX9-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB10_30
-; GFX9-NEXT: .LBB10_29:
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX9-NEXT: s_branch .LBB10_32
+; GFX9-NEXT: .LBB10_26:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr9
-; GFX9-NEXT: .LBB10_30: ; %Flow123
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB10_36
-; GFX9-NEXT: ; %bb.31: ; %frem.compute
+; GFX9-NEXT: s_cbranch_scc0 .LBB10_32
+; GFX9-NEXT: .LBB10_27: ; %frem.compute
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v14, v11
; GFX9-NEXT: v_frexp_mant_f32_e32 v9, v11
; GFX9-NEXT: v_frexp_mant_f32_e32 v11, v10
@@ -8784,11 +8685,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v13, v13, v17, v18
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v11
; GFX9-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_35
-; GFX9-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX9-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v11, v14, v15
; GFX9-NEXT: v_add_u32_e32 v11, 11, v11
-; GFX9-NEXT: .LBB10_33: ; %frem.loop_body
+; GFX9-NEXT: .LBB10_29: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v14, v12
; GFX9-NEXT: v_mul_f32_e32 v12, v14, v13
@@ -8800,10 +8701,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v11
; GFX9-NEXT: v_ldexp_f32 v12, v12, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_33
-; GFX9-NEXT: ; %bb.34: ; %Flow
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_29
+; GFX9-NEXT: ; %bb.30: ; %Flow
; GFX9-NEXT: v_mov_b32_e32 v12, v14
-; GFX9-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX9-NEXT: .LBB10_31: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v11, -10, v11
; GFX9-NEXT: v_ldexp_f32 v11, v12, v11
; GFX9-NEXT: v_mul_f32_e32 v12, v11, v13
@@ -8816,7 +8717,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v9, v9
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v9, s2, v9, v8
-; GFX9-NEXT: .LBB10_36: ; %Flow124
+; GFX9-NEXT: .LBB10_32: ; %Flow124
; GFX9-NEXT: s_movk_i32 s6, 0x7c00
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v0
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v2|, s6
@@ -8862,16 +8763,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc_lo
-; GFX10-NEXT: s_branch .LBB10_3
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX10-NEXT: s_branch .LBB10_8
; GFX10-NEXT: .LBB10_2:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: .LBB10_3: ; %Flow135
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_9
-; GFX10-NEXT: ; %bb.4: ; %frem.compute85
+; GFX10-NEXT: s_cbranch_scc0 .LBB10_8
+; GFX10-NEXT: .LBB10_3: ; %frem.compute85
; GFX10-NEXT: v_frexp_mant_f32_e32 v4, v6
; GFX10-NEXT: v_frexp_mant_f32_e32 v8, v5
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
@@ -8897,11 +8797,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX10-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_8
-; GFX10-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX10-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_6: ; %frem.loop_body93
+; GFX10-NEXT: .LBB10_5: ; %frem.loop_body93
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -8913,11 +8813,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v8, v6, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v6, v6, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX10-NEXT: ; %bb.7: ; %Flow133
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_5
+; GFX10-NEXT: ; %bb.6: ; %Flow133
; GFX10-NEXT: v_mov_b32_e32 v8, s2
; GFX10-NEXT: v_mov_b32_e32 v6, v9
-; GFX10-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX10-NEXT: .LBB10_7: ; %frem.loop_exit94
; GFX10-NEXT: v_add_nc_u32_e32 v8, -10, v8
; GFX10-NEXT: v_ldexp_f32 v6, v6, v8
; GFX10-NEXT: v_mul_f32_e32 v7, v6, v7
@@ -8929,27 +8829,26 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v4, v5, v4
; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX10-NEXT: v_bfi_b32 v4, 0x7fff, v4, v2
-; GFX10-NEXT: .LBB10_9:
+; GFX10-NEXT: .LBB10_8:
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e64 v8, |v5|
; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v8, v7
-; GFX10-NEXT: s_cbranch_vccz .LBB10_11
-; GFX10-NEXT: ; %bb.10: ; %frem.else53
+; GFX10-NEXT: s_cbranch_vccz .LBB10_10
+; GFX10-NEXT: ; %bb.9: ; %frem.else53
; GFX10-NEXT: v_and_b32_e32 v6, 0x8000, v5
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo
-; GFX10-NEXT: s_branch .LBB10_12
-; GFX10-NEXT: .LBB10_11:
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_11
+; GFX10-NEXT: s_branch .LBB10_16
+; GFX10-NEXT: .LBB10_10:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr6
-; GFX10-NEXT: .LBB10_12: ; %Flow131
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_18
-; GFX10-NEXT: ; %bb.13: ; %frem.compute52
+; GFX10-NEXT: s_cbranch_scc0 .LBB10_16
+; GFX10-NEXT: .LBB10_11: ; %frem.compute52
; GFX10-NEXT: v_frexp_mant_f32_e32 v6, v8
; GFX10-NEXT: v_frexp_mant_f32_e32 v10, v7
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v9, v8
@@ -8975,11 +8874,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v9, v9, v12, v13
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v10
; GFX10-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_17
-; GFX10-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX10-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_15: ; %frem.loop_body60
+; GFX10-NEXT: .LBB10_13: ; %frem.loop_body60
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v11, v8
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -8991,11 +8890,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v10, v8, v7
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_15
-; GFX10-NEXT: ; %bb.16: ; %Flow129
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_13
+; GFX10-NEXT: ; %bb.14: ; %Flow129
; GFX10-NEXT: v_mov_b32_e32 v10, s2
; GFX10-NEXT: v_mov_b32_e32 v8, v11
-; GFX10-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX10-NEXT: .LBB10_15: ; %frem.loop_exit61
; GFX10-NEXT: v_add_nc_u32_e32 v10, -10, v10
; GFX10-NEXT: v_ldexp_f32 v8, v8, v10
; GFX10-NEXT: v_mul_f32_e32 v9, v8, v9
@@ -9007,26 +8906,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v6, v7, v6
; GFX10-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX10-NEXT: v_bfi_b32 v6, 0x7fff, v6, v5
-; GFX10-NEXT: .LBB10_18:
+; GFX10-NEXT: .LBB10_16:
; GFX10-NEXT: v_cvt_f32_f16_e64 v9, |v3|
; GFX10-NEXT: v_cvt_f32_f16_e64 v8, |v1|
; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
-; GFX10-NEXT: s_cbranch_vccz .LBB10_20
-; GFX10-NEXT: ; %bb.19: ; %frem.else20
+; GFX10-NEXT: s_cbranch_vccz .LBB10_18
+; GFX10-NEXT: ; %bb.17: ; %frem.else20
; GFX10-NEXT: v_and_b32_e32 v7, 0x8000, v3
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v7, vcc_lo
-; GFX10-NEXT: s_branch .LBB10_21
-; GFX10-NEXT: .LBB10_20:
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX10-NEXT: s_branch .LBB10_24
+; GFX10-NEXT: .LBB10_18:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr7
-; GFX10-NEXT: .LBB10_21: ; %Flow127
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX10-NEXT: ; %bb.22: ; %frem.compute19
+; GFX10-NEXT: s_cbranch_scc0 .LBB10_24
+; GFX10-NEXT: .LBB10_19: ; %frem.compute19
; GFX10-NEXT: v_frexp_mant_f32_e32 v7, v9
; GFX10-NEXT: v_frexp_mant_f32_e32 v11, v8
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
@@ -9052,11 +8950,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v10, v10, v13, v14
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
; GFX10-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_26
-; GFX10-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX10-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_24: ; %frem.loop_body27
+; GFX10-NEXT: .LBB10_21: ; %frem.loop_body27
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v12, v9
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -9068,11 +8966,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v11, v9, v8
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v9, v9, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX10-NEXT: ; %bb.25: ; %Flow125
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_21
+; GFX10-NEXT: ; %bb.22: ; %Flow125
; GFX10-NEXT: v_mov_b32_e32 v11, s2
; GFX10-NEXT: v_mov_b32_e32 v9, v12
-; GFX10-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX10-NEXT: .LBB10_23: ; %frem.loop_exit28
; GFX10-NEXT: v_add_nc_u32_e32 v11, -10, v11
; GFX10-NEXT: v_ldexp_f32 v9, v9, v11
; GFX10-NEXT: v_mul_f32_e32 v10, v9, v10
@@ -9084,27 +8982,26 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v7, v8, v7
; GFX10-NEXT: v_cvt_f16_f32_e32 v7, v7
; GFX10-NEXT: v_bfi_b32 v7, 0x7fff, v7, v3
-; GFX10-NEXT: .LBB10_27:
+; GFX10-NEXT: .LBB10_24:
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v3
; GFX10-NEXT: v_cvt_f32_f16_sdwa v10, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e64 v11, |v8|
; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v11, v10
-; GFX10-NEXT: s_cbranch_vccz .LBB10_29
-; GFX10-NEXT: ; %bb.28: ; %frem.else
+; GFX10-NEXT: s_cbranch_vccz .LBB10_26
+; GFX10-NEXT: ; %bb.25: ; %frem.else
; GFX10-NEXT: v_and_b32_e32 v9, 0x8000, v8
; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v11, v10
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc_lo
-; GFX10-NEXT: s_branch .LBB10_30
-; GFX10-NEXT: .LBB10_29:
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX10-NEXT: s_branch .LBB10_32
+; GFX10-NEXT: .LBB10_26:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr9
-; GFX10-NEXT: .LBB10_30: ; %Flow123
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_36
-; GFX10-NEXT: ; %bb.31: ; %frem.compute
+; GFX10-NEXT: s_cbranch_scc0 .LBB10_32
+; GFX10-NEXT: .LBB10_27: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e32 v9, v11
; GFX10-NEXT: v_frexp_mant_f32_e32 v13, v10
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v12, v11
@@ -9130,11 +9027,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v12, v12, v15, v16
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v13
; GFX10-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_35
-; GFX10-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX10-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_33: ; %frem.loop_body
+; GFX10-NEXT: .LBB10_29: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v14, v11
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -9146,11 +9043,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v13, v11, v10
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_33
-; GFX10-NEXT: ; %bb.34: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_29
+; GFX10-NEXT: ; %bb.30: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v13, s2
; GFX10-NEXT: v_mov_b32_e32 v11, v14
-; GFX10-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX10-NEXT: .LBB10_31: ; %frem.loop_exit
; GFX10-NEXT: v_add_nc_u32_e32 v13, -10, v13
; GFX10-NEXT: v_ldexp_f32 v11, v11, v13
; GFX10-NEXT: v_mul_f32_e32 v12, v11, v12
@@ -9162,7 +9059,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v9, v10, v9
; GFX10-NEXT: v_cvt_f16_f32_e32 v9, v9
; GFX10-NEXT: v_bfi_b32 v9, 0x7fff, v9, v8
-; GFX10-NEXT: .LBB10_36: ; %Flow124
+; GFX10-NEXT: .LBB10_32: ; %Flow124
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v2|
; GFX10-NEXT: v_cmp_nle_f16_e64 s3, 0x7c00, |v5|
@@ -9209,17 +9106,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_3
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX11-TRUE16-NEXT: s_branch .LBB10_7
; GFX11-TRUE16-NEXT: .LBB10_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
-; GFX11-TRUE16-NEXT: .LBB10_3: ; %Flow135
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
-; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB10_7
+; GFX11-TRUE16-NEXT: .LBB10_3: ; %frem.compute85
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v6
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v5
@@ -9253,12 +9149,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v5, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
-; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_6
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
+; GFX11-TRUE16-NEXT: .LBB10_5: ; %frem.loop_body93
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v4, v6
@@ -9273,10 +9169,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX11-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_5
+; GFX11-TRUE16-NEXT: .LBB10_6: ; %frem.loop_exit94
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
-; GFX11-TRUE16-NEXT: .LBB10_8:
+; GFX11-TRUE16-NEXT: .LBB10_7:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9284,24 +9180,23 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, |v6.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_10
-; GFX11-TRUE16-NEXT: ; %bb.9: ; %frem.else53
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_9
+; GFX11-TRUE16-NEXT: ; %bb.8: ; %frem.else53
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v5.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_11
-; GFX11-TRUE16-NEXT: .LBB10_10:
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_10
+; GFX11-TRUE16-NEXT: s_branch .LBB10_14
+; GFX11-TRUE16-NEXT: .LBB10_9:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-TRUE16-NEXT: .LBB10_11: ; %Flow131
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
-; GFX11-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB10_14
+; GFX11-TRUE16-NEXT: .LBB10_10: ; %frem.compute52
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v9
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v9, v8
@@ -9335,12 +9230,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v9, v9, v12, v13
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v10
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v9, v9, v8, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_13
+; GFX11-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body60.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
+; GFX11-TRUE16-NEXT: .LBB10_12: ; %frem.loop_body60
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v7, v9
@@ -9355,32 +9250,31 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
-; GFX11-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_12
+; GFX11-TRUE16-NEXT: .LBB10_13: ; %frem.loop_exit61
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-TRUE16-NEXT: .LBB10_16:
+; GFX11-TRUE16-NEXT: .LBB10_14:
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v10, |v1.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, |v3.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v10, v9
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_18
-; GFX11-TRUE16-NEXT: ; %bb.17: ; %frem.else20
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_16
+; GFX11-TRUE16-NEXT: ; %bb.15: ; %frem.else20
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_19
-; GFX11-TRUE16-NEXT: .LBB10_18:
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_17
+; GFX11-TRUE16-NEXT: s_branch .LBB10_21
+; GFX11-TRUE16-NEXT: .LBB10_16:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-TRUE16-NEXT: .LBB10_19: ; %Flow127
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX11-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB10_21
+; GFX11-TRUE16-NEXT: .LBB10_17: ; %frem.compute19
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v10
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v10, v9
@@ -9414,12 +9308,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v10, v10, v13, v14
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v10, v10, v9, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX11-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_20
+; GFX11-TRUE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT: .LBB10_19: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v8, v10
@@ -9434,10 +9328,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
-; GFX11-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX11-TRUE16-NEXT: .LBB10_20: ; %frem.loop_exit28
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-TRUE16-NEXT: .LBB10_24:
+; GFX11-TRUE16-NEXT: .LBB10_21:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9445,24 +9339,23 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v12, |v10.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v13, v12
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_26
-; GFX11-TRUE16-NEXT: ; %bb.25: ; %frem.else
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_23
+; GFX11-TRUE16-NEXT: ; %bb.22: ; %frem.else
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v9.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v13, v12
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_27
-; GFX11-TRUE16-NEXT: .LBB10_26:
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX11-TRUE16-NEXT: s_branch .LBB10_28
+; GFX11-TRUE16-NEXT: .LBB10_23:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-TRUE16-NEXT: .LBB10_27: ; %Flow123
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
-; GFX11-TRUE16-NEXT: ; %bb.28: ; %frem.compute
+; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB10_28
+; GFX11-TRUE16-NEXT: .LBB10_24: ; %frem.compute
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v13
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v13
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v13, v12
@@ -9496,12 +9389,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v13, v13, v16, v17
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v14
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v13, v13, v12, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX11-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_27
+; GFX11-TRUE16-NEXT: ; %bb.25: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB10_26: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v11, v13
@@ -9516,10 +9409,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
-; GFX11-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_26
+; GFX11-TRUE16-NEXT: .LBB10_27: ; %frem.loop_exit
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-TRUE16-NEXT: .LBB10_32: ; %Flow124
+; GFX11-TRUE16-NEXT: .LBB10_28: ; %Flow124
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
@@ -9564,17 +9457,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB10_3
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX11-FAKE16-NEXT: s_branch .LBB10_8
; GFX11-FAKE16-NEXT: .LBB10_2:
; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
-; GFX11-FAKE16-NEXT: .LBB10_3: ; %Flow135
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_9
-; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB10_8
+; GFX11-FAKE16-NEXT: .LBB10_3: ; %frem.compute85
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, v6
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v8, v5
; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
@@ -9609,12 +9501,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_8
-; GFX11-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_6: ; %frem.loop_body93
+; GFX11-FAKE16-NEXT: .LBB10_5: ; %frem.loop_body93
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v6
@@ -9630,11 +9522,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v6, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX11-FAKE16-NEXT: ; %bb.7: ; %Flow133
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_5
+; GFX11-FAKE16-NEXT: ; %bb.6: ; %Flow133
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v9
-; GFX11-FAKE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX11-FAKE16-NEXT: .LBB10_7: ; %frem.loop_exit94
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, -10, v8
; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v6, v8
@@ -9651,7 +9543,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX11-FAKE16-NEXT: v_bfi_b32 v4, 0x7fff, v4, v0
-; GFX11-FAKE16-NEXT: .LBB10_9:
+; GFX11-FAKE16-NEXT: .LBB10_8:
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9659,24 +9551,23 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v8, |v6|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_11
-; GFX11-FAKE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_10
+; GFX11-FAKE16-NEXT: ; %bb.9: ; %frem.else53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0x8000, v5
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB10_12
-; GFX11-FAKE16-NEXT: .LBB10_11:
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
+; GFX11-FAKE16-NEXT: s_branch .LBB10_16
+; GFX11-FAKE16-NEXT: .LBB10_10:
; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-FAKE16-NEXT: .LBB10_12: ; %Flow131
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_18
-; GFX11-FAKE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB10_16
+; GFX11-FAKE16-NEXT: .LBB10_11: ; %frem.compute52
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v7, v9
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v11, v8
; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
@@ -9711,12 +9602,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_17
-; GFX11-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX11-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_15: ; %frem.loop_body60
+; GFX11-FAKE16-NEXT: .LBB10_13: ; %frem.loop_body60
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v12, v9
@@ -9732,11 +9623,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v9, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_15
-; GFX11-FAKE16-NEXT: ; %bb.16: ; %Flow129
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_13
+; GFX11-FAKE16-NEXT: ; %bb.14: ; %Flow129
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, s2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v12
-; GFX11-FAKE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX11-FAKE16-NEXT: .LBB10_15: ; %frem.loop_exit61
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, -10, v11
; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v9, v11
@@ -9753,29 +9644,28 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v7, v7
; GFX11-FAKE16-NEXT: v_bfi_b32 v7, 0x7fff, v7, v5
-; GFX11-FAKE16-NEXT: .LBB10_18:
+; GFX11-FAKE16-NEXT: .LBB10_16:
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v10, |v1|
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, |v3|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v10, v9
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_20
-; GFX11-FAKE16-NEXT: ; %bb.19: ; %frem.else20
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_18
+; GFX11-FAKE16-NEXT: ; %bb.17: ; %frem.else20
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x8000, v1
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v1, v8, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB10_21
-; GFX11-FAKE16-NEXT: .LBB10_20:
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX11-FAKE16-NEXT: s_branch .LBB10_24
+; GFX11-FAKE16-NEXT: .LBB10_18:
; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-FAKE16-NEXT: .LBB10_21: ; %Flow127
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX11-FAKE16-NEXT: ; %bb.22: ; %frem.compute19
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB10_24
+; GFX11-FAKE16-NEXT: .LBB10_19: ; %frem.compute19
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v8, v10
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v12, v9
; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
@@ -9810,12 +9700,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v12
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_26
-; GFX11-FAKE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX11-FAKE16-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_24: ; %frem.loop_body27
+; GFX11-FAKE16-NEXT: .LBB10_21: ; %frem.loop_body27
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, v10
@@ -9831,11 +9721,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v10, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX11-FAKE16-NEXT: ; %bb.25: ; %Flow125
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_21
+; GFX11-FAKE16-NEXT: ; %bb.22: ; %Flow125
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v12, s2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, v13
-; GFX11-FAKE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX11-FAKE16-NEXT: .LBB10_23: ; %frem.loop_exit28
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, -10, v12
; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v10, v12
@@ -9852,7 +9742,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v8, v8
; GFX11-FAKE16-NEXT: v_bfi_b32 v8, 0x7fff, v8, v1
-; GFX11-FAKE16-NEXT: .LBB10_27:
+; GFX11-FAKE16-NEXT: .LBB10_24:
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9860,24 +9750,23 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v12, |v10|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v13, v12
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_29
-; GFX11-FAKE16-NEXT: ; %bb.28: ; %frem.else
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_26
+; GFX11-FAKE16-NEXT: ; %bb.25: ; %frem.else
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0x8000, v9
; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v13, v12
; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v11, vcc_lo
-; GFX11-FAKE16-NEXT: s_branch .LBB10_30
-; GFX11-FAKE16-NEXT: .LBB10_29:
+; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX11-FAKE16-NEXT: s_branch .LBB10_32
+; GFX11-FAKE16-NEXT: .LBB10_26:
; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-FAKE16-NEXT: .LBB10_30: ; %Flow123
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_36
-; GFX11-FAKE16-NEXT: ; %bb.31: ; %frem.compute
+; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB10_32
+; GFX11-FAKE16-NEXT: .LBB10_27: ; %frem.compute
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v11, v13
; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v15, v12
; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v13
@@ -9912,12 +9801,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_35
-; GFX11-FAKE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX11-FAKE16-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_33: ; %frem.loop_body
+; GFX11-FAKE16-NEXT: .LBB10_29: ; %frem.loop_body
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v16, v13
@@ -9933,11 +9822,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v13, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_33
-; GFX11-FAKE16-NEXT: ; %bb.34: ; %Flow
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_29
+; GFX11-FAKE16-NEXT: ; %bb.30: ; %Flow
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v15, s2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, v16
-; GFX11-FAKE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX11-FAKE16-NEXT: .LBB10_31: ; %frem.loop_exit
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, -10, v15
; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v13, v15
@@ -9954,7 +9843,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v11, v11
; GFX11-FAKE16-NEXT: v_bfi_b32 v11, 0x7fff, v11, v9
-; GFX11-FAKE16-NEXT: .LBB10_36: ; %Flow124
+; GFX11-FAKE16-NEXT: .LBB10_32: ; %Flow124
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -10009,17 +9898,17 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s9
; GFX1150-TRUE16-NEXT: s_mov_b32 s9, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_7
; GFX1150-TRUE16-NEXT: .LBB10_2:
; GFX1150-TRUE16-NEXT: s_mov_b32 s9, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: .LBB10_3: ; %Flow135
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
-; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_7
+; GFX1150-TRUE16-NEXT: .LBB10_3: ; %frem.compute85
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
@@ -10052,12 +9941,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
-; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_6
+; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s8, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
+; GFX1150-TRUE16-NEXT: .LBB10_5: ; %frem.loop_body93
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -10073,10 +9962,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX1150-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_5
+; GFX1150-TRUE16-NEXT: .LBB10_6: ; %frem.loop_exit94
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: .LBB10_8:
+; GFX1150-TRUE16-NEXT: .LBB10_7:
; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1150-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
@@ -10085,25 +9974,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
-; GFX1150-TRUE16-NEXT: ; %bb.9: ; %frem.else53
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_9
+; GFX1150-TRUE16-NEXT: ; %bb.8: ; %frem.else53
; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
; GFX1150-TRUE16-NEXT: s_mov_b32 s10, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_11
-; GFX1150-TRUE16-NEXT: .LBB10_10:
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_10
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_14
+; GFX1150-TRUE16-NEXT: .LBB10_9:
; GFX1150-TRUE16-NEXT: s_mov_b32 s10, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB10_11: ; %Flow131
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s10, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s10, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
-; GFX1150-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_14
+; GFX1150-TRUE16-NEXT: .LBB10_10: ; %frem.compute52
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
@@ -10136,12 +10025,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_13
+; GFX1150-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body60.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s8, s9, s8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s8, s8, 11
-; GFX1150-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
+; GFX1150-TRUE16-NEXT: .LBB10_12: ; %frem.loop_body60
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -10157,35 +10046,35 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
-; GFX1150-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_12
+; GFX1150-TRUE16-NEXT: .LBB10_13: ; %frem.loop_exit61
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB10_16:
+; GFX1150-TRUE16-NEXT: .LBB10_14:
; GFX1150-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1150-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s8
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
-; GFX1150-TRUE16-NEXT: ; %bb.17: ; %frem.else20
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_16
+; GFX1150-TRUE16-NEXT: ; %bb.15: ; %frem.else20
; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
; GFX1150-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_19
-; GFX1150-TRUE16-NEXT: .LBB10_18:
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_17
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_21
+; GFX1150-TRUE16-NEXT: .LBB10_16:
; GFX1150-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB10_19: ; %Flow127
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1150-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_21
+; GFX1150-TRUE16-NEXT: .LBB10_17: ; %frem.compute19
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
@@ -10218,12 +10107,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX1150-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_20
+; GFX1150-TRUE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT: .LBB10_19: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -10239,10 +10128,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
-; GFX1150-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX1150-TRUE16-NEXT: .LBB10_20: ; %frem.loop_exit28
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB10_24:
+; GFX1150-TRUE16-NEXT: .LBB10_21:
; GFX1150-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
; GFX1150-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
@@ -10251,25 +10140,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
-; GFX1150-TRUE16-NEXT: ; %bb.25: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_23
+; GFX1150-TRUE16-NEXT: ; %bb.22: ; %frem.else
; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
; GFX1150-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
; GFX1150-TRUE16-NEXT: s_mov_b32 s12, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_27
-; GFX1150-TRUE16-NEXT: .LBB10_26:
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_28
+; GFX1150-TRUE16-NEXT: .LBB10_23:
; GFX1150-TRUE16-NEXT: s_mov_b32 s12, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-TRUE16-NEXT: .LBB10_27: ; %Flow123
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
-; GFX1150-TRUE16-NEXT: ; %bb.28: ; %frem.compute
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_28
+; GFX1150-TRUE16-NEXT: .LBB10_24: ; %frem.compute
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
@@ -10302,12 +10191,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX1150-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_27
+; GFX1150-TRUE16-NEXT: ; %bb.25: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s10, s11, s10
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s10, s10, 11
-; GFX1150-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: .LBB10_26: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
@@ -10323,10 +10212,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
-; GFX1150-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_26
+; GFX1150-TRUE16-NEXT: .LBB10_27: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-TRUE16-NEXT: .LBB10_32: ; %Flow124
+; GFX1150-TRUE16-NEXT: .LBB10_28: ; %Flow124
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1150-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -10390,17 +10279,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_3
+; GFX1150-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_8
; GFX1150-FAKE16-NEXT: .LBB10_2:
; GFX1150-FAKE16-NEXT: s_mov_b32 s9, -1
; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-FAKE16-NEXT: .LBB10_3: ; %Flow135
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1150-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
-; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_9
-; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_8
+; GFX1150-FAKE16-NEXT: .LBB10_3: ; %frem.compute85
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s6
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s8
; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
@@ -10434,12 +10322,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_8
-; GFX1150-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; GFX1150-FAKE16-NEXT: s_sub_i32 s6, s8, s6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-FAKE16-NEXT: .LBB10_6: ; %frem.loop_body93
+; GFX1150-FAKE16-NEXT: .LBB10_5: ; %frem.loop_body93
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -10457,11 +10345,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX1150-FAKE16-NEXT: ; %bb.7: ; %Flow133
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_5
+; GFX1150-FAKE16-NEXT: ; %bb.6: ; %Flow133
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, s6
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, v5
-; GFX1150-FAKE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX1150-FAKE16-NEXT: .LBB10_7: ; %frem.loop_exit94
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
@@ -10480,7 +10368,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s5
-; GFX1150-FAKE16-NEXT: .LBB10_9:
+; GFX1150-FAKE16-NEXT: .LBB10_8:
; GFX1150-FAKE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1150-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1150-FAKE16-NEXT: s_and_b32 s5, s8, 0x7fff
@@ -10489,8 +10377,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_11
-; GFX1150-FAKE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_10
+; GFX1150-FAKE16-NEXT: ; %bb.9: ; %frem.else53
; GFX1150-FAKE16-NEXT: s_and_b32 s11, 0x8000, s8
; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v1, s11
@@ -10498,17 +10386,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_12
-; GFX1150-FAKE16-NEXT: .LBB10_11:
+; GFX1150-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_16
+; GFX1150-FAKE16-NEXT: .LBB10_10:
; GFX1150-FAKE16-NEXT: s_mov_b32 s11, -1
; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-FAKE16-NEXT: .LBB10_12: ; %Flow131
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-FAKE16-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_18
-; GFX1150-FAKE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_16
+; GFX1150-FAKE16-NEXT: .LBB10_11: ; %frem.compute52
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s9
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s10
; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
@@ -10542,12 +10429,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_17
-; GFX1150-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX1150-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
; GFX1150-FAKE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-FAKE16-NEXT: .LBB10_15: ; %frem.loop_body60
+; GFX1150-FAKE16-NEXT: .LBB10_13: ; %frem.loop_body60
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -10565,11 +10452,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_15
-; GFX1150-FAKE16-NEXT: ; %bb.16: ; %Flow129
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_13
+; GFX1150-FAKE16-NEXT: ; %bb.14: ; %Flow129
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, s9
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, v6
-; GFX1150-FAKE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX1150-FAKE16-NEXT: .LBB10_15: ; %frem.loop_exit61
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
@@ -10588,15 +10475,15 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s8
-; GFX1150-FAKE16-NEXT: .LBB10_18:
+; GFX1150-FAKE16-NEXT: .LBB10_16:
; GFX1150-FAKE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1150-FAKE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s10, s8
; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_20
-; GFX1150-FAKE16-NEXT: ; %bb.19: ; %frem.else20
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_18
+; GFX1150-FAKE16-NEXT: ; %bb.17: ; %frem.else20
; GFX1150-FAKE16-NEXT: s_and_b32 s11, 0x8000, s7
; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, s11
@@ -10604,17 +10491,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_21
-; GFX1150-FAKE16-NEXT: .LBB10_20:
+; GFX1150-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_24
+; GFX1150-FAKE16-NEXT: .LBB10_18:
; GFX1150-FAKE16-NEXT: s_mov_b32 s11, -1
; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-FAKE16-NEXT: .LBB10_21: ; %Flow127
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-FAKE16-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX1150-FAKE16-NEXT: ; %bb.22: ; %frem.compute19
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_24
+; GFX1150-FAKE16-NEXT: .LBB10_19: ; %frem.compute19
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s9
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s10
; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
@@ -10648,12 +10534,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_26
-; GFX1150-FAKE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX1150-FAKE16-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
; GFX1150-FAKE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-FAKE16-NEXT: .LBB10_24: ; %frem.loop_body27
+; GFX1150-FAKE16-NEXT: .LBB10_21: ; %frem.loop_body27
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -10671,11 +10557,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1150-FAKE16-NEXT: ; %bb.25: ; %Flow125
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_21
+; GFX1150-FAKE16-NEXT: ; %bb.22: ; %Flow125
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, s9
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX1150-FAKE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX1150-FAKE16-NEXT: .LBB10_23: ; %frem.loop_exit28
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
@@ -10694,7 +10580,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, s7
-; GFX1150-FAKE16-NEXT: .LBB10_27:
+; GFX1150-FAKE16-NEXT: .LBB10_24:
; GFX1150-FAKE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1150-FAKE16-NEXT: s_lshr_b32 s9, s2, 16
; GFX1150-FAKE16-NEXT: s_and_b32 s7, s10, 0x7fff
@@ -10703,8 +10589,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s11, s11
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s12, s11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_29
-; GFX1150-FAKE16-NEXT: ; %bb.28: ; %frem.else
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_26
+; GFX1150-FAKE16-NEXT: ; %bb.25: ; %frem.else
; GFX1150-FAKE16-NEXT: s_and_b32 s13, 0x8000, s10
; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s12, s11
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, s13
@@ -10712,17 +10598,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_30
-; GFX1150-FAKE16-NEXT: .LBB10_29:
+; GFX1150-FAKE16-NEXT: s_and_b32 s13, s13, exec_lo
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_32
+; GFX1150-FAKE16-NEXT: .LBB10_26:
; GFX1150-FAKE16-NEXT: s_mov_b32 s13, -1
; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-FAKE16-NEXT: .LBB10_30: ; %Flow123
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_and_b32 s13, s13, exec_lo
-; GFX1150-FAKE16-NEXT: s_cselect_b32 s13, 1, 0
-; GFX1150-FAKE16-NEXT: s_cmp_lg_u32 s13, 1
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_36
-; GFX1150-FAKE16-NEXT: ; %bb.31: ; %frem.compute
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_32
+; GFX1150-FAKE16-NEXT: .LBB10_27: ; %frem.compute
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, s11
; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s12
; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
@@ -10756,12 +10641,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_35
-; GFX1150-FAKE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX1150-FAKE16-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX1150-FAKE16-NEXT: s_sub_i32 s11, s12, s11
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s11, s11, 11
-; GFX1150-FAKE16-NEXT: .LBB10_33: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT: .LBB10_29: ; %frem.loop_body
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v8, v5
@@ -10779,11 +10664,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_33
-; GFX1150-FAKE16-NEXT: ; %bb.34: ; %Flow
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_29
+; GFX1150-FAKE16-NEXT: ; %bb.30: ; %Flow
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, s11
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v8
-; GFX1150-FAKE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX1150-FAKE16-NEXT: .LBB10_31: ; %frem.loop_exit
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v5, v5, v7
@@ -10802,7 +10687,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, s10
-; GFX1150-FAKE16-NEXT: .LBB10_36: ; %Flow124
+; GFX1150-FAKE16-NEXT: .LBB10_32: ; %Flow124
; GFX1150-FAKE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1150-FAKE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1150-FAKE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -10869,18 +10754,17 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s9
; GFX1200-TRUE16-NEXT: s_mov_b32 s9, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_3
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_7
; GFX1200-TRUE16-NEXT: .LBB10_2:
; GFX1200-TRUE16-NEXT: s_mov_b32 s9, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: .LBB10_3: ; %Flow135
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
-; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_7
+; GFX1200-TRUE16-NEXT: .LBB10_3: ; %frem.compute85
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
@@ -10913,12 +10797,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
-; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_6
+; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s8, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
+; GFX1200-TRUE16-NEXT: .LBB10_5: ; %frem.loop_body93
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -10937,10 +10821,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX1200-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_5
+; GFX1200-TRUE16-NEXT: .LBB10_6: ; %frem.loop_exit94
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: .LBB10_8:
+; GFX1200-TRUE16-NEXT: .LBB10_7:
; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
@@ -10952,8 +10836,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
-; GFX1200-TRUE16-NEXT: ; %bb.9: ; %frem.else53
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_9
+; GFX1200-TRUE16-NEXT: ; %bb.8: ; %frem.else53
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
@@ -10961,18 +10845,17 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
; GFX1200-TRUE16-NEXT: s_mov_b32 s10, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_11
-; GFX1200-TRUE16-NEXT: .LBB10_10:
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_10
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_14
+; GFX1200-TRUE16-NEXT: .LBB10_9:
; GFX1200-TRUE16-NEXT: s_mov_b32 s10, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB10_11: ; %Flow131
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s10, 1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s10, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
-; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_14
+; GFX1200-TRUE16-NEXT: .LBB10_10: ; %frem.compute52
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
@@ -11006,12 +10889,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_13
+; GFX1200-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body60.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s8, s9, s8
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s8, s8, 11
-; GFX1200-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
+; GFX1200-TRUE16-NEXT: .LBB10_12: ; %frem.loop_body60
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -11030,10 +10913,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
-; GFX1200-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_12
+; GFX1200-TRUE16-NEXT: .LBB10_13: ; %frem.loop_exit61
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB10_16:
+; GFX1200-TRUE16-NEXT: .LBB10_14:
; GFX1200-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1200-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -11042,8 +10925,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
-; GFX1200-TRUE16-NEXT: ; %bb.17: ; %frem.else20
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_16
+; GFX1200-TRUE16-NEXT: ; %bb.15: ; %frem.else20
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
@@ -11051,18 +10934,17 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
; GFX1200-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_19
-; GFX1200-TRUE16-NEXT: .LBB10_18:
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_17
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_21
+; GFX1200-TRUE16-NEXT: .LBB10_16:
; GFX1200-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB10_19: ; %Flow127
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1200-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_21
+; GFX1200-TRUE16-NEXT: .LBB10_17: ; %frem.compute19
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
@@ -11096,12 +10978,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX1200-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_20
+; GFX1200-TRUE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT: .LBB10_19: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -11120,10 +11002,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
-; GFX1200-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX1200-TRUE16-NEXT: .LBB10_20: ; %frem.loop_exit28
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB10_24:
+; GFX1200-TRUE16-NEXT: .LBB10_21:
; GFX1200-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
; GFX1200-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
@@ -11135,8 +11017,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
-; GFX1200-TRUE16-NEXT: ; %bb.25: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_23
+; GFX1200-TRUE16-NEXT: ; %bb.22: ; %frem.else
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
; GFX1200-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
@@ -11144,18 +11026,17 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
; GFX1200-TRUE16-NEXT: s_mov_b32 s12, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_27
-; GFX1200-TRUE16-NEXT: .LBB10_26:
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_28
+; GFX1200-TRUE16-NEXT: .LBB10_23:
; GFX1200-TRUE16-NEXT: s_mov_b32 s12, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-TRUE16-NEXT: .LBB10_27: ; %Flow123
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
-; GFX1200-TRUE16-NEXT: ; %bb.28: ; %frem.compute
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_28
+; GFX1200-TRUE16-NEXT: .LBB10_24: ; %frem.compute
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
@@ -11189,12 +11070,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX1200-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_27
+; GFX1200-TRUE16-NEXT: ; %bb.25: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s10, s11, s10
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s10, s10, 11
-; GFX1200-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: .LBB10_26: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
@@ -11213,10 +11094,10 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
-; GFX1200-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_26
+; GFX1200-TRUE16-NEXT: .LBB10_27: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-TRUE16-NEXT: .LBB10_32: ; %Flow124
+; GFX1200-TRUE16-NEXT: .LBB10_28: ; %Flow124
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -11283,18 +11164,17 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_3
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_8
; GFX1200-FAKE16-NEXT: .LBB10_2:
; GFX1200-FAKE16-NEXT: s_mov_b32 s9, -1
; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-FAKE16-NEXT: .LBB10_3: ; %Flow135
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1200-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_9
-; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.compute85
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_8
+; GFX1200-FAKE16-NEXT: .LBB10_3: ; %frem.compute85
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s6
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s8
; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
@@ -11329,12 +11209,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_8
-; GFX1200-FAKE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s6, s8, s6
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-FAKE16-NEXT: .LBB10_6: ; %frem.loop_body93
+; GFX1200-FAKE16-NEXT: .LBB10_5: ; %frem.loop_body93
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -11354,11 +11234,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX1200-FAKE16-NEXT: ; %bb.7: ; %Flow133
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_5
+; GFX1200-FAKE16-NEXT: ; %bb.6: ; %Flow133
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, s6
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, v5
-; GFX1200-FAKE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX1200-FAKE16-NEXT: .LBB10_7: ; %frem.loop_exit94
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
@@ -11378,7 +11258,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s5
-; GFX1200-FAKE16-NEXT: .LBB10_9:
+; GFX1200-FAKE16-NEXT: .LBB10_8:
; GFX1200-FAKE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1200-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -11390,8 +11270,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_11
-; GFX1200-FAKE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_10
+; GFX1200-FAKE16-NEXT: ; %bb.9: ; %frem.else53
; GFX1200-FAKE16-NEXT: s_and_b32 s11, 0x8000, s8
; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, s11
@@ -11400,18 +11280,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_12
-; GFX1200-FAKE16-NEXT: .LBB10_11:
+; GFX1200-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_16
+; GFX1200-FAKE16-NEXT: .LBB10_10:
; GFX1200-FAKE16-NEXT: s_mov_b32 s11, -1
; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-FAKE16-NEXT: .LBB10_12: ; %Flow131
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1200-FAKE16-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_18
-; GFX1200-FAKE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_16
+; GFX1200-FAKE16-NEXT: .LBB10_11: ; %frem.compute52
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s9
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s10
; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
@@ -11446,12 +11324,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_17
-; GFX1200-FAKE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_15
+; GFX1200-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-FAKE16-NEXT: .LBB10_15: ; %frem.loop_body60
+; GFX1200-FAKE16-NEXT: .LBB10_13: ; %frem.loop_body60
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -11471,11 +11349,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_15
-; GFX1200-FAKE16-NEXT: ; %bb.16: ; %Flow129
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_13
+; GFX1200-FAKE16-NEXT: ; %bb.14: ; %Flow129
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, s9
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, v6
-; GFX1200-FAKE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX1200-FAKE16-NEXT: .LBB10_15: ; %frem.loop_exit61
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
@@ -11495,7 +11373,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s8
-; GFX1200-FAKE16-NEXT: .LBB10_18:
+; GFX1200-FAKE16-NEXT: .LBB10_16:
; GFX1200-FAKE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1200-FAKE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -11504,8 +11382,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_20
-; GFX1200-FAKE16-NEXT: ; %bb.19: ; %frem.else20
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_18
+; GFX1200-FAKE16-NEXT: ; %bb.17: ; %frem.else20
; GFX1200-FAKE16-NEXT: s_and_b32 s11, 0x8000, s7
; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -11515,18 +11393,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_21
-; GFX1200-FAKE16-NEXT: .LBB10_20:
+; GFX1200-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_24
+; GFX1200-FAKE16-NEXT: .LBB10_18:
; GFX1200-FAKE16-NEXT: s_mov_b32 s11, -1
; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-FAKE16-NEXT: .LBB10_21: ; %Flow127
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1200-FAKE16-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX1200-FAKE16-NEXT: ; %bb.22: ; %frem.compute19
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_24
+; GFX1200-FAKE16-NEXT: .LBB10_19: ; %frem.compute19
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s9
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s10
; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
@@ -11561,12 +11437,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_26
-; GFX1200-FAKE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_23
+; GFX1200-FAKE16-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-FAKE16-NEXT: .LBB10_24: ; %frem.loop_body27
+; GFX1200-FAKE16-NEXT: .LBB10_21: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -11586,11 +11462,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1200-FAKE16-NEXT: ; %bb.25: ; %Flow125
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_21
+; GFX1200-FAKE16-NEXT: ; %bb.22: ; %Flow125
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, s9
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX1200-FAKE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX1200-FAKE16-NEXT: .LBB10_23: ; %frem.loop_exit28
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
@@ -11610,7 +11486,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, s7
-; GFX1200-FAKE16-NEXT: .LBB10_27:
+; GFX1200-FAKE16-NEXT: .LBB10_24:
; GFX1200-FAKE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1200-FAKE16-NEXT: s_lshr_b32 s9, s2, 16
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -11622,8 +11498,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s12, s11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_29
-; GFX1200-FAKE16-NEXT: ; %bb.28: ; %frem.else
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_26
+; GFX1200-FAKE16-NEXT: ; %bb.25: ; %frem.else
; GFX1200-FAKE16-NEXT: s_and_b32 s13, 0x8000, s10
; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s12, s11
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, s13
@@ -11632,18 +11508,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_30
-; GFX1200-FAKE16-NEXT: .LBB10_29:
+; GFX1200-FAKE16-NEXT: s_and_b32 s13, s13, exec_lo
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_32
+; GFX1200-FAKE16-NEXT: .LBB10_26:
; GFX1200-FAKE16-NEXT: s_mov_b32 s13, -1
; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-FAKE16-NEXT: .LBB10_30: ; %Flow123
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-FAKE16-NEXT: s_and_b32 s13, s13, exec_lo
-; GFX1200-FAKE16-NEXT: s_cselect_b32 s13, 1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cmp_lg_u32 s13, 1
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_36
-; GFX1200-FAKE16-NEXT: ; %bb.31: ; %frem.compute
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_32
+; GFX1200-FAKE16-NEXT: .LBB10_27: ; %frem.compute
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, s11
; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s12
; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
@@ -11678,12 +11552,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_35
-; GFX1200-FAKE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_31
+; GFX1200-FAKE16-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX1200-FAKE16-NEXT: s_sub_co_i32 s11, s12, s11
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s11, s11, 11
-; GFX1200-FAKE16-NEXT: .LBB10_33: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT: .LBB10_29: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v8, v5
@@ -11703,11 +11577,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_33
-; GFX1200-FAKE16-NEXT: ; %bb.34: ; %Flow
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_29
+; GFX1200-FAKE16-NEXT: ; %bb.30: ; %Flow
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, s11
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v8
-; GFX1200-FAKE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX1200-FAKE16-NEXT: .LBB10_31: ; %frem.loop_exit
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v5, v7
@@ -11727,7 +11601,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, s10
-; GFX1200-FAKE16-NEXT: .LBB10_36: ; %Flow124
+; GFX1200-FAKE16-NEXT: .LBB10_32: ; %Flow124
; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1200-FAKE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-FAKE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -11799,16 +11673,15 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
; SI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_branch .LBB11_3
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cbranch_scc1 .LBB11_3
+; SI-NEXT: s_branch .LBB11_8
; SI-NEXT: .LBB11_2:
; SI-NEXT: s_mov_b64 s[2:3], -1
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: .LBB11_3: ; %Flow53
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cselect_b32 s2, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s2, 1
-; SI-NEXT: s_cbranch_scc1 .LBB11_9
-; SI-NEXT: ; %bb.4: ; %frem.compute15
+; SI-NEXT: s_cbranch_scc0 .LBB11_8
+; SI-NEXT: .LBB11_3: ; %frem.compute15
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
@@ -11843,11 +11716,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v6, v6, v8, v9
; SI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB11_8
-; SI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB11_7
+; SI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB11_6: ; %frem.loop_body23
+; SI-NEXT: .LBB11_5: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v7, v5
; SI-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -11859,10 +11732,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v5, v5, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB11_6
-; SI-NEXT: ; %bb.7: ; %Flow51
+; SI-NEXT: s_cbranch_scc1 .LBB11_5
+; SI-NEXT: ; %bb.6: ; %Flow51
; SI-NEXT: v_mov_b32_e32 v5, v7
-; SI-NEXT: .LBB11_8: ; %frem.loop_exit24
+; SI-NEXT: .LBB11_7: ; %frem.loop_exit24
; SI-NEXT: s_add_i32 s3, s3, -11
; SI-NEXT: v_ldexp_f32_e64 v5, v5, s3
; SI-NEXT: v_mul_f32_e32 v6, v5, v6
@@ -11874,25 +11747,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v4, v4, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; SI-NEXT: .LBB11_9:
+; SI-NEXT: .LBB11_8:
; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB11_11
-; SI-NEXT: ; %bb.10: ; %frem.else
+; SI-NEXT: s_cbranch_vccz .LBB11_10
+; SI-NEXT: ; %bb.9: ; %frem.else
; SI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
; SI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_branch .LBB11_12
-; SI-NEXT: .LBB11_11:
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cbranch_scc1 .LBB11_11
+; SI-NEXT: s_branch .LBB11_16
+; SI-NEXT: .LBB11_10:
; SI-NEXT: s_mov_b64 s[2:3], -1
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: .LBB11_12: ; %Flow49
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cselect_b32 s2, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s2, 1
-; SI-NEXT: s_cbranch_scc1 .LBB11_18
-; SI-NEXT: ; %bb.13: ; %frem.compute
+; SI-NEXT: s_cbranch_scc0 .LBB11_16
+; SI-NEXT: .LBB11_11: ; %frem.compute
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v1
@@ -11927,11 +11799,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v7, v7, v9, v10
; SI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB11_17
-; SI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB11_15
+; SI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB11_15: ; %frem.loop_body
+; SI-NEXT: .LBB11_13: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v8, v6
; SI-NEXT: v_mul_f32_e32 v6, v8, v7
@@ -11943,10 +11815,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v6, v6, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB11_15
-; SI-NEXT: ; %bb.16: ; %Flow
+; SI-NEXT: s_cbranch_scc1 .LBB11_13
+; SI-NEXT: ; %bb.14: ; %Flow
; SI-NEXT: v_mov_b32_e32 v6, v8
-; SI-NEXT: .LBB11_17: ; %frem.loop_exit
+; SI-NEXT: .LBB11_15: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s3, s3, -11
; SI-NEXT: v_ldexp_f32_e64 v6, v6, s3
; SI-NEXT: v_mul_f32_e32 v7, v6, v7
@@ -11958,7 +11830,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v5, v5, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; SI-NEXT: .LBB11_18: ; %Flow50
+; SI-NEXT: .LBB11_16: ; %Flow50
; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; SI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -11996,16 +11868,15 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
; CI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_branch .LBB11_3
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB11_3
+; CI-NEXT: s_branch .LBB11_8
; CI-NEXT: .LBB11_2:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr4
-; CI-NEXT: .LBB11_3: ; %Flow53
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB11_9
-; CI-NEXT: ; %bb.4: ; %frem.compute15
+; CI-NEXT: s_cbranch_scc0 .LBB11_8
+; CI-NEXT: .LBB11_3: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; CI-NEXT: v_ldexp_f32_e64 v5, v5, 1
; CI-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
@@ -12029,11 +11900,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v6
; CI-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB11_8
-; CI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB11_7
+; CI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; CI-NEXT: v_sub_i32_e32 v6, vcc, v9, v10
; CI-NEXT: v_add_i32_e32 v6, vcc, 12, v6
-; CI-NEXT: .LBB11_6: ; %frem.loop_body23
+; CI-NEXT: .LBB11_5: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v9, v7
; CI-NEXT: v_mul_f32_e32 v7, v9, v8
@@ -12045,10 +11916,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v6, vcc, -12, v6
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v6
; CI-NEXT: v_ldexp_f32_e64 v7, v7, 12
-; CI-NEXT: s_cbranch_vccnz .LBB11_6
-; CI-NEXT: ; %bb.7: ; %Flow51
+; CI-NEXT: s_cbranch_vccnz .LBB11_5
+; CI-NEXT: ; %bb.6: ; %Flow51
; CI-NEXT: v_mov_b32_e32 v7, v9
-; CI-NEXT: .LBB11_8: ; %frem.loop_exit24
+; CI-NEXT: .LBB11_7: ; %frem.loop_exit24
; CI-NEXT: v_add_i32_e32 v6, vcc, -11, v6
; CI-NEXT: v_ldexp_f32_e32 v6, v7, v6
; CI-NEXT: v_mul_f32_e32 v7, v6, v8
@@ -12060,25 +11931,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; CI-NEXT: .LBB11_9:
+; CI-NEXT: .LBB11_8:
; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB11_11
-; CI-NEXT: ; %bb.10: ; %frem.else
+; CI-NEXT: s_cbranch_vccz .LBB11_10
+; CI-NEXT: ; %bb.9: ; %frem.else
; CI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
; CI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_branch .LBB11_12
-; CI-NEXT: .LBB11_11:
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB11_11
+; CI-NEXT: s_branch .LBB11_16
+; CI-NEXT: .LBB11_10:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr5
-; CI-NEXT: .LBB11_12: ; %Flow49
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB11_18
-; CI-NEXT: ; %bb.13: ; %frem.compute
+; CI-NEXT: s_cbranch_scc0 .LBB11_16
+; CI-NEXT: .LBB11_11: ; %frem.compute
; CI-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; CI-NEXT: v_ldexp_f32_e64 v6, v6, 1
; CI-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
@@ -12102,11 +11972,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v7
; CI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB11_17
-; CI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB11_15
+; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v7, vcc, v10, v11
; CI-NEXT: v_add_i32_e32 v7, vcc, 12, v7
-; CI-NEXT: .LBB11_15: ; %frem.loop_body
+; CI-NEXT: .LBB11_13: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v10, v8
; CI-NEXT: v_mul_f32_e32 v8, v10, v9
@@ -12118,10 +11988,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v7, vcc, -12, v7
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v7
; CI-NEXT: v_ldexp_f32_e64 v8, v8, 12
-; CI-NEXT: s_cbranch_vccnz .LBB11_15
-; CI-NEXT: ; %bb.16: ; %Flow
+; CI-NEXT: s_cbranch_vccnz .LBB11_13
+; CI-NEXT: ; %bb.14: ; %Flow
; CI-NEXT: v_mov_b32_e32 v8, v10
-; CI-NEXT: .LBB11_17: ; %frem.loop_exit
+; CI-NEXT: .LBB11_15: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v7, vcc, -11, v7
; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
; CI-NEXT: v_mul_f32_e32 v8, v7, v9
@@ -12133,7 +12003,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v5, v6, v5
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; CI-NEXT: .LBB11_18: ; %Flow50
+; CI-NEXT: .LBB11_16: ; %Flow50
; CI-NEXT: s_mov_b32 s4, 0x7f800000
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -12171,16 +12041,15 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
; VI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB11_3
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB11_3
+; VI-NEXT: s_branch .LBB11_8
; VI-NEXT: .LBB11_2:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr4
-; VI-NEXT: .LBB11_3: ; %Flow53
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB11_9
-; VI-NEXT: ; %bb.4: ; %frem.compute15
+; VI-NEXT: s_cbranch_scc0 .LBB11_8
+; VI-NEXT: .LBB11_3: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; VI-NEXT: v_ldexp_f32 v5, v5, 1
; VI-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
@@ -12204,11 +12073,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v6
; VI-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB11_8
-; VI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB11_7
+; VI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; VI-NEXT: v_sub_u32_e32 v6, vcc, v9, v10
; VI-NEXT: v_add_u32_e32 v6, vcc, 12, v6
-; VI-NEXT: .LBB11_6: ; %frem.loop_body23
+; VI-NEXT: .LBB11_5: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v9, v7
; VI-NEXT: v_mul_f32_e32 v7, v9, v8
@@ -12220,10 +12089,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v6, vcc, -12, v6
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v6
; VI-NEXT: v_ldexp_f32 v7, v7, 12
-; VI-NEXT: s_cbranch_vccnz .LBB11_6
-; VI-NEXT: ; %bb.7: ; %Flow51
+; VI-NEXT: s_cbranch_vccnz .LBB11_5
+; VI-NEXT: ; %bb.6: ; %Flow51
; VI-NEXT: v_mov_b32_e32 v7, v9
-; VI-NEXT: .LBB11_8: ; %frem.loop_exit24
+; VI-NEXT: .LBB11_7: ; %frem.loop_exit24
; VI-NEXT: v_add_u32_e32 v6, vcc, -11, v6
; VI-NEXT: v_ldexp_f32 v6, v7, v6
; VI-NEXT: v_mul_f32_e32 v7, v6, v8
@@ -12235,25 +12104,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v4, v5, v4
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; VI-NEXT: .LBB11_9:
+; VI-NEXT: .LBB11_8:
; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB11_11
-; VI-NEXT: ; %bb.10: ; %frem.else
+; VI-NEXT: s_cbranch_vccz .LBB11_10
+; VI-NEXT: ; %bb.9: ; %frem.else
; VI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
; VI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB11_12
-; VI-NEXT: .LBB11_11:
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB11_11
+; VI-NEXT: s_branch .LBB11_16
+; VI-NEXT: .LBB11_10:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr5
-; VI-NEXT: .LBB11_12: ; %Flow49
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB11_18
-; VI-NEXT: ; %bb.13: ; %frem.compute
+; VI-NEXT: s_cbranch_scc0 .LBB11_16
+; VI-NEXT: .LBB11_11: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; VI-NEXT: v_ldexp_f32 v6, v6, 1
; VI-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
@@ -12277,11 +12145,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v7
; VI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB11_17
-; VI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB11_15
+; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v7, vcc, v10, v11
; VI-NEXT: v_add_u32_e32 v7, vcc, 12, v7
-; VI-NEXT: .LBB11_15: ; %frem.loop_body
+; VI-NEXT: .LBB11_13: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v10, v8
; VI-NEXT: v_mul_f32_e32 v8, v10, v9
@@ -12293,10 +12161,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v7, vcc, -12, v7
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v7
; VI-NEXT: v_ldexp_f32 v8, v8, 12
-; VI-NEXT: s_cbranch_vccnz .LBB11_15
-; VI-NEXT: ; %bb.16: ; %Flow
+; VI-NEXT: s_cbranch_vccnz .LBB11_13
+; VI-NEXT: ; %bb.14: ; %Flow
; VI-NEXT: v_mov_b32_e32 v8, v10
-; VI-NEXT: .LBB11_17: ; %frem.loop_exit
+; VI-NEXT: .LBB11_15: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v7, vcc, -11, v7
; VI-NEXT: v_ldexp_f32 v7, v8, v7
; VI-NEXT: v_mul_f32_e32 v8, v7, v9
@@ -12308,7 +12176,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v5, v6, v5
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; VI-NEXT: .LBB11_18: ; %Flow50
+; VI-NEXT: .LBB11_16: ; %Flow50
; VI-NEXT: s_mov_b32 s4, 0x7f800000
; VI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -12341,16 +12209,15 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB11_3
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB11_3
+; GFX9-NEXT: s_branch .LBB11_8
; GFX9-NEXT: .LBB11_2:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr4
-; GFX9-NEXT: .LBB11_3: ; %Flow53
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB11_9
-; GFX9-NEXT: ; %bb.4: ; %frem.compute15
+; GFX9-NEXT: s_cbranch_scc0 .LBB11_8
+; GFX9-NEXT: .LBB11_3: ; %frem.compute15
; GFX9-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; GFX9-NEXT: v_ldexp_f32 v5, v5, 1
; GFX9-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
@@ -12374,11 +12241,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v8, v8, v12, v13
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v6
; GFX9-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_8
-; GFX9-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_7
+; GFX9-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX9-NEXT: v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT: v_add_u32_e32 v6, 12, v6
-; GFX9-NEXT: .LBB11_6: ; %frem.loop_body23
+; GFX9-NEXT: .LBB11_5: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v9, v7
; GFX9-NEXT: v_mul_f32_e32 v7, v9, v8
@@ -12390,10 +12257,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v6
; GFX9-NEXT: v_ldexp_f32 v7, v7, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_6
-; GFX9-NEXT: ; %bb.7: ; %Flow51
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_5
+; GFX9-NEXT: ; %bb.6: ; %Flow51
; GFX9-NEXT: v_mov_b32_e32 v7, v9
-; GFX9-NEXT: .LBB11_8: ; %frem.loop_exit24
+; GFX9-NEXT: .LBB11_7: ; %frem.loop_exit24
; GFX9-NEXT: v_add_u32_e32 v6, -11, v6
; GFX9-NEXT: v_ldexp_f32 v6, v7, v6
; GFX9-NEXT: v_mul_f32_e32 v7, v6, v8
@@ -12405,25 +12272,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v0
-; GFX9-NEXT: .LBB11_9:
+; GFX9-NEXT: .LBB11_8:
; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB11_11
-; GFX9-NEXT: ; %bb.10: ; %frem.else
+; GFX9-NEXT: s_cbranch_vccz .LBB11_10
+; GFX9-NEXT: ; %bb.9: ; %frem.else
; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v1
; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB11_12
-; GFX9-NEXT: .LBB11_11:
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB11_11
+; GFX9-NEXT: s_branch .LBB11_16
+; GFX9-NEXT: .LBB11_10:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr5
-; GFX9-NEXT: .LBB11_12: ; %Flow49
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB11_18
-; GFX9-NEXT: ; %bb.13: ; %frem.compute
+; GFX9-NEXT: s_cbranch_scc0 .LBB11_16
+; GFX9-NEXT: .LBB11_11: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; GFX9-NEXT: v_ldexp_f32 v6, v6, 1
; GFX9-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
@@ -12447,11 +12313,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v9, v9, v13, v14
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v7
; GFX9-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_17
-; GFX9-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_15
+; GFX9-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v7, v10, v11
; GFX9-NEXT: v_add_u32_e32 v7, 12, v7
-; GFX9-NEXT: .LBB11_15: ; %frem.loop_body
+; GFX9-NEXT: .LBB11_13: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v10, v8
; GFX9-NEXT: v_mul_f32_e32 v8, v10, v9
@@ -12463,10 +12329,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v7
; GFX9-NEXT: v_ldexp_f32 v8, v8, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_15
-; GFX9-NEXT: ; %bb.16: ; %Flow
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_13
+; GFX9-NEXT: ; %bb.14: ; %Flow
; GFX9-NEXT: v_mov_b32_e32 v8, v10
-; GFX9-NEXT: .LBB11_17: ; %frem.loop_exit
+; GFX9-NEXT: .LBB11_15: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v7, -11, v7
; GFX9-NEXT: v_ldexp_f32 v7, v8, v7
; GFX9-NEXT: v_mul_f32_e32 v8, v7, v9
@@ -12478,7 +12344,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v5, v6, v5
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v1
-; GFX9-NEXT: .LBB11_18: ; %Flow50
+; GFX9-NEXT: .LBB11_16: ; %Flow50
; GFX9-NEXT: s_mov_b32 s4, 0x7f800000
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; GFX9-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -12512,16 +12378,15 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
-; GFX10-NEXT: s_branch .LBB11_3
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB11_3
+; GFX10-NEXT: s_branch .LBB11_8
; GFX10-NEXT: .LBB11_2:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: .LBB11_3: ; %Flow53
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB11_9
-; GFX10-NEXT: ; %bb.4: ; %frem.compute15
+; GFX10-NEXT: s_cbranch_scc0 .LBB11_8
+; GFX10-NEXT: .LBB11_3: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; GFX10-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
@@ -12547,11 +12412,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v8
; GFX10-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB11_8
-; GFX10-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB11_7
+; GFX10-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB11_6: ; %frem.loop_body23
+; GFX10-NEXT: .LBB11_5: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -12563,11 +12428,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v8, v6, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v6, v6, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB11_6
-; GFX10-NEXT: ; %bb.7: ; %Flow51
+; GFX10-NEXT: s_cbranch_scc1 .LBB11_5
+; GFX10-NEXT: ; %bb.6: ; %Flow51
; GFX10-NEXT: v_mov_b32_e32 v8, s2
; GFX10-NEXT: v_mov_b32_e32 v6, v9
-; GFX10-NEXT: .LBB11_8: ; %frem.loop_exit24
+; GFX10-NEXT: .LBB11_7: ; %frem.loop_exit24
; GFX10-NEXT: v_add_nc_u32_e32 v8, -11, v8
; GFX10-NEXT: v_ldexp_f32 v6, v6, v8
; GFX10-NEXT: v_mul_f32_e32 v7, v6, v7
@@ -12578,25 +12443,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v5, v4
; GFX10-NEXT: v_bfi_b32 v4, 0x7fffffff, v4, v0
-; GFX10-NEXT: .LBB11_9:
+; GFX10-NEXT: .LBB11_8:
; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v3|
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB11_11
-; GFX10-NEXT: ; %bb.10: ; %frem.else
+; GFX10-NEXT: s_cbranch_vccz .LBB11_10
+; GFX10-NEXT: ; %bb.9: ; %frem.else
; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v1
; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc_lo
-; GFX10-NEXT: s_branch .LBB11_12
-; GFX10-NEXT: .LBB11_11:
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB11_11
+; GFX10-NEXT: s_branch .LBB11_16
+; GFX10-NEXT: .LBB11_10:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr5
-; GFX10-NEXT: .LBB11_12: ; %Flow49
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB11_18
-; GFX10-NEXT: ; %bb.13: ; %frem.compute
+; GFX10-NEXT: s_cbranch_scc0 .LBB11_16
+; GFX10-NEXT: .LBB11_11: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; GFX10-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
@@ -12622,11 +12486,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v8, v8, v11, v12
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v9
; GFX10-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB11_17
-; GFX10-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB11_15
+; GFX10-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB11_15: ; %frem.loop_body
+; GFX10-NEXT: .LBB11_13: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v10, v7
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -12638,11 +12502,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v9, v7, v6
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v7, v7, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB11_15
-; GFX10-NEXT: ; %bb.16: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB11_13
+; GFX10-NEXT: ; %bb.14: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v9, s2
; GFX10-NEXT: v_mov_b32_e32 v7, v10
-; GFX10-NEXT: .LBB11_17: ; %frem.loop_exit
+; GFX10-NEXT: .LBB11_15: ; %frem.loop_exit
; GFX10-NEXT: v_add_nc_u32_e32 v9, -11, v9
; GFX10-NEXT: v_ldexp_f32 v7, v7, v9
; GFX10-NEXT: v_mul_f32_e32 v8, v7, v8
@@ -12653,7 +12517,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v5, v6, v5
; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX10-NEXT: .LBB11_18: ; %Flow50
+; GFX10-NEXT: .LBB11_16: ; %Flow50
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
@@ -12685,17 +12549,16 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
-; GFX11-NEXT: s_branch .LBB11_3
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB11_3
+; GFX11-NEXT: s_branch .LBB11_8
; GFX11-NEXT: .LBB11_2:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr4
-; GFX11-NEXT: .LBB11_3: ; %Flow53
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB11_9
-; GFX11-NEXT: ; %bb.4: ; %frem.compute15
+; GFX11-NEXT: s_cbranch_scc0 .LBB11_8
+; GFX11-NEXT: .LBB11_3: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; GFX11-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
@@ -12730,12 +12593,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB11_8
-; GFX11-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB11_7
+; GFX11-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB11_6: ; %frem.loop_body23
+; GFX11-NEXT: .LBB11_5: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v9, v6
@@ -12751,11 +12614,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v6, v6, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB11_6
-; GFX11-NEXT: ; %bb.7: ; %Flow51
+; GFX11-NEXT: s_cbranch_scc1 .LBB11_5
+; GFX11-NEXT: ; %bb.6: ; %Flow51
; GFX11-NEXT: v_mov_b32_e32 v8, s2
; GFX11-NEXT: v_mov_b32_e32 v6, v9
-; GFX11-NEXT: .LBB11_8: ; %frem.loop_exit24
+; GFX11-NEXT: .LBB11_7: ; %frem.loop_exit24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_nc_u32_e32 v8, -11, v8
; GFX11-NEXT: v_ldexp_f32 v6, v6, v8
@@ -12771,26 +12634,25 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v4, v5, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v4, 0x7fffffff, v4, v0
-; GFX11-NEXT: .LBB11_9:
+; GFX11-NEXT: .LBB11_8:
; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v3|
; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB11_11
-; GFX11-NEXT: ; %bb.10: ; %frem.else
+; GFX11-NEXT: s_cbranch_vccz .LBB11_10
+; GFX11-NEXT: ; %bb.9: ; %frem.else
; GFX11-NEXT: v_and_b32_e32 v5, 0x80000000, v1
; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc_lo
-; GFX11-NEXT: s_branch .LBB11_12
-; GFX11-NEXT: .LBB11_11:
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB11_11
+; GFX11-NEXT: s_branch .LBB11_16
+; GFX11-NEXT: .LBB11_10:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr5
-; GFX11-NEXT: .LBB11_12: ; %Flow49
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB11_18
-; GFX11-NEXT: ; %bb.13: ; %frem.compute
+; GFX11-NEXT: s_cbranch_scc0 .LBB11_16
+; GFX11-NEXT: .LBB11_11: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; GFX11-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
@@ -12825,12 +12687,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB11_17
-; GFX11-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB11_15
+; GFX11-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB11_15: ; %frem.loop_body
+; GFX11-NEXT: .LBB11_13: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v10, v7
@@ -12846,11 +12708,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v7, v7, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB11_15
-; GFX11-NEXT: ; %bb.16: ; %Flow
+; GFX11-NEXT: s_cbranch_scc1 .LBB11_13
+; GFX11-NEXT: ; %bb.14: ; %Flow
; GFX11-NEXT: v_mov_b32_e32 v9, s2
; GFX11-NEXT: v_mov_b32_e32 v7, v10
-; GFX11-NEXT: .LBB11_17: ; %frem.loop_exit
+; GFX11-NEXT: .LBB11_15: ; %frem.loop_exit
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_nc_u32_e32 v9, -11, v9
; GFX11-NEXT: v_ldexp_f32 v7, v7, v9
@@ -12866,7 +12728,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v5, v6, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX11-NEXT: .LBB11_18: ; %Flow50
+; GFX11-NEXT: .LBB11_16: ; %Flow50
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
@@ -12907,17 +12769,16 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v0, s6, v0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB11_3
+; GFX1150-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB11_3
+; GFX1150-NEXT: s_branch .LBB11_8
; GFX1150-NEXT: .LBB11_2:
; GFX1150-NEXT: s_mov_b32 s7, -1
; GFX1150-NEXT: ; implicit-def: $vgpr0
-; GFX1150-NEXT: .LBB11_3: ; %Flow53
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s7, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB11_9
-; GFX1150-NEXT: ; %bb.4: ; %frem.compute15
+; GFX1150-NEXT: s_cbranch_scc0 .LBB11_8
+; GFX1150-NEXT: .LBB11_3: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s4|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v0, |s6|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
@@ -12951,12 +12812,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1150-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB11_8
-; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB11_7
+; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_sub_i32 s7, s7, s8
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s7, s7, 12
-; GFX1150-NEXT: .LBB11_6: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB11_5: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v5, v2
@@ -12974,11 +12835,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v2, v2, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB11_6
-; GFX1150-NEXT: ; %bb.7: ; %Flow51
+; GFX1150-NEXT: s_cbranch_scc1 .LBB11_5
+; GFX1150-NEXT: ; %bb.6: ; %Flow51
; GFX1150-NEXT: v_mov_b32_e32 v4, s7
; GFX1150-NEXT: v_mov_b32_e32 v2, v5
-; GFX1150-NEXT: .LBB11_8: ; %frem.loop_exit24
+; GFX1150-NEXT: .LBB11_7: ; %frem.loop_exit24
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_add_nc_u32_e32 v4, -11, v4
; GFX1150-NEXT: v_ldexp_f32 v2, v2, v4
@@ -12995,13 +12856,13 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1150-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s6
-; GFX1150-NEXT: .LBB11_9:
+; GFX1150-NEXT: .LBB11_8:
; GFX1150-NEXT: s_and_b32 s6, s5, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s7, s2, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_cmp_ngt_f32 s6, s7
-; GFX1150-NEXT: s_cbranch_scc0 .LBB11_11
-; GFX1150-NEXT: ; %bb.10: ; %frem.else
+; GFX1150-NEXT: s_cbranch_scc0 .LBB11_10
+; GFX1150-NEXT: ; %bb.9: ; %frem.else
; GFX1150-NEXT: s_and_b32 s8, 0x80000000, s5
; GFX1150-NEXT: s_cmp_eq_f32 s6, s7
; GFX1150-NEXT: v_mov_b32_e32 v1, s8
@@ -13009,17 +12870,16 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
-; GFX1150-NEXT: s_branch .LBB11_12
-; GFX1150-NEXT: .LBB11_11:
+; GFX1150-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB11_11
+; GFX1150-NEXT: s_branch .LBB11_16
+; GFX1150-NEXT: .LBB11_10:
; GFX1150-NEXT: s_mov_b32 s7, -1
; GFX1150-NEXT: ; implicit-def: $vgpr1
-; GFX1150-NEXT: .LBB11_12: ; %Flow49
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s7, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB11_18
-; GFX1150-NEXT: ; %bb.13: ; %frem.compute
+; GFX1150-NEXT: s_cbranch_scc0 .LBB11_16
+; GFX1150-NEXT: .LBB11_11: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f32_e64 v2, |s2|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s5|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v4, s5
@@ -13053,12 +12913,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1150-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB11_17
-; GFX1150-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB11_15
+; GFX1150-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s7, s7, s8
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s7, s7, 12
-; GFX1150-NEXT: .LBB11_15: ; %frem.loop_body
+; GFX1150-NEXT: .LBB11_13: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v6, v3
@@ -13076,11 +12936,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB11_15
-; GFX1150-NEXT: ; %bb.16: ; %Flow
+; GFX1150-NEXT: s_cbranch_scc1 .LBB11_13
+; GFX1150-NEXT: ; %bb.14: ; %Flow
; GFX1150-NEXT: v_mov_b32_e32 v5, s7
; GFX1150-NEXT: v_mov_b32_e32 v3, v6
-; GFX1150-NEXT: .LBB11_17: ; %frem.loop_exit
+; GFX1150-NEXT: .LBB11_15: ; %frem.loop_exit
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_add_nc_u32_e32 v5, -11, v5
; GFX1150-NEXT: v_ldexp_f32 v3, v3, v5
@@ -13097,7 +12957,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1150-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s5
-; GFX1150-NEXT: .LBB11_18: ; %Flow50
+; GFX1150-NEXT: .LBB11_16: ; %Flow50
; GFX1150-NEXT: s_cmp_lg_f32 s4, 0
; GFX1150-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-NEXT: s_cselect_b32 s4, -1, 0
@@ -13135,23 +12995,25 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_and_b32 s7, s4, 0x7fffffff
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_cmp_ngt_f32 s3, s7
-; GFX1200-NEXT: s_cbranch_scc0 .LBB11_2
+; GFX1200-NEXT: s_cbranch_scc0 .LBB11_3
; GFX1200-NEXT: ; %bb.1: ; %frem.else16
; GFX1200-NEXT: s_and_b32 s8, 0x80000000, s6
; GFX1200-NEXT: s_cmp_eq_f32 s3, s7
; GFX1200-NEXT: s_cselect_b32 s7, s8, s6
; GFX1200-NEXT: s_mov_b32 s8, 0
-; GFX1200-NEXT: s_branch .LBB11_3
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB11_4
; GFX1200-NEXT: .LBB11_2:
+; GFX1200-NEXT: v_mov_b32_e32 v0, s7
+; GFX1200-NEXT: s_branch .LBB11_9
+; GFX1200-NEXT: .LBB11_3:
; GFX1200-NEXT: s_mov_b32 s8, -1
; GFX1200-NEXT: ; implicit-def: $sgpr7
-; GFX1200-NEXT: .LBB11_3: ; %Flow53
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s8, 1, 0
-; GFX1200-NEXT: s_cmp_lg_u32 s8, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB11_9
-; GFX1200-NEXT: ; %bb.4: ; %frem.compute15
+; GFX1200-NEXT: s_cbranch_scc0 .LBB11_2
+; GFX1200-NEXT: .LBB11_4: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s4|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v0, |s6|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
@@ -13232,31 +13094,31 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1200-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s6
-; GFX1200-NEXT: s_branch .LBB11_10
; GFX1200-NEXT: .LBB11_9:
-; GFX1200-NEXT: v_mov_b32_e32 v0, s7
-; GFX1200-NEXT: .LBB11_10:
; GFX1200-NEXT: s_and_b32 s6, s5, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s7, s2, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_ngt_f32 s6, s7
; GFX1200-NEXT: s_cbranch_scc0 .LBB11_12
-; GFX1200-NEXT: ; %bb.11: ; %frem.else
+; GFX1200-NEXT: ; %bb.10: ; %frem.else
; GFX1200-NEXT: s_and_b32 s8, 0x80000000, s5
; GFX1200-NEXT: s_cmp_eq_f32 s6, s7
; GFX1200-NEXT: s_cselect_b32 s7, s8, s5
; GFX1200-NEXT: s_mov_b32 s8, 0
-; GFX1200-NEXT: s_branch .LBB11_13
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB11_13
+; GFX1200-NEXT: .LBB11_11:
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v1, s7
+; GFX1200-NEXT: s_branch .LBB11_18
; GFX1200-NEXT: .LBB11_12:
; GFX1200-NEXT: s_mov_b32 s8, -1
; GFX1200-NEXT: ; implicit-def: $sgpr7
-; GFX1200-NEXT: .LBB11_13: ; %Flow49
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s8, 1, 0
-; GFX1200-NEXT: s_cmp_lg_u32 s8, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB11_19
-; GFX1200-NEXT: ; %bb.14: ; %frem.compute
+; GFX1200-NEXT: s_cbranch_scc0 .LBB11_11
+; GFX1200-NEXT: .LBB11_13: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f32_e64 v2, |s2|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s5|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v4, s5
@@ -13291,13 +13153,13 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1200-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB11_18
-; GFX1200-NEXT: ; %bb.15: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB11_17
+; GFX1200-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s7, s7, s8
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s7, s7, 12
-; GFX1200-NEXT: .LBB11_16: ; %frem.loop_body
+; GFX1200-NEXT: .LBB11_15: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v6, v3
@@ -13317,11 +13179,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB11_16
-; GFX1200-NEXT: ; %bb.17: ; %Flow
+; GFX1200-NEXT: s_cbranch_scc1 .LBB11_15
+; GFX1200-NEXT: ; %bb.16: ; %Flow
; GFX1200-NEXT: v_mov_b32_e32 v5, s7
; GFX1200-NEXT: v_mov_b32_e32 v3, v6
-; GFX1200-NEXT: .LBB11_18: ; %frem.loop_exit
+; GFX1200-NEXT: .LBB11_17: ; %frem.loop_exit
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_add_nc_u32_e32 v5, -11, v5
; GFX1200-NEXT: v_ldexp_f32 v3, v3, v5
@@ -13339,11 +13201,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1200-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s5
-; GFX1200-NEXT: s_branch .LBB11_20
-; GFX1200-NEXT: .LBB11_19:
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v1, s7
-; GFX1200-NEXT: .LBB11_20: ; %Flow50
+; GFX1200-NEXT: .LBB11_18: ; %Flow50
; GFX1200-NEXT: s_cmp_lg_f32 s4, 0
; GFX1200-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-NEXT: s_cselect_b32 s4, -1, 0
@@ -13395,16 +13253,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
; SI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_branch .LBB12_3
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cbranch_scc1 .LBB12_3
+; SI-NEXT: s_branch .LBB12_8
; SI-NEXT: .LBB12_2:
; SI-NEXT: s_mov_b64 s[2:3], -1
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: .LBB12_3: ; %Flow127
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cselect_b32 s2, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s2, 1
-; SI-NEXT: s_cbranch_scc1 .LBB12_9
-; SI-NEXT: ; %bb.4: ; %frem.compute77
+; SI-NEXT: s_cbranch_scc0 .LBB12_8
+; SI-NEXT: .LBB12_3: ; %frem.compute77
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v8, v0
@@ -13439,11 +13296,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v10, v10, v12, v13
; SI-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_8
-; SI-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_7
+; SI-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_6: ; %frem.loop_body85
+; SI-NEXT: .LBB12_5: ; %frem.loop_body85
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v11, v9
; SI-NEXT: v_mul_f32_e32 v9, v11, v10
@@ -13455,10 +13312,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v9, v9, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_6
-; SI-NEXT: ; %bb.7: ; %Flow125
+; SI-NEXT: s_cbranch_scc1 .LBB12_5
+; SI-NEXT: ; %bb.6: ; %Flow125
; SI-NEXT: v_mov_b32_e32 v9, v11
-; SI-NEXT: .LBB12_8: ; %frem.loop_exit86
+; SI-NEXT: .LBB12_7: ; %frem.loop_exit86
; SI-NEXT: s_add_i32 s3, s3, -11
; SI-NEXT: v_ldexp_f32_e64 v9, v9, s3
; SI-NEXT: v_mul_f32_e32 v10, v9, v10
@@ -13470,25 +13327,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v8, v8, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v8, s2, v8, v0
-; SI-NEXT: .LBB12_9:
+; SI-NEXT: .LBB12_8:
; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB12_11
-; SI-NEXT: ; %bb.10: ; %frem.else47
+; SI-NEXT: s_cbranch_vccz .LBB12_10
+; SI-NEXT: ; %bb.9: ; %frem.else47
; SI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
; SI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_branch .LBB12_12
-; SI-NEXT: .LBB12_11:
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cbranch_scc1 .LBB12_11
+; SI-NEXT: s_branch .LBB12_16
+; SI-NEXT: .LBB12_10:
; SI-NEXT: s_mov_b64 s[2:3], -1
; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: .LBB12_12: ; %Flow123
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cselect_b32 s2, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s2, 1
-; SI-NEXT: s_cbranch_scc1 .LBB12_18
-; SI-NEXT: ; %bb.13: ; %frem.compute46
+; SI-NEXT: s_cbranch_scc0 .LBB12_16
+; SI-NEXT: .LBB12_11: ; %frem.compute46
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v9, v1
@@ -13523,11 +13379,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v11, v11, v13, v14
; SI-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_17
-; SI-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_15
+; SI-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_15: ; %frem.loop_body54
+; SI-NEXT: .LBB12_13: ; %frem.loop_body54
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v12, v10
; SI-NEXT: v_mul_f32_e32 v10, v12, v11
@@ -13539,10 +13395,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v10, v10, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_15
-; SI-NEXT: ; %bb.16: ; %Flow121
+; SI-NEXT: s_cbranch_scc1 .LBB12_13
+; SI-NEXT: ; %bb.14: ; %Flow121
; SI-NEXT: v_mov_b32_e32 v10, v12
-; SI-NEXT: .LBB12_17: ; %frem.loop_exit55
+; SI-NEXT: .LBB12_15: ; %frem.loop_exit55
; SI-NEXT: s_add_i32 s3, s3, -11
; SI-NEXT: v_ldexp_f32_e64 v10, v10, s3
; SI-NEXT: v_mul_f32_e32 v11, v10, v11
@@ -13554,25 +13410,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v9, v9, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; SI-NEXT: .LBB12_18:
+; SI-NEXT: .LBB12_16:
; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB12_20
-; SI-NEXT: ; %bb.19: ; %frem.else16
+; SI-NEXT: s_cbranch_vccz .LBB12_18
+; SI-NEXT: ; %bb.17: ; %frem.else16
; SI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
; SI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_branch .LBB12_21
-; SI-NEXT: .LBB12_20:
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cbranch_scc1 .LBB12_19
+; SI-NEXT: s_branch .LBB12_24
+; SI-NEXT: .LBB12_18:
; SI-NEXT: s_mov_b64 s[2:3], -1
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: .LBB12_21: ; %Flow119
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cselect_b32 s2, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s2, 1
-; SI-NEXT: s_cbranch_scc1 .LBB12_27
-; SI-NEXT: ; %bb.22: ; %frem.compute15
+; SI-NEXT: s_cbranch_scc0 .LBB12_24
+; SI-NEXT: .LBB12_19: ; %frem.compute15
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v2|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v10, v2
@@ -13607,11 +13462,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v12, v12, v14, v15
; SI-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_26
-; SI-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_23
+; SI-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_24: ; %frem.loop_body23
+; SI-NEXT: .LBB12_21: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v13, v11
; SI-NEXT: v_mul_f32_e32 v11, v13, v12
@@ -13623,10 +13478,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v11, v11, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_24
-; SI-NEXT: ; %bb.25: ; %Flow117
+; SI-NEXT: s_cbranch_scc1 .LBB12_21
+; SI-NEXT: ; %bb.22: ; %Flow117
; SI-NEXT: v_mov_b32_e32 v11, v13
-; SI-NEXT: .LBB12_26: ; %frem.loop_exit24
+; SI-NEXT: .LBB12_23: ; %frem.loop_exit24
; SI-NEXT: s_add_i32 s3, s3, -11
; SI-NEXT: v_ldexp_f32_e64 v11, v11, s3
; SI-NEXT: v_mul_f32_e32 v12, v11, v12
@@ -13638,25 +13493,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v10, v10, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v10, s2, v10, v2
-; SI-NEXT: .LBB12_27:
+; SI-NEXT: .LBB12_24:
; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB12_29
-; SI-NEXT: ; %bb.28: ; %frem.else
+; SI-NEXT: s_cbranch_vccz .LBB12_26
+; SI-NEXT: ; %bb.25: ; %frem.else
; SI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
; SI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_branch .LBB12_30
-; SI-NEXT: .LBB12_29:
+; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT: s_cbranch_scc1 .LBB12_27
+; SI-NEXT: s_branch .LBB12_32
+; SI-NEXT: .LBB12_26:
; SI-NEXT: s_mov_b64 s[2:3], -1
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: .LBB12_30: ; %Flow115
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cselect_b32 s2, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s2, 1
-; SI-NEXT: s_cbranch_scc1 .LBB12_36
-; SI-NEXT: ; %bb.31: ; %frem.compute
+; SI-NEXT: s_cbranch_scc0 .LBB12_32
+; SI-NEXT: .LBB12_27: ; %frem.compute
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v11, v3
@@ -13691,11 +13545,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v13, v13, v15, v16
; SI-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_35
-; SI-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_31
+; SI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_33: ; %frem.loop_body
+; SI-NEXT: .LBB12_29: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v14, v12
; SI-NEXT: v_mul_f32_e32 v12, v14, v13
@@ -13707,10 +13561,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v12, v12, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_33
-; SI-NEXT: ; %bb.34: ; %Flow
+; SI-NEXT: s_cbranch_scc1 .LBB12_29
+; SI-NEXT: ; %bb.30: ; %Flow
; SI-NEXT: v_mov_b32_e32 v12, v14
-; SI-NEXT: .LBB12_35: ; %frem.loop_exit
+; SI-NEXT: .LBB12_31: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s3, s3, -11
; SI-NEXT: v_ldexp_f32_e64 v12, v12, s3
; SI-NEXT: v_mul_f32_e32 v13, v12, v13
@@ -13722,7 +13576,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v11, v11, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; SI-NEXT: .LBB12_36: ; %Flow116
+; SI-NEXT: .LBB12_32: ; %Flow116
; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; SI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -13768,16 +13622,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
; CI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_branch .LBB12_3
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB12_3
+; CI-NEXT: s_branch .LBB12_8
; CI-NEXT: .LBB12_2:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr8
-; CI-NEXT: .LBB12_3: ; %Flow127
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB12_9
-; CI-NEXT: ; %bb.4: ; %frem.compute77
+; CI-NEXT: s_cbranch_scc0 .LBB12_8
+; CI-NEXT: .LBB12_3: ; %frem.compute77
; CI-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; CI-NEXT: v_ldexp_f32_e64 v9, v9, 1
; CI-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
@@ -13801,11 +13654,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v12, v12, v16, v17
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v10
; CI-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_8
-; CI-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB12_7
+; CI-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
; CI-NEXT: v_sub_i32_e32 v10, vcc, v13, v14
; CI-NEXT: v_add_i32_e32 v10, vcc, 12, v10
-; CI-NEXT: .LBB12_6: ; %frem.loop_body85
+; CI-NEXT: .LBB12_5: ; %frem.loop_body85
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v13, v11
; CI-NEXT: v_mul_f32_e32 v11, v13, v12
@@ -13817,10 +13670,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v10, vcc, -12, v10
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v10
; CI-NEXT: v_ldexp_f32_e64 v11, v11, 12
-; CI-NEXT: s_cbranch_vccnz .LBB12_6
-; CI-NEXT: ; %bb.7: ; %Flow125
+; CI-NEXT: s_cbranch_vccnz .LBB12_5
+; CI-NEXT: ; %bb.6: ; %Flow125
; CI-NEXT: v_mov_b32_e32 v11, v13
-; CI-NEXT: .LBB12_8: ; %frem.loop_exit86
+; CI-NEXT: .LBB12_7: ; %frem.loop_exit86
; CI-NEXT: v_add_i32_e32 v10, vcc, -11, v10
; CI-NEXT: v_ldexp_f32_e32 v10, v11, v10
; CI-NEXT: v_mul_f32_e32 v11, v10, v12
@@ -13832,25 +13685,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v8, v9, v8
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v8, s2, v8, v0
-; CI-NEXT: .LBB12_9:
+; CI-NEXT: .LBB12_8:
; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB12_11
-; CI-NEXT: ; %bb.10: ; %frem.else47
+; CI-NEXT: s_cbranch_vccz .LBB12_10
+; CI-NEXT: ; %bb.9: ; %frem.else47
; CI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
; CI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_branch .LBB12_12
-; CI-NEXT: .LBB12_11:
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB12_11
+; CI-NEXT: s_branch .LBB12_16
+; CI-NEXT: .LBB12_10:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr9
-; CI-NEXT: .LBB12_12: ; %Flow123
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB12_18
-; CI-NEXT: ; %bb.13: ; %frem.compute46
+; CI-NEXT: s_cbranch_scc0 .LBB12_16
+; CI-NEXT: .LBB12_11: ; %frem.compute46
; CI-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; CI-NEXT: v_ldexp_f32_e64 v10, v10, 1
; CI-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
@@ -13874,11 +13726,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v13, v13, v17, v18
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v11
; CI-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_17
-; CI-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB12_15
+; CI-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
; CI-NEXT: v_sub_i32_e32 v11, vcc, v14, v15
; CI-NEXT: v_add_i32_e32 v11, vcc, 12, v11
-; CI-NEXT: .LBB12_15: ; %frem.loop_body54
+; CI-NEXT: .LBB12_13: ; %frem.loop_body54
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v14, v12
; CI-NEXT: v_mul_f32_e32 v12, v14, v13
@@ -13890,10 +13742,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v11, vcc, -12, v11
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v11
; CI-NEXT: v_ldexp_f32_e64 v12, v12, 12
-; CI-NEXT: s_cbranch_vccnz .LBB12_15
-; CI-NEXT: ; %bb.16: ; %Flow121
+; CI-NEXT: s_cbranch_vccnz .LBB12_13
+; CI-NEXT: ; %bb.14: ; %Flow121
; CI-NEXT: v_mov_b32_e32 v12, v14
-; CI-NEXT: .LBB12_17: ; %frem.loop_exit55
+; CI-NEXT: .LBB12_15: ; %frem.loop_exit55
; CI-NEXT: v_add_i32_e32 v11, vcc, -11, v11
; CI-NEXT: v_ldexp_f32_e32 v11, v12, v11
; CI-NEXT: v_mul_f32_e32 v12, v11, v13
@@ -13905,25 +13757,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v9, v10, v9
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; CI-NEXT: .LBB12_18:
+; CI-NEXT: .LBB12_16:
; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB12_20
-; CI-NEXT: ; %bb.19: ; %frem.else16
+; CI-NEXT: s_cbranch_vccz .LBB12_18
+; CI-NEXT: ; %bb.17: ; %frem.else16
; CI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
; CI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_branch .LBB12_21
-; CI-NEXT: .LBB12_20:
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB12_19
+; CI-NEXT: s_branch .LBB12_24
+; CI-NEXT: .LBB12_18:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr10
-; CI-NEXT: .LBB12_21: ; %Flow119
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB12_27
-; CI-NEXT: ; %bb.22: ; %frem.compute15
+; CI-NEXT: s_cbranch_scc0 .LBB12_24
+; CI-NEXT: .LBB12_19: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; CI-NEXT: v_ldexp_f32_e64 v11, v11, 1
; CI-NEXT: v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
@@ -13947,11 +13798,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v14, v14, v18, v19
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v12
; CI-NEXT: v_div_fixup_f32 v14, v14, v11, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_26
-; CI-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB12_23
+; CI-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
; CI-NEXT: v_sub_i32_e32 v12, vcc, v15, v16
; CI-NEXT: v_add_i32_e32 v12, vcc, 12, v12
-; CI-NEXT: .LBB12_24: ; %frem.loop_body23
+; CI-NEXT: .LBB12_21: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v15, v13
; CI-NEXT: v_mul_f32_e32 v13, v15, v14
@@ -13963,10 +13814,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v12, vcc, -12, v12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v12
; CI-NEXT: v_ldexp_f32_e64 v13, v13, 12
-; CI-NEXT: s_cbranch_vccnz .LBB12_24
-; CI-NEXT: ; %bb.25: ; %Flow117
+; CI-NEXT: s_cbranch_vccnz .LBB12_21
+; CI-NEXT: ; %bb.22: ; %Flow117
; CI-NEXT: v_mov_b32_e32 v13, v15
-; CI-NEXT: .LBB12_26: ; %frem.loop_exit24
+; CI-NEXT: .LBB12_23: ; %frem.loop_exit24
; CI-NEXT: v_add_i32_e32 v12, vcc, -11, v12
; CI-NEXT: v_ldexp_f32_e32 v12, v13, v12
; CI-NEXT: v_mul_f32_e32 v13, v12, v14
@@ -13978,25 +13829,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v10, v11, v10
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v10, s2, v10, v2
-; CI-NEXT: .LBB12_27:
+; CI-NEXT: .LBB12_24:
; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB12_29
-; CI-NEXT: ; %bb.28: ; %frem.else
+; CI-NEXT: s_cbranch_vccz .LBB12_26
+; CI-NEXT: ; %bb.25: ; %frem.else
; CI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
; CI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_branch .LBB12_30
-; CI-NEXT: .LBB12_29:
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB12_27
+; CI-NEXT: s_branch .LBB12_32
+; CI-NEXT: .LBB12_26:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr11
-; CI-NEXT: .LBB12_30: ; %Flow115
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB12_36
-; CI-NEXT: ; %bb.31: ; %frem.compute
+; CI-NEXT: s_cbranch_scc0 .LBB12_32
+; CI-NEXT: .LBB12_27: ; %frem.compute
; CI-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; CI-NEXT: v_ldexp_f32_e64 v12, v12, 1
; CI-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
@@ -14020,11 +13870,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f32 v15, v15, v19, v20
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v13
; CI-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_35
-; CI-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB12_31
+; CI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v13, vcc, v16, v17
; CI-NEXT: v_add_i32_e32 v13, vcc, 12, v13
-; CI-NEXT: .LBB12_33: ; %frem.loop_body
+; CI-NEXT: .LBB12_29: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v16, v14
; CI-NEXT: v_mul_f32_e32 v14, v16, v15
@@ -14036,10 +13886,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_add_i32_e32 v13, vcc, -12, v13
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v13
; CI-NEXT: v_ldexp_f32_e64 v14, v14, 12
-; CI-NEXT: s_cbranch_vccnz .LBB12_33
-; CI-NEXT: ; %bb.34: ; %Flow
+; CI-NEXT: s_cbranch_vccnz .LBB12_29
+; CI-NEXT: ; %bb.30: ; %Flow
; CI-NEXT: v_mov_b32_e32 v14, v16
-; CI-NEXT: .LBB12_35: ; %frem.loop_exit
+; CI-NEXT: .LBB12_31: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v13, vcc, -11, v13
; CI-NEXT: v_ldexp_f32_e32 v13, v14, v13
; CI-NEXT: v_mul_f32_e32 v14, v13, v15
@@ -14051,7 +13901,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v11, v12, v11
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; CI-NEXT: .LBB12_36: ; %Flow116
+; CI-NEXT: .LBB12_32: ; %Flow116
; CI-NEXT: s_mov_b32 s4, 0x7f800000
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -14097,16 +13947,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
; VI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB12_3
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB12_3
+; VI-NEXT: s_branch .LBB12_8
; VI-NEXT: .LBB12_2:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr8
-; VI-NEXT: .LBB12_3: ; %Flow127
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB12_9
-; VI-NEXT: ; %bb.4: ; %frem.compute77
+; VI-NEXT: s_cbranch_scc0 .LBB12_8
+; VI-NEXT: .LBB12_3: ; %frem.compute77
; VI-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; VI-NEXT: v_ldexp_f32 v9, v9, 1
; VI-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
@@ -14130,11 +13979,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v12, v12, v16, v17
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v10
; VI-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_8
-; VI-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB12_7
+; VI-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
; VI-NEXT: v_sub_u32_e32 v10, vcc, v13, v14
; VI-NEXT: v_add_u32_e32 v10, vcc, 12, v10
-; VI-NEXT: .LBB12_6: ; %frem.loop_body85
+; VI-NEXT: .LBB12_5: ; %frem.loop_body85
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v13, v11
; VI-NEXT: v_mul_f32_e32 v11, v13, v12
@@ -14146,10 +13995,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v10, vcc, -12, v10
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v10
; VI-NEXT: v_ldexp_f32 v11, v11, 12
-; VI-NEXT: s_cbranch_vccnz .LBB12_6
-; VI-NEXT: ; %bb.7: ; %Flow125
+; VI-NEXT: s_cbranch_vccnz .LBB12_5
+; VI-NEXT: ; %bb.6: ; %Flow125
; VI-NEXT: v_mov_b32_e32 v11, v13
-; VI-NEXT: .LBB12_8: ; %frem.loop_exit86
+; VI-NEXT: .LBB12_7: ; %frem.loop_exit86
; VI-NEXT: v_add_u32_e32 v10, vcc, -11, v10
; VI-NEXT: v_ldexp_f32 v10, v11, v10
; VI-NEXT: v_mul_f32_e32 v11, v10, v12
@@ -14161,25 +14010,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v8, v9, v8
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v8, s2, v8, v0
-; VI-NEXT: .LBB12_9:
+; VI-NEXT: .LBB12_8:
; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB12_11
-; VI-NEXT: ; %bb.10: ; %frem.else47
+; VI-NEXT: s_cbranch_vccz .LBB12_10
+; VI-NEXT: ; %bb.9: ; %frem.else47
; VI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
; VI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB12_12
-; VI-NEXT: .LBB12_11:
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB12_11
+; VI-NEXT: s_branch .LBB12_16
+; VI-NEXT: .LBB12_10:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr9
-; VI-NEXT: .LBB12_12: ; %Flow123
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB12_18
-; VI-NEXT: ; %bb.13: ; %frem.compute46
+; VI-NEXT: s_cbranch_scc0 .LBB12_16
+; VI-NEXT: .LBB12_11: ; %frem.compute46
; VI-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; VI-NEXT: v_ldexp_f32 v10, v10, 1
; VI-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
@@ -14203,11 +14051,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v13, v13, v17, v18
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v11
; VI-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_17
-; VI-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB12_15
+; VI-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
; VI-NEXT: v_sub_u32_e32 v11, vcc, v14, v15
; VI-NEXT: v_add_u32_e32 v11, vcc, 12, v11
-; VI-NEXT: .LBB12_15: ; %frem.loop_body54
+; VI-NEXT: .LBB12_13: ; %frem.loop_body54
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v14, v12
; VI-NEXT: v_mul_f32_e32 v12, v14, v13
@@ -14219,10 +14067,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v11, vcc, -12, v11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v11
; VI-NEXT: v_ldexp_f32 v12, v12, 12
-; VI-NEXT: s_cbranch_vccnz .LBB12_15
-; VI-NEXT: ; %bb.16: ; %Flow121
+; VI-NEXT: s_cbranch_vccnz .LBB12_13
+; VI-NEXT: ; %bb.14: ; %Flow121
; VI-NEXT: v_mov_b32_e32 v12, v14
-; VI-NEXT: .LBB12_17: ; %frem.loop_exit55
+; VI-NEXT: .LBB12_15: ; %frem.loop_exit55
; VI-NEXT: v_add_u32_e32 v11, vcc, -11, v11
; VI-NEXT: v_ldexp_f32 v11, v12, v11
; VI-NEXT: v_mul_f32_e32 v12, v11, v13
@@ -14234,25 +14082,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v9, v10, v9
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; VI-NEXT: .LBB12_18:
+; VI-NEXT: .LBB12_16:
; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB12_20
-; VI-NEXT: ; %bb.19: ; %frem.else16
+; VI-NEXT: s_cbranch_vccz .LBB12_18
+; VI-NEXT: ; %bb.17: ; %frem.else16
; VI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
; VI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB12_21
-; VI-NEXT: .LBB12_20:
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB12_19
+; VI-NEXT: s_branch .LBB12_24
+; VI-NEXT: .LBB12_18:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr10
-; VI-NEXT: .LBB12_21: ; %Flow119
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB12_27
-; VI-NEXT: ; %bb.22: ; %frem.compute15
+; VI-NEXT: s_cbranch_scc0 .LBB12_24
+; VI-NEXT: .LBB12_19: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; VI-NEXT: v_ldexp_f32 v11, v11, 1
; VI-NEXT: v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
@@ -14276,11 +14123,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v14, v14, v18, v19
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v12
; VI-NEXT: v_div_fixup_f32 v14, v14, v11, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_26
-; VI-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB12_23
+; VI-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
; VI-NEXT: v_sub_u32_e32 v12, vcc, v15, v16
; VI-NEXT: v_add_u32_e32 v12, vcc, 12, v12
-; VI-NEXT: .LBB12_24: ; %frem.loop_body23
+; VI-NEXT: .LBB12_21: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v15, v13
; VI-NEXT: v_mul_f32_e32 v13, v15, v14
@@ -14292,10 +14139,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v12, vcc, -12, v12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v12
; VI-NEXT: v_ldexp_f32 v13, v13, 12
-; VI-NEXT: s_cbranch_vccnz .LBB12_24
-; VI-NEXT: ; %bb.25: ; %Flow117
+; VI-NEXT: s_cbranch_vccnz .LBB12_21
+; VI-NEXT: ; %bb.22: ; %Flow117
; VI-NEXT: v_mov_b32_e32 v13, v15
-; VI-NEXT: .LBB12_26: ; %frem.loop_exit24
+; VI-NEXT: .LBB12_23: ; %frem.loop_exit24
; VI-NEXT: v_add_u32_e32 v12, vcc, -11, v12
; VI-NEXT: v_ldexp_f32 v12, v13, v12
; VI-NEXT: v_mul_f32_e32 v13, v12, v14
@@ -14307,25 +14154,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v10, v11, v10
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v10, s2, v10, v2
-; VI-NEXT: .LBB12_27:
+; VI-NEXT: .LBB12_24:
; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB12_29
-; VI-NEXT: ; %bb.28: ; %frem.else
+; VI-NEXT: s_cbranch_vccz .LBB12_26
+; VI-NEXT: ; %bb.25: ; %frem.else
; VI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
; VI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_branch .LBB12_30
-; VI-NEXT: .LBB12_29:
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB12_27
+; VI-NEXT: s_branch .LBB12_32
+; VI-NEXT: .LBB12_26:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr11
-; VI-NEXT: .LBB12_30: ; %Flow115
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB12_36
-; VI-NEXT: ; %bb.31: ; %frem.compute
+; VI-NEXT: s_cbranch_scc0 .LBB12_32
+; VI-NEXT: .LBB12_27: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; VI-NEXT: v_ldexp_f32 v12, v12, 1
; VI-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
@@ -14349,11 +14195,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f32 v15, v15, v19, v20
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v13
; VI-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_35
-; VI-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB12_31
+; VI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v13, vcc, v16, v17
; VI-NEXT: v_add_u32_e32 v13, vcc, 12, v13
-; VI-NEXT: .LBB12_33: ; %frem.loop_body
+; VI-NEXT: .LBB12_29: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v16, v14
; VI-NEXT: v_mul_f32_e32 v14, v16, v15
@@ -14365,10 +14211,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_add_u32_e32 v13, vcc, -12, v13
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v13
; VI-NEXT: v_ldexp_f32 v14, v14, 12
-; VI-NEXT: s_cbranch_vccnz .LBB12_33
-; VI-NEXT: ; %bb.34: ; %Flow
+; VI-NEXT: s_cbranch_vccnz .LBB12_29
+; VI-NEXT: ; %bb.30: ; %Flow
; VI-NEXT: v_mov_b32_e32 v14, v16
-; VI-NEXT: .LBB12_35: ; %frem.loop_exit
+; VI-NEXT: .LBB12_31: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v13, vcc, -11, v13
; VI-NEXT: v_ldexp_f32 v13, v14, v13
; VI-NEXT: v_mul_f32_e32 v14, v13, v15
@@ -14380,7 +14226,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v11, v12, v11
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; VI-NEXT: .LBB12_36: ; %Flow116
+; VI-NEXT: .LBB12_32: ; %Flow116
; VI-NEXT: s_mov_b32 s4, 0x7f800000
; VI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -14421,16 +14267,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
; GFX9-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB12_3
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB12_3
+; GFX9-NEXT: s_branch .LBB12_8
; GFX9-NEXT: .LBB12_2:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr8
-; GFX9-NEXT: .LBB12_3: ; %Flow127
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB12_9
-; GFX9-NEXT: ; %bb.4: ; %frem.compute77
+; GFX9-NEXT: s_cbranch_scc0 .LBB12_8
+; GFX9-NEXT: .LBB12_3: ; %frem.compute77
; GFX9-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; GFX9-NEXT: v_ldexp_f32 v9, v9, 1
; GFX9-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
@@ -14454,11 +14299,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v12, v12, v16, v17
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v10
; GFX9-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_8
-; GFX9-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_7
+; GFX9-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
; GFX9-NEXT: v_sub_u32_e32 v10, v13, v14
; GFX9-NEXT: v_add_u32_e32 v10, 12, v10
-; GFX9-NEXT: .LBB12_6: ; %frem.loop_body85
+; GFX9-NEXT: .LBB12_5: ; %frem.loop_body85
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v13, v11
; GFX9-NEXT: v_mul_f32_e32 v11, v13, v12
@@ -14470,10 +14315,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v10
; GFX9-NEXT: v_ldexp_f32 v11, v11, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_6
-; GFX9-NEXT: ; %bb.7: ; %Flow125
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_5
+; GFX9-NEXT: ; %bb.6: ; %Flow125
; GFX9-NEXT: v_mov_b32_e32 v11, v13
-; GFX9-NEXT: .LBB12_8: ; %frem.loop_exit86
+; GFX9-NEXT: .LBB12_7: ; %frem.loop_exit86
; GFX9-NEXT: v_add_u32_e32 v10, -11, v10
; GFX9-NEXT: v_ldexp_f32 v10, v11, v10
; GFX9-NEXT: v_mul_f32_e32 v11, v10, v12
@@ -14485,25 +14330,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v8, v9, v8
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v8, s2, v8, v0
-; GFX9-NEXT: .LBB12_9:
+; GFX9-NEXT: .LBB12_8:
; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB12_11
-; GFX9-NEXT: ; %bb.10: ; %frem.else47
+; GFX9-NEXT: s_cbranch_vccz .LBB12_10
+; GFX9-NEXT: ; %bb.9: ; %frem.else47
; GFX9-NEXT: v_and_b32_e32 v9, 0x80000000, v1
; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB12_12
-; GFX9-NEXT: .LBB12_11:
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB12_11
+; GFX9-NEXT: s_branch .LBB12_16
+; GFX9-NEXT: .LBB12_10:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr9
-; GFX9-NEXT: .LBB12_12: ; %Flow123
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB12_18
-; GFX9-NEXT: ; %bb.13: ; %frem.compute46
+; GFX9-NEXT: s_cbranch_scc0 .LBB12_16
+; GFX9-NEXT: .LBB12_11: ; %frem.compute46
; GFX9-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; GFX9-NEXT: v_ldexp_f32 v10, v10, 1
; GFX9-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
@@ -14527,11 +14371,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v13, v13, v17, v18
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v11
; GFX9-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_17
-; GFX9-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_15
+; GFX9-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
; GFX9-NEXT: v_sub_u32_e32 v11, v14, v15
; GFX9-NEXT: v_add_u32_e32 v11, 12, v11
-; GFX9-NEXT: .LBB12_15: ; %frem.loop_body54
+; GFX9-NEXT: .LBB12_13: ; %frem.loop_body54
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v14, v12
; GFX9-NEXT: v_mul_f32_e32 v12, v14, v13
@@ -14543,10 +14387,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v11
; GFX9-NEXT: v_ldexp_f32 v12, v12, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_15
-; GFX9-NEXT: ; %bb.16: ; %Flow121
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_13
+; GFX9-NEXT: ; %bb.14: ; %Flow121
; GFX9-NEXT: v_mov_b32_e32 v12, v14
-; GFX9-NEXT: .LBB12_17: ; %frem.loop_exit55
+; GFX9-NEXT: .LBB12_15: ; %frem.loop_exit55
; GFX9-NEXT: v_add_u32_e32 v11, -11, v11
; GFX9-NEXT: v_ldexp_f32 v11, v12, v11
; GFX9-NEXT: v_mul_f32_e32 v12, v11, v13
@@ -14558,25 +14402,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v9, v10, v9
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v9, s2, v9, v1
-; GFX9-NEXT: .LBB12_18:
+; GFX9-NEXT: .LBB12_16:
; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB12_20
-; GFX9-NEXT: ; %bb.19: ; %frem.else16
+; GFX9-NEXT: s_cbranch_vccz .LBB12_18
+; GFX9-NEXT: ; %bb.17: ; %frem.else16
; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2
; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
; GFX9-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB12_21
-; GFX9-NEXT: .LBB12_20:
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB12_19
+; GFX9-NEXT: s_branch .LBB12_24
+; GFX9-NEXT: .LBB12_18:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr10
-; GFX9-NEXT: .LBB12_21: ; %Flow119
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB12_27
-; GFX9-NEXT: ; %bb.22: ; %frem.compute15
+; GFX9-NEXT: s_cbranch_scc0 .LBB12_24
+; GFX9-NEXT: .LBB12_19: ; %frem.compute15
; GFX9-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; GFX9-NEXT: v_ldexp_f32 v11, v11, 1
; GFX9-NEXT: v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
@@ -14600,11 +14443,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v14, v14, v18, v19
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v12
; GFX9-NEXT: v_div_fixup_f32 v14, v14, v11, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_26
-; GFX9-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_23
+; GFX9-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
; GFX9-NEXT: v_sub_u32_e32 v12, v15, v16
; GFX9-NEXT: v_add_u32_e32 v12, 12, v12
-; GFX9-NEXT: .LBB12_24: ; %frem.loop_body23
+; GFX9-NEXT: .LBB12_21: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v15, v13
; GFX9-NEXT: v_mul_f32_e32 v13, v15, v14
@@ -14616,10 +14459,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v12
; GFX9-NEXT: v_ldexp_f32 v13, v13, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_24
-; GFX9-NEXT: ; %bb.25: ; %Flow117
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_21
+; GFX9-NEXT: ; %bb.22: ; %Flow117
; GFX9-NEXT: v_mov_b32_e32 v13, v15
-; GFX9-NEXT: .LBB12_26: ; %frem.loop_exit24
+; GFX9-NEXT: .LBB12_23: ; %frem.loop_exit24
; GFX9-NEXT: v_add_u32_e32 v12, -11, v12
; GFX9-NEXT: v_ldexp_f32 v12, v13, v12
; GFX9-NEXT: v_mul_f32_e32 v13, v12, v14
@@ -14631,25 +14474,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v10, v11, v10
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v10, s2, v10, v2
-; GFX9-NEXT: .LBB12_27:
+; GFX9-NEXT: .LBB12_24:
; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB12_29
-; GFX9-NEXT: ; %bb.28: ; %frem.else
+; GFX9-NEXT: s_cbranch_vccz .LBB12_26
+; GFX9-NEXT: ; %bb.25: ; %frem.else
; GFX9-NEXT: v_and_b32_e32 v11, 0x80000000, v3
; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_branch .LBB12_30
-; GFX9-NEXT: .LBB12_29:
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB12_27
+; GFX9-NEXT: s_branch .LBB12_32
+; GFX9-NEXT: .LBB12_26:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr11
-; GFX9-NEXT: .LBB12_30: ; %Flow115
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB12_36
-; GFX9-NEXT: ; %bb.31: ; %frem.compute
+; GFX9-NEXT: s_cbranch_scc0 .LBB12_32
+; GFX9-NEXT: .LBB12_27: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; GFX9-NEXT: v_ldexp_f32 v12, v12, 1
; GFX9-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
@@ -14673,11 +14515,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f32 v15, v15, v19, v20
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v13
; GFX9-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_35
-; GFX9-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_31
+; GFX9-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v13, v16, v17
; GFX9-NEXT: v_add_u32_e32 v13, 12, v13
-; GFX9-NEXT: .LBB12_33: ; %frem.loop_body
+; GFX9-NEXT: .LBB12_29: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v16, v14
; GFX9-NEXT: v_mul_f32_e32 v14, v16, v15
@@ -14689,10 +14531,10 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v13
; GFX9-NEXT: v_ldexp_f32 v14, v14, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_33
-; GFX9-NEXT: ; %bb.34: ; %Flow
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_29
+; GFX9-NEXT: ; %bb.30: ; %Flow
; GFX9-NEXT: v_mov_b32_e32 v14, v16
-; GFX9-NEXT: .LBB12_35: ; %frem.loop_exit
+; GFX9-NEXT: .LBB12_31: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v13, -11, v13
; GFX9-NEXT: v_ldexp_f32 v13, v14, v13
; GFX9-NEXT: v_mul_f32_e32 v14, v13, v15
@@ -14704,7 +14546,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v11, v12, v11
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v11, s2, v11, v3
-; GFX9-NEXT: .LBB12_36: ; %Flow116
+; GFX9-NEXT: .LBB12_32: ; %Flow116
; GFX9-NEXT: s_mov_b32 s4, 0x7f800000
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; GFX9-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -14746,16 +14588,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc_lo
-; GFX10-NEXT: s_branch .LBB12_3
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_3
+; GFX10-NEXT: s_branch .LBB12_8
; GFX10-NEXT: .LBB12_2:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr8
-; GFX10-NEXT: .LBB12_3: ; %Flow127
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_9
-; GFX10-NEXT: ; %bb.4: ; %frem.compute77
+; GFX10-NEXT: s_cbranch_scc0 .LBB12_8
+; GFX10-NEXT: .LBB12_3: ; %frem.compute77
; GFX10-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; GFX10-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v11, v0
@@ -14781,11 +14622,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v11, v11, v14, v15
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v12
; GFX10-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_8
-; GFX10-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_7
+; GFX10-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_6: ; %frem.loop_body85
+; GFX10-NEXT: .LBB12_5: ; %frem.loop_body85
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v13, v10
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -14797,11 +14638,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v12, v10, v9
; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v10, v10, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_6
-; GFX10-NEXT: ; %bb.7: ; %Flow125
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_5
+; GFX10-NEXT: ; %bb.6: ; %Flow125
; GFX10-NEXT: v_mov_b32_e32 v12, s2
; GFX10-NEXT: v_mov_b32_e32 v10, v13
-; GFX10-NEXT: .LBB12_8: ; %frem.loop_exit86
+; GFX10-NEXT: .LBB12_7: ; %frem.loop_exit86
; GFX10-NEXT: v_add_nc_u32_e32 v12, -11, v12
; GFX10-NEXT: v_ldexp_f32 v10, v10, v12
; GFX10-NEXT: v_mul_f32_e32 v11, v10, v11
@@ -14812,25 +14653,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v8, v9, v8
; GFX10-NEXT: v_bfi_b32 v8, 0x7fffffff, v8, v0
-; GFX10-NEXT: .LBB12_9:
+; GFX10-NEXT: .LBB12_8:
; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v5|
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB12_11
-; GFX10-NEXT: ; %bb.10: ; %frem.else47
+; GFX10-NEXT: s_cbranch_vccz .LBB12_10
+; GFX10-NEXT: ; %bb.9: ; %frem.else47
; GFX10-NEXT: v_and_b32_e32 v9, 0x80000000, v1
; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc_lo
-; GFX10-NEXT: s_branch .LBB12_12
-; GFX10-NEXT: .LBB12_11:
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_11
+; GFX10-NEXT: s_branch .LBB12_16
+; GFX10-NEXT: .LBB12_10:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr9
-; GFX10-NEXT: .LBB12_12: ; %Flow123
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_18
-; GFX10-NEXT: ; %bb.13: ; %frem.compute46
+; GFX10-NEXT: s_cbranch_scc0 .LBB12_16
+; GFX10-NEXT: .LBB12_11: ; %frem.compute46
; GFX10-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; GFX10-NEXT: v_frexp_mant_f32_e64 v9, |v1|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v12, v1
@@ -14856,11 +14696,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v12, v12, v15, v16
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v13
; GFX10-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_17
-; GFX10-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_15
+; GFX10-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_15: ; %frem.loop_body54
+; GFX10-NEXT: .LBB12_13: ; %frem.loop_body54
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v14, v11
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -14872,11 +14712,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v13, v11, v10
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v11, v11, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_15
-; GFX10-NEXT: ; %bb.16: ; %Flow121
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_13
+; GFX10-NEXT: ; %bb.14: ; %Flow121
; GFX10-NEXT: v_mov_b32_e32 v13, s2
; GFX10-NEXT: v_mov_b32_e32 v11, v14
-; GFX10-NEXT: .LBB12_17: ; %frem.loop_exit55
+; GFX10-NEXT: .LBB12_15: ; %frem.loop_exit55
; GFX10-NEXT: v_add_nc_u32_e32 v13, -11, v13
; GFX10-NEXT: v_ldexp_f32 v11, v11, v13
; GFX10-NEXT: v_mul_f32_e32 v12, v11, v12
@@ -14887,25 +14727,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v9, v10, v9
; GFX10-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX10-NEXT: .LBB12_18:
+; GFX10-NEXT: .LBB12_16:
; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v2|, |v6|
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB12_20
-; GFX10-NEXT: ; %bb.19: ; %frem.else16
+; GFX10-NEXT: s_cbranch_vccz .LBB12_18
+; GFX10-NEXT: ; %bb.17: ; %frem.else16
; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v2
; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc_lo
-; GFX10-NEXT: s_branch .LBB12_21
-; GFX10-NEXT: .LBB12_20:
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_19
+; GFX10-NEXT: s_branch .LBB12_24
+; GFX10-NEXT: .LBB12_18:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr10
-; GFX10-NEXT: .LBB12_21: ; %Flow119
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_27
-; GFX10-NEXT: ; %bb.22: ; %frem.compute15
+; GFX10-NEXT: s_cbranch_scc0 .LBB12_24
+; GFX10-NEXT: .LBB12_19: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; GFX10-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v13, v2
@@ -14931,11 +14770,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v13, v13, v16, v17
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v14
; GFX10-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_26
-; GFX10-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_23
+; GFX10-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_24: ; %frem.loop_body23
+; GFX10-NEXT: .LBB12_21: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v15, v12
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -14947,11 +14786,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v14, v12, v11
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v12, v12, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_24
-; GFX10-NEXT: ; %bb.25: ; %Flow117
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_21
+; GFX10-NEXT: ; %bb.22: ; %Flow117
; GFX10-NEXT: v_mov_b32_e32 v14, s2
; GFX10-NEXT: v_mov_b32_e32 v12, v15
-; GFX10-NEXT: .LBB12_26: ; %frem.loop_exit24
+; GFX10-NEXT: .LBB12_23: ; %frem.loop_exit24
; GFX10-NEXT: v_add_nc_u32_e32 v14, -11, v14
; GFX10-NEXT: v_ldexp_f32 v12, v12, v14
; GFX10-NEXT: v_mul_f32_e32 v13, v12, v13
@@ -14962,25 +14801,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v11, v12, v11, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v10, v11, v10
; GFX10-NEXT: v_bfi_b32 v10, 0x7fffffff, v10, v2
-; GFX10-NEXT: .LBB12_27:
+; GFX10-NEXT: .LBB12_24:
; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v3|, |v7|
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB12_29
-; GFX10-NEXT: ; %bb.28: ; %frem.else
+; GFX10-NEXT: s_cbranch_vccz .LBB12_26
+; GFX10-NEXT: ; %bb.25: ; %frem.else
; GFX10-NEXT: v_and_b32_e32 v11, 0x80000000, v3
; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc_lo
-; GFX10-NEXT: s_branch .LBB12_30
-; GFX10-NEXT: .LBB12_29:
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_27
+; GFX10-NEXT: s_branch .LBB12_32
+; GFX10-NEXT: .LBB12_26:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr11
-; GFX10-NEXT: .LBB12_30: ; %Flow115
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_36
-; GFX10-NEXT: ; %bb.31: ; %frem.compute
+; GFX10-NEXT: s_cbranch_scc0 .LBB12_32
+; GFX10-NEXT: .LBB12_27: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; GFX10-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v14, v3
@@ -15006,11 +14844,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v14, v14, v17, v18
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v15
; GFX10-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_35
-; GFX10-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_31
+; GFX10-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_33: ; %frem.loop_body
+; GFX10-NEXT: .LBB12_29: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v16, v13
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -15022,11 +14860,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v15, v13, v12
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v13, v13, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_33
-; GFX10-NEXT: ; %bb.34: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_29
+; GFX10-NEXT: ; %bb.30: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v15, s2
; GFX10-NEXT: v_mov_b32_e32 v13, v16
-; GFX10-NEXT: .LBB12_35: ; %frem.loop_exit
+; GFX10-NEXT: .LBB12_31: ; %frem.loop_exit
; GFX10-NEXT: v_add_nc_u32_e32 v15, -11, v15
; GFX10-NEXT: v_ldexp_f32 v13, v13, v15
; GFX10-NEXT: v_mul_f32_e32 v14, v13, v14
@@ -15037,7 +14875,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v11, v12, v11
; GFX10-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX10-NEXT: .LBB12_36: ; %Flow116
+; GFX10-NEXT: .LBB12_32: ; %Flow116
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX10-NEXT: v_mov_b32_e32 v4, 0
@@ -15077,17 +14915,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc_lo
-; GFX11-NEXT: s_branch .LBB12_3
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_3
+; GFX11-NEXT: s_branch .LBB12_8
; GFX11-NEXT: .LBB12_2:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr8
-; GFX11-NEXT: .LBB12_3: ; %Flow127
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_9
-; GFX11-NEXT: ; %bb.4: ; %frem.compute77
+; GFX11-NEXT: s_cbranch_scc0 .LBB12_8
+; GFX11-NEXT: .LBB12_3: ; %frem.compute77
; GFX11-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; GFX11-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v11, v0
@@ -15122,12 +14959,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_8
-; GFX11-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_7
+; GFX11-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_6: ; %frem.loop_body85
+; GFX11-NEXT: .LBB12_5: ; %frem.loop_body85
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v13, v10
@@ -15143,11 +14980,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v10, v10, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_6
-; GFX11-NEXT: ; %bb.7: ; %Flow125
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_5
+; GFX11-NEXT: ; %bb.6: ; %Flow125
; GFX11-NEXT: v_mov_b32_e32 v12, s2
; GFX11-NEXT: v_mov_b32_e32 v10, v13
-; GFX11-NEXT: .LBB12_8: ; %frem.loop_exit86
+; GFX11-NEXT: .LBB12_7: ; %frem.loop_exit86
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_nc_u32_e32 v12, -11, v12
; GFX11-NEXT: v_ldexp_f32 v10, v10, v12
@@ -15163,26 +15000,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v8, v9, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v8, 0x7fffffff, v8, v0
-; GFX11-NEXT: .LBB12_9:
+; GFX11-NEXT: .LBB12_8:
; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v5|
; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB12_11
-; GFX11-NEXT: ; %bb.10: ; %frem.else47
+; GFX11-NEXT: s_cbranch_vccz .LBB12_10
+; GFX11-NEXT: ; %bb.9: ; %frem.else47
; GFX11-NEXT: v_and_b32_e32 v9, 0x80000000, v1
; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc_lo
-; GFX11-NEXT: s_branch .LBB12_12
-; GFX11-NEXT: .LBB12_11:
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_11
+; GFX11-NEXT: s_branch .LBB12_16
+; GFX11-NEXT: .LBB12_10:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr9
-; GFX11-NEXT: .LBB12_12: ; %Flow123
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_18
-; GFX11-NEXT: ; %bb.13: ; %frem.compute46
+; GFX11-NEXT: s_cbranch_scc0 .LBB12_16
+; GFX11-NEXT: .LBB12_11: ; %frem.compute46
; GFX11-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; GFX11-NEXT: v_frexp_mant_f32_e64 v9, |v1|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v12, v1
@@ -15217,12 +15053,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_17
-; GFX11-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_15
+; GFX11-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_15: ; %frem.loop_body54
+; GFX11-NEXT: .LBB12_13: ; %frem.loop_body54
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v14, v11
@@ -15238,11 +15074,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v11, v11, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_15
-; GFX11-NEXT: ; %bb.16: ; %Flow121
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_13
+; GFX11-NEXT: ; %bb.14: ; %Flow121
; GFX11-NEXT: v_mov_b32_e32 v13, s2
; GFX11-NEXT: v_mov_b32_e32 v11, v14
-; GFX11-NEXT: .LBB12_17: ; %frem.loop_exit55
+; GFX11-NEXT: .LBB12_15: ; %frem.loop_exit55
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_nc_u32_e32 v13, -11, v13
; GFX11-NEXT: v_ldexp_f32 v11, v11, v13
@@ -15258,26 +15094,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v9, v10, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX11-NEXT: .LBB12_18:
+; GFX11-NEXT: .LBB12_16:
; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v2|, |v6|
; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB12_20
-; GFX11-NEXT: ; %bb.19: ; %frem.else16
+; GFX11-NEXT: s_cbranch_vccz .LBB12_18
+; GFX11-NEXT: ; %bb.17: ; %frem.else16
; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v2
; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc_lo
-; GFX11-NEXT: s_branch .LBB12_21
-; GFX11-NEXT: .LBB12_20:
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_19
+; GFX11-NEXT: s_branch .LBB12_24
+; GFX11-NEXT: .LBB12_18:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr10
-; GFX11-NEXT: .LBB12_21: ; %Flow119
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_27
-; GFX11-NEXT: ; %bb.22: ; %frem.compute15
+; GFX11-NEXT: s_cbranch_scc0 .LBB12_24
+; GFX11-NEXT: .LBB12_19: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; GFX11-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v13, v2
@@ -15312,12 +15147,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_26
-; GFX11-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_23
+; GFX11-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_24: ; %frem.loop_body23
+; GFX11-NEXT: .LBB12_21: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v15, v12
@@ -15333,11 +15168,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v12, v12, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_24
-; GFX11-NEXT: ; %bb.25: ; %Flow117
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_21
+; GFX11-NEXT: ; %bb.22: ; %Flow117
; GFX11-NEXT: v_mov_b32_e32 v14, s2
; GFX11-NEXT: v_mov_b32_e32 v12, v15
-; GFX11-NEXT: .LBB12_26: ; %frem.loop_exit24
+; GFX11-NEXT: .LBB12_23: ; %frem.loop_exit24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_nc_u32_e32 v14, -11, v14
; GFX11-NEXT: v_ldexp_f32 v12, v12, v14
@@ -15353,26 +15188,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v10, v11, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v10, 0x7fffffff, v10, v2
-; GFX11-NEXT: .LBB12_27:
+; GFX11-NEXT: .LBB12_24:
; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v3|, |v7|
; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB12_29
-; GFX11-NEXT: ; %bb.28: ; %frem.else
+; GFX11-NEXT: s_cbranch_vccz .LBB12_26
+; GFX11-NEXT: ; %bb.25: ; %frem.else
; GFX11-NEXT: v_and_b32_e32 v11, 0x80000000, v3
; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc_lo
-; GFX11-NEXT: s_branch .LBB12_30
-; GFX11-NEXT: .LBB12_29:
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_27
+; GFX11-NEXT: s_branch .LBB12_32
+; GFX11-NEXT: .LBB12_26:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr11
-; GFX11-NEXT: .LBB12_30: ; %Flow115
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_36
-; GFX11-NEXT: ; %bb.31: ; %frem.compute
+; GFX11-NEXT: s_cbranch_scc0 .LBB12_32
+; GFX11-NEXT: .LBB12_27: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; GFX11-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v14, v3
@@ -15407,12 +15241,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v15
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_35
-; GFX11-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_31
+; GFX11-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_33: ; %frem.loop_body
+; GFX11-NEXT: .LBB12_29: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v16, v13
@@ -15428,11 +15262,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v13, v13, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_33
-; GFX11-NEXT: ; %bb.34: ; %Flow
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_29
+; GFX11-NEXT: ; %bb.30: ; %Flow
; GFX11-NEXT: v_mov_b32_e32 v15, s2
; GFX11-NEXT: v_mov_b32_e32 v13, v16
-; GFX11-NEXT: .LBB12_35: ; %frem.loop_exit
+; GFX11-NEXT: .LBB12_31: ; %frem.loop_exit
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_nc_u32_e32 v15, -11, v15
; GFX11-NEXT: v_ldexp_f32 v13, v13, v15
@@ -15448,7 +15282,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v11, v12, v11
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX11-NEXT: .LBB12_36: ; %Flow116
+; GFX11-NEXT: .LBB12_32: ; %Flow116
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX11-NEXT: v_mov_b32_e32 v4, 0
@@ -15501,17 +15335,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB12_3
+; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_3
+; GFX1150-NEXT: s_branch .LBB12_8
; GFX1150-NEXT: .LBB12_2:
; GFX1150-NEXT: s_mov_b32 s11, -1
; GFX1150-NEXT: ; implicit-def: $vgpr0
-; GFX1150-NEXT: .LBB12_3: ; %Flow127
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_9
-; GFX1150-NEXT: ; %bb.4: ; %frem.compute77
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_8
+; GFX1150-NEXT: .LBB12_3: ; %frem.compute77
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s6|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v0, |s8|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
@@ -15545,12 +15378,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1150-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_8
-; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_7
+; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_6: ; %frem.loop_body85
+; GFX1150-NEXT: .LBB12_5: ; %frem.loop_body85
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v5, v2
@@ -15568,11 +15401,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v2, v2, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_6
-; GFX1150-NEXT: ; %bb.7: ; %Flow125
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_5
+; GFX1150-NEXT: ; %bb.6: ; %Flow125
; GFX1150-NEXT: v_mov_b32_e32 v4, s11
; GFX1150-NEXT: v_mov_b32_e32 v2, v5
-; GFX1150-NEXT: .LBB12_8: ; %frem.loop_exit86
+; GFX1150-NEXT: .LBB12_7: ; %frem.loop_exit86
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_add_nc_u32_e32 v4, -11, v4
; GFX1150-NEXT: v_ldexp_f32 v2, v2, v4
@@ -15589,13 +15422,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1150-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s8
-; GFX1150-NEXT: .LBB12_9:
+; GFX1150-NEXT: .LBB12_8:
; GFX1150-NEXT: s_and_b32 s8, s10, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s11, s4, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_cmp_ngt_f32 s8, s11
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_11
-; GFX1150-NEXT: ; %bb.10: ; %frem.else47
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_10
+; GFX1150-NEXT: ; %bb.9: ; %frem.else47
; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s10
; GFX1150-NEXT: s_cmp_eq_f32 s8, s11
; GFX1150-NEXT: v_mov_b32_e32 v1, s12
@@ -15603,17 +15436,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v1, s10, v1, vcc_lo
-; GFX1150-NEXT: s_branch .LBB12_12
-; GFX1150-NEXT: .LBB12_11:
+; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_11
+; GFX1150-NEXT: s_branch .LBB12_16
+; GFX1150-NEXT: .LBB12_10:
; GFX1150-NEXT: s_mov_b32 s11, -1
; GFX1150-NEXT: ; implicit-def: $vgpr1
-; GFX1150-NEXT: .LBB12_12: ; %Flow123
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_18
-; GFX1150-NEXT: ; %bb.13: ; %frem.compute46
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_16
+; GFX1150-NEXT: .LBB12_11: ; %frem.compute46
; GFX1150-NEXT: v_frexp_mant_f32_e64 v2, |s4|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s10|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
@@ -15647,12 +15479,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1150-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_17
-; GFX1150-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_15
+; GFX1150-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_15: ; %frem.loop_body54
+; GFX1150-NEXT: .LBB12_13: ; %frem.loop_body54
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v6, v3
@@ -15670,11 +15502,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_15
-; GFX1150-NEXT: ; %bb.16: ; %Flow121
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_13
+; GFX1150-NEXT: ; %bb.14: ; %Flow121
; GFX1150-NEXT: v_mov_b32_e32 v5, s11
; GFX1150-NEXT: v_mov_b32_e32 v3, v6
-; GFX1150-NEXT: .LBB12_17: ; %frem.loop_exit55
+; GFX1150-NEXT: .LBB12_15: ; %frem.loop_exit55
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_add_nc_u32_e32 v5, -11, v5
; GFX1150-NEXT: v_ldexp_f32 v3, v3, v5
@@ -15691,13 +15523,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1150-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s10
-; GFX1150-NEXT: .LBB12_18:
+; GFX1150-NEXT: .LBB12_16:
; GFX1150-NEXT: s_and_b32 s10, s9, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s11, s3, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_cmp_ngt_f32 s10, s11
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_20
-; GFX1150-NEXT: ; %bb.19: ; %frem.else16
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_18
+; GFX1150-NEXT: ; %bb.17: ; %frem.else16
; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s9
; GFX1150-NEXT: s_cmp_eq_f32 s10, s11
; GFX1150-NEXT: v_mov_b32_e32 v2, s12
@@ -15705,17 +15537,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v2, s9, v2, vcc_lo
-; GFX1150-NEXT: s_branch .LBB12_21
-; GFX1150-NEXT: .LBB12_20:
+; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_19
+; GFX1150-NEXT: s_branch .LBB12_24
+; GFX1150-NEXT: .LBB12_18:
; GFX1150-NEXT: s_mov_b32 s11, -1
; GFX1150-NEXT: ; implicit-def: $vgpr2
-; GFX1150-NEXT: .LBB12_21: ; %Flow119
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_27
-; GFX1150-NEXT: ; %bb.22: ; %frem.compute15
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_24
+; GFX1150-NEXT: .LBB12_19: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f32_e64 v3, |s3|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v2, |s9|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
@@ -15749,12 +15580,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX1150-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_26
-; GFX1150-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_23
+; GFX1150-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_24: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB12_21: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v7, v4
@@ -15772,11 +15603,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_24
-; GFX1150-NEXT: ; %bb.25: ; %Flow117
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_21
+; GFX1150-NEXT: ; %bb.22: ; %Flow117
; GFX1150-NEXT: v_mov_b32_e32 v6, s11
; GFX1150-NEXT: v_mov_b32_e32 v4, v7
-; GFX1150-NEXT: .LBB12_26: ; %frem.loop_exit24
+; GFX1150-NEXT: .LBB12_23: ; %frem.loop_exit24
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_add_nc_u32_e32 v6, -11, v6
; GFX1150-NEXT: v_ldexp_f32 v4, v4, v6
@@ -15793,13 +15624,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v2, v3, v2
; GFX1150-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s9
-; GFX1150-NEXT: .LBB12_27:
+; GFX1150-NEXT: .LBB12_24:
; GFX1150-NEXT: s_and_b32 s9, s7, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s11, s2, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_cmp_ngt_f32 s9, s11
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_29
-; GFX1150-NEXT: ; %bb.28: ; %frem.else
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_26
+; GFX1150-NEXT: ; %bb.25: ; %frem.else
; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s7
; GFX1150-NEXT: s_cmp_eq_f32 s9, s11
; GFX1150-NEXT: v_mov_b32_e32 v3, s12
@@ -15807,17 +15638,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v3, s7, v3, vcc_lo
-; GFX1150-NEXT: s_branch .LBB12_30
-; GFX1150-NEXT: .LBB12_29:
+; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_27
+; GFX1150-NEXT: s_branch .LBB12_32
+; GFX1150-NEXT: .LBB12_26:
; GFX1150-NEXT: s_mov_b32 s11, -1
; GFX1150-NEXT: ; implicit-def: $vgpr3
-; GFX1150-NEXT: .LBB12_30: ; %Flow115
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s11, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_36
-; GFX1150-NEXT: ; %bb.31: ; %frem.compute
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_32
+; GFX1150-NEXT: .LBB12_27: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f32_e64 v4, |s2|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v3, |s7|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v6, s7
@@ -15851,12 +15681,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1150-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_35
-; GFX1150-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_31
+; GFX1150-NEXT: ; %bb.28: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_33: ; %frem.loop_body
+; GFX1150-NEXT: .LBB12_29: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v8, v5
@@ -15874,11 +15704,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_33
-; GFX1150-NEXT: ; %bb.34: ; %Flow
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_29
+; GFX1150-NEXT: ; %bb.30: ; %Flow
; GFX1150-NEXT: v_mov_b32_e32 v7, s11
; GFX1150-NEXT: v_mov_b32_e32 v5, v8
-; GFX1150-NEXT: .LBB12_35: ; %frem.loop_exit
+; GFX1150-NEXT: .LBB12_31: ; %frem.loop_exit
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_add_nc_u32_e32 v7, -11, v7
; GFX1150-NEXT: v_ldexp_f32 v5, v5, v7
@@ -15895,7 +15725,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v4, v3
; GFX1150-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, s7
-; GFX1150-NEXT: .LBB12_36: ; %Flow116
+; GFX1150-NEXT: .LBB12_32: ; %Flow116
; GFX1150-NEXT: s_cmp_lg_f32 s6, 0
; GFX1150-NEXT: v_mov_b32_e32 v4, 0
; GFX1150-NEXT: s_cselect_b32 s6, -1, 0
@@ -15951,23 +15781,25 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_and_b32 s11, s6, 0x7fffffff
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_cmp_ngt_f32 s5, s11
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_2
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_3
; GFX1200-NEXT: ; %bb.1: ; %frem.else78
; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s8
; GFX1200-NEXT: s_cmp_eq_f32 s5, s11
; GFX1200-NEXT: s_cselect_b32 s11, s12, s8
; GFX1200-NEXT: s_mov_b32 s12, 0
-; GFX1200-NEXT: s_branch .LBB12_3
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_4
; GFX1200-NEXT: .LBB12_2:
+; GFX1200-NEXT: v_mov_b32_e32 v0, s11
+; GFX1200-NEXT: s_branch .LBB12_9
+; GFX1200-NEXT: .LBB12_3:
; GFX1200-NEXT: s_mov_b32 s12, -1
; GFX1200-NEXT: ; implicit-def: $sgpr11
-; GFX1200-NEXT: .LBB12_3: ; %Flow127
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s12, 1, 0
-; GFX1200-NEXT: s_cmp_lg_u32 s12, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_9
-; GFX1200-NEXT: ; %bb.4: ; %frem.compute77
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_2
+; GFX1200-NEXT: .LBB12_4: ; %frem.compute77
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s6|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v0, |s8|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
@@ -16047,31 +15879,31 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1200-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s8
-; GFX1200-NEXT: s_branch .LBB12_10
; GFX1200-NEXT: .LBB12_9:
-; GFX1200-NEXT: v_mov_b32_e32 v0, s11
-; GFX1200-NEXT: .LBB12_10:
; GFX1200-NEXT: s_and_b32 s8, s10, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s11, s4, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_ngt_f32 s8, s11
; GFX1200-NEXT: s_cbranch_scc0 .LBB12_12
-; GFX1200-NEXT: ; %bb.11: ; %frem.else47
+; GFX1200-NEXT: ; %bb.10: ; %frem.else47
; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s10
; GFX1200-NEXT: s_cmp_eq_f32 s8, s11
; GFX1200-NEXT: s_cselect_b32 s11, s12, s10
; GFX1200-NEXT: s_mov_b32 s12, 0
-; GFX1200-NEXT: s_branch .LBB12_13
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_13
+; GFX1200-NEXT: .LBB12_11:
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v1, s11
+; GFX1200-NEXT: s_branch .LBB12_18
; GFX1200-NEXT: .LBB12_12:
; GFX1200-NEXT: s_mov_b32 s12, -1
; GFX1200-NEXT: ; implicit-def: $sgpr11
-; GFX1200-NEXT: .LBB12_13: ; %Flow123
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s12, 1, 0
-; GFX1200-NEXT: s_cmp_lg_u32 s12, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_19
-; GFX1200-NEXT: ; %bb.14: ; %frem.compute46
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_11
+; GFX1200-NEXT: .LBB12_13: ; %frem.compute46
; GFX1200-NEXT: v_frexp_mant_f32_e64 v2, |s4|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s10|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
@@ -16106,13 +15938,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1200-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_18
-; GFX1200-NEXT: ; %bb.15: ; %frem.loop_body54.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_17
+; GFX1200-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_16: ; %frem.loop_body54
+; GFX1200-NEXT: .LBB12_15: ; %frem.loop_body54
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v6, v3
@@ -16132,11 +15964,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_16
-; GFX1200-NEXT: ; %bb.17: ; %Flow121
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_15
+; GFX1200-NEXT: ; %bb.16: ; %Flow121
; GFX1200-NEXT: v_mov_b32_e32 v5, s11
; GFX1200-NEXT: v_mov_b32_e32 v3, v6
-; GFX1200-NEXT: .LBB12_18: ; %frem.loop_exit55
+; GFX1200-NEXT: .LBB12_17: ; %frem.loop_exit55
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_add_nc_u32_e32 v5, -11, v5
; GFX1200-NEXT: v_ldexp_f32 v3, v3, v5
@@ -16154,32 +15986,31 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1200-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s10
-; GFX1200-NEXT: s_branch .LBB12_20
-; GFX1200-NEXT: .LBB12_19:
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v1, s11
-; GFX1200-NEXT: .LBB12_20:
+; GFX1200-NEXT: .LBB12_18:
; GFX1200-NEXT: s_and_b32 s10, s9, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s11, s3, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_ngt_f32 s10, s11
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_22
-; GFX1200-NEXT: ; %bb.21: ; %frem.else16
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_21
+; GFX1200-NEXT: ; %bb.19: ; %frem.else16
; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s9
; GFX1200-NEXT: s_cmp_eq_f32 s10, s11
; GFX1200-NEXT: s_cselect_b32 s11, s12, s9
; GFX1200-NEXT: s_mov_b32 s12, 0
-; GFX1200-NEXT: s_branch .LBB12_23
-; GFX1200-NEXT: .LBB12_22:
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_22
+; GFX1200-NEXT: .LBB12_20:
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v2, s11
+; GFX1200-NEXT: s_branch .LBB12_27
+; GFX1200-NEXT: .LBB12_21:
; GFX1200-NEXT: s_mov_b32 s12, -1
; GFX1200-NEXT: ; implicit-def: $sgpr11
-; GFX1200-NEXT: .LBB12_23: ; %Flow119
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s12, 1, 0
-; GFX1200-NEXT: s_cmp_lg_u32 s12, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_29
-; GFX1200-NEXT: ; %bb.24: ; %frem.compute15
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_20
+; GFX1200-NEXT: .LBB12_22: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f32_e64 v3, |s3|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v2, |s9|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
@@ -16214,13 +16045,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX1200-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_28
-; GFX1200-NEXT: ; %bb.25: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_26
+; GFX1200-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_26: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB12_24: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v7, v4
@@ -16240,11 +16071,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_26
-; GFX1200-NEXT: ; %bb.27: ; %Flow117
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_24
+; GFX1200-NEXT: ; %bb.25: ; %Flow117
; GFX1200-NEXT: v_mov_b32_e32 v6, s11
; GFX1200-NEXT: v_mov_b32_e32 v4, v7
-; GFX1200-NEXT: .LBB12_28: ; %frem.loop_exit24
+; GFX1200-NEXT: .LBB12_26: ; %frem.loop_exit24
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_add_nc_u32_e32 v6, -11, v6
; GFX1200-NEXT: v_ldexp_f32 v4, v4, v6
@@ -16262,32 +16093,31 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v2, v3, v2
; GFX1200-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s9
-; GFX1200-NEXT: s_branch .LBB12_30
-; GFX1200-NEXT: .LBB12_29:
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v2, s11
-; GFX1200-NEXT: .LBB12_30:
+; GFX1200-NEXT: .LBB12_27:
; GFX1200-NEXT: s_and_b32 s9, s7, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s11, s2, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_ngt_f32 s9, s11
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_32
-; GFX1200-NEXT: ; %bb.31: ; %frem.else
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_30
+; GFX1200-NEXT: ; %bb.28: ; %frem.else
; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s7
; GFX1200-NEXT: s_cmp_eq_f32 s9, s11
; GFX1200-NEXT: s_cselect_b32 s11, s12, s7
; GFX1200-NEXT: s_mov_b32 s12, 0
-; GFX1200-NEXT: s_branch .LBB12_33
-; GFX1200-NEXT: .LBB12_32:
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_31
+; GFX1200-NEXT: .LBB12_29:
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v3, s11
+; GFX1200-NEXT: s_branch .LBB12_36
+; GFX1200-NEXT: .LBB12_30:
; GFX1200-NEXT: s_mov_b32 s12, -1
; GFX1200-NEXT: ; implicit-def: $sgpr11
-; GFX1200-NEXT: .LBB12_33: ; %Flow115
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s12, 1, 0
-; GFX1200-NEXT: s_cmp_lg_u32 s12, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_39
-; GFX1200-NEXT: ; %bb.34: ; %frem.compute
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_29
+; GFX1200-NEXT: .LBB12_31: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f32_e64 v4, |s2|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v3, |s7|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, s7
@@ -16322,13 +16152,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1200-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_38
-; GFX1200-NEXT: ; %bb.35: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_35
+; GFX1200-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_36: ; %frem.loop_body
+; GFX1200-NEXT: .LBB12_33: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v8, v5
@@ -16348,11 +16178,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_36
-; GFX1200-NEXT: ; %bb.37: ; %Flow
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_33
+; GFX1200-NEXT: ; %bb.34: ; %Flow
; GFX1200-NEXT: v_mov_b32_e32 v7, s11
; GFX1200-NEXT: v_mov_b32_e32 v5, v8
-; GFX1200-NEXT: .LBB12_38: ; %frem.loop_exit
+; GFX1200-NEXT: .LBB12_35: ; %frem.loop_exit
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_add_nc_u32_e32 v7, -11, v7
; GFX1200-NEXT: v_ldexp_f32 v5, v5, v7
@@ -16370,11 +16200,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v3, v4, v3
; GFX1200-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, s7
-; GFX1200-NEXT: s_branch .LBB12_40
-; GFX1200-NEXT: .LBB12_39:
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v3, s11
-; GFX1200-NEXT: .LBB12_40: ; %Flow116
+; GFX1200-NEXT: .LBB12_36: ; %Flow116
; GFX1200-NEXT: s_cmp_lg_f32 s6, 0
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_cselect_b32 s6, -1, 0
@@ -16447,7 +16273,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_readfirstlane_b32 s4, v4
; SI-NEXT: v_readfirstlane_b32 s5, v5
; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
-; SI-NEXT: s_cbranch_vccz .LBB13_2
+; SI-NEXT: s_cbranch_vccz .LBB13_3
; SI-NEXT: ; %bb.1: ; %frem.else16
; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_mov_b32_e32 v1, s11
@@ -16457,16 +16283,18 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_cselect_b32 s1, s12, s7
; SI-NEXT: s_cselect_b32 s0, 0, s6
; SI-NEXT: s_mov_b64 s[12:13], 0
-; SI-NEXT: s_branch .LBB13_3
+; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
+; SI-NEXT: s_cbranch_scc1 .LBB13_4
; SI-NEXT: .LBB13_2:
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: s_branch .LBB13_9
+; SI-NEXT: .LBB13_3:
; SI-NEXT: s_mov_b64 s[12:13], -1
; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
-; SI-NEXT: .LBB13_3: ; %Flow53
; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
-; SI-NEXT: s_cselect_b32 s12, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s12, 1
-; SI-NEXT: s_cbranch_scc1 .LBB13_9
-; SI-NEXT: ; %bb.4: ; %frem.compute15
+; SI-NEXT: s_cbranch_scc0 .LBB13_2
+; SI-NEXT: .LBB13_4: ; %frem.compute15
; SI-NEXT: s_and_b32 s0, s7, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[6:7]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -16565,17 +16393,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], s14
; SI-NEXT: v_mov_b32_e32 v2, s7
; SI-NEXT: v_bfi_b32 v1, s0, v1, v2
-; SI-NEXT: s_branch .LBB13_10
; SI-NEXT: .LBB13_9:
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: .LBB13_10:
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: v_cmp_ngt_f64_e64 s[0:1], |s[2:3]|, |v[2:3]|
; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
; SI-NEXT: s_cbranch_vccz .LBB13_12
-; SI-NEXT: ; %bb.11: ; %frem.else
+; SI-NEXT: ; %bb.10: ; %frem.else
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[2:3]|, |v[2:3]|
@@ -16584,16 +16408,18 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_cselect_b32 s1, s12, s3
; SI-NEXT: s_cselect_b32 s0, 0, s2
; SI-NEXT: s_mov_b64 s[12:13], 0
-; SI-NEXT: s_branch .LBB13_13
+; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
+; SI-NEXT: s_cbranch_scc1 .LBB13_13
+; SI-NEXT: .LBB13_11:
+; SI-NEXT: v_mov_b32_e32 v3, s1
+; SI-NEXT: v_mov_b32_e32 v2, s0
+; SI-NEXT: s_branch .LBB13_18
; SI-NEXT: .LBB13_12:
; SI-NEXT: s_mov_b64 s[12:13], -1
; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
-; SI-NEXT: .LBB13_13: ; %Flow49
; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
-; SI-NEXT: s_cselect_b32 s12, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s12, 1
-; SI-NEXT: s_cbranch_scc1 .LBB13_19
-; SI-NEXT: ; %bb.14: ; %frem.compute
+; SI-NEXT: s_cbranch_scc0 .LBB13_11
+; SI-NEXT: .LBB13_13: ; %frem.compute
; SI-NEXT: s_and_b32 s0, s3, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[2:3]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -16639,14 +16465,14 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f64 v[4:5], v[14:15], v[8:9], v[12:13]
; SI-NEXT: s_cmp_lt_i32 s16, 27
; SI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
-; SI-NEXT: s_cbranch_scc1 .LBB13_18
-; SI-NEXT: ; %bb.15: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB13_17
+; SI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s0, s13, s17
; SI-NEXT: s_add_i32 s16, s0, 26
; SI-NEXT: s_mov_b32 s13, 0x432fffff
; SI-NEXT: v_mov_b32_e32 v12, 0x43300000
; SI-NEXT: v_mov_b32_e32 v8, 0
-; SI-NEXT: .LBB13_16: ; %frem.loop_body
+; SI-NEXT: .LBB13_15: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v11, v7
; SI-NEXT: v_mov_b32_e32 v10, v6
@@ -16665,11 +16491,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_cndmask_b32_e32 v7, v7, v14, vcc
; SI-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc
; SI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; SI-NEXT: s_cbranch_scc1 .LBB13_16
-; SI-NEXT: ; %bb.17: ; %Flow
+; SI-NEXT: s_cbranch_scc1 .LBB13_15
+; SI-NEXT: ; %bb.16: ; %Flow
; SI-NEXT: v_mov_b32_e32 v6, v10
; SI-NEXT: v_mov_b32_e32 v7, v11
-; SI-NEXT: .LBB13_18: ; %frem.loop_exit
+; SI-NEXT: .LBB13_17: ; %frem.loop_exit
; SI-NEXT: s_sub_i32 s0, s16, 25
; SI-NEXT: v_ldexp_f64 v[6:7], v[6:7], s0
; SI-NEXT: s_mov_b32 s0, -1
@@ -16692,11 +16518,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f64 v[2:3], v[2:3], s14
; SI-NEXT: v_mov_b32_e32 v4, s3
; SI-NEXT: v_bfi_b32 v3, s0, v3, v4
-; SI-NEXT: s_branch .LBB13_20
-; SI-NEXT: .LBB13_19:
-; SI-NEXT: v_mov_b32_e32 v3, s1
-; SI-NEXT: v_mov_b32_e32 v2, s0
-; SI-NEXT: .LBB13_20: ; %Flow50
+; SI-NEXT: .LBB13_18: ; %Flow50
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
; SI-NEXT: v_cmp_lg_f64_e64 s[0:1], s[10:11], 0
@@ -16738,16 +16560,15 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_mov_b64 s[2:3], 0
; CI-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
; CI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; CI-NEXT: s_branch .LBB13_3
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB13_3
+; CI-NEXT: s_branch .LBB13_8
; CI-NEXT: .LBB13_2:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr8_vgpr9
-; CI-NEXT: .LBB13_3: ; %Flow53
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB13_9
-; CI-NEXT: ; %bb.4: ; %frem.compute15
+; CI-NEXT: s_cbranch_scc0 .LBB13_8
+; CI-NEXT: .LBB13_3: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v15, v[4:5]
; CI-NEXT: v_frexp_exp_i32_f64_e32 v14, v[0:1]
@@ -16770,11 +16591,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v17
; CI-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB13_8
-; CI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB13_7
+; CI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; CI-NEXT: v_sub_i32_e32 v14, vcc, v14, v15
; CI-NEXT: v_add_i32_e32 v17, vcc, 26, v14
-; CI-NEXT: .LBB13_6: ; %frem.loop_body23
+; CI-NEXT: .LBB13_5: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v15, v13
; CI-NEXT: v_mov_b32_e32 v14, v12
@@ -16788,11 +16609,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
; CI-NEXT: v_subrev_i32_e32 v17, vcc, 26, v17
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v17
-; CI-NEXT: s_cbranch_vccnz .LBB13_6
-; CI-NEXT: ; %bb.7: ; %Flow51
+; CI-NEXT: s_cbranch_vccnz .LBB13_5
+; CI-NEXT: ; %bb.6: ; %Flow51
; CI-NEXT: v_mov_b32_e32 v12, v14
; CI-NEXT: v_mov_b32_e32 v13, v15
-; CI-NEXT: .LBB13_8: ; %frem.loop_exit24
+; CI-NEXT: .LBB13_7: ; %frem.loop_exit24
; CI-NEXT: v_subrev_i32_e32 v14, vcc, 25, v17
; CI-NEXT: v_ldexp_f64 v[12:13], v[12:13], v14
; CI-NEXT: s_brev_b32 s2, -2
@@ -16805,26 +16626,25 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
; CI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; CI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; CI-NEXT: .LBB13_9:
+; CI-NEXT: .LBB13_8:
; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB13_11
-; CI-NEXT: ; %bb.10: ; %frem.else
+; CI-NEXT: s_cbranch_vccz .LBB13_10
+; CI-NEXT: ; %bb.9: ; %frem.else
; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
; CI-NEXT: v_and_b32_e32 v10, 0x80000000, v3
; CI-NEXT: s_mov_b64 s[2:3], 0
; CI-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
; CI-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
-; CI-NEXT: s_branch .LBB13_12
-; CI-NEXT: .LBB13_11:
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB13_11
+; CI-NEXT: s_branch .LBB13_16
+; CI-NEXT: .LBB13_10:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr10_vgpr11
-; CI-NEXT: .LBB13_12: ; %Flow49
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB13_18
-; CI-NEXT: ; %bb.13: ; %frem.compute
+; CI-NEXT: s_cbranch_scc0 .LBB13_16
+; CI-NEXT: .LBB13_11: ; %frem.compute
; CI-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v17, v[6:7]
; CI-NEXT: v_frexp_exp_i32_f64_e32 v16, v[2:3]
@@ -16847,11 +16667,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v19
; CI-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB13_17
-; CI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB13_15
+; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v16, vcc, v16, v17
; CI-NEXT: v_add_i32_e32 v19, vcc, 26, v16
-; CI-NEXT: .LBB13_15: ; %frem.loop_body
+; CI-NEXT: .LBB13_13: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v17, v15
; CI-NEXT: v_mov_b32_e32 v16, v14
@@ -16865,11 +16685,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
; CI-NEXT: v_subrev_i32_e32 v19, vcc, 26, v19
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v19
-; CI-NEXT: s_cbranch_vccnz .LBB13_15
-; CI-NEXT: ; %bb.16: ; %Flow
+; CI-NEXT: s_cbranch_vccnz .LBB13_13
+; CI-NEXT: ; %bb.14: ; %Flow
; CI-NEXT: v_mov_b32_e32 v14, v16
; CI-NEXT: v_mov_b32_e32 v15, v17
-; CI-NEXT: .LBB13_17: ; %frem.loop_exit
+; CI-NEXT: .LBB13_15: ; %frem.loop_exit
; CI-NEXT: v_subrev_i32_e32 v16, vcc, 25, v19
; CI-NEXT: v_ldexp_f64 v[14:15], v[14:15], v16
; CI-NEXT: s_brev_b32 s2, -2
@@ -16882,7 +16702,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc
; CI-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; CI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; CI-NEXT: .LBB13_18: ; %Flow50
+; CI-NEXT: .LBB13_16: ; %Flow50
; CI-NEXT: s_mov_b32 s4, 0
; CI-NEXT: s_mov_b32 s5, 0x7ff00000
; CI-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[4:5]
@@ -16924,16 +16744,15 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: s_mov_b64 s[2:3], 0
; VI-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
; VI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; VI-NEXT: s_branch .LBB13_3
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB13_3
+; VI-NEXT: s_branch .LBB13_8
; VI-NEXT: .LBB13_2:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr8_vgpr9
-; VI-NEXT: .LBB13_3: ; %Flow53
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB13_9
-; VI-NEXT: ; %bb.4: ; %frem.compute15
+; VI-NEXT: s_cbranch_scc0 .LBB13_8
+; VI-NEXT: .LBB13_3: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v15, v[4:5]
; VI-NEXT: v_frexp_exp_i32_f64_e32 v14, v[0:1]
@@ -16956,11 +16775,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v17
; VI-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB13_8
-; VI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB13_7
+; VI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; VI-NEXT: v_sub_u32_e32 v14, vcc, v14, v15
; VI-NEXT: v_add_u32_e32 v17, vcc, 26, v14
-; VI-NEXT: .LBB13_6: ; %frem.loop_body23
+; VI-NEXT: .LBB13_5: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v15, v13
; VI-NEXT: v_mov_b32_e32 v14, v12
@@ -16974,11 +16793,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
; VI-NEXT: v_subrev_u32_e32 v17, vcc, 26, v17
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v17
-; VI-NEXT: s_cbranch_vccnz .LBB13_6
-; VI-NEXT: ; %bb.7: ; %Flow51
+; VI-NEXT: s_cbranch_vccnz .LBB13_5
+; VI-NEXT: ; %bb.6: ; %Flow51
; VI-NEXT: v_mov_b32_e32 v12, v14
; VI-NEXT: v_mov_b32_e32 v13, v15
-; VI-NEXT: .LBB13_8: ; %frem.loop_exit24
+; VI-NEXT: .LBB13_7: ; %frem.loop_exit24
; VI-NEXT: v_subrev_u32_e32 v14, vcc, 25, v17
; VI-NEXT: v_ldexp_f64 v[12:13], v[12:13], v14
; VI-NEXT: s_brev_b32 s2, -2
@@ -16991,26 +16810,25 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
; VI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; VI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; VI-NEXT: .LBB13_9:
+; VI-NEXT: .LBB13_8:
; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB13_11
-; VI-NEXT: ; %bb.10: ; %frem.else
+; VI-NEXT: s_cbranch_vccz .LBB13_10
+; VI-NEXT: ; %bb.9: ; %frem.else
; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
; VI-NEXT: v_and_b32_e32 v10, 0x80000000, v3
; VI-NEXT: s_mov_b64 s[2:3], 0
; VI-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
; VI-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
-; VI-NEXT: s_branch .LBB13_12
-; VI-NEXT: .LBB13_11:
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB13_11
+; VI-NEXT: s_branch .LBB13_16
+; VI-NEXT: .LBB13_10:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr10_vgpr11
-; VI-NEXT: .LBB13_12: ; %Flow49
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB13_18
-; VI-NEXT: ; %bb.13: ; %frem.compute
+; VI-NEXT: s_cbranch_scc0 .LBB13_16
+; VI-NEXT: .LBB13_11: ; %frem.compute
; VI-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v17, v[6:7]
; VI-NEXT: v_frexp_exp_i32_f64_e32 v16, v[2:3]
@@ -17033,11 +16851,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v19
; VI-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB13_17
-; VI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB13_15
+; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v16, vcc, v16, v17
; VI-NEXT: v_add_u32_e32 v19, vcc, 26, v16
-; VI-NEXT: .LBB13_15: ; %frem.loop_body
+; VI-NEXT: .LBB13_13: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v17, v15
; VI-NEXT: v_mov_b32_e32 v16, v14
@@ -17051,11 +16869,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
; VI-NEXT: v_subrev_u32_e32 v19, vcc, 26, v19
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v19
-; VI-NEXT: s_cbranch_vccnz .LBB13_15
-; VI-NEXT: ; %bb.16: ; %Flow
+; VI-NEXT: s_cbranch_vccnz .LBB13_13
+; VI-NEXT: ; %bb.14: ; %Flow
; VI-NEXT: v_mov_b32_e32 v14, v16
; VI-NEXT: v_mov_b32_e32 v15, v17
-; VI-NEXT: .LBB13_17: ; %frem.loop_exit
+; VI-NEXT: .LBB13_15: ; %frem.loop_exit
; VI-NEXT: v_subrev_u32_e32 v16, vcc, 25, v19
; VI-NEXT: v_ldexp_f64 v[14:15], v[14:15], v16
; VI-NEXT: s_brev_b32 s2, -2
@@ -17068,7 +16886,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc
; VI-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; VI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; VI-NEXT: .LBB13_18: ; %Flow50
+; VI-NEXT: .LBB13_16: ; %Flow50
; VI-NEXT: s_mov_b32 s2, 0
; VI-NEXT: s_mov_b32 s3, 0x7ff00000
; VI-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[4:5]
@@ -17105,16 +16923,15 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; GFX9-NEXT: s_branch .LBB13_3
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB13_3
+; GFX9-NEXT: s_branch .LBB13_8
; GFX9-NEXT: .LBB13_2:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX9-NEXT: .LBB13_3: ; %Flow53
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB13_9
-; GFX9-NEXT: ; %bb.4: ; %frem.compute15
+; GFX9-NEXT: s_cbranch_scc0 .LBB13_8
+; GFX9-NEXT: .LBB13_3: ; %frem.compute15
; GFX9-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v15, v[4:5]
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v14, v[0:1]
@@ -17137,11 +16954,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v17
; GFX9-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_8
-; GFX9-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_7
+; GFX9-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX9-NEXT: v_sub_u32_e32 v14, v14, v15
; GFX9-NEXT: v_add_u32_e32 v17, 26, v14
-; GFX9-NEXT: .LBB13_6: ; %frem.loop_body23
+; GFX9-NEXT: .LBB13_5: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v15, v13
; GFX9-NEXT: v_mov_b32_e32 v14, v12
@@ -17155,11 +16972,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v18, vcc
; GFX9-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v17
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_6
-; GFX9-NEXT: ; %bb.7: ; %Flow51
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_5
+; GFX9-NEXT: ; %bb.6: ; %Flow51
; GFX9-NEXT: v_mov_b32_e32 v12, v14
; GFX9-NEXT: v_mov_b32_e32 v13, v15
-; GFX9-NEXT: .LBB13_8: ; %frem.loop_exit24
+; GFX9-NEXT: .LBB13_7: ; %frem.loop_exit24
; GFX9-NEXT: v_subrev_u32_e32 v14, 25, v17
; GFX9-NEXT: v_ldexp_f64 v[12:13], v[12:13], v14
; GFX9-NEXT: s_brev_b32 s2, -2
@@ -17172,26 +16989,25 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
; GFX9-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX9-NEXT: v_bfi_b32 v9, s2, v9, v1
-; GFX9-NEXT: .LBB13_9:
+; GFX9-NEXT: .LBB13_8:
; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB13_11
-; GFX9-NEXT: ; %bb.10: ; %frem.else
+; GFX9-NEXT: s_cbranch_vccz .LBB13_10
+; GFX9-NEXT: ; %bb.9: ; %frem.else
; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v3
; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
-; GFX9-NEXT: s_branch .LBB13_12
-; GFX9-NEXT: .LBB13_11:
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB13_11
+; GFX9-NEXT: s_branch .LBB13_16
+; GFX9-NEXT: .LBB13_10:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr10_vgpr11
-; GFX9-NEXT: .LBB13_12: ; %Flow49
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB13_18
-; GFX9-NEXT: ; %bb.13: ; %frem.compute
+; GFX9-NEXT: s_cbranch_scc0 .LBB13_16
+; GFX9-NEXT: .LBB13_11: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v17, v[6:7]
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v16, v[2:3]
@@ -17214,11 +17030,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v19
; GFX9-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_17
-; GFX9-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_15
+; GFX9-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v16, v16, v17
; GFX9-NEXT: v_add_u32_e32 v19, 26, v16
-; GFX9-NEXT: .LBB13_15: ; %frem.loop_body
+; GFX9-NEXT: .LBB13_13: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v17, v15
; GFX9-NEXT: v_mov_b32_e32 v16, v14
@@ -17232,11 +17048,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v20, vcc
; GFX9-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v19
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_15
-; GFX9-NEXT: ; %bb.16: ; %Flow
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_13
+; GFX9-NEXT: ; %bb.14: ; %Flow
; GFX9-NEXT: v_mov_b32_e32 v14, v16
; GFX9-NEXT: v_mov_b32_e32 v15, v17
-; GFX9-NEXT: .LBB13_17: ; %frem.loop_exit
+; GFX9-NEXT: .LBB13_15: ; %frem.loop_exit
; GFX9-NEXT: v_subrev_u32_e32 v16, 25, v19
; GFX9-NEXT: v_ldexp_f64 v[14:15], v[14:15], v16
; GFX9-NEXT: s_brev_b32 s2, -2
@@ -17249,7 +17065,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc
; GFX9-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX9-NEXT: v_bfi_b32 v11, s2, v11, v3
-; GFX9-NEXT: .LBB13_18: ; %Flow50
+; GFX9-NEXT: .LBB13_16: ; %Flow50
; GFX9-NEXT: s_mov_b32 s2, 0
; GFX9-NEXT: s_mov_b32 s3, 0x7ff00000
; GFX9-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[4:5]
@@ -17287,16 +17103,15 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX10-NEXT: s_branch .LBB13_3
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB13_3
+; GFX10-NEXT: s_branch .LBB13_8
; GFX10-NEXT: .LBB13_2:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX10-NEXT: .LBB13_3: ; %Flow53
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB13_9
-; GFX10-NEXT: ; %bb.4: ; %frem.compute15
+; GFX10-NEXT: s_cbranch_scc0 .LBB13_8
+; GFX10-NEXT: .LBB13_3: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
@@ -17320,11 +17135,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
; GFX10-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB13_8
-; GFX10-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB13_7
+; GFX10-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 26
-; GFX10-NEXT: .LBB13_6: ; %frem.loop_body23
+; GFX10-NEXT: .LBB13_5: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v15, v11
; GFX10-NEXT: v_mov_b32_e32 v14, v10
@@ -17338,12 +17153,12 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB13_6
-; GFX10-NEXT: ; %bb.7: ; %Flow51
+; GFX10-NEXT: s_cbranch_scc1 .LBB13_5
+; GFX10-NEXT: ; %bb.6: ; %Flow51
; GFX10-NEXT: v_mov_b32_e32 v17, s2
; GFX10-NEXT: v_mov_b32_e32 v10, v14
; GFX10-NEXT: v_mov_b32_e32 v11, v15
-; GFX10-NEXT: .LBB13_8: ; %frem.loop_exit24
+; GFX10-NEXT: .LBB13_7: ; %frem.loop_exit24
; GFX10-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
; GFX10-NEXT: v_mul_f64 v[12:13], v[10:11], v[12:13]
@@ -17355,26 +17170,25 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX10-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX10-NEXT: .LBB13_9:
+; GFX10-NEXT: .LBB13_8:
; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB13_11
-; GFX10-NEXT: ; %bb.10: ; %frem.else
+; GFX10-NEXT: s_cbranch_vccz .LBB13_10
+; GFX10-NEXT: ; %bb.9: ; %frem.else
; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v3
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX10-NEXT: s_branch .LBB13_12
-; GFX10-NEXT: .LBB13_11:
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB13_11
+; GFX10-NEXT: s_branch .LBB13_16
+; GFX10-NEXT: .LBB13_10:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr10_vgpr11
-; GFX10-NEXT: .LBB13_12: ; %Flow49
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB13_18
-; GFX10-NEXT: ; %bb.13: ; %frem.compute
+; GFX10-NEXT: s_cbranch_scc0 .LBB13_16
+; GFX10-NEXT: .LBB13_11: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
@@ -17398,11 +17212,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
; GFX10-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB13_17
-; GFX10-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB13_15
+; GFX10-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 26
-; GFX10-NEXT: .LBB13_15: ; %frem.loop_body
+; GFX10-NEXT: .LBB13_13: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v17, v13
; GFX10-NEXT: v_mov_b32_e32 v16, v12
@@ -17416,12 +17230,12 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v20, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v19, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB13_15
-; GFX10-NEXT: ; %bb.16: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB13_13
+; GFX10-NEXT: ; %bb.14: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v19, s2
; GFX10-NEXT: v_mov_b32_e32 v12, v16
; GFX10-NEXT: v_mov_b32_e32 v13, v17
-; GFX10-NEXT: .LBB13_17: ; %frem.loop_exit
+; GFX10-NEXT: .LBB13_15: ; %frem.loop_exit
; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
; GFX10-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
; GFX10-NEXT: v_mul_f64 v[14:15], v[12:13], v[14:15]
@@ -17433,7 +17247,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX10-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX10-NEXT: .LBB13_18: ; %Flow50
+; GFX10-NEXT: .LBB13_16: ; %Flow50
; GFX10-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX10-NEXT: v_mov_b32_e32 v4, 0
@@ -17469,17 +17283,16 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX11-NEXT: s_branch .LBB13_3
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB13_3
+; GFX11-NEXT: s_branch .LBB13_8
; GFX11-NEXT: .LBB13_2:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX11-NEXT: .LBB13_3: ; %Flow53
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB13_9
-; GFX11-NEXT: ; %bb.4: ; %frem.compute15
+; GFX11-NEXT: s_cbranch_scc0 .LBB13_8
+; GFX11-NEXT: .LBB13_3: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
@@ -17511,13 +17324,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB13_8
-; GFX11-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB13_7
+; GFX11-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 26
; GFX11-NEXT: .p2align 6
-; GFX11-NEXT: .LBB13_6: ; %frem.loop_body23
+; GFX11-NEXT: .LBB13_5: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
@@ -17533,11 +17346,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB13_6
-; GFX11-NEXT: ; %bb.7: ; %Flow51
+; GFX11-NEXT: s_cbranch_scc1 .LBB13_5
+; GFX11-NEXT: ; %bb.6: ; %Flow51
; GFX11-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
; GFX11-NEXT: v_mov_b32_e32 v11, v15
-; GFX11-NEXT: .LBB13_8: ; %frem.loop_exit24
+; GFX11-NEXT: .LBB13_7: ; %frem.loop_exit24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
@@ -17553,28 +17366,27 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX11-NEXT: .LBB13_9:
+; GFX11-NEXT: .LBB13_8:
; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB13_11
-; GFX11-NEXT: ; %bb.10: ; %frem.else
+; GFX11-NEXT: s_cbranch_vccz .LBB13_10
+; GFX11-NEXT: ; %bb.9: ; %frem.else
; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v3
; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX11-NEXT: s_branch .LBB13_12
-; GFX11-NEXT: .LBB13_11:
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB13_11
+; GFX11-NEXT: s_branch .LBB13_16
+; GFX11-NEXT: .LBB13_10:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr10_vgpr11
-; GFX11-NEXT: .LBB13_12: ; %Flow49
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB13_18
-; GFX11-NEXT: ; %bb.13: ; %frem.compute
+; GFX11-NEXT: s_cbranch_scc0 .LBB13_16
+; GFX11-NEXT: .LBB13_11: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
@@ -17606,13 +17418,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB13_17
-; GFX11-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB13_15
+; GFX11-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 26
; GFX11-NEXT: .p2align 6
-; GFX11-NEXT: .LBB13_15: ; %frem.loop_body
+; GFX11-NEXT: .LBB13_13: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
@@ -17628,11 +17440,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
; GFX11-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB13_15
-; GFX11-NEXT: ; %bb.16: ; %Flow
+; GFX11-NEXT: s_cbranch_scc1 .LBB13_13
+; GFX11-NEXT: ; %bb.14: ; %Flow
; GFX11-NEXT: v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
; GFX11-NEXT: v_mov_b32_e32 v13, v17
-; GFX11-NEXT: .LBB13_17: ; %frem.loop_exit
+; GFX11-NEXT: .LBB13_15: ; %frem.loop_exit
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
; GFX11-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
@@ -17648,7 +17460,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX11-NEXT: .LBB13_18: ; %Flow50
+; GFX11-NEXT: .LBB13_16: ; %Flow50
; GFX11-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -17682,17 +17494,16 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
; GFX1150-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB13_3
+; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB13_3
+; GFX1150-NEXT: s_branch .LBB13_8
; GFX1150-NEXT: .LBB13_2:
; GFX1150-NEXT: s_mov_b32 s2, -1
; GFX1150-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX1150-NEXT: .LBB13_3: ; %Flow53
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB13_9
-; GFX1150-NEXT: ; %bb.4: ; %frem.compute15
+; GFX1150-NEXT: s_cbranch_scc0 .LBB13_8
+; GFX1150-NEXT: .LBB13_3: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
@@ -17723,13 +17534,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
; GFX1150-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB13_8
-; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB13_7
+; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_sub_i32 s2, s2, s3
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s2, s2, 26
; GFX1150-NEXT: .p2align 6
-; GFX1150-NEXT: .LBB13_6: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB13_5: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
@@ -17745,11 +17556,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB13_6
-; GFX1150-NEXT: ; %bb.7: ; %Flow51
+; GFX1150-NEXT: s_cbranch_scc1 .LBB13_5
+; GFX1150-NEXT: ; %bb.6: ; %Flow51
; GFX1150-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
; GFX1150-NEXT: v_mov_b32_e32 v11, v15
-; GFX1150-NEXT: .LBB13_8: ; %frem.loop_exit24
+; GFX1150-NEXT: .LBB13_7: ; %frem.loop_exit24
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
@@ -17765,28 +17576,27 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX1150-NEXT: .LBB13_9:
+; GFX1150-NEXT: .LBB13_8:
; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1150-NEXT: s_cbranch_vccz .LBB13_11
-; GFX1150-NEXT: ; %bb.10: ; %frem.else
+; GFX1150-NEXT: s_cbranch_vccz .LBB13_10
+; GFX1150-NEXT: ; %bb.9: ; %frem.else
; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
; GFX1150-NEXT: v_and_b32_e32 v10, 0x80000000, v3
; GFX1150-NEXT: s_mov_b32 s2, 0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
; GFX1150-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB13_12
-; GFX1150-NEXT: .LBB13_11:
+; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB13_11
+; GFX1150-NEXT: s_branch .LBB13_16
+; GFX1150-NEXT: .LBB13_10:
; GFX1150-NEXT: s_mov_b32 s2, -1
; GFX1150-NEXT: ; implicit-def: $vgpr10_vgpr11
-; GFX1150-NEXT: .LBB13_12: ; %Flow49
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB13_18
-; GFX1150-NEXT: ; %bb.13: ; %frem.compute
+; GFX1150-NEXT: s_cbranch_scc0 .LBB13_16
+; GFX1150-NEXT: .LBB13_11: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
@@ -17817,13 +17627,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
; GFX1150-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB13_17
-; GFX1150-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB13_15
+; GFX1150-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s2, s2, s3
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s2, s2, 26
; GFX1150-NEXT: .p2align 6
-; GFX1150-NEXT: .LBB13_15: ; %frem.loop_body
+; GFX1150-NEXT: .LBB13_13: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
@@ -17839,11 +17649,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB13_15
-; GFX1150-NEXT: ; %bb.16: ; %Flow
+; GFX1150-NEXT: s_cbranch_scc1 .LBB13_13
+; GFX1150-NEXT: ; %bb.14: ; %Flow
; GFX1150-NEXT: v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
; GFX1150-NEXT: v_mov_b32_e32 v13, v17
-; GFX1150-NEXT: .LBB13_17: ; %frem.loop_exit
+; GFX1150-NEXT: .LBB13_15: ; %frem.loop_exit
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
@@ -17859,7 +17669,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX1150-NEXT: .LBB13_18: ; %Flow50
+; GFX1150-NEXT: .LBB13_16: ; %Flow50
; GFX1150-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1150-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -17893,17 +17703,16 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX1200-NEXT: s_branch .LBB13_3
+; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB13_3
+; GFX1200-NEXT: s_branch .LBB13_8
; GFX1200-NEXT: .LBB13_2:
; GFX1200-NEXT: s_mov_b32 s2, -1
; GFX1200-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX1200-NEXT: .LBB13_3: ; %Flow53
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1200-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB13_9
-; GFX1200-NEXT: ; %bb.4: ; %frem.compute15
+; GFX1200-NEXT: s_cbranch_scc0 .LBB13_8
+; GFX1200-NEXT: .LBB13_3: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
@@ -17935,12 +17744,12 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
; GFX1200-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB13_8
-; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB13_7
+; GFX1200-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_sub_co_i32 s2, s2, s3
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 26
-; GFX1200-NEXT: .LBB13_6: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB13_5: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1200-NEXT: v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
@@ -17957,11 +17766,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB13_6
-; GFX1200-NEXT: ; %bb.7: ; %Flow51
+; GFX1200-NEXT: s_cbranch_scc1 .LBB13_5
+; GFX1200-NEXT: ; %bb.6: ; %Flow51
; GFX1200-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
; GFX1200-NEXT: v_mov_b32_e32 v11, v15
-; GFX1200-NEXT: .LBB13_8: ; %frem.loop_exit24
+; GFX1200-NEXT: .LBB13_7: ; %frem.loop_exit24
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
@@ -17978,12 +17787,12 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX1200-NEXT: .LBB13_9:
+; GFX1200-NEXT: .LBB13_8:
; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cbranch_vccz .LBB13_11
-; GFX1200-NEXT: ; %bb.10: ; %frem.else
+; GFX1200-NEXT: s_cbranch_vccz .LBB13_10
+; GFX1200-NEXT: ; %bb.9: ; %frem.else
; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
; GFX1200-NEXT: v_and_b32_e32 v10, 0x80000000, v3
; GFX1200-NEXT: s_mov_b32 s2, 0
@@ -17991,18 +17800,17 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX1200-NEXT: s_branch .LBB13_12
-; GFX1200-NEXT: .LBB13_11:
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB13_11
+; GFX1200-NEXT: s_branch .LBB13_16
+; GFX1200-NEXT: .LBB13_10:
; GFX1200-NEXT: s_mov_b32 s2, -1
; GFX1200-NEXT: ; implicit-def: $vgpr10_vgpr11
-; GFX1200-NEXT: .LBB13_12: ; %Flow49
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB13_18
-; GFX1200-NEXT: ; %bb.13: ; %frem.compute
+; GFX1200-NEXT: s_cbranch_scc0 .LBB13_16
+; GFX1200-NEXT: .LBB13_11: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
@@ -18034,12 +17842,13 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
; GFX1200-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB13_17
-; GFX1200-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB13_15
+; GFX1200-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s2, s2, s3
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 26
-; GFX1200-NEXT: .LBB13_15: ; %frem.loop_body
+; GFX1200-NEXT: .LBB13_13: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
@@ -18058,11 +17867,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB13_15
-; GFX1200-NEXT: ; %bb.16: ; %Flow
+; GFX1200-NEXT: s_cbranch_scc1 .LBB13_13
+; GFX1200-NEXT: ; %bb.14: ; %Flow
; GFX1200-NEXT: v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
; GFX1200-NEXT: v_mov_b32_e32 v13, v17
-; GFX1200-NEXT: .LBB13_17: ; %frem.loop_exit
+; GFX1200-NEXT: .LBB13_15: ; %frem.loop_exit
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
@@ -18079,9 +17888,10 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX1200-NEXT: .LBB13_18: ; %Flow50
+; GFX1200-NEXT: .LBB13_16: ; %Flow50
; GFX1200-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX1200-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[2:3]|
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -18298,7 +18108,7 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_readfirstlane_b32 s4, v2
; SI-NEXT: v_readfirstlane_b32 s5, v3
; SI-NEXT: s_and_b64 vcc, exec, s[6:7]
-; SI-NEXT: s_cbranch_vccz .LBB15_2
+; SI-NEXT: s_cbranch_vccz .LBB15_3
; SI-NEXT: ; %bb.1: ; %frem.else16
; SI-NEXT: v_cmp_eq_f64_e64 s[6:7], |s[2:3]|, 1.0
; SI-NEXT: s_and_b32 s8, s3, 0x80000000
@@ -18306,16 +18116,18 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: s_cselect_b32 s7, s8, s3
; SI-NEXT: s_cselect_b32 s6, 0, s2
; SI-NEXT: s_mov_b64 s[8:9], 0
-; SI-NEXT: s_branch .LBB15_3
+; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; SI-NEXT: s_cbranch_scc1 .LBB15_4
; SI-NEXT: .LBB15_2:
+; SI-NEXT: v_mov_b32_e32 v0, s6
+; SI-NEXT: v_mov_b32_e32 v1, s7
+; SI-NEXT: s_branch .LBB15_9
+; SI-NEXT: .LBB15_3:
; SI-NEXT: s_mov_b64 s[8:9], -1
; SI-NEXT: ; implicit-def: $sgpr6_sgpr7
-; SI-NEXT: .LBB15_3: ; %Flow52
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
-; SI-NEXT: s_cselect_b32 s8, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s8, 1
-; SI-NEXT: s_cbranch_scc1 .LBB15_9
-; SI-NEXT: ; %bb.4: ; %frem.compute15
+; SI-NEXT: s_cbranch_scc0 .LBB15_2
+; SI-NEXT: .LBB15_4: ; %frem.compute15
; SI-NEXT: s_and_b32 s6, s3, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
; SI-NEXT: s_cmp_lt_i32 s6, 0x7ff00000
@@ -18325,44 +18137,44 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_mov_b32_e32 v2, s2
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[2:3]
-; SI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
+; SI-NEXT: s_brev_b32 s8, -2
; SI-NEXT: v_readfirstlane_b32 s6, v2
; SI-NEXT: s_cselect_b32 s7, s6, 0
; SI-NEXT: s_add_i32 s9, s7, -1
-; SI-NEXT: s_brev_b32 s8, -2
+; SI-NEXT: v_ldexp_f64 v[1:2], v[0:1], 26
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_cmp_lt_i32 s9, 27
; SI-NEXT: s_cbranch_scc1 .LBB15_8
; SI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
; SI-NEXT: s_add_i32 s9, s7, 25
-; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
+; SI-NEXT: v_mov_b32_e32 v5, 0x43300000
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: s_mov_b32 s7, 0x432fffff
; SI-NEXT: .LBB15_6: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v3, v5
-; SI-NEXT: v_mov_b32_e32 v2, v4
-; SI-NEXT: v_bfi_b32 v1, s8, v6, v3
-; SI-NEXT: v_add_f64 v[4:5], v[2:3], v[0:1]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
-; SI-NEXT: v_add_f64 v[4:5], v[4:5], -v[0:1]
+; SI-NEXT: v_mov_b32_e32 v4, v2
+; SI-NEXT: v_mov_b32_e32 v3, v1
+; SI-NEXT: v_bfi_b32 v1, s8, v5, v4
+; SI-NEXT: v_add_f64 v[6:7], v[3:4], v[0:1]
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[3:4]|, s[6:7]
+; SI-NEXT: v_add_f64 v[1:2], v[6:7], -v[0:1]
; SI-NEXT: s_sub_i32 s9, s9, 26
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc
-; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
-; SI-NEXT: v_add_f64 v[4:5], v[2:3], -v[4:5]
+; SI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; SI-NEXT: v_add_f64 v[1:2], v[3:4], -v[1:2]
; SI-NEXT: s_cmp_gt_i32 s9, 26
-; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; SI-NEXT: v_add_f64 v[7:8], v[4:5], 1.0
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
-; SI-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[1:2]
+; SI-NEXT: v_add_f64 v[6:7], v[1:2], 1.0
+; SI-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; SI-NEXT: v_ldexp_f64 v[1:2], v[1:2], 26
; SI-NEXT: s_cbranch_scc1 .LBB15_6
; SI-NEXT: ; %bb.7: ; %Flow50
-; SI-NEXT: v_mov_b32_e32 v5, v3
-; SI-NEXT: v_mov_b32_e32 v4, v2
+; SI-NEXT: v_mov_b32_e32 v1, v3
+; SI-NEXT: v_mov_b32_e32 v2, v4
; SI-NEXT: .LBB15_8: ; %frem.loop_exit24
; SI-NEXT: s_sub_i32 s6, s9, 25
-; SI-NEXT: v_ldexp_f64 v[0:1], v[4:5], s6
+; SI-NEXT: v_ldexp_f64 v[0:1], v[1:2], s6
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s7, 0x432fffff
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[6:7]
@@ -18381,31 +18193,29 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; SI-NEXT: v_mov_b32_e32 v2, s3
; SI-NEXT: v_bfi_b32 v1, s6, v1, v2
-; SI-NEXT: s_branch .LBB15_10
; SI-NEXT: .LBB15_9:
-; SI-NEXT: v_mov_b32_e32 v0, s6
-; SI-NEXT: v_mov_b32_e32 v1, s7
-; SI-NEXT: .LBB15_10:
; SI-NEXT: v_cmp_ngt_f64_e64 s[6:7], |s[4:5]|, 1.0
; SI-NEXT: s_and_b64 vcc, exec, s[6:7]
; SI-NEXT: s_cbranch_vccz .LBB15_12
-; SI-NEXT: ; %bb.11: ; %frem.else
+; SI-NEXT: ; %bb.10: ; %frem.else
; SI-NEXT: v_cmp_eq_f64_e64 s[6:7], |s[4:5]|, 1.0
; SI-NEXT: s_and_b32 s8, s5, 0x80000000
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s7, s8, s5
; SI-NEXT: s_cselect_b32 s6, 0, s4
; SI-NEXT: s_mov_b64 s[8:9], 0
-; SI-NEXT: s_branch .LBB15_13
+; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; SI-NEXT: s_cbranch_scc1 .LBB15_13
+; SI-NEXT: .LBB15_11:
+; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v3, s7
+; SI-NEXT: s_branch .LBB15_18
; SI-NEXT: .LBB15_12:
; SI-NEXT: s_mov_b64 s[8:9], -1
; SI-NEXT: ; implicit-def: $sgpr6_sgpr7
-; SI-NEXT: .LBB15_13: ; %Flow48
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
-; SI-NEXT: s_cselect_b32 s8, 1, 0
-; SI-NEXT: s_cmp_lg_u32 s8, 1
-; SI-NEXT: s_cbranch_scc1 .LBB15_19
-; SI-NEXT: ; %bb.14: ; %frem.compute
+; SI-NEXT: s_cbranch_scc0 .LBB15_11
+; SI-NEXT: .LBB15_13: ; %frem.compute
; SI-NEXT: s_and_b32 s6, s5, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[4:5]|
; SI-NEXT: s_cmp_lt_i32 s6, 0x7ff00000
@@ -18415,44 +18225,44 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_frexp_exp_i32_f64_e32 v4, s[4:5]
-; SI-NEXT: v_ldexp_f64 v[6:7], v[2:3], 26
+; SI-NEXT: s_brev_b32 s8, -2
; SI-NEXT: v_readfirstlane_b32 s6, v4
; SI-NEXT: s_cselect_b32 s7, s6, 0
; SI-NEXT: s_add_i32 s9, s7, -1
-; SI-NEXT: s_brev_b32 s8, -2
+; SI-NEXT: v_ldexp_f64 v[3:4], v[2:3], 26
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_cmp_lt_i32 s9, 27
-; SI-NEXT: s_cbranch_scc1 .LBB15_18
-; SI-NEXT: ; %bb.15: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB15_17
+; SI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; SI-NEXT: s_add_i32 s9, s7, 25
-; SI-NEXT: v_mov_b32_e32 v8, 0x43300000
+; SI-NEXT: v_mov_b32_e32 v7, 0x43300000
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: .LBB15_16: ; %frem.loop_body
+; SI-NEXT: .LBB15_15: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v5, v7
-; SI-NEXT: v_mov_b32_e32 v4, v6
-; SI-NEXT: v_bfi_b32 v3, s8, v8, v5
-; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[2:3]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
-; SI-NEXT: v_add_f64 v[6:7], v[6:7], -v[2:3]
+; SI-NEXT: v_mov_b32_e32 v6, v4
+; SI-NEXT: v_mov_b32_e32 v5, v3
+; SI-NEXT: v_bfi_b32 v3, s8, v7, v6
+; SI-NEXT: v_add_f64 v[8:9], v[5:6], v[2:3]
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[5:6]|, s[6:7]
+; SI-NEXT: v_add_f64 v[3:4], v[8:9], -v[2:3]
; SI-NEXT: s_sub_i32 s9, s9, 26
-; SI-NEXT: v_cndmask_b32_e32 v7, v7, v5, vcc
-; SI-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc
-; SI-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; SI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; SI-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; SI-NEXT: v_add_f64 v[3:4], v[5:6], -v[3:4]
; SI-NEXT: s_cmp_gt_i32 s9, 26
-; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
-; SI-NEXT: v_add_f64 v[9:10], v[6:7], 1.0
-; SI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
-; SI-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
-; SI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; SI-NEXT: s_cbranch_scc1 .LBB15_16
-; SI-NEXT: ; %bb.17: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v7, v5
-; SI-NEXT: v_mov_b32_e32 v6, v4
-; SI-NEXT: .LBB15_18: ; %frem.loop_exit
+; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[3:4]
+; SI-NEXT: v_add_f64 v[8:9], v[3:4], 1.0
+; SI-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
+; SI-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; SI-NEXT: v_ldexp_f64 v[3:4], v[3:4], 26
+; SI-NEXT: s_cbranch_scc1 .LBB15_15
+; SI-NEXT: ; %bb.16: ; %Flow
+; SI-NEXT: v_mov_b32_e32 v3, v5
+; SI-NEXT: v_mov_b32_e32 v4, v6
+; SI-NEXT: .LBB15_17: ; %frem.loop_exit
; SI-NEXT: s_sub_i32 s6, s9, 25
-; SI-NEXT: v_ldexp_f64 v[2:3], v[6:7], s6
+; SI-NEXT: v_ldexp_f64 v[2:3], v[3:4], s6
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s7, 0x432fffff
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
@@ -18471,11 +18281,7 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; SI-NEXT: v_mov_b32_e32 v4, s5
; SI-NEXT: v_bfi_b32 v3, s6, v3, v4
-; SI-NEXT: s_branch .LBB15_20
-; SI-NEXT: .LBB15_19:
-; SI-NEXT: v_mov_b32_e32 v2, s6
-; SI-NEXT: v_mov_b32_e32 v3, s7
-; SI-NEXT: .LBB15_20: ; %Flow49
+; SI-NEXT: .LBB15_18: ; %Flow49
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
; SI-NEXT: v_cmp_nge_f64_e64 vcc, |s[2:3]|, v[4:5]
@@ -18509,25 +18315,24 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: s_mov_b64 s[2:3], 0
; CI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
; CI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; CI-NEXT: s_branch .LBB15_3
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB15_3
+; CI-NEXT: s_branch .LBB15_8
; CI-NEXT: .LBB15_2:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr4_vgpr5
-; CI-NEXT: .LBB15_3: ; %Flow52
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB15_9
-; CI-NEXT: ; %bb.4: ; %frem.compute15
+; CI-NEXT: s_cbranch_scc0 .LBB15_8
+; CI-NEXT: .LBB15_3: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v6
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v8
-; CI-NEXT: s_cbranch_vccnz .LBB15_8
-; CI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB15_7
+; CI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; CI-NEXT: v_add_i32_e32 v8, vcc, 25, v6
-; CI-NEXT: .LBB15_6: ; %frem.loop_body23
+; CI-NEXT: .LBB15_5: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v7, v5
; CI-NEXT: v_mov_b32_e32 v6, v4
@@ -18540,11 +18345,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; CI-NEXT: v_subrev_i32_e32 v8, vcc, 26, v8
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v8
-; CI-NEXT: s_cbranch_vccnz .LBB15_6
-; CI-NEXT: ; %bb.7: ; %Flow50
+; CI-NEXT: s_cbranch_vccnz .LBB15_5
+; CI-NEXT: ; %bb.6: ; %Flow50
; CI-NEXT: v_mov_b32_e32 v4, v6
; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: .LBB15_8: ; %frem.loop_exit24
+; CI-NEXT: .LBB15_7: ; %frem.loop_exit24
; CI-NEXT: v_subrev_i32_e32 v6, vcc, 25, v8
; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; CI-NEXT: s_brev_b32 s2, -2
@@ -18555,35 +18360,34 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; CI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; CI-NEXT: .LBB15_9:
+; CI-NEXT: .LBB15_8:
; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, 1.0
; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB15_11
-; CI-NEXT: ; %bb.10: ; %frem.else
+; CI-NEXT: s_cbranch_vccz .LBB15_10
+; CI-NEXT: ; %bb.9: ; %frem.else
; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
; CI-NEXT: v_and_b32_e32 v6, 0x80000000, v3
; CI-NEXT: s_mov_b64 s[2:3], 0
; CI-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc
; CI-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc
-; CI-NEXT: s_branch .LBB15_12
-; CI-NEXT: .LBB15_11:
+; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; CI-NEXT: s_cbranch_scc1 .LBB15_11
+; CI-NEXT: s_branch .LBB15_16
+; CI-NEXT: .LBB15_10:
; CI-NEXT: s_mov_b64 s[2:3], -1
; CI-NEXT: ; implicit-def: $vgpr6_vgpr7
-; CI-NEXT: .LBB15_12: ; %Flow48
; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cselect_b32 s2, 1, 0
-; CI-NEXT: s_cmp_lg_u32 s2, 1
-; CI-NEXT: s_cbranch_scc1 .LBB15_18
-; CI-NEXT: ; %bb.13: ; %frem.compute
+; CI-NEXT: s_cbranch_scc0 .LBB15_16
+; CI-NEXT: .LBB15_11: ; %frem.compute
; CI-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; CI-NEXT: v_add_i32_e32 v10, vcc, -1, v8
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v10
-; CI-NEXT: s_cbranch_vccnz .LBB15_17
-; CI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB15_15
+; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; CI-NEXT: v_add_i32_e32 v10, vcc, 25, v8
-; CI-NEXT: .LBB15_15: ; %frem.loop_body
+; CI-NEXT: .LBB15_13: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v9, v7
; CI-NEXT: v_mov_b32_e32 v8, v6
@@ -18596,11 +18400,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; CI-NEXT: v_subrev_i32_e32 v10, vcc, 26, v10
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v10
-; CI-NEXT: s_cbranch_vccnz .LBB15_15
-; CI-NEXT: ; %bb.16: ; %Flow
+; CI-NEXT: s_cbranch_vccnz .LBB15_13
+; CI-NEXT: ; %bb.14: ; %Flow
; CI-NEXT: v_mov_b32_e32 v6, v8
; CI-NEXT: v_mov_b32_e32 v7, v9
-; CI-NEXT: .LBB15_17: ; %frem.loop_exit
+; CI-NEXT: .LBB15_15: ; %frem.loop_exit
; CI-NEXT: v_subrev_i32_e32 v8, vcc, 25, v10
; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; CI-NEXT: s_brev_b32 s2, -2
@@ -18611,7 +18415,7 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; CI-NEXT: v_bfi_b32 v7, s2, v7, v3
-; CI-NEXT: .LBB15_18: ; %Flow49
+; CI-NEXT: .LBB15_16: ; %Flow49
; CI-NEXT: s_mov_b32 s4, 0
; CI-NEXT: s_mov_b32 s5, 0x7ff00000
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[4:5]
@@ -18643,25 +18447,24 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; VI-NEXT: s_mov_b64 s[2:3], 0
; VI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
; VI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; VI-NEXT: s_branch .LBB15_3
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB15_3
+; VI-NEXT: s_branch .LBB15_8
; VI-NEXT: .LBB15_2:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr4_vgpr5
-; VI-NEXT: .LBB15_3: ; %Flow52
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB15_9
-; VI-NEXT: ; %bb.4: ; %frem.compute15
+; VI-NEXT: s_cbranch_scc0 .LBB15_8
+; VI-NEXT: .LBB15_3: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v6
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v8
-; VI-NEXT: s_cbranch_vccnz .LBB15_8
-; VI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB15_7
+; VI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; VI-NEXT: v_add_u32_e32 v8, vcc, 25, v6
-; VI-NEXT: .LBB15_6: ; %frem.loop_body23
+; VI-NEXT: .LBB15_5: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v7, v5
; VI-NEXT: v_mov_b32_e32 v6, v4
@@ -18674,11 +18477,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; VI-NEXT: v_subrev_u32_e32 v8, vcc, 26, v8
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v8
-; VI-NEXT: s_cbranch_vccnz .LBB15_6
-; VI-NEXT: ; %bb.7: ; %Flow50
+; VI-NEXT: s_cbranch_vccnz .LBB15_5
+; VI-NEXT: ; %bb.6: ; %Flow50
; VI-NEXT: v_mov_b32_e32 v4, v6
; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: .LBB15_8: ; %frem.loop_exit24
+; VI-NEXT: .LBB15_7: ; %frem.loop_exit24
; VI-NEXT: v_subrev_u32_e32 v6, vcc, 25, v8
; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; VI-NEXT: s_brev_b32 s2, -2
@@ -18689,35 +18492,34 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; VI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; VI-NEXT: .LBB15_9:
+; VI-NEXT: .LBB15_8:
; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, 1.0
; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB15_11
-; VI-NEXT: ; %bb.10: ; %frem.else
+; VI-NEXT: s_cbranch_vccz .LBB15_10
+; VI-NEXT: ; %bb.9: ; %frem.else
; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
; VI-NEXT: v_and_b32_e32 v6, 0x80000000, v3
; VI-NEXT: s_mov_b64 s[2:3], 0
; VI-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc
; VI-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc
-; VI-NEXT: s_branch .LBB15_12
-; VI-NEXT: .LBB15_11:
+; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cbranch_scc1 .LBB15_11
+; VI-NEXT: s_branch .LBB15_16
+; VI-NEXT: .LBB15_10:
; VI-NEXT: s_mov_b64 s[2:3], -1
; VI-NEXT: ; implicit-def: $vgpr6_vgpr7
-; VI-NEXT: .LBB15_12: ; %Flow48
; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_cmp_lg_u32 s2, 1
-; VI-NEXT: s_cbranch_scc1 .LBB15_18
-; VI-NEXT: ; %bb.13: ; %frem.compute
+; VI-NEXT: s_cbranch_scc0 .LBB15_16
+; VI-NEXT: .LBB15_11: ; %frem.compute
; VI-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; VI-NEXT: v_add_u32_e32 v10, vcc, -1, v8
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v10
-; VI-NEXT: s_cbranch_vccnz .LBB15_17
-; VI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB15_15
+; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; VI-NEXT: v_add_u32_e32 v10, vcc, 25, v8
-; VI-NEXT: .LBB15_15: ; %frem.loop_body
+; VI-NEXT: .LBB15_13: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v9, v7
; VI-NEXT: v_mov_b32_e32 v8, v6
@@ -18730,11 +18532,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; VI-NEXT: v_subrev_u32_e32 v10, vcc, 26, v10
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v10
-; VI-NEXT: s_cbranch_vccnz .LBB15_15
-; VI-NEXT: ; %bb.16: ; %Flow
+; VI-NEXT: s_cbranch_vccnz .LBB15_13
+; VI-NEXT: ; %bb.14: ; %Flow
; VI-NEXT: v_mov_b32_e32 v6, v8
; VI-NEXT: v_mov_b32_e32 v7, v9
-; VI-NEXT: .LBB15_17: ; %frem.loop_exit
+; VI-NEXT: .LBB15_15: ; %frem.loop_exit
; VI-NEXT: v_subrev_u32_e32 v8, vcc, 25, v10
; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; VI-NEXT: s_brev_b32 s2, -2
@@ -18745,7 +18547,7 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; VI-NEXT: v_bfi_b32 v7, s2, v7, v3
-; VI-NEXT: .LBB15_18: ; %Flow49
+; VI-NEXT: .LBB15_16: ; %Flow49
; VI-NEXT: s_mov_b32 s2, 0
; VI-NEXT: s_mov_b32 s3, 0x7ff00000
; VI-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[2:3]
@@ -18776,25 +18578,24 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; GFX9-NEXT: s_branch .LBB15_3
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB15_3
+; GFX9-NEXT: s_branch .LBB15_8
; GFX9-NEXT: .LBB15_2:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX9-NEXT: .LBB15_3: ; %Flow52
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB15_9
-; GFX9-NEXT: ; %bb.4: ; %frem.compute15
+; GFX9-NEXT: s_cbranch_scc0 .LBB15_8
+; GFX9-NEXT: .LBB15_3: ; %frem.compute15
; GFX9-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX9-NEXT: v_add_u32_e32 v8, -1, v6
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v8
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_8
-; GFX9-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_7
+; GFX9-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX9-NEXT: v_add_u32_e32 v8, 25, v6
-; GFX9-NEXT: .LBB15_6: ; %frem.loop_body23
+; GFX9-NEXT: .LBB15_5: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
@@ -18807,11 +18608,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v8
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_6
-; GFX9-NEXT: ; %bb.7: ; %Flow50
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_5
+; GFX9-NEXT: ; %bb.6: ; %Flow50
; GFX9-NEXT: v_mov_b32_e32 v4, v6
; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: .LBB15_8: ; %frem.loop_exit24
+; GFX9-NEXT: .LBB15_7: ; %frem.loop_exit24
; GFX9-NEXT: v_subrev_u32_e32 v6, 25, v8
; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX9-NEXT: s_brev_b32 s2, -2
@@ -18822,35 +18623,34 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v1
-; GFX9-NEXT: .LBB15_9:
+; GFX9-NEXT: .LBB15_8:
; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, 1.0
; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB15_11
-; GFX9-NEXT: ; %bb.10: ; %frem.else
+; GFX9-NEXT: s_cbranch_vccz .LBB15_10
+; GFX9-NEXT: ; %bb.9: ; %frem.else
; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
; GFX9-NEXT: v_and_b32_e32 v6, 0x80000000, v3
; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc
-; GFX9-NEXT: s_branch .LBB15_12
-; GFX9-NEXT: .LBB15_11:
+; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cbranch_scc1 .LBB15_11
+; GFX9-NEXT: s_branch .LBB15_16
+; GFX9-NEXT: .LBB15_10:
; GFX9-NEXT: s_mov_b64 s[2:3], -1
; GFX9-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX9-NEXT: .LBB15_12: ; %Flow48
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_cmp_lg_u32 s2, 1
-; GFX9-NEXT: s_cbranch_scc1 .LBB15_18
-; GFX9-NEXT: ; %bb.13: ; %frem.compute
+; GFX9-NEXT: s_cbranch_scc0 .LBB15_16
+; GFX9-NEXT: .LBB15_11: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX9-NEXT: v_add_u32_e32 v10, -1, v8
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v10
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_17
-; GFX9-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_15
+; GFX9-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX9-NEXT: v_add_u32_e32 v10, 25, v8
-; GFX9-NEXT: .LBB15_15: ; %frem.loop_body
+; GFX9-NEXT: .LBB15_13: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v9, v7
; GFX9-NEXT: v_mov_b32_e32 v8, v6
@@ -18863,11 +18663,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc
; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v10
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_15
-; GFX9-NEXT: ; %bb.16: ; %Flow
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_13
+; GFX9-NEXT: ; %bb.14: ; %Flow
; GFX9-NEXT: v_mov_b32_e32 v6, v8
; GFX9-NEXT: v_mov_b32_e32 v7, v9
-; GFX9-NEXT: .LBB15_17: ; %frem.loop_exit
+; GFX9-NEXT: .LBB15_15: ; %frem.loop_exit
; GFX9-NEXT: v_subrev_u32_e32 v8, 25, v10
; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; GFX9-NEXT: s_brev_b32 s2, -2
@@ -18878,7 +18678,7 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GFX9-NEXT: v_bfi_b32 v7, s2, v7, v3
-; GFX9-NEXT: .LBB15_18: ; %Flow49
+; GFX9-NEXT: .LBB15_16: ; %Flow49
; GFX9-NEXT: s_mov_b32 s2, 0
; GFX9-NEXT: s_mov_b32 s3, 0x7ff00000
; GFX9-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[2:3]
@@ -18908,26 +18708,25 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX10-NEXT: s_branch .LBB15_3
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB15_3
+; GFX10-NEXT: s_branch .LBB15_8
; GFX10-NEXT: .LBB15_2:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX10-NEXT: .LBB15_3: ; %Flow52
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB15_9
-; GFX10-NEXT: ; %bb.4: ; %frem.compute15
+; GFX10-NEXT: s_cbranch_scc0 .LBB15_8
+; GFX10-NEXT: .LBB15_3: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
; GFX10-NEXT: v_add_nc_u32_e32 v8, -1, v6
; GFX10-NEXT: v_readfirstlane_b32 s2, v6
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
-; GFX10-NEXT: s_cbranch_vccnz .LBB15_8
-; GFX10-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB15_7
+; GFX10-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_add_i32 s2, s2, 25
-; GFX10-NEXT: .LBB15_6: ; %frem.loop_body23
+; GFX10-NEXT: .LBB15_5: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v7, v5
; GFX10-NEXT: v_mov_b32_e32 v6, v4
@@ -18940,12 +18739,12 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB15_6
-; GFX10-NEXT: ; %bb.7: ; %Flow50
+; GFX10-NEXT: s_cbranch_scc1 .LBB15_5
+; GFX10-NEXT: ; %bb.6: ; %Flow50
; GFX10-NEXT: v_mov_b32_e32 v8, s2
; GFX10-NEXT: v_mov_b32_e32 v4, v6
; GFX10-NEXT: v_mov_b32_e32 v5, v7
-; GFX10-NEXT: .LBB15_8: ; %frem.loop_exit24
+; GFX10-NEXT: .LBB15_7: ; %frem.loop_exit24
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
@@ -18955,36 +18754,35 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX10-NEXT: .LBB15_9:
+; GFX10-NEXT: .LBB15_8:
; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB15_11
-; GFX10-NEXT: ; %bb.10: ; %frem.else
+; GFX10-NEXT: s_cbranch_vccz .LBB15_10
+; GFX10-NEXT: ; %bb.9: ; %frem.else
; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
; GFX10-NEXT: v_and_b32_e32 v6, 0x80000000, v3
; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
-; GFX10-NEXT: s_branch .LBB15_12
-; GFX10-NEXT: .LBB15_11:
+; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cbranch_scc1 .LBB15_11
+; GFX10-NEXT: s_branch .LBB15_16
+; GFX10-NEXT: .LBB15_10:
; GFX10-NEXT: s_mov_b32 s2, -1
; GFX10-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX10-NEXT: .LBB15_12: ; %Flow48
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: s_cmp_lg_u32 s2, 1
-; GFX10-NEXT: s_cbranch_scc1 .LBB15_18
-; GFX10-NEXT: ; %bb.13: ; %frem.compute
+; GFX10-NEXT: s_cbranch_scc0 .LBB15_16
+; GFX10-NEXT: .LBB15_11: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX10-NEXT: v_add_nc_u32_e32 v10, -1, v8
; GFX10-NEXT: v_readfirstlane_b32 s2, v8
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX10-NEXT: s_cbranch_vccnz .LBB15_17
-; GFX10-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB15_15
+; GFX10-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX10-NEXT: s_add_i32 s2, s2, 25
-; GFX10-NEXT: .LBB15_15: ; %frem.loop_body
+; GFX10-NEXT: .LBB15_13: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v9, v7
; GFX10-NEXT: v_mov_b32_e32 v8, v6
@@ -18997,12 +18795,12 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB15_15
-; GFX10-NEXT: ; %bb.16: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB15_13
+; GFX10-NEXT: ; %bb.14: ; %Flow
; GFX10-NEXT: v_mov_b32_e32 v10, s2
; GFX10-NEXT: v_mov_b32_e32 v6, v8
; GFX10-NEXT: v_mov_b32_e32 v7, v9
-; GFX10-NEXT: .LBB15_17: ; %frem.loop_exit
+; GFX10-NEXT: .LBB15_15: ; %frem.loop_exit
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
; GFX10-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
@@ -19012,7 +18810,7 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
-; GFX10-NEXT: .LBB15_18: ; %Flow49
+; GFX10-NEXT: .LBB15_16: ; %Flow49
; GFX10-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
@@ -19040,17 +18838,16 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX11-NEXT: s_branch .LBB15_3
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB15_3
+; GFX11-NEXT: s_branch .LBB15_8
; GFX11-NEXT: .LBB15_2:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX11-NEXT: .LBB15_3: ; %Flow52
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB15_9
-; GFX11-NEXT: ; %bb.4: ; %frem.compute15
+; GFX11-NEXT: s_cbranch_scc0 .LBB15_8
+; GFX11-NEXT: .LBB15_3: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -19059,10 +18856,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: v_readfirstlane_b32 s2, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
-; GFX11-NEXT: s_cbranch_vccnz .LBB15_8
-; GFX11-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB15_7
+; GFX11-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_add_i32 s2, s2, 25
-; GFX11-NEXT: .LBB15_6: ; %frem.loop_body23
+; GFX11-NEXT: .LBB15_5: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
@@ -19077,11 +18874,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB15_6
-; GFX11-NEXT: ; %bb.7: ; %Flow50
+; GFX11-NEXT: s_cbranch_scc1 .LBB15_5
+; GFX11-NEXT: ; %bb.6: ; %Flow50
; GFX11-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
; GFX11-NEXT: v_mov_b32_e32 v4, v6
-; GFX11-NEXT: .LBB15_8: ; %frem.loop_exit24
+; GFX11-NEXT: .LBB15_7: ; %frem.loop_exit24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
@@ -19094,28 +18891,27 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX11-NEXT: .LBB15_9:
+; GFX11-NEXT: .LBB15_8:
; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB15_11
-; GFX11-NEXT: ; %bb.10: ; %frem.else
+; GFX11-NEXT: s_cbranch_vccz .LBB15_10
+; GFX11-NEXT: ; %bb.9: ; %frem.else
; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
; GFX11-NEXT: v_and_b32_e32 v6, 0x80000000, v3
; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
-; GFX11-NEXT: s_branch .LBB15_12
-; GFX11-NEXT: .LBB15_11:
+; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cbranch_scc1 .LBB15_11
+; GFX11-NEXT: s_branch .LBB15_16
+; GFX11-NEXT: .LBB15_10:
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX11-NEXT: .LBB15_12: ; %Flow48
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-NEXT: s_cbranch_scc1 .LBB15_18
-; GFX11-NEXT: ; %bb.13: ; %frem.compute
+; GFX11-NEXT: s_cbranch_scc0 .LBB15_16
+; GFX11-NEXT: .LBB15_11: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -19124,10 +18920,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: v_readfirstlane_b32 s2, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX11-NEXT: s_cbranch_vccnz .LBB15_17
-; GFX11-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB15_15
+; GFX11-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX11-NEXT: s_add_i32 s2, s2, 25
-; GFX11-NEXT: .LBB15_15: ; %frem.loop_body
+; GFX11-NEXT: .LBB15_13: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
@@ -19142,11 +18938,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB15_15
-; GFX11-NEXT: ; %bb.16: ; %Flow
+; GFX11-NEXT: s_cbranch_scc1 .LBB15_13
+; GFX11-NEXT: ; %bb.14: ; %Flow
; GFX11-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
; GFX11-NEXT: v_mov_b32_e32 v6, v8
-; GFX11-NEXT: .LBB15_17: ; %frem.loop_exit
+; GFX11-NEXT: .LBB15_15: ; %frem.loop_exit
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
@@ -19159,7 +18955,7 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
-; GFX11-NEXT: .LBB15_18: ; %Flow49
+; GFX11-NEXT: .LBB15_16: ; %Flow49
; GFX11-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
; GFX11-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v5 :: v_dual_cndmask_b32 v0, 0, v4
; GFX11-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
@@ -19186,17 +18982,16 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX1150-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB15_3
+; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB15_3
+; GFX1150-NEXT: s_branch .LBB15_8
; GFX1150-NEXT: .LBB15_2:
; GFX1150-NEXT: s_mov_b32 s2, -1
; GFX1150-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX1150-NEXT: .LBB15_3: ; %Flow52
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB15_9
-; GFX1150-NEXT: ; %bb.4: ; %frem.compute15
+; GFX1150-NEXT: s_cbranch_scc0 .LBB15_8
+; GFX1150-NEXT: .LBB15_3: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -19205,10 +19000,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: v_readfirstlane_b32 s2, v6
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
-; GFX1150-NEXT: s_cbranch_vccnz .LBB15_8
-; GFX1150-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB15_7
+; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_add_i32 s2, s2, 25
-; GFX1150-NEXT: .LBB15_6: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB15_5: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
@@ -19223,11 +19018,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB15_6
-; GFX1150-NEXT: ; %bb.7: ; %Flow50
+; GFX1150-NEXT: s_cbranch_scc1 .LBB15_5
+; GFX1150-NEXT: ; %bb.6: ; %Flow50
; GFX1150-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
; GFX1150-NEXT: v_mov_b32_e32 v4, v6
-; GFX1150-NEXT: .LBB15_8: ; %frem.loop_exit24
+; GFX1150-NEXT: .LBB15_7: ; %frem.loop_exit24
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
@@ -19240,28 +19035,27 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX1150-NEXT: .LBB15_9:
+; GFX1150-NEXT: .LBB15_8:
; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1150-NEXT: s_cbranch_vccz .LBB15_11
-; GFX1150-NEXT: ; %bb.10: ; %frem.else
+; GFX1150-NEXT: s_cbranch_vccz .LBB15_10
+; GFX1150-NEXT: ; %bb.9: ; %frem.else
; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
; GFX1150-NEXT: v_and_b32_e32 v6, 0x80000000, v3
; GFX1150-NEXT: s_mov_b32 s2, 0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
; GFX1150-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
-; GFX1150-NEXT: s_branch .LBB15_12
-; GFX1150-NEXT: .LBB15_11:
+; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1150-NEXT: s_cbranch_scc1 .LBB15_11
+; GFX1150-NEXT: s_branch .LBB15_16
+; GFX1150-NEXT: .LBB15_10:
; GFX1150-NEXT: s_mov_b32 s2, -1
; GFX1150-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX1150-NEXT: .LBB15_12: ; %Flow48
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1150-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-NEXT: s_cbranch_scc1 .LBB15_18
-; GFX1150-NEXT: ; %bb.13: ; %frem.compute
+; GFX1150-NEXT: s_cbranch_scc0 .LBB15_16
+; GFX1150-NEXT: .LBB15_11: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -19270,10 +19064,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: v_readfirstlane_b32 s2, v8
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX1150-NEXT: s_cbranch_vccnz .LBB15_17
-; GFX1150-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB15_15
+; GFX1150-NEXT: ; %bb.12: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_add_i32 s2, s2, 25
-; GFX1150-NEXT: .LBB15_15: ; %frem.loop_body
+; GFX1150-NEXT: .LBB15_13: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
@@ -19288,11 +19082,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB15_15
-; GFX1150-NEXT: ; %bb.16: ; %Flow
+; GFX1150-NEXT: s_cbranch_scc1 .LBB15_13
+; GFX1150-NEXT: ; %bb.14: ; %Flow
; GFX1150-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
; GFX1150-NEXT: v_mov_b32_e32 v6, v8
-; GFX1150-NEXT: .LBB15_17: ; %frem.loop_exit
+; GFX1150-NEXT: .LBB15_15: ; %frem.loop_exit
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
@@ -19305,7 +19099,7 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
-; GFX1150-NEXT: .LBB15_18: ; %Flow49
+; GFX1150-NEXT: .LBB15_16: ; %Flow49
; GFX1150-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
; GFX1150-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v5 :: v_dual_cndmask_b32 v0, 0, v4
; GFX1150-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
@@ -19332,17 +19126,16 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX1200-NEXT: s_branch .LBB15_3
+; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB15_3
+; GFX1200-NEXT: s_branch .LBB15_8
; GFX1200-NEXT: .LBB15_2:
; GFX1200-NEXT: s_mov_b32 s2, -1
; GFX1200-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX1200-NEXT: .LBB15_3: ; %Flow52
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1200-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB15_9
-; GFX1200-NEXT: ; %bb.4: ; %frem.compute15
+; GFX1200-NEXT: s_cbranch_scc0 .LBB15_8
+; GFX1200-NEXT: .LBB15_3: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -19351,10 +19144,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: v_readfirstlane_b32 s2, v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
-; GFX1200-NEXT: s_cbranch_vccnz .LBB15_8
-; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB15_7
+; GFX1200-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_add_co_i32 s2, s2, 25
-; GFX1200-NEXT: .LBB15_6: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB15_5: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1200-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
@@ -19370,11 +19163,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB15_6
-; GFX1200-NEXT: ; %bb.7: ; %Flow50
+; GFX1200-NEXT: s_cbranch_scc1 .LBB15_5
+; GFX1200-NEXT: ; %bb.6: ; %Flow50
; GFX1200-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
; GFX1200-NEXT: v_mov_b32_e32 v4, v6
-; GFX1200-NEXT: .LBB15_8: ; %frem.loop_exit24
+; GFX1200-NEXT: .LBB15_7: ; %frem.loop_exit24
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
@@ -19388,12 +19181,12 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX1200-NEXT: .LBB15_9:
+; GFX1200-NEXT: .LBB15_8:
; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cbranch_vccz .LBB15_11
-; GFX1200-NEXT: ; %bb.10: ; %frem.else
+; GFX1200-NEXT: s_cbranch_vccz .LBB15_10
+; GFX1200-NEXT: ; %bb.9: ; %frem.else
; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
; GFX1200-NEXT: v_and_b32_e32 v6, 0x80000000, v3
; GFX1200-NEXT: s_mov_b32 s2, 0
@@ -19401,18 +19194,17 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
-; GFX1200-NEXT: s_branch .LBB15_12
-; GFX1200-NEXT: .LBB15_11:
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1200-NEXT: s_cbranch_scc1 .LBB15_11
+; GFX1200-NEXT: s_branch .LBB15_16
+; GFX1200-NEXT: .LBB15_10:
; GFX1200-NEXT: s_mov_b32 s2, -1
; GFX1200-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX1200-NEXT: .LBB15_12: ; %Flow48
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1200-NEXT: s_cbranch_scc1 .LBB15_18
-; GFX1200-NEXT: ; %bb.13: ; %frem.compute
+; GFX1200-NEXT: s_cbranch_scc0 .LBB15_16
+; GFX1200-NEXT: .LBB15_11: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -19421,10 +19213,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: v_readfirstlane_b32 s2, v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX1200-NEXT: s_cbranch_vccnz .LBB15_17
-; GFX1200-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB15_15
+; GFX1200-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 25
-; GFX1200-NEXT: .LBB15_15: ; %frem.loop_body
+; GFX1200-NEXT: .LBB15_13: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
@@ -19441,11 +19234,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB15_15
-; GFX1200-NEXT: ; %bb.16: ; %Flow
+; GFX1200-NEXT: s_cbranch_scc1 .LBB15_13
+; GFX1200-NEXT: ; %bb.14: ; %Flow
; GFX1200-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
; GFX1200-NEXT: v_mov_b32_e32 v6, v8
-; GFX1200-NEXT: .LBB15_17: ; %frem.loop_exit
+; GFX1200-NEXT: .LBB15_15: ; %frem.loop_exit
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
@@ -19459,7 +19252,7 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
-; GFX1200-NEXT: .LBB15_18: ; %Flow49
+; GFX1200-NEXT: .LBB15_16: ; %Flow49
; GFX1200-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v5 :: v_dual_cndmask_b32 v0, 0, v4
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index e95e1763ce30a6..621d0dedb463fe 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -7649,150 +7649,74 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; EG-NEXT: MOV T20.W, T20.Z,
; EG-NEXT: MOV * T14.W, T14.Z,
; EG-NEXT: 28(3.923636e-44), 0(0.000000e+00)
-
-; GFX12-TRUE16-LABEL: constant_sextload_v16i1_to_v16i64:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v32, 0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v32, s[2:3]
-; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
-; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s3, 14
-; GFX12-TRUE16-NEXT: s_lshr_b32 s6, s3, 15
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v28, s3 :: v_dual_mov_b32 v1, s5
-; GFX12-TRUE16-NEXT: s_lshr_b32 s10, s3, 13
-; GFX12-TRUE16-NEXT: s_lshr_b32 s12, s3, 10
-; GFX12-TRUE16-NEXT: s_lshr_b32 s14, s3, 11
-; GFX12-TRUE16-NEXT: s_lshr_b32 s8, s3, 12
-; GFX12-TRUE16-NEXT: s_lshr_b32 s16, s3, 8
-; GFX12-TRUE16-NEXT: s_lshr_b32 s18, s3, 9
-; GFX12-TRUE16-NEXT: s_lshr_b32 s20, s3, 6
-; GFX12-TRUE16-NEXT: s_lshr_b32 s22, s3, 7
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX12-TRUE16-NEXT: s_lshr_b32 s24, s3, 4
-; GFX12-TRUE16-NEXT: s_lshr_b32 s26, s3, 5
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX12-TRUE16-NEXT: s_lshr_b32 s28, s3, 2
-; GFX12-TRUE16-NEXT: s_lshr_b32 s30, s3, 3
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v5, s9
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v9, s13
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v13, s17
-; GFX12-TRUE16-NEXT: v_bfe_i32 v28, v28, 0, 1
-; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s3, 1
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v7, s11
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v15, s19
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v14, s18 :: v_dual_mov_b32 v17, s21
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v16, s20 :: v_dual_mov_b32 v19, s23
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v18, s22 :: v_dual_mov_b32 v21, s25
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v20, s24 :: v_dual_mov_b32 v23, s27
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v22, s26 :: v_dual_mov_b32 v25, s29
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v24, s28 :: v_dual_mov_b32 v27, s31
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v26, s30 :: v_dual_mov_b32 v31, s3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v30, s2
-; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: global_store_b128 v32, v[0:3], s[0:1] offset:112
-; GFX12-TRUE16-NEXT: global_store_b128 v32, v[4:7], s[0:1] offset:96
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v29, 31, v28
-; GFX12-TRUE16-NEXT: s_clause 0x5
-; GFX12-TRUE16-NEXT: global_store_b128 v32, v[8:11], s[0:1] offset:80
-; GFX12-TRUE16-NEXT: global_store_b128 v32, v[12:15], s[0:1] offset:64
-; GFX12-TRUE16-NEXT: global_store_b128 v32, v[16:19], s[0:1] offset:48
-; GFX12-TRUE16-NEXT: global_store_b128 v32, v[20:23], s[0:1] offset:32
-; GFX12-TRUE16-NEXT: global_store_b128 v32, v[24:27], s[0:1] offset:16
-; GFX12-TRUE16-NEXT: global_store_b128 v32, v[28:31], s[0:1]
-; GFX12-TRUE16-NEXT: s_endpgm
-
-; GFX12-FAKE16-LABEL: constant_sextload_v16i1_to_v16i64:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v32, 0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: global_load_u16 v0, v32, s[2:3]
-; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-FAKE16-NEXT: v_readfirstlane_b32 s3, v0
-; GFX12-FAKE16-NEXT: s_lshr_b32 s4, s3, 14
-; GFX12-FAKE16-NEXT: s_lshr_b32 s6, s3, 15
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v28, s3 :: v_dual_mov_b32 v1, s5
-; GFX12-FAKE16-NEXT: s_lshr_b32 s10, s3, 13
-; GFX12-FAKE16-NEXT: s_lshr_b32 s12, s3, 10
-; GFX12-FAKE16-NEXT: s_lshr_b32 s14, s3, 11
-; GFX12-FAKE16-NEXT: s_lshr_b32 s8, s3, 12
-; GFX12-FAKE16-NEXT: s_lshr_b32 s16, s3, 8
-; GFX12-FAKE16-NEXT: s_lshr_b32 s18, s3, 9
-; GFX12-FAKE16-NEXT: s_lshr_b32 s20, s3, 6
-; GFX12-FAKE16-NEXT: s_lshr_b32 s22, s3, 7
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX12-FAKE16-NEXT: s_lshr_b32 s24, s3, 4
-; GFX12-FAKE16-NEXT: s_lshr_b32 s26, s3, 5
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX12-FAKE16-NEXT: s_lshr_b32 s28, s3, 2
-; GFX12-FAKE16-NEXT: s_lshr_b32 s30, s3, 3
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v5, s9
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v9, s13
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v13, s17
-; GFX12-FAKE16-NEXT: v_bfe_i32 v28, v28, 0, 1
-; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s3, 1
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v7, s11
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v15, s19
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v14, s18 :: v_dual_mov_b32 v17, s21
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v16, s20 :: v_dual_mov_b32 v19, s23
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v18, s22 :: v_dual_mov_b32 v21, s25
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v20, s24 :: v_dual_mov_b32 v23, s27
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v22, s26 :: v_dual_mov_b32 v25, s29
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v24, s28 :: v_dual_mov_b32 v27, s31
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_dual_mov_b32 v26, s30 :: v_dual_mov_b32 v31, s3
-; GFX12-FAKE16-NEXT: v_mov_b32_e32 v30, s2
-; GFX12-FAKE16-NEXT: s_clause 0x1
-; GFX12-FAKE16-NEXT: global_store_b128 v32, v[0:3], s[0:1] offset:112
-; GFX12-FAKE16-NEXT: global_store_b128 v32, v[4:7], s[0:1] offset:96
-; GFX12-FAKE16-NEXT: v_ashrrev_i32_e32 v29, 31, v28
-; GFX12-FAKE16-NEXT: s_clause 0x5
-; GFX12-FAKE16-NEXT: global_store_b128 v32, v[8:11], s[0:1] offset:80
-; GFX12-FAKE16-NEXT: global_store_b128 v32, v[12:15], s[0:1] offset:64
-; GFX12-FAKE16-NEXT: global_store_b128 v32, v[16:19], s[0:1] offset:48
-; GFX12-FAKE16-NEXT: global_store_b128 v32, v[20:23], s[0:1] offset:32
-; GFX12-FAKE16-NEXT: global_store_b128 v32, v[24:27], s[0:1] offset:16
-; GFX12-FAKE16-NEXT: global_store_b128 v32, v[28:31], s[0:1]
-; GFX12-FAKE16-NEXT: s_endpgm
-
-
+;
+; GFX12-LABEL: constant_sextload_v16i1_to_v16i64:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_u16 s2, s[2:3], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_lshr_b32 s6, s2, 14
+; GFX12-NEXT: s_lshr_b32 s8, s2, 15
+; GFX12-NEXT: s_lshr_b32 s10, s2, 12
+; GFX12-NEXT: s_lshr_b32 s12, s2, 13
+; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX12-NEXT: s_lshr_b32 s14, s2, 10
+; GFX12-NEXT: s_lshr_b32 s16, s2, 11
+; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v1, s7
+; GFX12-NEXT: s_lshr_b32 s18, s2, 8
+; GFX12-NEXT: s_lshr_b32 s20, s2, 9
+; GFX12-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v3, s9
+; GFX12-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
+; GFX12-NEXT: s_lshr_b32 s22, s2, 6
+; GFX12-NEXT: s_lshr_b32 s24, s2, 7
+; GFX12-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v4, s10 :: v_dual_mov_b32 v7, s13
+; GFX12-NEXT: v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v9, s15
+; GFX12-NEXT: s_lshr_b32 s26, s2, 4
+; GFX12-NEXT: s_lshr_b32 s28, s2, 5
+; GFX12-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX12-NEXT: s_lshr_b32 s30, s2, 2
+; GFX12-NEXT: s_lshr_b32 s34, s2, 3
+; GFX12-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v11, s17
+; GFX12-NEXT: v_dual_mov_b32 v10, s16 :: v_dual_mov_b32 v13, s19
+; GFX12-NEXT: s_lshr_b32 s36, s2, 1
+; GFX12-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v12, s18 :: v_dual_mov_b32 v15, s21
+; GFX12-NEXT: v_mov_b32_e32 v14, s20
+; GFX12-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:112
+; GFX12-NEXT: global_store_b128 v24, v[4:7], s[0:1] offset:96
+; GFX12-NEXT: v_dual_mov_b32 v0, s22 :: v_dual_mov_b32 v3, s25
+; GFX12-NEXT: v_dual_mov_b32 v1, s23 :: v_dual_mov_b32 v2, s24
+; GFX12-NEXT: v_mov_b32_e32 v5, s27
+; GFX12-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
+; GFX12-NEXT: s_bfe_i64 s[2:3], s[36:37], 0x10000
+; GFX12-NEXT: v_dual_mov_b32 v4, s26 :: v_dual_mov_b32 v7, s29
+; GFX12-NEXT: v_dual_mov_b32 v6, s28 :: v_dual_mov_b32 v17, s31
+; GFX12-NEXT: v_dual_mov_b32 v16, s30 :: v_dual_mov_b32 v19, s35
+; GFX12-NEXT: v_dual_mov_b32 v18, s34 :: v_dual_mov_b32 v21, s5
+; GFX12-NEXT: v_dual_mov_b32 v20, s4 :: v_dual_mov_b32 v23, s3
+; GFX12-NEXT: v_mov_b32_e32 v22, s2
+; GFX12-NEXT: s_clause 0x5
+; GFX12-NEXT: global_store_b128 v24, v[8:11], s[0:1] offset:80
+; GFX12-NEXT: global_store_b128 v24, v[12:15], s[0:1] offset:64
+; GFX12-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:48
+; GFX12-NEXT: global_store_b128 v24, v[4:7], s[0:1] offset:32
+; GFX12-NEXT: global_store_b128 v24, v[16:19], s[0:1] offset:16
+; GFX12-NEXT: global_store_b128 v24, v[20:23], s[0:1]
+; GFX12-NEXT: s_endpgm
+;
; GFX1250-LABEL: constant_sextload_v16i1_to_v16i64:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -7801,67 +7725,74 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: global_load_u16 v0, v32, s[2:3] nv
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_readfirstlane_b32 s3, v0
-; GFX1250-NEXT: s_lshr_b32 s4, s3, 14
-; GFX1250-NEXT: s_lshr_b32 s6, s3, 15
-; GFX1250-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v28, s3 :: v_dual_mov_b32 v0, s4
-; GFX1250-NEXT: s_lshr_b32 s10, s3, 13
-; GFX1250-NEXT: s_lshr_b32 s12, s3, 10
-; GFX1250-NEXT: s_lshr_b32 s14, s3, 11
-; GFX1250-NEXT: s_lshr_b32 s8, s3, 12
-; GFX1250-NEXT: s_lshr_b32 s16, s3, 8
-; GFX1250-NEXT: s_lshr_b32 s18, s3, 9
-; GFX1250-NEXT: s_lshr_b32 s20, s3, 6
-; GFX1250-NEXT: s_lshr_b32 s22, s3, 7
-; GFX1250-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX1250-NEXT: s_load_u16 s2, s[2:3], 0x0 nv
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_lshr_b32 s6, s2, 14
+; GFX1250-NEXT: s_lshr_b32 s8, s2, 15
+; GFX1250-NEXT: s_lshr_b32 s10, s2, 12
+; GFX1250-NEXT: s_lshr_b32 s12, s2, 13
+; GFX1250-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX1250-NEXT: s_lshr_b32 s14, s2, 10
+; GFX1250-NEXT: s_lshr_b32 s16, s2, 11
; GFX1250-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
; GFX1250-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX1250-NEXT: s_lshr_b32 s24, s3, 4
-; GFX1250-NEXT: s_lshr_b32 s26, s3, 5
-; GFX1250-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v0, s6
+; GFX1250-NEXT: s_lshr_b32 s18, s2, 8
+; GFX1250-NEXT: s_lshr_b32 s20, s2, 9
+; GFX1250-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_mov_b32 v2, s8
+; GFX1250-NEXT: v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
+; GFX1250-NEXT: s_lshr_b32 s22, s2, 6
+; GFX1250-NEXT: s_lshr_b32 s24, s2, 7
; GFX1250-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX1250-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX1250-NEXT: s_lshr_b32 s28, s3, 2
-; GFX1250-NEXT: s_lshr_b32 s30, s3, 3
-; GFX1250-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v6, s12
+; GFX1250-NEXT: v_dual_mov_b32 v7, s13 :: v_dual_mov_b32 v8, s14
+; GFX1250-NEXT: s_lshr_b32 s26, s2, 4
+; GFX1250-NEXT: s_lshr_b32 s28, s2, 5
; GFX1250-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
-; GFX1250-NEXT: v_dual_mov_b32 v3, s7 :: v_dual_mov_b32 v4, s8
-; GFX1250-NEXT: v_dual_mov_b32 v7, s11 :: v_dual_mov_b32 v8, s12
-; GFX1250-NEXT: v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
-; GFX1250-NEXT: v_dual_mov_b32 v11, s15 :: v_dual_mov_b32 v12, s16
-; GFX1250-NEXT: v_bfe_i32 v28, v28, 0, 1
-; GFX1250-NEXT: s_lshr_b32 s2, s3, 1
-; GFX1250-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX1250-NEXT: s_lshr_b32 s30, s2, 2
+; GFX1250-NEXT: s_lshr_b32 s34, s2, 3
; GFX1250-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v5, s9 :: v_dual_mov_b32 v6, s10
-; GFX1250-NEXT: v_dual_mov_b32 v13, s17 :: v_dual_mov_b32 v14, s18
-; GFX1250-NEXT: v_dual_mov_b32 v15, s19 :: v_dual_mov_b32 v16, s20
-; GFX1250-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v9, s15 :: v_dual_mov_b32 v10, s16
+; GFX1250-NEXT: v_dual_mov_b32 v11, s17 :: v_dual_mov_b32 v12, s18
+; GFX1250-NEXT: s_lshr_b32 s36, s2, 1
; GFX1250-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v17, s21 :: v_dual_mov_b32 v18, s22
-; GFX1250-NEXT: v_dual_mov_b32 v19, s23 :: v_dual_mov_b32 v20, s24
-; GFX1250-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX1250-NEXT: v_dual_mov_b32 v21, s25 :: v_dual_mov_b32 v22, s26
-; GFX1250-NEXT: v_dual_mov_b32 v23, s27 :: v_dual_mov_b32 v24, s28
-; GFX1250-NEXT: v_dual_mov_b32 v25, s29 :: v_dual_mov_b32 v26, s30
-; GFX1250-NEXT: v_dual_mov_b32 v27, s31 :: v_dual_mov_b32 v30, s2
-; GFX1250-NEXT: v_dual_mov_b32 v31, s3 :: v_dual_ashrrev_i32 v29, 31, v28
-; GFX1250-NEXT: s_clause 0x7
-; GFX1250-NEXT: global_store_b128 v32, v[0:3], s[0:1] offset:112
-; GFX1250-NEXT: global_store_b128 v32, v[4:7], s[0:1] offset:96
-; GFX1250-NEXT: global_store_b128 v32, v[8:11], s[0:1] offset:80
-; GFX1250-NEXT: global_store_b128 v32, v[12:15], s[0:1] offset:64
-; GFX1250-NEXT: global_store_b128 v32, v[16:19], s[0:1] offset:48
-; GFX1250-NEXT: global_store_b128 v32, v[20:23], s[0:1] offset:32
-; GFX1250-NEXT: global_store_b128 v32, v[24:27], s[0:1] offset:16
-; GFX1250-NEXT: global_store_b128 v32, v[28:31], s[0:1]
+; GFX1250-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v13, s19 :: v_dual_mov_b32 v14, s20
+; GFX1250-NEXT: v_mov_b32_e32 v15, s21
+; GFX1250-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX1250-NEXT: s_clause 0x1
+; GFX1250-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:112
+; GFX1250-NEXT: global_store_b128 v24, v[4:7], s[0:1] offset:96
+; GFX1250-NEXT: s_wait_xcnt 0x1
+; GFX1250-NEXT: v_dual_mov_b32 v0, s22 :: v_dual_mov_b32 v1, s23
+; GFX1250-NEXT: v_dual_mov_b32 v2, s24 :: v_dual_mov_b32 v3, s25
+; GFX1250-NEXT: s_wait_xcnt 0x0
+; GFX1250-NEXT: v_mov_b32_e32 v4, s26
+; GFX1250-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
+; GFX1250-NEXT: s_bfe_i64 s[2:3], s[36:37], 0x10000
+; GFX1250-NEXT: v_dual_mov_b32 v5, s27 :: v_dual_mov_b32 v6, s28
+; GFX1250-NEXT: v_dual_mov_b32 v7, s29 :: v_dual_mov_b32 v16, s30
+; GFX1250-NEXT: v_dual_mov_b32 v17, s31 :: v_dual_mov_b32 v18, s34
+; GFX1250-NEXT: v_dual_mov_b32 v19, s35 :: v_dual_mov_b32 v20, s4
+; GFX1250-NEXT: v_dual_mov_b32 v21, s5 :: v_dual_mov_b32 v22, s2
+; GFX1250-NEXT: v_mov_b32_e32 v23, s3
+; GFX1250-NEXT: s_clause 0x5
+; GFX1250-NEXT: global_store_b128 v24, v[8:11], s[0:1] offset:80
+; GFX1250-NEXT: global_store_b128 v24, v[12:15], s[0:1] offset:64
+; GFX1250-NEXT: global_store_b128 v24, v[0:3], s[0:1] offset:48
+; GFX1250-NEXT: global_store_b128 v24, v[4:7], s[0:1] offset:32
+; GFX1250-NEXT: global_store_b128 v24, v[16:19], s[0:1] offset:16
+; GFX1250-NEXT: global_store_b128 v24, v[20:23], s[0:1]
; GFX1250-NEXT: s_endpgm
+
+
+
+
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = sext <16 x i1> %load to <16 x i64>
store <16 x i64> %ext, ptr addrspace(1) %out
>From 71b93ca249ca6650fbecdea466f3f1679095e4dc Mon Sep 17 00:00:00 2001
From: John Lu <John.Lu at amd.com>
Date: Fri, 2 Oct 2026 09:50:58 -0500
Subject: [PATCH 7/7] Update tests
Signed-off-by: John Lu <John.Lu at amd.com>
---
llvm/test/CodeGen/AMDGPU/frem.ll | 13054 +++++++---------
.../CodeGen/AMDGPU/itofp-odd-width-load.ll | 34 +-
2 files changed, 5860 insertions(+), 7228 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 267e722b406193..f26e177173bd8e 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -28,41 +28,28 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e64 v4, |v1|
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v4
-; SI-NEXT: s_cbranch_vccz .LBB0_2
-; SI-NEXT: ; %bb.1: ; %frem.else
-; SI-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v4
-; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc1 .LBB0_3
-; SI-NEXT: s_branch .LBB0_8
-; SI-NEXT: .LBB0_2:
-; SI-NEXT: s_mov_b64 s[0:1], -1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc0 .LBB0_8
-; SI-NEXT: .LBB0_3: ; %frem.compute
+; SI-NEXT: v_cvt_f32_f16_e64 v2, |v1|
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
+; SI-NEXT: s_cbranch_vccz .LBB0_4
+; SI-NEXT: ; %bb.1: ; %frem.compute
; SI-NEXT: s_mov_b32 s3, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v3
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v4
+; SI-NEXT: v_frexp_mant_f32_e32 v4, v3
+; SI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s3
+; SI-NEXT: v_frexp_mant_f32_e32 v4, v2
+; SI-NEXT: s_cselect_b32 s2, s0, 0
+; SI-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: v_frexp_mant_f32_e32 v2, v3
-; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; SI-NEXT: v_ldexp_f32_e64 v3, v2, 11
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s3
-; SI-NEXT: v_frexp_mant_f32_e32 v2, v4
-; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NEXT: v_ldexp_f32_e64 v2, v2, 1
+; SI-NEXT: v_ldexp_f32_e64 v2, v4, 1
; SI-NEXT: v_div_scale_f32 v5, s[4:5], v2, v2, 1.0
; SI-NEXT: v_rcp_f32_e32 v6, v5
-; SI-NEXT: s_cselect_b32 s2, s0, 0
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v4
+; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
; SI-NEXT: v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT: v_fma_f32 v7, -v5, v6, 1.0
@@ -79,11 +66,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB0_7
-; SI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB0_5
+; SI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s1, s2, s3
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB0_5: ; %frem.loop_body
+; SI-NEXT: .LBB0_3: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v5, v3
; SI-NEXT: v_mul_f32_e32 v3, v5, v4
@@ -95,12 +82,18 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB0_5
-; SI-NEXT: ; %bb.6: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v3, v5
-; SI-NEXT: .LBB0_7: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB0_3
+; SI-NEXT: s_branch .LBB0_6
+; SI-NEXT: .LBB0_4: ; %frem.else
+; SI-NEXT: v_and_b32_e32 v4, 0x8000, v0
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
+; SI-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc
+; SI-NEXT: s_branch .LBB0_7
+; SI-NEXT: .LBB0_5:
+; SI-NEXT: v_mov_b32_e32 v5, v3
+; SI-NEXT: .LBB0_6: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s1, s1, -10
-; SI-NEXT: v_ldexp_f32_e64 v3, v3, s1
+; SI-NEXT: v_ldexp_f32_e64 v3, v5, s1
; SI-NEXT: v_mul_f32_e32 v4, v3, v4
; SI-NEXT: v_rndne_f32_e32 v4, v4
; SI-NEXT: v_fma_f32 v3, -v4, v2, v3
@@ -112,7 +105,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_and_b32_e32 v3, 0x8000, v0
; SI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: .LBB0_8: ; %Flow19
+; SI-NEXT: .LBB0_7:
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; SI-NEXT: s_mov_b32 s0, 0x7f800000
@@ -140,71 +133,64 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; CI-NEXT: buffer_load_ushort v1, off, s[0:3], 0 offset:8
; CI-NEXT: s_waitcnt vmcnt(1)
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |v0|
+; CI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e64 v3, |v1|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
-; CI-NEXT: s_cbranch_vccz .LBB0_2
-; CI-NEXT: ; %bb.1: ; %frem.else
-; CI-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
-; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc1 .LBB0_3
-; CI-NEXT: s_branch .LBB0_8
-; CI-NEXT: .LBB0_2:
-; CI-NEXT: s_mov_b64 s[0:1], -1
-; CI-NEXT: ; implicit-def: $vgpr2
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc0 .LBB0_8
-; CI-NEXT: .LBB0_3: ; %frem.compute
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
-; CI-NEXT: v_frexp_mant_f32_e32 v2, v4
-; CI-NEXT: v_frexp_mant_f32_e32 v4, v3
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
-; CI-NEXT: v_ldexp_f32_e64 v3, v4, 1
+; CI-NEXT: v_cvt_f32_f16_e64 v2, |v1|
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
+; CI-NEXT: s_cbranch_vccz .LBB0_4
+; CI-NEXT: ; %bb.1: ; %frem.compute
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
+; CI-NEXT: v_frexp_mant_f32_e32 v3, v3
+; CI-NEXT: v_ldexp_f32_e64 v6, v3, 11
+; CI-NEXT: v_frexp_mant_f32_e32 v3, v2
+; CI-NEXT: v_ldexp_f32_e64 v3, v3, 1
; CI-NEXT: v_div_scale_f32 v9, s[0:1], v3, v3, 1.0
-; CI-NEXT: v_ldexp_f32_e64 v5, v2, 11
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8
; CI-NEXT: v_not_b32_e32 v4, v2
; CI-NEXT: v_add_i32_e32 v4, vcc, v4, v7
-; CI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; CI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; CI-NEXT: v_rcp_f32_e32 v10, v9
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; CI-NEXT: v_fma_f32 v10, v11, v10, v10
-; CI-NEXT: v_mul_f32_e32 v11, v6, v10
-; CI-NEXT: v_fma_f32 v12, -v9, v11, v6
+; CI-NEXT: v_mul_f32_e32 v11, v5, v10
+; CI-NEXT: v_fma_f32 v12, -v9, v11, v5
; CI-NEXT: v_fma_f32 v11, v12, v10, v11
-; CI-NEXT: v_fma_f32 v6, -v9, v11, v6
+; CI-NEXT: v_fma_f32 v5, -v9, v11, v5
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
+; CI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB0_7
-; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB0_5
+; CI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT: v_add_i32_e32 v4, vcc, 11, v4
-; CI-NEXT: .LBB0_5: ; %frem.loop_body
+; CI-NEXT: .LBB0_3: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v5
-; CI-NEXT: v_mul_f32_e32 v5, v7, v6
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v5, -v5, v3, v7
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v8, v5, v3
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; CI-NEXT: v_mov_b32_e32 v7, v6
+; CI-NEXT: v_mul_f32_e32 v6, v7, v5
+; CI-NEXT: v_rndne_f32_e32 v6, v6
+; CI-NEXT: v_fma_f32 v6, -v6, v3, v7
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; CI-NEXT: v_add_f32_e32 v8, v6, v3
+; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
+; CI-NEXT: v_ldexp_f32_e64 v6, v6, 11
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11
-; CI-NEXT: s_cbranch_vccnz .LBB0_5
-; CI-NEXT: ; %bb.6: ; %Flow
-; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: .LBB0_7: ; %frem.loop_exit
+; CI-NEXT: s_cbranch_vccnz .LBB0_3
+; CI-NEXT: s_branch .LBB0_6
+; CI-NEXT: .LBB0_4: ; %frem.else
+; CI-NEXT: v_and_b32_e32 v4, 0x8000, v0
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
+; CI-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc
+; CI-NEXT: s_branch .LBB0_7
+; CI-NEXT: .LBB0_5:
+; CI-NEXT: v_mov_b32_e32 v7, v6
+; CI-NEXT: .LBB0_6: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v4, vcc, -10, v4
-; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
-; CI-NEXT: v_mul_f32_e32 v5, v4, v6
+; CI-NEXT: v_ldexp_f32_e32 v4, v7, v4
+; CI-NEXT: v_mul_f32_e32 v5, v4, v5
; CI-NEXT: v_rndne_f32_e32 v5, v5
; CI-NEXT: v_fma_f32 v4, -v5, v3, v4
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -215,7 +201,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_and_b32_e32 v3, 0x8000, v0
; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; CI-NEXT: v_or_b32_e32 v2, v2, v3
-; CI-NEXT: .LBB0_8: ; %Flow19
+; CI-NEXT: .LBB0_7:
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; CI-NEXT: s_mov_b32 s0, 0x7f800000
@@ -243,71 +229,64 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_mov_b32_e32 v2, s3
; VI-NEXT: flat_load_ushort v1, v[1:2]
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_cvt_f32_f16_e64 v4, |v0|
+; VI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e64 v3, |v1|
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
-; VI-NEXT: s_cbranch_vccz .LBB0_2
-; VI-NEXT: ; %bb.1: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
-; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB0_3
-; VI-NEXT: s_branch .LBB0_8
-; VI-NEXT: .LBB0_2:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr2
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB0_8
-; VI-NEXT: .LBB0_3: ; %frem.compute
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
-; VI-NEXT: v_frexp_mant_f32_e32 v2, v4
-; VI-NEXT: v_frexp_mant_f32_e32 v4, v3
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
-; VI-NEXT: v_ldexp_f32 v3, v4, 1
+; VI-NEXT: v_cvt_f32_f16_e64 v2, |v1|
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
+; VI-NEXT: s_cbranch_vccz .LBB0_4
+; VI-NEXT: ; %bb.1: ; %frem.compute
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
+; VI-NEXT: v_frexp_mant_f32_e32 v3, v3
+; VI-NEXT: v_ldexp_f32 v6, v3, 11
+; VI-NEXT: v_frexp_mant_f32_e32 v3, v2
+; VI-NEXT: v_ldexp_f32 v3, v3, 1
; VI-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
-; VI-NEXT: v_ldexp_f32 v5, v2, 11
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT: v_not_b32_e32 v4, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v7
-; VI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; VI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; VI-NEXT: v_rcp_f32_e32 v10, v9
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT: v_fma_f32 v10, v11, v10, v10
-; VI-NEXT: v_mul_f32_e32 v11, v6, v10
-; VI-NEXT: v_fma_f32 v12, -v9, v11, v6
+; VI-NEXT: v_mul_f32_e32 v11, v5, v10
+; VI-NEXT: v_fma_f32 v12, -v9, v11, v5
; VI-NEXT: v_fma_f32 v11, v12, v10, v11
-; VI-NEXT: v_fma_f32 v6, -v9, v11, v6
+; VI-NEXT: v_fma_f32 v5, -v9, v11, v5
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
+; VI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; VI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB0_7
-; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB0_5
+; VI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT: v_add_u32_e32 v4, vcc, 11, v4
-; VI-NEXT: .LBB0_5: ; %frem.loop_body
+; VI-NEXT: .LBB0_3: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v5
-; VI-NEXT: v_mul_f32_e32 v5, v7, v6
-; VI-NEXT: v_rndne_f32_e32 v5, v5
-; VI-NEXT: v_fma_f32 v5, -v5, v3, v7
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; VI-NEXT: v_add_f32_e32 v8, v5, v3
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; VI-NEXT: v_mov_b32_e32 v7, v6
+; VI-NEXT: v_mul_f32_e32 v6, v7, v5
+; VI-NEXT: v_rndne_f32_e32 v6, v6
+; VI-NEXT: v_fma_f32 v6, -v6, v3, v7
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; VI-NEXT: v_add_f32_e32 v8, v6, v3
+; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
+; VI-NEXT: v_ldexp_f32 v6, v6, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; VI-NEXT: v_ldexp_f32 v5, v5, 11
-; VI-NEXT: s_cbranch_vccnz .LBB0_5
-; VI-NEXT: ; %bb.6: ; %Flow
-; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: .LBB0_7: ; %frem.loop_exit
+; VI-NEXT: s_cbranch_vccnz .LBB0_3
+; VI-NEXT: s_branch .LBB0_6
+; VI-NEXT: .LBB0_4: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v4, 0x8000, v0
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
+; VI-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc
+; VI-NEXT: s_branch .LBB0_7
+; VI-NEXT: .LBB0_5:
+; VI-NEXT: v_mov_b32_e32 v7, v6
+; VI-NEXT: .LBB0_6: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v4, vcc, -10, v4
-; VI-NEXT: v_ldexp_f32 v4, v5, v4
-; VI-NEXT: v_mul_f32_e32 v5, v4, v6
+; VI-NEXT: v_ldexp_f32 v4, v7, v4
+; VI-NEXT: v_mul_f32_e32 v5, v4, v5
; VI-NEXT: v_rndne_f32_e32 v5, v5
; VI-NEXT: v_fma_f32 v4, -v5, v3, v4
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -317,7 +296,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_cvt_f16_f32_e32 v2, v2
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; VI-NEXT: .LBB0_8: ; %Flow19
+; VI-NEXT: .LBB0_7:
; VI-NEXT: v_mov_b32_e32 v3, s0
; VI-NEXT: s_movk_i32 s0, 0x7c00
; VI-NEXT: v_mov_b32_e32 v4, s1
@@ -338,33 +317,20 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: global_load_ushort v0, v2, s[2:3]
; GFX9-NEXT: global_load_ushort v1, v2, s[6:7] offset:8
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v4, |v0|
+; GFX9-NEXT: v_cvt_f32_f16_e64 v3, |v0|
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v3, |v1|
-; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
-; GFX9-NEXT: s_cbranch_vccz .LBB0_2
-; GFX9-NEXT: ; %bb.1: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX9-NEXT: s_branch .LBB0_8
-; GFX9-NEXT: .LBB0_2:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr2
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB0_8
-; GFX9-NEXT: .LBB0_3: ; %frem.compute
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
-; GFX9-NEXT: v_frexp_mant_f32_e32 v2, v4
-; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v3
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
-; GFX9-NEXT: v_ldexp_f32 v3, v4, 1
+; GFX9-NEXT: v_cvt_f32_f16_e64 v2, |v1|
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
+; GFX9-NEXT: s_cbranch_vccz .LBB0_4
+; GFX9-NEXT: ; %bb.1: ; %frem.compute
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
+; GFX9-NEXT: v_frexp_mant_f32_e32 v3, v3
+; GFX9-NEXT: v_ldexp_f32 v6, v3, 11
+; GFX9-NEXT: v_frexp_mant_f32_e32 v3, v2
+; GFX9-NEXT: v_ldexp_f32 v3, v3, 1
; GFX9-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
-; GFX9-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
-; GFX9-NEXT: v_ldexp_f32 v5, v2, 11
+; GFX9-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
; GFX9-NEXT: v_add_u32_e32 v2, -1, v8
; GFX9-NEXT: v_not_b32_e32 v4, v2
; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
@@ -372,37 +338,43 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT: v_fma_f32 v10, v11, v10, v10
-; GFX9-NEXT: v_mul_f32_e32 v11, v6, v10
-; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v6
+; GFX9-NEXT: v_mul_f32_e32 v11, v5, v10
+; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v5
; GFX9-NEXT: v_fma_f32 v11, v12, v10, v11
-; GFX9-NEXT: v_fma_f32 v6, -v9, v11, v6
+; GFX9-NEXT: v_fma_f32 v5, -v9, v11, v5
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v6, v6, v10, v11
+; GFX9-NEXT: v_div_fmas_f32 v5, v5, v10, v11
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; GFX9-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB0_7
-; GFX9-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB0_5
+; GFX9-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT: v_add_u32_e32 v4, 11, v4
-; GFX9-NEXT: .LBB0_5: ; %frem.loop_body
+; GFX9-NEXT: .LBB0_3: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
-; GFX9-NEXT: v_mul_f32_e32 v5, v7, v6
-; GFX9-NEXT: v_rndne_f32_e32 v5, v5
-; GFX9-NEXT: v_fma_f32 v5, -v5, v3, v7
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; GFX9-NEXT: v_add_f32_e32 v8, v5, v3
+; GFX9-NEXT: v_mov_b32_e32 v7, v6
+; GFX9-NEXT: v_mul_f32_e32 v6, v7, v5
+; GFX9-NEXT: v_rndne_f32_e32 v6, v6
+; GFX9-NEXT: v_fma_f32 v6, -v6, v3, v7
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; GFX9-NEXT: v_add_f32_e32 v8, v6, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GFX9-NEXT: v_add_u32_e32 v4, -11, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX9-NEXT: v_ldexp_f32 v6, v6, 11
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; GFX9-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB0_5
-; GFX9-NEXT: ; %bb.6: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: .LBB0_7: ; %frem.loop_exit
+; GFX9-NEXT: s_cbranch_vccnz .LBB0_3
+; GFX9-NEXT: s_branch .LBB0_6
+; GFX9-NEXT: .LBB0_4: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v4, 0x8000, v0
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc
+; GFX9-NEXT: s_branch .LBB0_7
+; GFX9-NEXT: .LBB0_5:
+; GFX9-NEXT: v_mov_b32_e32 v7, v6
+; GFX9-NEXT: .LBB0_6: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v4, -10, v4
-; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
-; GFX9-NEXT: v_mul_f32_e32 v5, v4, v6
+; GFX9-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX9-NEXT: v_rndne_f32_e32 v5, v5
; GFX9-NEXT: v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -412,7 +384,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v2, s2, v2, v0
-; GFX9-NEXT: .LBB0_8: ; %Flow19
+; GFX9-NEXT: .LBB0_7:
; GFX9-NEXT: s_movk_i32 s2, 0x7c00
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v1
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v0|, s2
@@ -434,37 +406,24 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: global_load_ushort v0, v2, s[2:3]
; GFX10-NEXT: global_load_ushort v1, v2, s[6:7] offset:8
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v4, |v0|
+; GFX10-NEXT: v_cvt_f32_f16_e64 v3, |v0|
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v3, |v1|
-; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v3
-; GFX10-NEXT: s_cbranch_vccz .LBB0_2
-; GFX10-NEXT: ; %bb.1: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX10-NEXT: s_branch .LBB0_8
-; GFX10-NEXT: .LBB0_2:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr2
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB0_8
-; GFX10-NEXT: .LBB0_3: ; %frem.compute
-; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v4
-; GFX10-NEXT: v_frexp_mant_f32_e32 v6, v3
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; GFX10-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
-; GFX10-NEXT: v_ldexp_f32 v3, v6, 1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v2, |v1|
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
+; GFX10-NEXT: s_cbranch_vccz .LBB0_5
+; GFX10-NEXT: ; %bb.1: ; %frem.compute
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v3
+; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v3
; GFX10-NEXT: v_readfirstlane_b32 s2, v5
+; GFX10-NEXT: v_ldexp_f32 v4, v3, 11
+; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v2
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
+; GFX10-NEXT: v_ldexp_f32 v3, v3, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v2
-; GFX10-NEXT: v_div_scale_f32 v7, s4, v3, v3, 1.0
; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX10-NEXT: v_rcp_f32_e32 v8, v7
+; GFX10-NEXT: v_div_scale_f32 v7, s4, v3, v3, 1.0
; GFX10-NEXT: v_not_b32_e32 v6, v2
+; GFX10-NEXT: v_rcp_f32_e32 v8, v7
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -478,11 +437,11 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX10-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB0_7
-; GFX10-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB0_6
+; GFX10-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB0_5: ; %frem.loop_body
+; GFX10-NEXT: .LBB0_3: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -494,13 +453,20 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_add_f32_e32 v6, v4, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB0_5
-; GFX10-NEXT: ; %bb.6: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX10-NEXT: ; %bb.4:
; GFX10-NEXT: v_mov_b32_e32 v6, s2
-; GFX10-NEXT: v_mov_b32_e32 v4, v7
+; GFX10-NEXT: s_branch .LBB0_7
+; GFX10-NEXT: .LBB0_5: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v4, 0x8000, v0
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc_lo
+; GFX10-NEXT: s_branch .LBB0_8
+; GFX10-NEXT: .LBB0_6:
+; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX10-NEXT: v_add_nc_u32_e32 v4, -10, v6
+; GFX10-NEXT: v_ldexp_f32 v4, v7, v4
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX10-NEXT: v_rndne_f32_e32 v5, v5
; GFX10-NEXT: v_fma_f32 v4, -v5, v3, v4
@@ -510,7 +476,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_ldexp_f32 v2, v3, v2
; GFX10-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX10-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX10-NEXT: .LBB0_8: ; %Flow19
+; GFX10-NEXT: .LBB0_8:
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
; GFX10-NEXT: v_mov_b32_e32 v3, 0
@@ -530,42 +496,26 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] offset:8
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.h|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v3, v2
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB0_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX11-TRUE16-NEXT: s_branch .LBB0_7
-; GFX11-TRUE16-NEXT: .LBB0_2:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB0_7
-; GFX11-TRUE16-NEXT: .LBB0_3: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v3
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, v3
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v2
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB0_5
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.compute
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v2
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v4
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v2
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v3, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v4, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v3, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX11-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
@@ -584,12 +534,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_6
-; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_4
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB0_5: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB0_3: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -604,10 +554,16 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_5
-; GFX11-TRUE16-NEXT: .LBB0_6: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX11-TRUE16-NEXT: .LBB0_4: ; %frem.loop_exit
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX11-TRUE16-NEXT: .LBB0_7: ; %Flow19
+; GFX11-TRUE16-NEXT: s_branch .LBB0_6
+; GFX11-TRUE16-NEXT: .LBB0_5: ; %frem.else
+; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: .LBB0_6:
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.h
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
@@ -628,44 +584,29 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: global_load_u16 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: global_load_u16 v1, v1, s[4:5] offset:8
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v4, |v0|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, |v0|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, |v1|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v2, |v1|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v3
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB0_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.else
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX11-FAKE16-NEXT: s_branch .LBB0_8
-; GFX11-FAKE16-NEXT: .LBB0_2:
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB0_8
-; GFX11-FAKE16-NEXT: .LBB0_3: ; %frem.compute
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, v4
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v6, v3
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v6, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB0_5
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.compute
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v3
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v3, 11
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v2
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX11-FAKE16-NEXT: v_not_b32_e32 v6, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-FAKE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -684,12 +625,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB0_7
-; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB0_6
+; GFX11-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB0_5: ; %frem.loop_body
+; GFX11-FAKE16-NEXT: .LBB0_3: ; %frem.loop_body
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -705,14 +646,22 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB0_5
-; GFX11-FAKE16-NEXT: ; %bb.6: ; %Flow
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX11-FAKE16-NEXT: ; %bb.4:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-FAKE16-NEXT: s_branch .LBB0_7
+; GFX11-FAKE16-NEXT: .LBB0_5: ; %frem.else
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x8000, v0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB0_8
+; GFX11-FAKE16-NEXT: .LBB0_6:
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v4
; GFX11-FAKE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -726,7 +675,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX11-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX11-FAKE16-NEXT: .LBB0_8: ; %Flow19
+; GFX11-FAKE16-NEXT: .LBB0_8:
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -749,39 +698,22 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
; GFX1150-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s2, s1, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s1, s0
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s0, s2
+; GFX1150-TRUE16-NEXT: s_and_b32 s1, s1, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s0, s0
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s1, s1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s1, s0
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB0_2
-; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s1, s0
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v0.l
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s2
-; GFX1150-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX1150-TRUE16-NEXT: s_branch .LBB0_7
-; GFX1150-TRUE16-NEXT: .LBB0_2:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB0_7
-; GFX1150-TRUE16-NEXT: .LBB0_3: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
+; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s0, s1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB0_5
+; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s1
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s0
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v4
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -805,12 +737,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_6
-; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s0, s1, s0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_4
+; GFX1150-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s0, s0, s1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s0, s0, 11
-; GFX1150-TRUE16-NEXT: .LBB0_5: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: .LBB0_3: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -826,10 +758,17 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_5
-; GFX1150-TRUE16-NEXT: .LBB0_6: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX1150-TRUE16-NEXT: .LBB0_4: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB0_7: ; %Flow19
+; GFX1150-TRUE16-NEXT: s_branch .LBB0_6
+; GFX1150-TRUE16-NEXT: .LBB0_5: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s0, s1
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v0.l
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s0
+; GFX1150-TRUE16-NEXT: .LBB0_6:
; GFX1150-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1150-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
@@ -854,41 +793,25 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s1, v1
; GFX1150-FAKE16-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s2, s1, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s1, s0
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s0, s2
+; GFX1150-FAKE16-NEXT: s_and_b32 s1, s1, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s0, s0
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s1, s1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s1, s0
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB0_2
-; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.else
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s1, s0
-; GFX1150-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; GFX1150-FAKE16-NEXT: s_mov_b32 s2, 0
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX1150-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX1150-FAKE16-NEXT: s_branch .LBB0_8
-; GFX1150-FAKE16-NEXT: .LBB0_2:
-; GFX1150-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB0_8
-; GFX1150-FAKE16-NEXT: .LBB0_3: ; %frem.compute
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s0
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s1
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s0, s1
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB0_5
+; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.compute
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s1
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s0
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s0, v5
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s1, v2
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -910,12 +833,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB0_7
-; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s0, s1, s0
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB0_6
+; GFX1150-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s0, s0, s1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s0, s0, 11
-; GFX1150-FAKE16-NEXT: .LBB0_5: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT: .LBB0_3: ; %frem.loop_body
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -933,14 +856,23 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB0_5
-; GFX1150-FAKE16-NEXT: ; %bb.6: ; %Flow
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX1150-FAKE16-NEXT: ; %bb.4:
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, s0
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1150-FAKE16-NEXT: s_branch .LBB0_7
+; GFX1150-FAKE16-NEXT: .LBB0_5: ; %frem.else
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s0, s1
+; GFX1150-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB0_8
+; GFX1150-FAKE16-NEXT: .LBB0_6:
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1150-FAKE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -956,7 +888,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX1150-FAKE16-NEXT: .LBB0_8: ; %Flow19
+; GFX1150-FAKE16-NEXT: .LBB0_8:
; GFX1150-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1150-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -981,39 +913,22 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
; GFX1200-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s2, s1, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s1, s0
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s0, s2
+; GFX1200-TRUE16-NEXT: s_and_b32 s1, s1, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s0, s0
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s1, s1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s1, s0
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB0_2
-; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s1, s0
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v0.l
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s2
-; GFX1200-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX1200-TRUE16-NEXT: s_branch .LBB0_7
-; GFX1200-TRUE16-NEXT: .LBB0_2:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB0_7
-; GFX1200-TRUE16-NEXT: .LBB0_3: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
+; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s0, s1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB0_5
+; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s1
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s0
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v4
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -1037,12 +952,12 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_6
-; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s0, s1, s0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_4
+; GFX1200-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s0, s0, s1
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, 11
-; GFX1200-TRUE16-NEXT: .LBB0_5: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: .LBB0_3: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -1061,10 +976,17 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_5
-; GFX1200-TRUE16-NEXT: .LBB0_6: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX1200-TRUE16-NEXT: .LBB0_4: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB0_7: ; %Flow19
+; GFX1200-TRUE16-NEXT: s_branch .LBB0_6
+; GFX1200-TRUE16-NEXT: .LBB0_5: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s0, s1
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v0.l
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s0
+; GFX1200-TRUE16-NEXT: .LBB0_6:
; GFX1200-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1200-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -1090,41 +1012,25 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s1, v1
; GFX1200-FAKE16-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s2, s1, 0x7fff
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s1, s0
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s0, s2
+; GFX1200-FAKE16-NEXT: s_and_b32 s1, s1, 0x7fff
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s0, s0
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s1, s1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s1, s0
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB0_2
-; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.else
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s1, s0
-; GFX1200-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; GFX1200-FAKE16-NEXT: s_mov_b32 s2, 0
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX1200-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
-; GFX1200-FAKE16-NEXT: s_branch .LBB0_8
-; GFX1200-FAKE16-NEXT: .LBB0_2:
-; GFX1200-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB0_8
-; GFX1200-FAKE16-NEXT: .LBB0_3: ; %frem.compute
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s0
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s1
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s0, s1
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB0_5
+; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.compute
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s1
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s0
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s0, v5
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s1, v2
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -1142,17 +1048,16 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v9, v10, v8
; GFX1200-FAKE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB0_7
-; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s0, s1, s0
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB0_6
+; GFX1200-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s0, s0, s1
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s0, s0, 11
-; GFX1200-FAKE16-NEXT: .LBB0_5: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT: .LBB0_3: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -1172,14 +1077,23 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_5
-; GFX1200-FAKE16-NEXT: ; %bb.6: ; %Flow
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB0_3
+; GFX1200-FAKE16-NEXT: ; %bb.4:
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, s0
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1200-FAKE16-NEXT: s_branch .LBB0_7
+; GFX1200-FAKE16-NEXT: .LBB0_5: ; %frem.else
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s0, s1
+; GFX1200-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB0_8
+; GFX1200-FAKE16-NEXT: .LBB0_6:
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-FAKE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -1196,7 +1110,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v0
-; GFX1200-FAKE16-NEXT: .LBB0_8: ; %Flow19
+; GFX1200-FAKE16-NEXT: .LBB0_8:
; GFX1200-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1200-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -2170,23 +2084,9 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; SI-NEXT: buffer_load_dword v1, off, s[4:7], 0 offset:16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
-; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB3_2
-; SI-NEXT: ; %bb.1: ; %frem.else
-; SI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
-; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc1 .LBB3_3
-; SI-NEXT: s_branch .LBB3_8
-; SI-NEXT: .LBB3_2:
-; SI-NEXT: s_mov_b64 s[2:3], -1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc0 .LBB3_8
-; SI-NEXT: .LBB3_3: ; %frem.compute
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v1|
+; SI-NEXT: s_cbranch_vccz .LBB3_4
+; SI-NEXT: ; %bb.1: ; %frem.compute
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
@@ -2221,11 +2121,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB3_7
-; SI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB3_5
+; SI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB3_5: ; %frem.loop_body
+; SI-NEXT: .LBB3_3: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v5, v3
; SI-NEXT: v_mul_f32_e32 v3, v5, v4
@@ -2237,12 +2137,18 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v3, v3, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB3_5
-; SI-NEXT: ; %bb.6: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v3, v5
-; SI-NEXT: .LBB3_7: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB3_3
+; SI-NEXT: s_branch .LBB3_6
+; SI-NEXT: .LBB3_4: ; %frem.else
+; SI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; SI-NEXT: s_branch .LBB3_7
+; SI-NEXT: .LBB3_5:
+; SI-NEXT: v_mov_b32_e32 v5, v3
+; SI-NEXT: .LBB3_6: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v3, v3, s3
+; SI-NEXT: v_ldexp_f32_e64 v3, v5, s3
; SI-NEXT: v_mul_f32_e32 v4, v3, v4
; SI-NEXT: v_rndne_f32_e32 v4, v4
; SI-NEXT: v_fma_f32 v3, -v4, v2, v3
@@ -2252,7 +2158,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_ldexp_f32_e64 v2, v2, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; SI-NEXT: .LBB3_8: ; %Flow17
+; SI-NEXT: .LBB3_7:
; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT: v_cmp_nge_f32_e64 s[4:5], |v0|, s4
@@ -2278,69 +2184,61 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; CI-NEXT: buffer_load_dword v1, off, s[4:7], 0 offset:16
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB3_2
-; CI-NEXT: ; %bb.1: ; %frem.else
-; CI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
-; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB3_3
-; CI-NEXT: s_branch .LBB3_8
-; CI-NEXT: .LBB3_2:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr2
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB3_8
-; CI-NEXT: .LBB3_3: ; %frem.compute
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v1|
+; CI-NEXT: s_cbranch_vccz .LBB3_4
+; CI-NEXT: ; %bb.1: ; %frem.compute
; CI-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; CI-NEXT: v_ldexp_f32_e64 v3, v3, 1
; CI-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
-; CI-NEXT: v_ldexp_f32_e64 v5, v2, 12
+; CI-NEXT: v_ldexp_f32_e64 v6, v2, 12
; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8
; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
; CI-NEXT: v_not_b32_e32 v4, v2
; CI-NEXT: v_add_i32_e32 v4, vcc, v4, v7
-; CI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; CI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; CI-NEXT: v_rcp_f32_e32 v10, v9
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; CI-NEXT: v_fma_f32 v10, v11, v10, v10
-; CI-NEXT: v_mul_f32_e32 v11, v6, v10
-; CI-NEXT: v_fma_f32 v12, -v9, v11, v6
+; CI-NEXT: v_mul_f32_e32 v11, v5, v10
+; CI-NEXT: v_fma_f32 v12, -v9, v11, v5
; CI-NEXT: v_fma_f32 v11, v12, v10, v11
-; CI-NEXT: v_fma_f32 v6, -v9, v11, v6
+; CI-NEXT: v_fma_f32 v5, -v9, v11, v5
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
+; CI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
-; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB3_7
-; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB3_5
+; CI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
; CI-NEXT: v_add_i32_e32 v4, vcc, 12, v4
-; CI-NEXT: .LBB3_5: ; %frem.loop_body
+; CI-NEXT: .LBB3_3: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v5
-; CI-NEXT: v_mul_f32_e32 v5, v7, v6
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v5, -v5, v3, v7
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v8, v5, v3
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; CI-NEXT: v_mov_b32_e32 v7, v6
+; CI-NEXT: v_mul_f32_e32 v6, v7, v5
+; CI-NEXT: v_rndne_f32_e32 v6, v6
+; CI-NEXT: v_fma_f32 v6, -v6, v3, v7
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; CI-NEXT: v_add_f32_e32 v8, v6, v3
+; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; CI-NEXT: v_add_i32_e32 v4, vcc, -12, v4
+; CI-NEXT: v_ldexp_f32_e64 v6, v6, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
-; CI-NEXT: v_ldexp_f32_e64 v5, v5, 12
-; CI-NEXT: s_cbranch_vccnz .LBB3_5
-; CI-NEXT: ; %bb.6: ; %Flow
-; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: .LBB3_7: ; %frem.loop_exit
+; CI-NEXT: s_cbranch_vccnz .LBB3_3
+; CI-NEXT: s_branch .LBB3_6
+; CI-NEXT: .LBB3_4: ; %frem.else
+; CI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; CI-NEXT: s_branch .LBB3_7
+; CI-NEXT: .LBB3_5:
+; CI-NEXT: v_mov_b32_e32 v7, v6
+; CI-NEXT: .LBB3_6: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
-; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
-; CI-NEXT: v_mul_f32_e32 v5, v4, v6
+; CI-NEXT: v_ldexp_f32_e32 v4, v7, v4
+; CI-NEXT: v_mul_f32_e32 v5, v4, v5
; CI-NEXT: v_rndne_f32_e32 v5, v5
; CI-NEXT: v_fma_f32 v4, -v5, v3, v4
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -2349,7 +2247,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; CI-NEXT: .LBB3_8: ; %Flow17
+; CI-NEXT: .LBB3_7:
; CI-NEXT: s_mov_b32 s4, 0x7f800000
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT: v_cmp_nge_f32_e64 s[4:5], |v0|, s4
@@ -2375,69 +2273,61 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_mov_b32_e32 v2, s3
; VI-NEXT: flat_load_dword v1, v[1:2]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB3_2
-; VI-NEXT: ; %bb.1: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
-; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB3_3
-; VI-NEXT: s_branch .LBB3_8
-; VI-NEXT: .LBB3_2:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr2
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB3_8
-; VI-NEXT: .LBB3_3: ; %frem.compute
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v1|
+; VI-NEXT: s_cbranch_vccz .LBB3_4
+; VI-NEXT: ; %bb.1: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; VI-NEXT: v_ldexp_f32 v3, v3, 1
; VI-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
-; VI-NEXT: v_ldexp_f32 v5, v2, 12
+; VI-NEXT: v_ldexp_f32 v6, v2, 12
; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
; VI-NEXT: v_not_b32_e32 v4, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v7
-; VI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; VI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; VI-NEXT: v_rcp_f32_e32 v10, v9
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT: v_fma_f32 v10, v11, v10, v10
-; VI-NEXT: v_mul_f32_e32 v11, v6, v10
-; VI-NEXT: v_fma_f32 v12, -v9, v11, v6
+; VI-NEXT: v_mul_f32_e32 v11, v5, v10
+; VI-NEXT: v_fma_f32 v12, -v9, v11, v5
; VI-NEXT: v_fma_f32 v11, v12, v10, v11
-; VI-NEXT: v_fma_f32 v6, -v9, v11, v6
+; VI-NEXT: v_fma_f32 v5, -v9, v11, v5
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
+; VI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
-; VI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB3_7
-; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB3_5
+; VI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v4
-; VI-NEXT: .LBB3_5: ; %frem.loop_body
+; VI-NEXT: .LBB3_3: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v5
-; VI-NEXT: v_mul_f32_e32 v5, v7, v6
-; VI-NEXT: v_rndne_f32_e32 v5, v5
-; VI-NEXT: v_fma_f32 v5, -v5, v3, v7
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; VI-NEXT: v_add_f32_e32 v8, v5, v3
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; VI-NEXT: v_mov_b32_e32 v7, v6
+; VI-NEXT: v_mul_f32_e32 v6, v7, v5
+; VI-NEXT: v_rndne_f32_e32 v6, v6
+; VI-NEXT: v_fma_f32 v6, -v6, v3, v7
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; VI-NEXT: v_add_f32_e32 v8, v6, v3
+; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, -12, v4
+; VI-NEXT: v_ldexp_f32 v6, v6, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
-; VI-NEXT: v_ldexp_f32 v5, v5, 12
-; VI-NEXT: s_cbranch_vccnz .LBB3_5
-; VI-NEXT: ; %bb.6: ; %Flow
-; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: .LBB3_7: ; %frem.loop_exit
+; VI-NEXT: s_cbranch_vccnz .LBB3_3
+; VI-NEXT: s_branch .LBB3_6
+; VI-NEXT: .LBB3_4: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; VI-NEXT: s_branch .LBB3_7
+; VI-NEXT: .LBB3_5:
+; VI-NEXT: v_mov_b32_e32 v7, v6
+; VI-NEXT: .LBB3_6: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
-; VI-NEXT: v_ldexp_f32 v4, v5, v4
-; VI-NEXT: v_mul_f32_e32 v5, v4, v6
+; VI-NEXT: v_ldexp_f32 v4, v7, v4
+; VI-NEXT: v_mul_f32_e32 v5, v4, v5
; VI-NEXT: v_rndne_f32_e32 v5, v5
; VI-NEXT: v_fma_f32 v4, -v5, v3, v4
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -2446,7 +2336,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_ldexp_f32 v2, v3, v2
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; VI-NEXT: .LBB3_8: ; %Flow17
+; VI-NEXT: .LBB3_7:
; VI-NEXT: v_mov_b32_e32 v3, s0
; VI-NEXT: s_mov_b32 s0, 0x7f800000
; VI-NEXT: v_mov_b32_e32 v4, s1
@@ -2467,30 +2357,16 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: global_load_dword v0, v2, s[2:3]
; GFX9-NEXT: global_load_dword v1, v2, s[6:7] offset:16
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB3_2
-; GFX9-NEXT: ; %bb.1: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB3_3
-; GFX9-NEXT: s_branch .LBB3_8
-; GFX9-NEXT: .LBB3_2:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr2
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB3_8
-; GFX9-NEXT: .LBB3_3: ; %frem.compute
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v1|
+; GFX9-NEXT: s_cbranch_vccz .LBB3_4
+; GFX9-NEXT: ; %bb.1: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; GFX9-NEXT: v_ldexp_f32 v3, v3, 1
; GFX9-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
-; GFX9-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; GFX9-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
-; GFX9-NEXT: v_ldexp_f32 v5, v2, 12
+; GFX9-NEXT: v_ldexp_f32 v6, v2, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
; GFX9-NEXT: v_add_u32_e32 v2, -1, v8
; GFX9-NEXT: v_not_b32_e32 v4, v2
@@ -2499,37 +2375,43 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT: v_fma_f32 v10, v11, v10, v10
-; GFX9-NEXT: v_mul_f32_e32 v11, v6, v10
-; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v6
+; GFX9-NEXT: v_mul_f32_e32 v11, v5, v10
+; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v5
; GFX9-NEXT: v_fma_f32 v11, v12, v10, v11
-; GFX9-NEXT: v_fma_f32 v6, -v9, v11, v6
+; GFX9-NEXT: v_fma_f32 v5, -v9, v11, v5
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v6, v6, v10, v11
+; GFX9-NEXT: v_div_fmas_f32 v5, v5, v10, v11
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
-; GFX9-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB3_7
-; GFX9-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB3_5
+; GFX9-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT: v_add_u32_e32 v4, 12, v4
-; GFX9-NEXT: .LBB3_5: ; %frem.loop_body
+; GFX9-NEXT: .LBB3_3: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
-; GFX9-NEXT: v_mul_f32_e32 v5, v7, v6
-; GFX9-NEXT: v_rndne_f32_e32 v5, v5
-; GFX9-NEXT: v_fma_f32 v5, -v5, v3, v7
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; GFX9-NEXT: v_add_f32_e32 v8, v5, v3
+; GFX9-NEXT: v_mov_b32_e32 v7, v6
+; GFX9-NEXT: v_mul_f32_e32 v6, v7, v5
+; GFX9-NEXT: v_rndne_f32_e32 v6, v6
+; GFX9-NEXT: v_fma_f32 v6, -v6, v3, v7
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; GFX9-NEXT: v_add_f32_e32 v8, v6, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GFX9-NEXT: v_add_u32_e32 v4, -12, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX9-NEXT: v_ldexp_f32 v6, v6, 12
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
-; GFX9-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB3_5
-; GFX9-NEXT: ; %bb.6: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: .LBB3_7: ; %frem.loop_exit
+; GFX9-NEXT: s_cbranch_vccnz .LBB3_3
+; GFX9-NEXT: s_branch .LBB3_6
+; GFX9-NEXT: .LBB3_4: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
+; GFX9-NEXT: s_branch .LBB3_7
+; GFX9-NEXT: .LBB3_5:
+; GFX9-NEXT: v_mov_b32_e32 v7, v6
+; GFX9-NEXT: .LBB3_6: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v4, -11, v4
-; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
-; GFX9-NEXT: v_mul_f32_e32 v5, v4, v6
+; GFX9-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX9-NEXT: v_rndne_f32_e32 v5, v5
; GFX9-NEXT: v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -2538,7 +2420,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_ldexp_f32 v2, v3, v2
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v2, s2, v2, v0
-; GFX9-NEXT: .LBB3_8: ; %Flow17
+; GFX9-NEXT: .LBB3_7:
; GFX9-NEXT: s_mov_b32 s2, 0x7f800000
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; GFX9-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s2
@@ -2560,23 +2442,9 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: global_load_dword v0, v2, s[2:3]
; GFX10-NEXT: global_load_dword v1, v2, s[6:7] offset:16
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v1|
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB3_2
-; GFX10-NEXT: ; %bb.1: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB3_3
-; GFX10-NEXT: s_branch .LBB3_8
-; GFX10-NEXT: .LBB3_2:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr2
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB3_8
-; GFX10-NEXT: .LBB3_3: ; %frem.compute
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v1|
+; GFX10-NEXT: s_cbranch_vccz .LBB3_5
+; GFX10-NEXT: ; %bb.1: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; GFX10-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
@@ -2602,11 +2470,11 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX10-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB3_7
-; GFX10-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB3_6
+; GFX10-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB3_5: ; %frem.loop_body
+; GFX10-NEXT: .LBB3_3: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -2618,13 +2486,20 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_add_f32_e32 v6, v4, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB3_5
-; GFX10-NEXT: ; %bb.6: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB3_3
+; GFX10-NEXT: ; %bb.4:
; GFX10-NEXT: v_mov_b32_e32 v6, s2
-; GFX10-NEXT: v_mov_b32_e32 v4, v7
+; GFX10-NEXT: s_branch .LBB3_7
+; GFX10-NEXT: .LBB3_5: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX10-NEXT: s_branch .LBB3_8
+; GFX10-NEXT: .LBB3_6:
+; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: .LBB3_7: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v6, -11, v6
-; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX10-NEXT: v_add_nc_u32_e32 v4, -11, v6
+; GFX10-NEXT: v_ldexp_f32 v4, v7, v4
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX10-NEXT: v_rndne_f32_e32 v5, v5
; GFX10-NEXT: v_fma_f32 v4, -v5, v3, v4
@@ -2633,7 +2508,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v2, v3, v2
; GFX10-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v0
-; GFX10-NEXT: .LBB3_8: ; %Flow17
+; GFX10-NEXT: .LBB3_8:
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v1
; GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX10-NEXT: v_mov_b32_e32 v3, 0
@@ -2653,24 +2528,9 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: global_load_b32 v0, v1, s[2:3]
; GFX11-NEXT: global_load_b32 v1, v1, s[4:5] offset:16
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v1|
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB3_2
-; GFX11-NEXT: ; %bb.1: ; %frem.else
-; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v0
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB3_3
-; GFX11-NEXT: s_branch .LBB3_8
-; GFX11-NEXT: .LBB3_2:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB3_8
-; GFX11-NEXT: .LBB3_3: ; %frem.compute
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v1|
+; GFX11-NEXT: s_cbranch_vccz .LBB3_5
+; GFX11-NEXT: ; %bb.1: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f32_e64 v3, |v1|
; GFX11-NEXT: v_frexp_mant_f32_e64 v2, |v0|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v5, v0
@@ -2705,12 +2565,12 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB3_7
-; GFX11-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB3_6
+; GFX11-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB3_5: ; %frem.loop_body
+; GFX11-NEXT: .LBB3_3: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v7, v4
@@ -2726,14 +2586,22 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB3_5
-; GFX11-NEXT: ; %bb.6: ; %Flow
+; GFX11-NEXT: s_cbranch_scc1 .LBB3_3
+; GFX11-NEXT: ; %bb.4:
; GFX11-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-NEXT: s_branch .LBB3_7
+; GFX11-NEXT: .LBB3_5: ; %frem.else
+; GFX11-NEXT: v_and_b32_e32 v2, 0x80000000, v0
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX11-NEXT: s_branch .LBB3_8
+; GFX11-NEXT: .LBB3_6:
+; GFX11-NEXT: v_mov_b32_e32 v7, v4
; GFX11-NEXT: .LBB3_7: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v6, -11, v6
-; GFX11-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v4, -11, v6
+; GFX11-NEXT: v_ldexp_f32 v4, v7, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX11-NEXT: v_rndne_f32_e32 v5, v5
@@ -2746,7 +2614,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_ldexp_f32 v2, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v0
-; GFX11-NEXT: .LBB3_8: ; %Flow17
+; GFX11-NEXT: .LBB3_8:
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v1
; GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -2769,24 +2637,9 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: s_waitcnt vmcnt(0)
; GFX1150-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v3
-; GFX1150-NEXT: s_cbranch_vccz .LBB3_2
-; GFX1150-NEXT: ; %bb.1: ; %frem.else
-; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v2
-; GFX1150-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v3
-; GFX1150-NEXT: s_mov_b32 s0, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-NEXT: v_cndmask_b32_e32 v3, v2, v4, vcc_lo
-; GFX1150-NEXT: s_and_b32 s0, s0, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB3_3
-; GFX1150-NEXT: s_branch .LBB3_8
-; GFX1150-NEXT: .LBB3_2:
-; GFX1150-NEXT: s_mov_b32 s0, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr3
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s0, s0, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB3_8
-; GFX1150-NEXT: .LBB3_3: ; %frem.compute
+; GFX1150-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v3
+; GFX1150-NEXT: s_cbranch_vccz .LBB3_5
+; GFX1150-NEXT: ; %bb.1: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v3, |v2|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v6, v2
@@ -2820,12 +2673,12 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1150-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB3_7
-; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB3_6
+; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s0, s0, s1
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s0, s0, 12
-; GFX1150-NEXT: .LBB3_5: ; %frem.loop_body
+; GFX1150-NEXT: .LBB3_3: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v8, v5
@@ -2843,17 +2696,25 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB3_5
-; GFX1150-NEXT: ; %bb.6: ; %Flow
+; GFX1150-NEXT: s_cbranch_scc1 .LBB3_3
+; GFX1150-NEXT: ; %bb.4:
; GFX1150-NEXT: v_mov_b32_e32 v7, s0
-; GFX1150-NEXT: v_mov_b32_e32 v5, v8
-; GFX1150-NEXT: .LBB3_7: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v7, -11, v7
-; GFX1150-NEXT: v_ldexp_f32 v5, v5, v7
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f32_e32 v6, v5, v6
-; GFX1150-NEXT: v_rndne_f32_e32 v6, v6
+; GFX1150-NEXT: s_branch .LBB3_7
+; GFX1150-NEXT: .LBB3_5: ; %frem.else
+; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v2
+; GFX1150-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v3
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-NEXT: s_branch .LBB3_8
+; GFX1150-NEXT: .LBB3_6:
+; GFX1150-NEXT: v_mov_b32_e32 v8, v5
+; GFX1150-NEXT: .LBB3_7: ; %frem.loop_exit
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v5, -11, v7
+; GFX1150-NEXT: v_ldexp_f32 v5, v8, v5
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_mul_f32_e32 v6, v5, v6
+; GFX1150-NEXT: v_rndne_f32_e32 v6, v6
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
; GFX1150-NEXT: v_fmac_f32_e32 v5, v6, v4
@@ -2863,14 +2724,13 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v4, v3
-; GFX1150-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v2
-; GFX1150-NEXT: .LBB3_8: ; %Flow17
+; GFX1150-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX1150-NEXT: .LBB3_8:
; GFX1150-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v0
; GFX1150-NEXT: v_cmp_nle_f32_e64 s0, 0x7f800000, v1
-; GFX1150-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v3, vcc_lo
-; GFX1150-NEXT: global_store_b32 v2, v0, s[8:9]
+; GFX1150-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, 0x7fc00000, v2
+; GFX1150-NEXT: global_store_b32 v3, v0, s[8:9]
; GFX1150-NEXT: s_endpgm
;
; GFX1200-LABEL: frem_f32:
@@ -2888,24 +2748,9 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v3
-; GFX1200-NEXT: s_cbranch_vccz .LBB3_2
-; GFX1200-NEXT: ; %bb.1: ; %frem.else
-; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v2
-; GFX1200-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v3
-; GFX1200-NEXT: s_mov_b32 s0, 0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-NEXT: v_cndmask_b32_e32 v3, v2, v4, vcc_lo
-; GFX1200-NEXT: s_and_b32 s0, s0, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB3_3
-; GFX1200-NEXT: s_branch .LBB3_8
-; GFX1200-NEXT: .LBB3_2:
-; GFX1200-NEXT: s_mov_b32 s0, -1
-; GFX1200-NEXT: ; implicit-def: $vgpr3
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s0, s0, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB3_8
-; GFX1200-NEXT: .LBB3_3: ; %frem.compute
+; GFX1200-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v3
+; GFX1200-NEXT: s_cbranch_vccz .LBB3_5
+; GFX1200-NEXT: ; %bb.1: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v3, |v2|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, v2
@@ -2935,17 +2780,16 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_fmac_f32_e32 v10, v11, v9
; GFX1200-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX1200-NEXT: s_denorm_mode 12
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1200-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB3_7
-; GFX1200-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB3_6
+; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s0, s0, s1
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s0, s0, 12
-; GFX1200-NEXT: .LBB3_5: ; %frem.loop_body
+; GFX1200-NEXT: .LBB3_3: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1200-NEXT: v_mov_b32_e32 v8, v5
@@ -2964,14 +2808,22 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB3_5
-; GFX1200-NEXT: ; %bb.6: ; %Flow
+; GFX1200-NEXT: s_cbranch_scc1 .LBB3_3
+; GFX1200-NEXT: ; %bb.4:
; GFX1200-NEXT: v_mov_b32_e32 v7, s0
-; GFX1200-NEXT: v_mov_b32_e32 v5, v8
+; GFX1200-NEXT: s_branch .LBB3_7
+; GFX1200-NEXT: .LBB3_5: ; %frem.else
+; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v2
+; GFX1200-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v3
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-NEXT: s_branch .LBB3_8
+; GFX1200-NEXT: .LBB3_6:
+; GFX1200-NEXT: v_mov_b32_e32 v8, v5
; GFX1200-NEXT: .LBB3_7: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v7, -11, v7
-; GFX1200-NEXT: v_ldexp_f32 v5, v5, v7
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v5, -11, v7
+; GFX1200-NEXT: v_ldexp_f32 v5, v8, v5
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1200-NEXT: v_rndne_f32_e32 v6, v6
@@ -2985,15 +2837,14 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v3, v4, v3
-; GFX1200-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v2
-; GFX1200-NEXT: .LBB3_8: ; %Flow17
+; GFX1200-NEXT: v_bfi_b32 v2, 0x7fffffff, v3, v2
+; GFX1200-NEXT: .LBB3_8:
; GFX1200-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v0
; GFX1200-NEXT: v_cmp_nle_f32_e64 s0, 0x7f800000, v1
-; GFX1200-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-NEXT: s_and_b32 vcc_lo, s0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v3, vcc_lo
-; GFX1200-NEXT: global_store_b32 v2, v0, s[8:9]
+; GFX1200-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, 0x7fc00000, v2
+; GFX1200-NEXT: global_store_b32 v3, v0, s[8:9]
; GFX1200-NEXT: s_endpgm
ptr addrspace(1) %in2) #0 {
%gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4
@@ -3577,33 +3428,12 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_readfirstlane_b32 s2, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ngt_f64_e64 s[0:1], |v[0:1]|, |v[2:3]|
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[2:3]|
; SI-NEXT: v_readfirstlane_b32 s3, v1
; SI-NEXT: v_readfirstlane_b32 s4, v2
; SI-NEXT: v_readfirstlane_b32 s5, v3
-; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
-; SI-NEXT: s_cbranch_vccz .LBB6_3
-; SI-NEXT: ; %bb.1: ; %frem.else
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: v_mov_b32_e32 v1, s5
-; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[2:3]|, |v[0:1]|
-; SI-NEXT: s_and_b32 s6, s3, 0x80000000
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s1, s6, s3
-; SI-NEXT: s_cselect_b32 s0, 0, s2
-; SI-NEXT: s_mov_b64 s[6:7], 0
-; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
-; SI-NEXT: s_cbranch_scc1 .LBB6_4
-; SI-NEXT: .LBB6_2:
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: s_branch .LBB6_9
-; SI-NEXT: .LBB6_3:
-; SI-NEXT: s_mov_b64 s[6:7], -1
-; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
-; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
-; SI-NEXT: s_cbranch_scc0 .LBB6_2
-; SI-NEXT: .LBB6_4: ; %frem.compute
+; SI-NEXT: s_cbranch_vccz .LBB6_4
+; SI-NEXT: ; %bb.1: ; %frem.compute
; SI-NEXT: s_and_b32 s0, s3, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -3615,7 +3445,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[2:3]
; SI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: s_cselect_b32 s7, s0, 0
+; SI-NEXT: s_cselect_b32 s11, s0, 0
; SI-NEXT: s_and_b32 s0, s5, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -3627,13 +3457,12 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[4:5]
; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1
; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: s_cselect_b32 s13, s0, 0
-; SI-NEXT: s_add_i32 s10, s13, -1
-; SI-NEXT: s_not_b32 s0, s10
-; SI-NEXT: s_add_i32 s12, s0, s7
+; SI-NEXT: s_cselect_b32 s12, s0, 0
+; SI-NEXT: s_add_i32 s7, s12, -1
+; SI-NEXT: s_not_b32 s0, s7
+; SI-NEXT: s_add_i32 s10, s0, s11
; SI-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], 1.0
-; SI-NEXT: s_brev_b32 s11, -2
-; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_brev_b32 s6, -2
; SI-NEXT: v_rcp_f64_e32 v[6:7], v[2:3]
; SI-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
; SI-NEXT: v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
@@ -3647,50 +3476,62 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], v[8:9]
; SI-NEXT: s_xor_b64 vcc, s[0:1], vcc
; SI-NEXT: v_div_fmas_f64 v[2:3], v[12:13], v[6:7], v[10:11]
-; SI-NEXT: s_cmp_lt_i32 s12, 27
+; SI-NEXT: s_cmp_lt_i32 s10, 27
; SI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
-; SI-NEXT: s_cbranch_scc1 .LBB6_8
-; SI-NEXT: ; %bb.5: ; %frem.loop_body.preheader
-; SI-NEXT: s_sub_i32 s0, s7, s13
-; SI-NEXT: s_add_i32 s12, s0, 26
-; SI-NEXT: s_mov_b32 s7, 0x432fffff
+; SI-NEXT: s_cbranch_scc1 .LBB6_5
+; SI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
+; SI-NEXT: s_sub_i32 s0, s11, s12
+; SI-NEXT: s_add_i32 s10, s0, 26
+; SI-NEXT: s_mov_b32 s0, -1
+; SI-NEXT: s_mov_b32 s1, 0x432fffff
; SI-NEXT: v_mov_b32_e32 v10, 0x43300000
-; SI-NEXT: v_mov_b32_e32 v6, 0
-; SI-NEXT: .LBB6_6: ; %frem.loop_body
+; SI-NEXT: v_mov_b32_e32 v8, 0
+; SI-NEXT: .LBB6_3: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v9, v5
-; SI-NEXT: v_mov_b32_e32 v8, v4
-; SI-NEXT: v_mul_f64 v[4:5], v[8:9], v[2:3]
-; SI-NEXT: s_sub_i32 s12, s12, 26
-; SI-NEXT: v_bfi_b32 v7, s11, v10, v5
-; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[6:7]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
-; SI-NEXT: v_add_f64 v[11:12], v[11:12], -v[6:7]
-; SI-NEXT: s_cmp_gt_i32 s12, 26
+; SI-NEXT: v_mov_b32_e32 v7, v5
+; SI-NEXT: v_mov_b32_e32 v6, v4
+; SI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3]
+; SI-NEXT: s_sub_i32 s10, s10, 26
+; SI-NEXT: v_bfi_b32 v9, s6, v10, v5
+; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[8:9]
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[0:1]
+; SI-NEXT: v_add_f64 v[11:12], v[11:12], -v[8:9]
+; SI-NEXT: s_cmp_gt_i32 s10, 26
; SI-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v11, v4, vcc
-; SI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[8:9]
+; SI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[0:1]
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc
; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; SI-NEXT: s_cbranch_scc1 .LBB6_6
-; SI-NEXT: ; %bb.7: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v4, v8
-; SI-NEXT: v_mov_b32_e32 v5, v9
-; SI-NEXT: .LBB6_8: ; %frem.loop_exit
-; SI-NEXT: s_sub_i32 s0, s12, 25
-; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], s0
-; SI-NEXT: s_mov_b32 s0, -1
-; SI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
-; SI-NEXT: s_mov_b32 s1, 0x432fffff
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[0:1]
-; SI-NEXT: s_brev_b32 s0, -2
+; SI-NEXT: s_cbranch_scc1 .LBB6_3
+; SI-NEXT: s_branch .LBB6_6
+; SI-NEXT: .LBB6_4: ; %frem.else
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: v_mov_b32_e32 v1, s5
+; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[2:3]|, |v[0:1]|
+; SI-NEXT: s_and_b32 s6, s3, 0x80000000
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s1, s6, s3
+; SI-NEXT: s_cselect_b32 s0, 0, s2
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: s_branch .LBB6_7
+; SI-NEXT: .LBB6_5:
+; SI-NEXT: v_mov_b32_e32 v7, v5
+; SI-NEXT: v_mov_b32_e32 v6, v4
+; SI-NEXT: .LBB6_6: ; %frem.loop_exit
+; SI-NEXT: s_sub_i32 s0, s10, 25
+; SI-NEXT: v_ldexp_f64 v[4:5], v[6:7], s0
; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
-; SI-NEXT: v_bfi_b32 v7, s0, v6, v3
+; SI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
+; SI-NEXT: s_mov_b32 s0, -1
+; SI-NEXT: v_bfi_b32 v7, s6, v6, v3
; SI-NEXT: v_mov_b32_e32 v6, 0
; SI-NEXT: v_add_f64 v[8:9], v[2:3], v[6:7]
+; SI-NEXT: s_mov_b32 s1, 0x432fffff
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[0:1]
; SI-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
; SI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
@@ -3699,10 +3540,10 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], s10
+; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], s7
; SI-NEXT: v_mov_b32_e32 v2, s3
-; SI-NEXT: v_bfi_b32 v1, s0, v1, v2
-; SI-NEXT: .LBB6_9: ; %Flow17
+; SI-NEXT: v_bfi_b32 v1, s6, v1, v2
+; SI-NEXT: .LBB6_7:
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: v_mov_b32_e32 v3, 0x7ff00000
; SI-NEXT: v_cmp_lg_f64_e64 s[0:1], s[4:5], 0
@@ -3730,24 +3571,9 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; CI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB6_2
-; CI-NEXT: ; %bb.1: ; %frem.else
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
-; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
-; CI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB6_3
-; CI-NEXT: s_branch .LBB6_8
-; CI-NEXT: .LBB6_2:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr4_vgpr5
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB6_8
-; CI-NEXT: .LBB6_3: ; %frem.compute
+; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; CI-NEXT: s_cbranch_vccz .LBB6_4
+; CI-NEXT: ; %bb.1: ; %frem.compute
; CI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v11, v[2:3]
; CI-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
@@ -3770,11 +3596,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v13
; CI-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB6_7
-; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB6_5
+; CI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v10, vcc, v10, v11
; CI-NEXT: v_add_i32_e32 v13, vcc, 26, v10
-; CI-NEXT: .LBB6_5: ; %frem.loop_body
+; CI-NEXT: .LBB6_3: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v11, v9
; CI-NEXT: v_mov_b32_e32 v10, v8
@@ -3788,13 +3614,20 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
; CI-NEXT: v_subrev_i32_e32 v13, vcc, 26, v13
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v13
-; CI-NEXT: s_cbranch_vccnz .LBB6_5
-; CI-NEXT: ; %bb.6: ; %Flow
-; CI-NEXT: v_mov_b32_e32 v8, v10
-; CI-NEXT: v_mov_b32_e32 v9, v11
-; CI-NEXT: .LBB6_7: ; %frem.loop_exit
-; CI-NEXT: v_subrev_i32_e32 v10, vcc, 25, v13
-; CI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
+; CI-NEXT: s_cbranch_vccnz .LBB6_3
+; CI-NEXT: s_branch .LBB6_6
+; CI-NEXT: .LBB6_4: ; %frem.else
+; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; CI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
+; CI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
+; CI-NEXT: s_branch .LBB6_7
+; CI-NEXT: .LBB6_5:
+; CI-NEXT: v_mov_b32_e32 v11, v9
+; CI-NEXT: v_mov_b32_e32 v10, v8
+; CI-NEXT: .LBB6_6: ; %frem.loop_exit
+; CI-NEXT: v_subrev_i32_e32 v8, vcc, 25, v13
+; CI-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
; CI-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
@@ -3805,7 +3638,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; CI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; CI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; CI-NEXT: .LBB6_8: ; %Flow17
+; CI-NEXT: .LBB6_7:
; CI-NEXT: s_mov_b32 s4, 0
; CI-NEXT: s_mov_b32 s5, 0x7ff00000
; CI-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[2:3]
@@ -3831,24 +3664,9 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB6_2
-; VI-NEXT: ; %bb.1: ; %frem.else
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
-; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
-; VI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB6_3
-; VI-NEXT: s_branch .LBB6_8
-; VI-NEXT: .LBB6_2:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr4_vgpr5
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB6_8
-; VI-NEXT: .LBB6_3: ; %frem.compute
+; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; VI-NEXT: s_cbranch_vccz .LBB6_4
+; VI-NEXT: ; %bb.1: ; %frem.compute
; VI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v11, v[2:3]
; VI-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
@@ -3871,11 +3689,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v13
; VI-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB6_7
-; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB6_5
+; VI-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v10, vcc, v10, v11
; VI-NEXT: v_add_u32_e32 v13, vcc, 26, v10
-; VI-NEXT: .LBB6_5: ; %frem.loop_body
+; VI-NEXT: .LBB6_3: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v11, v9
; VI-NEXT: v_mov_b32_e32 v10, v8
@@ -3889,13 +3707,20 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
; VI-NEXT: v_subrev_u32_e32 v13, vcc, 26, v13
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v13
-; VI-NEXT: s_cbranch_vccnz .LBB6_5
-; VI-NEXT: ; %bb.6: ; %Flow
-; VI-NEXT: v_mov_b32_e32 v8, v10
-; VI-NEXT: v_mov_b32_e32 v9, v11
-; VI-NEXT: .LBB6_7: ; %frem.loop_exit
-; VI-NEXT: v_subrev_u32_e32 v10, vcc, 25, v13
-; VI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
+; VI-NEXT: s_cbranch_vccnz .LBB6_3
+; VI-NEXT: s_branch .LBB6_6
+; VI-NEXT: .LBB6_4: ; %frem.else
+; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; VI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
+; VI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
+; VI-NEXT: s_branch .LBB6_7
+; VI-NEXT: .LBB6_5:
+; VI-NEXT: v_mov_b32_e32 v11, v9
+; VI-NEXT: v_mov_b32_e32 v10, v8
+; VI-NEXT: .LBB6_6: ; %frem.loop_exit
+; VI-NEXT: v_subrev_u32_e32 v8, vcc, 25, v13
+; VI-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
; VI-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
@@ -3906,7 +3731,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; VI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; VI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; VI-NEXT: .LBB6_8: ; %Flow17
+; VI-NEXT: .LBB6_7:
; VI-NEXT: v_mov_b32_e32 v6, s0
; VI-NEXT: v_mov_b32_e32 v7, s1
; VI-NEXT: s_mov_b32 s0, 0
@@ -3929,24 +3754,9 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB6_2
-; GFX9-NEXT: ; %bb.1: ; %frem.else
-; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
-; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB6_3
-; GFX9-NEXT: s_branch .LBB6_8
-; GFX9-NEXT: .LBB6_2:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB6_8
-; GFX9-NEXT: .LBB6_3: ; %frem.compute
+; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; GFX9-NEXT: s_cbranch_vccz .LBB6_4
+; GFX9-NEXT: ; %bb.1: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v11, v[2:3]
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
@@ -3969,11 +3779,11 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[14:15], v[18:19]
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v13
; GFX9-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB6_7
-; GFX9-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB6_5
+; GFX9-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v10, v10, v11
; GFX9-NEXT: v_add_u32_e32 v13, 26, v10
-; GFX9-NEXT: .LBB6_5: ; %frem.loop_body
+; GFX9-NEXT: .LBB6_3: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v11, v9
; GFX9-NEXT: v_mov_b32_e32 v10, v8
@@ -3987,13 +3797,20 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc
; GFX9-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v13
-; GFX9-NEXT: s_cbranch_vccnz .LBB6_5
-; GFX9-NEXT: ; %bb.6: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v8, v10
-; GFX9-NEXT: v_mov_b32_e32 v9, v11
-; GFX9-NEXT: .LBB6_7: ; %frem.loop_exit
-; GFX9-NEXT: v_subrev_u32_e32 v10, 25, v13
-; GFX9-NEXT: v_ldexp_f64 v[8:9], v[8:9], v10
+; GFX9-NEXT: s_cbranch_vccnz .LBB6_3
+; GFX9-NEXT: s_branch .LBB6_6
+; GFX9-NEXT: .LBB6_4: ; %frem.else
+; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
+; GFX9-NEXT: s_branch .LBB6_7
+; GFX9-NEXT: .LBB6_5:
+; GFX9-NEXT: v_mov_b32_e32 v11, v9
+; GFX9-NEXT: v_mov_b32_e32 v10, v8
+; GFX9-NEXT: .LBB6_6: ; %frem.loop_exit
+; GFX9-NEXT: v_subrev_u32_e32 v8, 25, v13
+; GFX9-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
; GFX9-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
@@ -4004,7 +3821,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v1
-; GFX9-NEXT: .LBB6_8: ; %Flow17
+; GFX9-NEXT: .LBB6_7:
; GFX9-NEXT: s_mov_b32 s2, 0
; GFX9-NEXT: s_mov_b32 s3, 0x7ff00000
; GFX9-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[2:3]
@@ -4028,83 +3845,76 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB6_2
-; GFX10-NEXT: ; %bb.1: ; %frem.else
-; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB6_3
-; GFX10-NEXT: s_branch .LBB6_8
-; GFX10-NEXT: .LBB6_2:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB6_8
-; GFX10-NEXT: .LBB6_3: ; %frem.compute
+; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX10-NEXT: s_cbranch_vccz .LBB6_5
+; GFX10-NEXT: ; %bb.1: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
-; GFX10-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v7, v[2:3]
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
+; GFX10-NEXT: v_ldexp_f64 v[8:9], v[4:5], 26
; GFX10-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX10-NEXT: v_add_nc_u32_e32 v12, -1, v9
-; GFX10-NEXT: v_readfirstlane_b32 s3, v9
-; GFX10-NEXT: v_readfirstlane_b32 s2, v8
-; GFX10-NEXT: v_not_b32_e32 v9, v12
-; GFX10-NEXT: v_add_nc_u32_e32 v13, v9, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v12, -1, v7
+; GFX10-NEXT: v_readfirstlane_b32 s3, v7
+; GFX10-NEXT: v_readfirstlane_b32 s2, v6
+; GFX10-NEXT: v_not_b32_e32 v7, v12
+; GFX10-NEXT: v_add_nc_u32_e32 v13, v7, v6
; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], 1
-; GFX10-NEXT: v_div_scale_f64 v[8:9], s4, v[4:5], v[4:5], 1.0
-; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX10-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX10-NEXT: v_div_scale_f64 v[6:7], s4, v[4:5], v[4:5], 1.0
+; GFX10-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
+; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
-; GFX10-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX10-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX10-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX10-NEXT: v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
; GFX10-NEXT: v_mul_f64 v[16:17], v[14:15], v[10:11]
-; GFX10-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
-; GFX10-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
+; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[16:17], v[14:15]
+; GFX10-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[16:17]
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
-; GFX10-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB6_7
-; GFX10-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
+; GFX10-NEXT: s_cbranch_vccnz .LBB6_6
+; GFX10-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 26
-; GFX10-NEXT: .LBB6_5: ; %frem.loop_body
+; GFX10-NEXT: .LBB6_3: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v11, v7
-; GFX10-NEXT: v_mov_b32_e32 v10, v6
+; GFX10-NEXT: v_mov_b32_e32 v11, v9
+; GFX10-NEXT: v_mov_b32_e32 v10, v8
; GFX10-NEXT: s_sub_i32 s2, s2, 26
; GFX10-NEXT: s_cmp_gt_i32 s2, 26
-; GFX10-NEXT: v_mul_f64 v[6:7], v[10:11], v[8:9]
-; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
-; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
-; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX10-NEXT: v_add_f64 v[13:14], v[6:7], v[4:5]
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v14, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
-; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB6_5
-; GFX10-NEXT: ; %bb.6: ; %Flow
+; GFX10-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7]
+; GFX10-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX10-NEXT: v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
+; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
+; GFX10-NEXT: v_add_f64 v[13:14], v[8:9], v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v13, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
+; GFX10-NEXT: s_cbranch_scc1 .LBB6_3
+; GFX10-NEXT: ; %bb.4:
; GFX10-NEXT: v_mov_b32_e32 v13, s2
-; GFX10-NEXT: v_mov_b32_e32 v6, v10
-; GFX10-NEXT: v_mov_b32_e32 v7, v11
+; GFX10-NEXT: s_branch .LBB6_7
+; GFX10-NEXT: .LBB6_5: ; %frem.else
+; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX10-NEXT: s_branch .LBB6_8
+; GFX10-NEXT: .LBB6_6:
+; GFX10-NEXT: v_mov_b32_e32 v11, v9
+; GFX10-NEXT: v_mov_b32_e32 v10, v8
; GFX10-NEXT: .LBB6_7: ; %frem.loop_exit
-; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
-; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
-; GFX10-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
-; GFX10-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
-; GFX10-NEXT: v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 25, v13
+; GFX10-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
+; GFX10-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
+; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX10-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX10-NEXT: v_add_f64 v[4:5], v[6:7], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX10-NEXT: .LBB6_8: ; %Flow17
+; GFX10-NEXT: .LBB6_8:
; GFX10-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX10-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX10-NEXT: v_mov_b32_e32 v6, 0
@@ -4125,92 +3935,84 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-NEXT: global_load_b64 v[2:3], v2, s[4:5]
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB6_2
-; GFX11-NEXT: ; %bb.1: ; %frem.else
-; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB6_3
-; GFX11-NEXT: s_branch .LBB6_8
-; GFX11-NEXT: .LBB6_2:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB6_8
-; GFX11-NEXT: .LBB6_3: ; %frem.compute
+; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX11-NEXT: s_cbranch_vccz .LBB6_5
+; GFX11-NEXT: ; %bb.1: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v7, v[2:3]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX11-NEXT: v_ldexp_f64 v[8:9], v[4:5], 26
; GFX11-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX11-NEXT: v_add_nc_u32_e32 v12, -1, v9
-; GFX11-NEXT: v_readfirstlane_b32 s3, v9
-; GFX11-NEXT: v_readfirstlane_b32 s2, v8
+; GFX11-NEXT: v_add_nc_u32_e32 v12, -1, v7
+; GFX11-NEXT: v_readfirstlane_b32 s3, v7
+; GFX11-NEXT: v_readfirstlane_b32 s2, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_not_b32_e32 v9, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v13, v9, v8
+; GFX11-NEXT: v_not_b32_e32 v7, v12
+; GFX11-NEXT: v_add_nc_u32_e32 v13, v7, v6
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
-; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX11-NEXT: v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
+; GFX11-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX11-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
-; GFX11-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX11-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX11-NEXT: v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
; GFX11-NEXT: v_mul_f64 v[16:17], v[14:15], v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
-; GFX11-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
+; GFX11-NEXT: v_fma_f64 v[6:7], -v[6:7], v[16:17], v[14:15]
+; GFX11-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[16:17]
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB6_7
-; GFX11-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
+; GFX11-NEXT: s_cbranch_vccnz .LBB6_6
+; GFX11-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 26
; GFX11-NEXT: .p2align 6
-; GFX11-NEXT: .LBB6_5: ; %frem.loop_body
+; GFX11-NEXT: .LBB6_3: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
+; GFX11-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
; GFX11-NEXT: s_sub_i32 s2, s2, 26
; GFX11-NEXT: s_cmp_gt_i32 s2, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[6:7], v[10:11], v[8:9]
-; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX11-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7]
+; GFX11-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX11-NEXT: v_add_f64 v[13:14], v[6:7], v[4:5]
+; GFX11-NEXT: v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
+; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
+; GFX11-NEXT: v_add_f64 v[13:14], v[8:9], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
-; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB6_5
-; GFX11-NEXT: ; %bb.6: ; %Flow
-; GFX11-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
-; GFX11-NEXT: v_mov_b32_e32 v7, v11
+; GFX11-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_cndmask_b32 v8, v8, v13
+; GFX11-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
+; GFX11-NEXT: s_cbranch_scc1 .LBB6_3
+; GFX11-NEXT: ; %bb.4:
+; GFX11-NEXT: v_mov_b32_e32 v13, s2
+; GFX11-NEXT: s_branch .LBB6_7
+; GFX11-NEXT: .LBB6_5: ; %frem.else
+; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX11-NEXT: s_branch .LBB6_8
+; GFX11-NEXT: .LBB6_6:
+; GFX11-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
; GFX11-NEXT: .LBB6_7: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
-; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
-; GFX11-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX11-NEXT: v_subrev_nc_u32_e32 v8, 25, v13
+; GFX11-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
+; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; GFX11-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX11-NEXT: v_add_f64 v[4:5], v[6:7], v[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4218,7 +4020,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX11-NEXT: .LBB6_8: ; %Flow17
+; GFX11-NEXT: .LBB6_8:
; GFX11-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX11-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -4238,91 +4040,83 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX1150-NEXT: global_load_b64 v[2:3], v2, s[4:5]
; GFX1150-NEXT: s_waitcnt vmcnt(0)
-; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
-; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1150-NEXT: s_cbranch_vccz .LBB6_2
-; GFX1150-NEXT: ; %bb.1: ; %frem.else
-; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX1150-NEXT: s_mov_b32 s2, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB6_3
-; GFX1150-NEXT: s_branch .LBB6_8
-; GFX1150-NEXT: .LBB6_2:
-; GFX1150-NEXT: s_mov_b32 s2, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB6_8
-; GFX1150-NEXT: .LBB6_3: ; %frem.compute
+; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX1150-NEXT: s_cbranch_vccz .LBB6_5
+; GFX1150-NEXT: ; %bb.1: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v7, v[2:3]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[4:5], 26
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX1150-NEXT: v_add_nc_u32_e32 v12, -1, v9
-; GFX1150-NEXT: v_readfirstlane_b32 s3, v9
-; GFX1150-NEXT: v_readfirstlane_b32 s2, v8
+; GFX1150-NEXT: v_add_nc_u32_e32 v12, -1, v7
+; GFX1150-NEXT: v_readfirstlane_b32 s3, v7
+; GFX1150-NEXT: v_readfirstlane_b32 s2, v6
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_not_b32_e32 v9, v12
-; GFX1150-NEXT: v_add_nc_u32_e32 v13, v9, v8
+; GFX1150-NEXT: v_not_b32_e32 v7, v12
+; GFX1150-NEXT: v_add_nc_u32_e32 v13, v7, v6
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], 1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
-; GFX1150-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX1150-NEXT: v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
+; GFX1150-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX1150-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX1150-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX1150-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX1150-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX1150-NEXT: v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f64 v[16:17], v[14:15], v[10:11]
-; GFX1150-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
+; GFX1150-NEXT: v_fma_f64 v[6:7], -v[6:7], v[16:17], v[14:15]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
+; GFX1150-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[16:17]
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
-; GFX1150-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB6_7
-; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
+; GFX1150-NEXT: s_cbranch_vccnz .LBB6_6
+; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s2, s2, s3
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s2, s2, 26
; GFX1150-NEXT: .p2align 6
-; GFX1150-NEXT: .LBB6_5: ; %frem.loop_body
+; GFX1150-NEXT: .LBB6_3: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-NEXT: v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
+; GFX1150-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
; GFX1150-NEXT: s_sub_i32 s2, s2, 26
; GFX1150-NEXT: s_cmp_gt_i32 s2, 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[6:7], v[10:11], v[8:9]
-; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX1150-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7]
+; GFX1150-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
-; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX1150-NEXT: v_add_f64 v[13:14], v[6:7], v[4:5]
+; GFX1150-NEXT: v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
+; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
+; GFX1150-NEXT: v_add_f64 v[13:14], v[8:9], v[4:5]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
-; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB6_5
-; GFX1150-NEXT: ; %bb.6: ; %Flow
-; GFX1150-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
-; GFX1150-NEXT: v_mov_b32_e32 v7, v11
+; GFX1150-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_cndmask_b32 v8, v8, v13
+; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
+; GFX1150-NEXT: s_cbranch_scc1 .LBB6_3
+; GFX1150-NEXT: ; %bb.4:
+; GFX1150-NEXT: v_mov_b32_e32 v13, s2
+; GFX1150-NEXT: s_branch .LBB6_7
+; GFX1150-NEXT: .LBB6_5: ; %frem.else
+; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX1150-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB6_8
+; GFX1150-NEXT: .LBB6_6:
+; GFX1150-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
; GFX1150-NEXT: .LBB6_7: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
-; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[8:9], v[6:7], v[8:9]
-; GFX1150-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX1150-NEXT: v_subrev_nc_u32_e32 v8, 25, v13
+; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_mul_f64 v[6:7], v[8:9], v[6:7]
+; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; GFX1150-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1150-NEXT: v_add_f64 v[4:5], v[6:7], v[4:5]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -4330,7 +4124,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX1150-NEXT: .LBB6_8: ; %Flow17
+; GFX1150-NEXT: .LBB6_8:
; GFX1150-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1150-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1150-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -4350,92 +4144,83 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX1200-NEXT: global_load_b64 v[2:3], v2, s[4:5]
; GFX1200-NEXT: s_wait_loadcnt 0x0
-; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
-; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1200-NEXT: s_cbranch_vccz .LBB6_2
-; GFX1200-NEXT: ; %bb.1: ; %frem.else
-; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
-; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX1200-NEXT: s_mov_b32 s2, 0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB6_3
-; GFX1200-NEXT: s_branch .LBB6_8
-; GFX1200-NEXT: .LBB6_2:
-; GFX1200-NEXT: s_mov_b32 s2, -1
-; GFX1200-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB6_8
-; GFX1200-NEXT: .LBB6_3: ; %frem.compute
+; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX1200-NEXT: s_cbranch_vccz .LBB6_5
+; GFX1200-NEXT: ; %bb.1: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v9, v[2:3]
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v8, v[0:1]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v7, v[2:3]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[4:5], 26
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
-; GFX1200-NEXT: v_add_nc_u32_e32 v12, -1, v9
-; GFX1200-NEXT: v_readfirstlane_b32 s3, v9
-; GFX1200-NEXT: v_readfirstlane_b32 s2, v8
+; GFX1200-NEXT: v_add_nc_u32_e32 v12, -1, v7
+; GFX1200-NEXT: v_readfirstlane_b32 s3, v7
+; GFX1200-NEXT: v_readfirstlane_b32 s2, v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_not_b32_e32 v9, v12
-; GFX1200-NEXT: v_add_nc_u32_e32 v13, v9, v8
+; GFX1200-NEXT: v_not_b32_e32 v7, v12
+; GFX1200-NEXT: v_add_nc_u32_e32 v13, v7, v6
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], 1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
-; GFX1200-NEXT: v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX1200-NEXT: v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
+; GFX1200-NEXT: v_rcp_f64_e32 v[10:11], v[6:7]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX1200-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX1200-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX1200-NEXT: v_fma_f64 v[14:15], -v[6:7], v[10:11], 1.0
; GFX1200-NEXT: v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
; GFX1200-NEXT: v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f64_e32 v[16:17], v[14:15], v[10:11]
-; GFX1200-NEXT: v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_fma_f64 v[6:7], -v[6:7], v[16:17], v[14:15]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
+; GFX1200-NEXT: v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[16:17]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v13
-; GFX1200-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB6_7
-; GFX1200-NEXT: ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
+; GFX1200-NEXT: s_cbranch_vccnz .LBB6_6
+; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s2, s2, s3
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 26
-; GFX1200-NEXT: .LBB6_5: ; %frem.loop_body
+; GFX1200-NEXT: .LBB6_3: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-NEXT: v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
+; GFX1200-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_mul_f64_e32 v[6:7], v[10:11], v[8:9]
-; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX1200-NEXT: v_mul_f64_e32 v[8:9], v[10:11], v[6:7]
+; GFX1200-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
-; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX1200-NEXT: v_add_f64_e32 v[13:14], v[6:7], v[4:5]
+; GFX1200-NEXT: v_fma_f64 v[8:9], -v[8:9], v[4:5], v[10:11]
+; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
+; GFX1200-NEXT: v_add_f64_e32 v[13:14], v[8:9], v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
-; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB6_5
-; GFX1200-NEXT: ; %bb.6: ; %Flow
-; GFX1200-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
-; GFX1200-NEXT: v_mov_b32_e32 v7, v11
+; GFX1200-NEXT: v_dual_cndmask_b32 v9, v9, v14 :: v_dual_cndmask_b32 v8, v8, v13
+; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[8:9], 26
+; GFX1200-NEXT: s_cbranch_scc1 .LBB6_3
+; GFX1200-NEXT: ; %bb.4:
+; GFX1200-NEXT: v_mov_b32_e32 v13, s2
+; GFX1200-NEXT: s_branch .LBB6_7
+; GFX1200-NEXT: .LBB6_5: ; %frem.else
+; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX1200-NEXT: s_branch .LBB6_8
+; GFX1200-NEXT: .LBB6_6:
+; GFX1200-NEXT: v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
; GFX1200-NEXT: .LBB6_7: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_subrev_nc_u32_e32 v10, 25, v13
-; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], v10
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_mul_f64_e32 v[8:9], v[6:7], v[8:9]
-; GFX1200-NEXT: v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX1200-NEXT: v_subrev_nc_u32_e32 v8, 25, v13
+; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[10:11], v8
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_mul_f64_e32 v[6:7], v[8:9], v[6:7]
+; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[6:7]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; GFX1200-NEXT: v_fma_f64 v[6:7], -v[6:7], v[4:5], v[8:9]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT: v_add_f64_e32 v[4:5], v[6:7], v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -4444,7 +4229,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], v12
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX1200-NEXT: .LBB6_8: ; %Flow17
+; GFX1200-NEXT: .LBB6_8:
; GFX1200-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
; GFX1200-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1200-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -5027,134 +4812,114 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_mov_b32 s4, s10
; SI-NEXT: s_mov_b32 s5, s11
; SI-NEXT: s_mov_b32 s3, s7
-; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:16
+; SI-NEXT: buffer_load_dword v2, off, s[4:7], 0
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], 0 offset:16
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; SI-NEXT: v_cvt_f32_f16_e64 v5, |v2|
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e64 v4, |v1|
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v4
-; SI-NEXT: s_cbranch_vccz .LBB9_2
-; SI-NEXT: ; %bb.1: ; %frem.else20
-; SI-NEXT: v_and_b32_e32 v2, 0xffff8000, v0
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v4
-; SI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc1 .LBB9_3
-; SI-NEXT: s_branch .LBB9_8
-; SI-NEXT: .LBB9_2:
-; SI-NEXT: s_mov_b64 s[0:1], -1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc0 .LBB9_8
-; SI-NEXT: .LBB9_3: ; %frem.compute19
+; SI-NEXT: v_cvt_f32_f16_e64 v4, |v3|
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
+; SI-NEXT: s_cbranch_vccz .LBB9_4
+; SI-NEXT: ; %bb.1: ; %frem.compute19
; SI-NEXT: s_mov_b32 s3, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s3
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v6, v5
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: v_frexp_mant_f32_e32 v2, v3
-; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; SI-NEXT: v_ldexp_f32_e64 v3, v2, 11
+; SI-NEXT: v_readfirstlane_b32 s0, v6
+; SI-NEXT: v_frexp_mant_f32_e32 v6, v5
+; SI-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s3
-; SI-NEXT: v_frexp_mant_f32_e32 v2, v4
-; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NEXT: v_ldexp_f32_e64 v2, v2, 1
-; SI-NEXT: v_div_scale_f32 v5, s[4:5], v2, v2, 1.0
-; SI-NEXT: v_rcp_f32_e32 v6, v5
+; SI-NEXT: v_frexp_mant_f32_e32 v6, v4
; SI-NEXT: s_cselect_b32 s2, s0, 0
+; SI-NEXT: v_cndmask_b32_e32 v6, v4, v6, vcc
; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s0, v4
-; SI-NEXT: v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
+; SI-NEXT: v_ldexp_f32_e64 v4, v6, 1
+; SI-NEXT: v_div_scale_f32 v7, s[4:5], v4, v4, 1.0
+; SI-NEXT: v_rcp_f32_e32 v8, v7
+; SI-NEXT: v_ldexp_f32_e64 v5, v5, 11
+; SI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT: v_fma_f32 v7, -v5, v6, 1.0
-; SI-NEXT: v_fma_f32 v6, v7, v6, v6
-; SI-NEXT: v_mul_f32_e32 v7, v4, v6
+; SI-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; SI-NEXT: v_fma_f32 v8, v9, v8, v8
+; SI-NEXT: v_mul_f32_e32 v9, v6, v8
; SI-NEXT: s_cselect_b32 s3, s0, 0
-; SI-NEXT: v_fma_f32 v8, -v5, v7, v4
+; SI-NEXT: v_fma_f32 v10, -v7, v9, v6
; SI-NEXT: s_add_i32 s0, s3, -1
-; SI-NEXT: v_fma_f32 v7, v8, v6, v7
+; SI-NEXT: v_fma_f32 v9, v10, v8, v9
; SI-NEXT: s_not_b32 s1, s0
-; SI-NEXT: v_fma_f32 v4, -v5, v7, v4
+; SI-NEXT: v_fma_f32 v6, -v7, v9, v6
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
; SI-NEXT: s_add_i32 s1, s1, s2
-; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
-; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
+; SI-NEXT: v_div_fmas_f32 v6, v6, v8, v9
+; SI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB9_7
-; SI-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB9_5
+; SI-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
; SI-NEXT: s_sub_i32 s1, s2, s3
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB9_5: ; %frem.loop_body27
+; SI-NEXT: .LBB9_3: ; %frem.loop_body27
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v5, v3
-; SI-NEXT: v_mul_f32_e32 v3, v5, v4
-; SI-NEXT: v_rndne_f32_e32 v3, v3
-; SI-NEXT: v_fma_f32 v3, -v3, v2, v5
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; SI-NEXT: v_add_f32_e32 v6, v3, v2
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; SI-NEXT: s_add_i32 s1, s1, -11
-; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
-; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB9_5
-; SI-NEXT: ; %bb.6: ; %Flow55
-; SI-NEXT: v_mov_b32_e32 v3, v5
-; SI-NEXT: .LBB9_7: ; %frem.loop_exit28
+; SI-NEXT: v_mov_b32_e32 v7, v5
+; SI-NEXT: v_mul_f32_e32 v5, v7, v6
+; SI-NEXT: v_rndne_f32_e32 v5, v5
+; SI-NEXT: v_fma_f32 v5, -v5, v4, v7
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; SI-NEXT: v_add_f32_e32 v8, v5, v4
+; SI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; SI-NEXT: s_add_i32 s1, s1, -11
+; SI-NEXT: v_ldexp_f32_e64 v5, v5, 11
+; SI-NEXT: s_cmp_gt_i32 s1, 11
+; SI-NEXT: s_cbranch_scc1 .LBB9_3
+; SI-NEXT: s_branch .LBB9_6
+; SI-NEXT: .LBB9_4: ; %frem.else20
+; SI-NEXT: v_and_b32_e32 v6, 0xffff8000, v2
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
+; SI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
+; SI-NEXT: s_branch .LBB9_7
+; SI-NEXT: .LBB9_5:
+; SI-NEXT: v_mov_b32_e32 v7, v5
+; SI-NEXT: .LBB9_6: ; %frem.loop_exit28
; SI-NEXT: s_add_i32 s1, s1, -10
-; SI-NEXT: v_ldexp_f32_e64 v3, v3, s1
-; SI-NEXT: v_mul_f32_e32 v4, v3, v4
-; SI-NEXT: v_rndne_f32_e32 v4, v4
-; SI-NEXT: v_fma_f32 v3, -v4, v2, v3
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; SI-NEXT: v_add_f32_e32 v2, v3, v2
-; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; SI-NEXT: v_ldexp_f32_e64 v2, v2, s0
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NEXT: v_and_b32_e32 v3, 0xffff8000, v0
-; SI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: .LBB9_8: ; %Flow58
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; SI-NEXT: v_cvt_f32_f16_e64 v6, |v3|
-; SI-NEXT: v_cvt_f32_f16_e64 v7, |v4|
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v7
-; SI-NEXT: s_cbranch_vccz .LBB9_10
-; SI-NEXT: ; %bb.9: ; %frem.else
-; SI-NEXT: v_and_b32_e32 v5, 0x8000, v3
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v7
-; SI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
-; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc1 .LBB9_11
-; SI-NEXT: s_branch .LBB9_16
-; SI-NEXT: .LBB9_10:
-; SI-NEXT: s_mov_b64 s[0:1], -1
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc0 .LBB9_16
-; SI-NEXT: .LBB9_11: ; %frem.compute
+; SI-NEXT: v_ldexp_f32_e64 v5, v7, s1
+; SI-NEXT: v_mul_f32_e32 v6, v5, v6
+; SI-NEXT: v_rndne_f32_e32 v6, v6
+; SI-NEXT: v_fma_f32 v5, -v6, v4, v5
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; SI-NEXT: v_add_f32_e32 v4, v5, v4
+; SI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
+; SI-NEXT: v_ldexp_f32_e64 v4, v4, s0
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: v_and_b32_e32 v5, 0xffff8000, v2
+; SI-NEXT: v_and_b32_e32 v4, 0x7fff, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: .LBB9_7:
+; SI-NEXT: v_cvt_f32_f16_e64 v6, |v0|
+; SI-NEXT: v_cvt_f32_f16_e64 v5, |v1|
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5
+; SI-NEXT: s_cbranch_vccz .LBB9_11
+; SI-NEXT: ; %bb.8: ; %frem.compute
; SI-NEXT: s_mov_b32 s3, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s3
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v6
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
+; SI-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s0, v7
+; SI-NEXT: v_frexp_mant_f32_e32 v7, v6
+; SI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s3
+; SI-NEXT: v_frexp_mant_f32_e32 v7, v5
+; SI-NEXT: s_cselect_b32 s2, s0, 0
+; SI-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s0, v5
-; SI-NEXT: v_frexp_mant_f32_e32 v5, v6
-; SI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
-; SI-NEXT: v_ldexp_f32_e64 v6, v5, 11
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s3
-; SI-NEXT: v_frexp_mant_f32_e32 v5, v7
-; SI-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
-; SI-NEXT: v_ldexp_f32_e64 v5, v5, 1
+; SI-NEXT: v_ldexp_f32_e64 v5, v7, 1
; SI-NEXT: v_div_scale_f32 v8, s[4:5], v5, v5, 1.0
; SI-NEXT: v_rcp_f32_e32 v9, v8
-; SI-NEXT: s_cselect_b32 s2, s0, 0
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v7, v7
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v7
+; SI-NEXT: v_ldexp_f32_e64 v6, v6, 11
; SI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT: v_fma_f32 v10, -v8, v9, 1.0
@@ -5171,11 +4936,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v7, v7, v9, v10
; SI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB9_15
-; SI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB9_12
+; SI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s1, s2, s3
; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB9_13: ; %frem.loop_body
+; SI-NEXT: .LBB9_10: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v8, v6
; SI-NEXT: v_mul_f32_e32 v6, v8, v7
@@ -5187,12 +4952,18 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s1, s1, -11
; SI-NEXT: v_ldexp_f32_e64 v6, v6, 11
; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB9_13
-; SI-NEXT: ; %bb.14: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v6, v8
-; SI-NEXT: .LBB9_15: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB9_10
+; SI-NEXT: s_branch .LBB9_13
+; SI-NEXT: .LBB9_11: ; %frem.else
+; SI-NEXT: v_and_b32_e32 v7, 0x8000, v0
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
+; SI-NEXT: v_cndmask_b32_e32 v5, v0, v7, vcc
+; SI-NEXT: s_branch .LBB9_14
+; SI-NEXT: .LBB9_12:
+; SI-NEXT: v_mov_b32_e32 v8, v6
+; SI-NEXT: .LBB9_13: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s1, s1, -10
-; SI-NEXT: v_ldexp_f32_e64 v6, v6, s1
+; SI-NEXT: v_ldexp_f32_e64 v6, v8, s1
; SI-NEXT: v_mul_f32_e32 v7, v6, v7
; SI-NEXT: v_rndne_f32_e32 v7, v7
; SI-NEXT: v_fma_f32 v6, -v7, v5, v6
@@ -5201,28 +4972,28 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; SI-NEXT: v_ldexp_f32_e64 v5, v5, s0
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-NEXT: v_and_b32_e32 v6, 0x8000, v3
+; SI-NEXT: v_and_b32_e32 v6, 0x8000, v0
; SI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: .LBB9_16: ; %Flow54
+; SI-NEXT: .LBB9_14:
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT: v_cvt_f32_f16_e64 v2, |v2|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; SI-NEXT: s_mov_b32 s2, 0x7f800000
-; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v3
+; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v2
+; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
+; SI-NEXT: v_mov_b32_e32 v2, 0x7e00
+; SI-NEXT: v_cndmask_b32_e32 v3, v2, v4, vcc
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v0
; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; SI-NEXT: v_mov_b32_e32 v0, 0x7e00
-; SI-NEXT: v_cndmask_b32_e32 v1, v0, v2, vcc
-; SI-NEXT: v_cvt_f32_f16_e32 v2, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_mov_b32 s10, -1
-; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
-; SI-NEXT: v_cvt_f32_f16_e64 v2, |v3|
-; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v2
-; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; SI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; SI-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_endpgm
@@ -5238,151 +5009,137 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_mov_b32 s4, s10
; CI-NEXT: s_mov_b32 s5, s11
; CI-NEXT: s_mov_b32 s3, s7
-; CI-NEXT: buffer_load_dword v0, off, s[4:7], 0
-; CI-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:16
+; CI-NEXT: buffer_load_dword v2, off, s[4:7], 0
+; CI-NEXT: buffer_load_dword v3, off, s[0:3], 0 offset:16
; CI-NEXT: s_waitcnt vmcnt(1)
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |v0|
+; CI-NEXT: v_cvt_f32_f16_e64 v5, |v2|
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e64 v3, |v1|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
-; CI-NEXT: s_cbranch_vccz .LBB9_2
-; CI-NEXT: ; %bb.1: ; %frem.else20
-; CI-NEXT: v_and_b32_e32 v2, 0xffff8000, v0
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
-; CI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc1 .LBB9_3
-; CI-NEXT: s_branch .LBB9_8
-; CI-NEXT: .LBB9_2:
-; CI-NEXT: s_mov_b64 s[0:1], -1
-; CI-NEXT: ; implicit-def: $vgpr2
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc0 .LBB9_8
-; CI-NEXT: .LBB9_3: ; %frem.compute19
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
-; CI-NEXT: v_frexp_mant_f32_e32 v2, v4
-; CI-NEXT: v_frexp_mant_f32_e32 v4, v3
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
-; CI-NEXT: v_ldexp_f32_e64 v3, v4, 1
-; CI-NEXT: v_div_scale_f32 v9, s[0:1], v3, v3, 1.0
-; CI-NEXT: v_ldexp_f32_e64 v5, v2, 11
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8
-; CI-NEXT: v_not_b32_e32 v4, v2
-; CI-NEXT: v_add_i32_e32 v4, vcc, v4, v7
-; CI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
-; CI-NEXT: v_rcp_f32_e32 v10, v9
+; CI-NEXT: v_cvt_f32_f16_e64 v4, |v3|
+; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
+; CI-NEXT: s_cbranch_vccz .LBB9_4
+; CI-NEXT: ; %bb.1: ; %frem.compute19
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v9, v5
+; CI-NEXT: v_frexp_mant_f32_e32 v5, v5
+; CI-NEXT: v_ldexp_f32_e64 v8, v5, 11
+; CI-NEXT: v_frexp_mant_f32_e32 v5, v4
+; CI-NEXT: v_ldexp_f32_e64 v5, v5, 1
+; CI-NEXT: v_div_scale_f32 v11, s[0:1], v5, v5, 1.0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v4
+; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v10
+; CI-NEXT: v_not_b32_e32 v6, v4
+; CI-NEXT: v_add_i32_e32 v6, vcc, v6, v9
+; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; CI-NEXT: v_rcp_f32_e32 v12, v11
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
-; CI-NEXT: v_fma_f32 v10, v11, v10, v10
-; CI-NEXT: v_mul_f32_e32 v11, v6, v10
-; CI-NEXT: v_fma_f32 v12, -v9, v11, v6
-; CI-NEXT: v_fma_f32 v11, v12, v10, v11
-; CI-NEXT: v_fma_f32 v6, -v9, v11, v6
+; CI-NEXT: v_fma_f32 v13, -v11, v12, 1.0
+; CI-NEXT: v_fma_f32 v12, v13, v12, v12
+; CI-NEXT: v_mul_f32_e32 v13, v7, v12
+; CI-NEXT: v_fma_f32 v14, -v11, v13, v7
+; CI-NEXT: v_fma_f32 v13, v14, v12, v13
+; CI-NEXT: v_fma_f32 v7, -v11, v13, v7
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
-; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB9_7
-; CI-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
-; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
-; CI-NEXT: v_add_i32_e32 v4, vcc, 11, v4
-; CI-NEXT: .LBB9_5: ; %frem.loop_body27
-; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v5
-; CI-NEXT: v_mul_f32_e32 v5, v7, v6
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v5, -v5, v3, v7
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v8, v5, v3
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
-; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11
+; CI-NEXT: v_div_fmas_f32 v7, v7, v12, v13
+; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
+; CI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
; CI-NEXT: s_cbranch_vccnz .LBB9_5
-; CI-NEXT: ; %bb.6: ; %Flow55
-; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: .LBB9_7: ; %frem.loop_exit28
-; CI-NEXT: v_add_i32_e32 v4, vcc, -10, v4
+; CI-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; CI-NEXT: v_sub_i32_e32 v6, vcc, v9, v10
+; CI-NEXT: v_add_i32_e32 v6, vcc, 11, v6
+; CI-NEXT: .LBB9_3: ; %frem.loop_body27
+; CI-NEXT: ; =>This Inner Loop Header: Depth=1
+; CI-NEXT: v_mov_b32_e32 v9, v8
+; CI-NEXT: v_mul_f32_e32 v8, v9, v7
+; CI-NEXT: v_rndne_f32_e32 v8, v8
+; CI-NEXT: v_fma_f32 v8, -v8, v5, v9
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; CI-NEXT: v_add_f32_e32 v10, v8, v5
+; CI-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; CI-NEXT: v_add_i32_e32 v6, vcc, -11, v6
+; CI-NEXT: v_ldexp_f32_e64 v8, v8, 11
+; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
+; CI-NEXT: s_cbranch_vccnz .LBB9_3
+; CI-NEXT: s_branch .LBB9_6
+; CI-NEXT: .LBB9_4: ; %frem.else20
+; CI-NEXT: v_and_b32_e32 v6, 0xffff8000, v2
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
+; CI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
+; CI-NEXT: s_branch .LBB9_7
+; CI-NEXT: .LBB9_5:
+; CI-NEXT: v_mov_b32_e32 v9, v8
+; CI-NEXT: .LBB9_6: ; %frem.loop_exit28
+; CI-NEXT: v_add_i32_e32 v6, vcc, -10, v6
+; CI-NEXT: v_ldexp_f32_e32 v6, v9, v6
+; CI-NEXT: v_mul_f32_e32 v7, v6, v7
+; CI-NEXT: v_rndne_f32_e32 v7, v7
+; CI-NEXT: v_fma_f32 v6, -v7, v5, v6
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; CI-NEXT: v_add_f32_e32 v5, v6, v5
+; CI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
-; CI-NEXT: v_mul_f32_e32 v5, v4, v6
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v4, -v5, v3, v4
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v3, v4, v3
-; CI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_and_b32_e32 v3, 0xffff8000, v0
-; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; CI-NEXT: v_or_b32_e32 v2, v2, v3
-; CI-NEXT: .LBB9_8: ; %Flow58
-; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; CI-NEXT: v_cvt_f32_f16_e64 v7, |v3|
-; CI-NEXT: v_cvt_f32_f16_e64 v6, |v4|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
-; CI-NEXT: s_cbranch_vccz .LBB9_10
-; CI-NEXT: ; %bb.9: ; %frem.else
-; CI-NEXT: v_and_b32_e32 v5, 0x8000, v3
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
-; CI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
-; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc1 .LBB9_11
-; CI-NEXT: s_branch .LBB9_16
-; CI-NEXT: .LBB9_10:
-; CI-NEXT: s_mov_b64 s[0:1], -1
-; CI-NEXT: ; implicit-def: $vgpr5
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc0 .LBB9_16
-; CI-NEXT: .LBB9_11: ; %frem.compute
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v7
-; CI-NEXT: v_frexp_mant_f32_e32 v5, v7
-; CI-NEXT: v_frexp_mant_f32_e32 v7, v6
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v6
-; CI-NEXT: v_ldexp_f32_e64 v6, v7, 1
+; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; CI-NEXT: v_and_b32_e32 v5, 0xffff8000, v2
+; CI-NEXT: v_and_b32_e32 v4, 0x7fff, v4
+; CI-NEXT: v_or_b32_e32 v4, v4, v5
+; CI-NEXT: .LBB9_7:
+; CI-NEXT: v_cvt_f32_f16_e64 v6, |v0|
+; CI-NEXT: v_cvt_f32_f16_e64 v5, |v1|
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5
+; CI-NEXT: s_cbranch_vccz .LBB9_11
+; CI-NEXT: ; %bb.8: ; %frem.compute
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v6
+; CI-NEXT: v_frexp_mant_f32_e32 v6, v6
+; CI-NEXT: v_ldexp_f32_e64 v9, v6, 11
+; CI-NEXT: v_frexp_mant_f32_e32 v6, v5
+; CI-NEXT: v_ldexp_f32_e64 v6, v6, 1
; CI-NEXT: v_div_scale_f32 v12, s[0:1], v6, v6, 1.0
-; CI-NEXT: v_ldexp_f32_e64 v8, v5, 11
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v5
; CI-NEXT: v_add_i32_e32 v5, vcc, -1, v11
; CI-NEXT: v_not_b32_e32 v7, v5
; CI-NEXT: v_add_i32_e32 v7, vcc, v7, v10
-; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
; CI-NEXT: v_rcp_f32_e32 v13, v12
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; CI-NEXT: v_fma_f32 v13, v14, v13, v13
-; CI-NEXT: v_mul_f32_e32 v14, v9, v13
-; CI-NEXT: v_fma_f32 v15, -v12, v14, v9
+; CI-NEXT: v_mul_f32_e32 v14, v8, v13
+; CI-NEXT: v_fma_f32 v15, -v12, v14, v8
; CI-NEXT: v_fma_f32 v14, v15, v13, v14
-; CI-NEXT: v_fma_f32 v9, -v12, v14, v9
+; CI-NEXT: v_fma_f32 v8, -v12, v14, v8
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
+; CI-NEXT: v_div_fmas_f32 v8, v8, v13, v14
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v7
-; CI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB9_15
-; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB9_12
+; CI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v7, vcc, v10, v11
; CI-NEXT: v_add_i32_e32 v7, vcc, 11, v7
-; CI-NEXT: .LBB9_13: ; %frem.loop_body
+; CI-NEXT: .LBB9_10: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v10, v8
-; CI-NEXT: v_mul_f32_e32 v8, v10, v9
-; CI-NEXT: v_rndne_f32_e32 v8, v8
-; CI-NEXT: v_fma_f32 v8, -v8, v6, v10
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; CI-NEXT: v_add_f32_e32 v11, v8, v6
-; CI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; CI-NEXT: v_mov_b32_e32 v10, v9
+; CI-NEXT: v_mul_f32_e32 v9, v10, v8
+; CI-NEXT: v_rndne_f32_e32 v9, v9
+; CI-NEXT: v_fma_f32 v9, -v9, v6, v10
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
+; CI-NEXT: v_add_f32_e32 v11, v9, v6
+; CI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; CI-NEXT: v_add_i32_e32 v7, vcc, -11, v7
+; CI-NEXT: v_ldexp_f32_e64 v9, v9, 11
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v7
-; CI-NEXT: v_ldexp_f32_e64 v8, v8, 11
-; CI-NEXT: s_cbranch_vccnz .LBB9_13
-; CI-NEXT: ; %bb.14: ; %Flow
-; CI-NEXT: v_mov_b32_e32 v8, v10
-; CI-NEXT: .LBB9_15: ; %frem.loop_exit
+; CI-NEXT: s_cbranch_vccnz .LBB9_10
+; CI-NEXT: s_branch .LBB9_13
+; CI-NEXT: .LBB9_11: ; %frem.else
+; CI-NEXT: v_and_b32_e32 v7, 0x8000, v0
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
+; CI-NEXT: v_cndmask_b32_e32 v5, v0, v7, vcc
+; CI-NEXT: s_branch .LBB9_14
+; CI-NEXT: .LBB9_12:
+; CI-NEXT: v_mov_b32_e32 v10, v9
+; CI-NEXT: .LBB9_13: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v7, vcc, -10, v7
-; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
-; CI-NEXT: v_mul_f32_e32 v8, v7, v9
+; CI-NEXT: v_ldexp_f32_e32 v7, v10, v7
+; CI-NEXT: v_mul_f32_e32 v8, v7, v8
; CI-NEXT: v_rndne_f32_e32 v8, v8
; CI-NEXT: v_fma_f32 v7, -v8, v6, v7
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
@@ -5390,28 +5147,28 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; CI-NEXT: v_ldexp_f32_e32 v5, v6, v5
; CI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; CI-NEXT: v_and_b32_e32 v6, 0x8000, v3
+; CI-NEXT: v_and_b32_e32 v6, 0x8000, v0
; CI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
; CI-NEXT: v_or_b32_e32 v5, v5, v6
-; CI-NEXT: .LBB9_16: ; %Flow54
+; CI-NEXT: .LBB9_14:
+; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; CI-NEXT: v_cvt_f32_f16_e64 v2, |v2|
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
; CI-NEXT: s_mov_b32 s2, 0x7f800000
-; CI-NEXT: s_mov_b32 s11, 0xf000
+; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v3
+; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v2
+; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
+; CI-NEXT: v_mov_b32_e32 v2, 0x7e00
+; CI-NEXT: v_cndmask_b32_e32 v3, v2, v4, vcc
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v0
; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; CI-NEXT: v_mov_b32_e32 v0, 0x7e00
-; CI-NEXT: v_cndmask_b32_e32 v1, v0, v2, vcc
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v4
-; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; CI-NEXT: s_mov_b32 s10, -1
-; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |v3|
-; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s2, v2
-; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; CI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; CI-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; CI-NEXT: v_and_b32_e32 v1, 0xffff, v3
+; CI-NEXT: s_mov_b32 s11, 0xf000
+; CI-NEXT: s_mov_b32 s10, -1
; CI-NEXT: v_or_b32_e32 v0, v1, v0
; CI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; CI-NEXT: s_endpgm
@@ -5430,71 +5187,64 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_mov_b32_e32 v2, s3
; VI-NEXT: flat_load_dword v1, v[1:2]
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_cvt_f32_f16_e64 v4, |v0|
+; VI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e64 v3, |v1|
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
-; VI-NEXT: s_cbranch_vccz .LBB9_2
-; VI-NEXT: ; %bb.1: ; %frem.else20
-; VI-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
-; VI-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB9_3
-; VI-NEXT: s_branch .LBB9_8
-; VI-NEXT: .LBB9_2:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr2
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB9_8
-; VI-NEXT: .LBB9_3: ; %frem.compute19
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
-; VI-NEXT: v_frexp_mant_f32_e32 v2, v4
-; VI-NEXT: v_frexp_mant_f32_e32 v4, v3
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
-; VI-NEXT: v_ldexp_f32 v3, v4, 1
+; VI-NEXT: v_cvt_f32_f16_e64 v2, |v1|
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
+; VI-NEXT: s_cbranch_vccz .LBB9_4
+; VI-NEXT: ; %bb.1: ; %frem.compute19
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
+; VI-NEXT: v_frexp_mant_f32_e32 v3, v3
+; VI-NEXT: v_ldexp_f32 v6, v3, 11
+; VI-NEXT: v_frexp_mant_f32_e32 v3, v2
+; VI-NEXT: v_ldexp_f32 v3, v3, 1
; VI-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
-; VI-NEXT: v_ldexp_f32 v5, v2, 11
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v8
; VI-NEXT: v_not_b32_e32 v4, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v7
-; VI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; VI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; VI-NEXT: v_rcp_f32_e32 v10, v9
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; VI-NEXT: v_fma_f32 v10, v11, v10, v10
-; VI-NEXT: v_mul_f32_e32 v11, v6, v10
-; VI-NEXT: v_fma_f32 v12, -v9, v11, v6
+; VI-NEXT: v_mul_f32_e32 v11, v5, v10
+; VI-NEXT: v_fma_f32 v12, -v9, v11, v5
; VI-NEXT: v_fma_f32 v11, v12, v10, v11
-; VI-NEXT: v_fma_f32 v6, -v9, v11, v6
+; VI-NEXT: v_fma_f32 v5, -v9, v11, v5
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
+; VI-NEXT: v_div_fmas_f32 v5, v5, v10, v11
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; VI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB9_7
-; VI-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
+; VI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB9_5
+; VI-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
; VI-NEXT: v_sub_u32_e32 v4, vcc, v7, v8
; VI-NEXT: v_add_u32_e32 v4, vcc, 11, v4
-; VI-NEXT: .LBB9_5: ; %frem.loop_body27
+; VI-NEXT: .LBB9_3: ; %frem.loop_body27
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v5
-; VI-NEXT: v_mul_f32_e32 v5, v7, v6
-; VI-NEXT: v_rndne_f32_e32 v5, v5
-; VI-NEXT: v_fma_f32 v5, -v5, v3, v7
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; VI-NEXT: v_add_f32_e32 v8, v5, v3
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; VI-NEXT: v_mov_b32_e32 v7, v6
+; VI-NEXT: v_mul_f32_e32 v6, v7, v5
+; VI-NEXT: v_rndne_f32_e32 v6, v6
+; VI-NEXT: v_fma_f32 v6, -v6, v3, v7
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; VI-NEXT: v_add_f32_e32 v8, v6, v3
+; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4
+; VI-NEXT: v_ldexp_f32 v6, v6, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; VI-NEXT: v_ldexp_f32 v5, v5, 11
-; VI-NEXT: s_cbranch_vccnz .LBB9_5
-; VI-NEXT: ; %bb.6: ; %Flow55
-; VI-NEXT: v_mov_b32_e32 v5, v7
-; VI-NEXT: .LBB9_7: ; %frem.loop_exit28
+; VI-NEXT: s_cbranch_vccnz .LBB9_3
+; VI-NEXT: s_branch .LBB9_6
+; VI-NEXT: .LBB9_4: ; %frem.else20
+; VI-NEXT: v_and_b32_e32 v4, 0x8000, v0
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
+; VI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc
+; VI-NEXT: s_branch .LBB9_7
+; VI-NEXT: .LBB9_5:
+; VI-NEXT: v_mov_b32_e32 v7, v6
+; VI-NEXT: .LBB9_6: ; %frem.loop_exit28
; VI-NEXT: v_add_u32_e32 v4, vcc, -10, v4
-; VI-NEXT: v_ldexp_f32 v4, v5, v4
-; VI-NEXT: v_mul_f32_e32 v5, v4, v6
+; VI-NEXT: v_ldexp_f32 v4, v7, v4
+; VI-NEXT: v_mul_f32_e32 v5, v4, v5
; VI-NEXT: v_rndne_f32_e32 v5, v5
; VI-NEXT: v_fma_f32 v4, -v5, v3, v4
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -5503,74 +5253,67 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v2, v3, v2
; VI-NEXT: v_cvt_f16_f32_e32 v2, v2
; VI-NEXT: s_movk_i32 s2, 0x7fff
-; VI-NEXT: v_bfi_b32 v2, s2, v2, v0
-; VI-NEXT: .LBB9_8:
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; VI-NEXT: v_bfi_b32 v3, s2, v2, v0
+; VI-NEXT: .LBB9_7:
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; VI-NEXT: v_cvt_f32_f16_e64 v7, |v3|
-; VI-NEXT: v_cvt_f32_f16_e64 v6, |v4|
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
-; VI-NEXT: s_cbranch_vccz .LBB9_10
-; VI-NEXT: ; %bb.9: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v5, 0x8000, v3
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
-; VI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB9_11
-; VI-NEXT: s_branch .LBB9_16
-; VI-NEXT: .LBB9_10:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr5
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB9_16
-; VI-NEXT: .LBB9_11: ; %frem.compute
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v7
-; VI-NEXT: v_frexp_mant_f32_e32 v5, v7
-; VI-NEXT: v_frexp_mant_f32_e32 v7, v6
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v11, v6
-; VI-NEXT: v_ldexp_f32 v6, v7, 1
+; VI-NEXT: v_cvt_f32_f16_e64 v6, |v2|
+; VI-NEXT: v_cvt_f32_f16_e64 v5, |v4|
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, v6, v5
+; VI-NEXT: s_cbranch_vccz .LBB9_11
+; VI-NEXT: ; %bb.8: ; %frem.compute
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v6
+; VI-NEXT: v_frexp_mant_f32_e32 v6, v6
+; VI-NEXT: v_ldexp_f32 v9, v6, 11
+; VI-NEXT: v_frexp_mant_f32_e32 v6, v5
+; VI-NEXT: v_ldexp_f32 v6, v6, 1
; VI-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
-; VI-NEXT: v_ldexp_f32 v8, v5, 11
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v11, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, -1, v11
; VI-NEXT: v_not_b32_e32 v7, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v10
-; VI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
; VI-NEXT: v_rcp_f32_e32 v13, v12
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; VI-NEXT: v_fma_f32 v13, v14, v13, v13
-; VI-NEXT: v_mul_f32_e32 v14, v9, v13
-; VI-NEXT: v_fma_f32 v15, -v12, v14, v9
+; VI-NEXT: v_mul_f32_e32 v14, v8, v13
+; VI-NEXT: v_fma_f32 v15, -v12, v14, v8
; VI-NEXT: v_fma_f32 v14, v15, v13, v14
-; VI-NEXT: v_fma_f32 v9, -v12, v14, v9
+; VI-NEXT: v_fma_f32 v8, -v12, v14, v8
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
+; VI-NEXT: v_div_fmas_f32 v8, v8, v13, v14
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v7
-; VI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB9_15
-; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB9_12
+; VI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v7, vcc, v10, v11
; VI-NEXT: v_add_u32_e32 v7, vcc, 11, v7
-; VI-NEXT: .LBB9_13: ; %frem.loop_body
+; VI-NEXT: .LBB9_10: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v10, v8
-; VI-NEXT: v_mul_f32_e32 v8, v10, v9
-; VI-NEXT: v_rndne_f32_e32 v8, v8
-; VI-NEXT: v_fma_f32 v8, -v8, v6, v10
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; VI-NEXT: v_add_f32_e32 v11, v8, v6
-; VI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; VI-NEXT: v_mov_b32_e32 v10, v9
+; VI-NEXT: v_mul_f32_e32 v9, v10, v8
+; VI-NEXT: v_rndne_f32_e32 v9, v9
+; VI-NEXT: v_fma_f32 v9, -v9, v6, v10
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
+; VI-NEXT: v_add_f32_e32 v11, v9, v6
+; VI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; VI-NEXT: v_add_u32_e32 v7, vcc, -11, v7
+; VI-NEXT: v_ldexp_f32 v9, v9, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v7
-; VI-NEXT: v_ldexp_f32 v8, v8, 11
-; VI-NEXT: s_cbranch_vccnz .LBB9_13
-; VI-NEXT: ; %bb.14: ; %Flow
-; VI-NEXT: v_mov_b32_e32 v8, v10
-; VI-NEXT: .LBB9_15: ; %frem.loop_exit
+; VI-NEXT: s_cbranch_vccnz .LBB9_10
+; VI-NEXT: s_branch .LBB9_13
+; VI-NEXT: .LBB9_11: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v7, 0x8000, v2
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
+; VI-NEXT: v_cndmask_b32_e32 v5, v2, v7, vcc
+; VI-NEXT: s_branch .LBB9_14
+; VI-NEXT: .LBB9_12:
+; VI-NEXT: v_mov_b32_e32 v10, v9
+; VI-NEXT: .LBB9_13: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v7, vcc, -10, v7
-; VI-NEXT: v_ldexp_f32 v7, v8, v7
-; VI-NEXT: v_mul_f32_e32 v8, v7, v9
+; VI-NEXT: v_ldexp_f32 v7, v10, v7
+; VI-NEXT: v_mul_f32_e32 v8, v7, v8
; VI-NEXT: v_rndne_f32_e32 v8, v8
; VI-NEXT: v_fma_f32 v7, -v8, v6, v7
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
@@ -5579,21 +5322,21 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v5, v6, v5
; VI-NEXT: v_cvt_f16_f32_e32 v5, v5
; VI-NEXT: s_movk_i32 s2, 0x7fff
-; VI-NEXT: v_bfi_b32 v5, s2, v5, v3
-; VI-NEXT: .LBB9_16: ; %Flow54
+; VI-NEXT: v_bfi_b32 v5, s2, v5, v2
+; VI-NEXT: .LBB9_14:
; VI-NEXT: s_movk_i32 s4, 0x7c00
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v1
; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |v0|, s4
; VI-NEXT: s_and_b64 vcc, s[2:3], vcc
; VI-NEXT: v_mov_b32_e32 v6, 0x7e00
-; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v4
-; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |v3|, s4
+; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |v2|, s4
; VI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; VI-NEXT: v_cndmask_b32_sdwa v3, v6, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_cndmask_b32_sdwa v2, v6, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -5606,33 +5349,20 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: global_load_dword v1, v2, s[2:3]
; GFX9-NEXT: global_load_dword v0, v2, s[6:7] offset:16
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v4, |v1|
+; GFX9-NEXT: v_cvt_f32_f16_e64 v3, |v1|
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v3, |v0|
-; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3
-; GFX9-NEXT: s_cbranch_vccz .LBB9_2
-; GFX9-NEXT: ; %bb.1: ; %frem.else20
-; GFX9-NEXT: v_and_b32_e32 v2, 0x8000, v1
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX9-NEXT: s_branch .LBB9_8
-; GFX9-NEXT: .LBB9_2:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr2
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB9_8
-; GFX9-NEXT: .LBB9_3: ; %frem.compute19
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v4
-; GFX9-NEXT: v_frexp_mant_f32_e32 v2, v4
-; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v3
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v8, v3
-; GFX9-NEXT: v_ldexp_f32 v3, v4, 1
+; GFX9-NEXT: v_cvt_f32_f16_e64 v2, |v0|
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2
+; GFX9-NEXT: s_cbranch_vccz .LBB9_4
+; GFX9-NEXT: ; %bb.1: ; %frem.compute19
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
+; GFX9-NEXT: v_frexp_mant_f32_e32 v3, v3
+; GFX9-NEXT: v_ldexp_f32 v6, v3, 11
+; GFX9-NEXT: v_frexp_mant_f32_e32 v3, v2
+; GFX9-NEXT: v_ldexp_f32 v3, v3, 1
; GFX9-NEXT: v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
-; GFX9-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
-; GFX9-NEXT: v_ldexp_f32 v5, v2, 11
+; GFX9-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
; GFX9-NEXT: v_add_u32_e32 v2, -1, v8
; GFX9-NEXT: v_not_b32_e32 v4, v2
; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
@@ -5640,37 +5370,43 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; GFX9-NEXT: v_fma_f32 v10, v11, v10, v10
-; GFX9-NEXT: v_mul_f32_e32 v11, v6, v10
-; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v6
+; GFX9-NEXT: v_mul_f32_e32 v11, v5, v10
+; GFX9-NEXT: v_fma_f32 v12, -v9, v11, v5
; GFX9-NEXT: v_fma_f32 v11, v12, v10, v11
-; GFX9-NEXT: v_fma_f32 v6, -v9, v11, v6
+; GFX9-NEXT: v_fma_f32 v5, -v9, v11, v5
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v6, v6, v10, v11
+; GFX9-NEXT: v_div_fmas_f32 v5, v5, v10, v11
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; GFX9-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_7
-; GFX9-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
+; GFX9-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_5
+; GFX9-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
; GFX9-NEXT: v_sub_u32_e32 v4, v7, v8
; GFX9-NEXT: v_add_u32_e32 v4, 11, v4
-; GFX9-NEXT: .LBB9_5: ; %frem.loop_body27
+; GFX9-NEXT: .LBB9_3: ; %frem.loop_body27
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
-; GFX9-NEXT: v_mul_f32_e32 v5, v7, v6
-; GFX9-NEXT: v_rndne_f32_e32 v5, v5
-; GFX9-NEXT: v_fma_f32 v5, -v5, v3, v7
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; GFX9-NEXT: v_add_f32_e32 v8, v5, v3
+; GFX9-NEXT: v_mov_b32_e32 v7, v6
+; GFX9-NEXT: v_mul_f32_e32 v6, v7, v5
+; GFX9-NEXT: v_rndne_f32_e32 v6, v6
+; GFX9-NEXT: v_fma_f32 v6, -v6, v3, v7
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; GFX9-NEXT: v_add_f32_e32 v8, v6, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GFX9-NEXT: v_add_u32_e32 v4, -11, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX9-NEXT: v_ldexp_f32 v6, v6, 11
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; GFX9-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_5
-; GFX9-NEXT: ; %bb.6: ; %Flow55
-; GFX9-NEXT: v_mov_b32_e32 v5, v7
-; GFX9-NEXT: .LBB9_7: ; %frem.loop_exit28
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_3
+; GFX9-NEXT: s_branch .LBB9_6
+; GFX9-NEXT: .LBB9_4: ; %frem.else20
+; GFX9-NEXT: v_and_b32_e32 v4, 0x8000, v1
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v4, vcc
+; GFX9-NEXT: s_branch .LBB9_7
+; GFX9-NEXT: .LBB9_5:
+; GFX9-NEXT: v_mov_b32_e32 v7, v6
+; GFX9-NEXT: .LBB9_6: ; %frem.loop_exit28
; GFX9-NEXT: v_add_u32_e32 v4, -10, v4
-; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
-; GFX9-NEXT: v_mul_f32_e32 v5, v4, v6
+; GFX9-NEXT: v_ldexp_f32 v4, v7, v4
+; GFX9-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX9-NEXT: v_rndne_f32_e32 v5, v5
; GFX9-NEXT: v_fma_f32 v4, -v5, v3, v4
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
@@ -5680,34 +5416,21 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v2, s2, v2, v1
-; GFX9-NEXT: .LBB9_8:
+; GFX9-NEXT: .LBB9_7:
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX9-NEXT: v_cvt_f32_f16_e64 v6, |v3|
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v5, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
-; GFX9-NEXT: s_cbranch_vccz .LBB9_10
-; GFX9-NEXT: ; %bb.9: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v4, 0x8000, v3
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB9_11
-; GFX9-NEXT: s_branch .LBB9_16
-; GFX9-NEXT: .LBB9_10:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr4
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB9_16
-; GFX9-NEXT: .LBB9_11: ; %frem.compute
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v6
-; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v6
-; GFX9-NEXT: v_frexp_mant_f32_e32 v6, v5
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v5
-; GFX9-NEXT: v_ldexp_f32 v5, v6, 1
+; GFX9-NEXT: v_cvt_f32_f16_e64 v5, |v3|
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v4, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
+; GFX9-NEXT: s_cbranch_vccz .LBB9_11
+; GFX9-NEXT: ; %bb.8: ; %frem.compute
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v5
+; GFX9-NEXT: v_frexp_mant_f32_e32 v5, v5
+; GFX9-NEXT: v_ldexp_f32 v8, v5, 11
+; GFX9-NEXT: v_frexp_mant_f32_e32 v5, v4
+; GFX9-NEXT: v_ldexp_f32 v5, v5, 1
; GFX9-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
-; GFX9-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
-; GFX9-NEXT: v_ldexp_f32 v7, v4, 11
+; GFX9-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v4
; GFX9-NEXT: v_add_u32_e32 v4, -1, v10
; GFX9-NEXT: v_not_b32_e32 v6, v4
; GFX9-NEXT: v_add_u32_e32 v6, v6, v9
@@ -5715,37 +5438,43 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; GFX9-NEXT: v_fma_f32 v12, v13, v12, v12
-; GFX9-NEXT: v_mul_f32_e32 v13, v8, v12
-; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v8
+; GFX9-NEXT: v_mul_f32_e32 v13, v7, v12
+; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v7
; GFX9-NEXT: v_fma_f32 v13, v14, v12, v13
-; GFX9-NEXT: v_fma_f32 v8, -v11, v13, v8
+; GFX9-NEXT: v_fma_f32 v7, -v11, v13, v7
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v8, v8, v12, v13
+; GFX9-NEXT: v_div_fmas_f32 v7, v7, v12, v13
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
-; GFX9-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX9-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_12
+; GFX9-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT: v_add_u32_e32 v6, 11, v6
-; GFX9-NEXT: .LBB9_13: ; %frem.loop_body
+; GFX9-NEXT: .LBB9_10: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v9, v7
-; GFX9-NEXT: v_mul_f32_e32 v7, v9, v8
-; GFX9-NEXT: v_rndne_f32_e32 v7, v7
-; GFX9-NEXT: v_fma_f32 v7, -v7, v5, v9
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; GFX9-NEXT: v_add_f32_e32 v10, v7, v5
+; GFX9-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-NEXT: v_mul_f32_e32 v8, v9, v7
+; GFX9-NEXT: v_rndne_f32_e32 v8, v8
+; GFX9-NEXT: v_fma_f32 v8, -v8, v5, v9
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; GFX9-NEXT: v_add_f32_e32 v10, v8, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GFX9-NEXT: v_add_u32_e32 v6, -11, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; GFX9-NEXT: v_ldexp_f32 v8, v8, 11
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
-; GFX9-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB9_13
-; GFX9-NEXT: ; %bb.14: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v7, v9
-; GFX9-NEXT: .LBB9_15: ; %frem.loop_exit
+; GFX9-NEXT: s_cbranch_vccnz .LBB9_10
+; GFX9-NEXT: s_branch .LBB9_13
+; GFX9-NEXT: .LBB9_11: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v6, 0x8000, v3
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v6, vcc
+; GFX9-NEXT: s_branch .LBB9_14
+; GFX9-NEXT: .LBB9_12:
+; GFX9-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-NEXT: .LBB9_13: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v6, -10, v6
-; GFX9-NEXT: v_ldexp_f32 v6, v7, v6
-; GFX9-NEXT: v_mul_f32_e32 v7, v6, v8
+; GFX9-NEXT: v_ldexp_f32 v6, v9, v6
+; GFX9-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX9-NEXT: v_rndne_f32_e32 v7, v7
; GFX9-NEXT: v_fma_f32 v6, -v7, v5, v6
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -5755,7 +5484,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v3
-; GFX9-NEXT: .LBB9_16: ; %Flow54
+; GFX9-NEXT: .LBB9_14:
; GFX9-NEXT: s_movk_i32 s4, 0x7c00
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v0
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v1|, s4
@@ -5782,37 +5511,24 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: global_load_dword v1, v2, s[2:3]
; GFX10-NEXT: global_load_dword v0, v2, s[6:7] offset:16
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v4, |v1|
+; GFX10-NEXT: v_cvt_f32_f16_e64 v3, |v1|
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v3, |v0|
-; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v3
-; GFX10-NEXT: s_cbranch_vccz .LBB9_2
-; GFX10-NEXT: ; %bb.1: ; %frem.else20
-; GFX10-NEXT: v_and_b32_e32 v2, 0x8000, v1
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX10-NEXT: s_branch .LBB9_8
-; GFX10-NEXT: .LBB9_2:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr2
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB9_8
-; GFX10-NEXT: .LBB9_3: ; %frem.compute19
-; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v4
-; GFX10-NEXT: v_frexp_mant_f32_e32 v6, v3
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; GFX10-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
-; GFX10-NEXT: v_ldexp_f32 v3, v6, 1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v2, |v0|
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
+; GFX10-NEXT: s_cbranch_vccz .LBB9_5
+; GFX10-NEXT: ; %bb.1: ; %frem.compute19
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v5, v3
+; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v3
; GFX10-NEXT: v_readfirstlane_b32 s2, v5
+; GFX10-NEXT: v_ldexp_f32 v4, v3, 11
+; GFX10-NEXT: v_frexp_mant_f32_e32 v3, v2
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
+; GFX10-NEXT: v_ldexp_f32 v3, v3, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v2
-; GFX10-NEXT: v_div_scale_f32 v7, s4, v3, v3, 1.0
; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX10-NEXT: v_rcp_f32_e32 v8, v7
+; GFX10-NEXT: v_div_scale_f32 v7, s4, v3, v3, 1.0
; GFX10-NEXT: v_not_b32_e32 v6, v2
+; GFX10-NEXT: v_rcp_f32_e32 v8, v7
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -5826,11 +5542,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX10-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB9_7
-; GFX10-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB9_6
+; GFX10-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB9_5: ; %frem.loop_body27
+; GFX10-NEXT: .LBB9_3: ; %frem.loop_body27
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -5842,13 +5558,20 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v6, v4, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB9_5
-; GFX10-NEXT: ; %bb.6: ; %Flow55
+; GFX10-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX10-NEXT: ; %bb.4:
; GFX10-NEXT: v_mov_b32_e32 v6, s2
-; GFX10-NEXT: v_mov_b32_e32 v4, v7
+; GFX10-NEXT: s_branch .LBB9_7
+; GFX10-NEXT: .LBB9_5: ; %frem.else20
+; GFX10-NEXT: v_and_b32_e32 v4, 0x8000, v1
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v4, vcc_lo
+; GFX10-NEXT: s_branch .LBB9_8
+; GFX10-NEXT: .LBB9_6:
+; GFX10-NEXT: v_mov_b32_e32 v7, v4
; GFX10-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX10-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX10-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX10-NEXT: v_add_nc_u32_e32 v4, -10, v6
+; GFX10-NEXT: v_ldexp_f32 v4, v7, v4
; GFX10-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX10-NEXT: v_rndne_f32_e32 v5, v5
; GFX10-NEXT: v_fma_f32 v4, -v5, v3, v4
@@ -5860,36 +5583,23 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_bfi_b32 v2, 0x7fff, v2, v1
; GFX10-NEXT: .LBB9_8:
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e64 v6, |v3|
-; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v6, v5
-; GFX10-NEXT: s_cbranch_vccz .LBB9_10
-; GFX10-NEXT: ; %bb.9: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v4, 0x8000, v3
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB9_11
-; GFX10-NEXT: s_branch .LBB9_16
-; GFX10-NEXT: .LBB9_10:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB9_16
-; GFX10-NEXT: .LBB9_11: ; %frem.compute
-; GFX10-NEXT: v_frexp_mant_f32_e32 v4, v6
-; GFX10-NEXT: v_frexp_mant_f32_e32 v8, v5
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
-; GFX10-NEXT: v_ldexp_f32 v6, v4, 11
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v4, v5
-; GFX10-NEXT: v_ldexp_f32 v5, v8, 1
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v4, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v5, |v3|
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
+; GFX10-NEXT: s_cbranch_vccz .LBB9_13
+; GFX10-NEXT: ; %bb.9: ; %frem.compute
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v5
+; GFX10-NEXT: v_frexp_mant_f32_e32 v5, v5
; GFX10-NEXT: v_readfirstlane_b32 s2, v7
+; GFX10-NEXT: v_ldexp_f32 v6, v5, 11
+; GFX10-NEXT: v_frexp_mant_f32_e32 v5, v4
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
+; GFX10-NEXT: v_ldexp_f32 v5, v5, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v4
-; GFX10-NEXT: v_div_scale_f32 v9, s4, v5, v5, 1.0
; GFX10-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX10-NEXT: v_rcp_f32_e32 v10, v9
+; GFX10-NEXT: v_div_scale_f32 v9, s4, v5, v5, 1.0
; GFX10-NEXT: v_not_b32_e32 v8, v4
+; GFX10-NEXT: v_rcp_f32_e32 v10, v9
; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX10-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -5903,11 +5613,11 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX10-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX10-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB9_14
+; GFX10-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB9_13: ; %frem.loop_body
+; GFX10-NEXT: .LBB9_11: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -5919,13 +5629,20 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v8, v6, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v6, v6, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB9_13
-; GFX10-NEXT: ; %bb.14: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB9_11
+; GFX10-NEXT: ; %bb.12:
; GFX10-NEXT: v_mov_b32_e32 v8, s2
-; GFX10-NEXT: v_mov_b32_e32 v6, v9
+; GFX10-NEXT: s_branch .LBB9_15
+; GFX10-NEXT: .LBB9_13: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v6, 0x8000, v3
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v6, vcc_lo
+; GFX10-NEXT: s_branch .LBB9_16
+; GFX10-NEXT: .LBB9_14:
+; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v8, -10, v8
-; GFX10-NEXT: v_ldexp_f32 v6, v6, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v6, -10, v8
+; GFX10-NEXT: v_ldexp_f32 v6, v9, v6
; GFX10-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX10-NEXT: v_rndne_f32_e32 v7, v7
; GFX10-NEXT: v_fma_f32 v6, -v7, v5, v6
@@ -5935,7 +5652,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v4, v5, v4
; GFX10-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX10-NEXT: v_bfi_b32 v4, 0x7fff, v4, v3
-; GFX10-NEXT: .LBB9_16: ; %Flow54
+; GFX10-NEXT: .LBB9_16:
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v1|
; GFX10-NEXT: v_cmp_nle_f16_e64 s3, 0x7c00, |v3|
@@ -5961,43 +5678,27 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: global_load_b32 v0, v1, s[2:3]
; GFX11-TRUE16-NEXT: global_load_b32 v1, v1, s[4:5] offset:16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v4, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.l|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, |v1.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v3
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else20
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX11-TRUE16-NEXT: s_branch .LBB9_7
-; GFX11-TRUE16-NEXT: .LBB9_2:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB9_7
-; GFX11-TRUE16-NEXT: .LBB9_3: ; %frem.compute19
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v4
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_5
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.compute19
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v3
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v2
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v3
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v5, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v5, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v4, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX11-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
@@ -6016,12 +5717,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_6
-; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_4
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB9_5: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT: .LBB9_3: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -6036,49 +5737,39 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_5
-; GFX11-TRUE16-NEXT: .LBB9_6: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX11-TRUE16-NEXT: .LBB9_4: ; %frem.loop_exit28
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX11-TRUE16-NEXT: .LBB9_7:
+; GFX11-TRUE16-NEXT: s_branch .LBB9_6
+; GFX11-TRUE16-NEXT: .LBB9_5: ; %frem.else20
+; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v2, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: .LBB9_6:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, |v3.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v5, |v3.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, |v4.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v6
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_9
-; GFX11-TRUE16-NEXT: ; %bb.8: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_10
-; GFX11-TRUE16-NEXT: s_branch .LBB9_14
-; GFX11-TRUE16-NEXT: .LBB9_9:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB9_14
-; GFX11-TRUE16-NEXT: .LBB9_10: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v7
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v6
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v6
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_11
+; GFX11-TRUE16-NEXT: ; %bb.7: ; %frem.compute
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v6
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v8
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v5
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, -1, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v7, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v7, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v8, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v7
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v8, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, null, v6, v6, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v7, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v10, v9
; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v6, 1.0
@@ -6097,12 +5788,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v7, v7, v6, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_13
-; GFX11-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_10
+; GFX11-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB9_12: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB9_9: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v5, v7
@@ -6117,10 +5808,16 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_12
-; GFX11-TRUE16-NEXT: .LBB9_13: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX11-TRUE16-NEXT: .LBB9_10: ; %frem.loop_exit
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-TRUE16-NEXT: .LBB9_14: ; %Flow54
+; GFX11-TRUE16-NEXT: s_branch .LBB9_12
+; GFX11-TRUE16-NEXT: .LBB9_11: ; %frem.else
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: .LBB9_12:
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
@@ -6145,44 +5842,29 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: global_load_b32 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: global_load_b32 v1, v1, s[4:5] offset:16
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v4, |v0|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, |v0|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v3, |v1|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v2, |v1|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v3
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB9_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.else20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0x8000, v0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v3
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX11-FAKE16-NEXT: s_branch .LBB9_8
-; GFX11-FAKE16-NEXT: .LBB9_2:
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB9_8
-; GFX11-FAKE16-NEXT: .LBB9_3: ; %frem.compute19
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, v4
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v6, v3
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v6, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB9_5
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.compute19
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v3
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v3, 11
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, v2
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX11-FAKE16-NEXT: v_not_b32_e32 v6, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
; GFX11-FAKE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -6201,12 +5883,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_7
-; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_6
+; GFX11-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB9_5: ; %frem.loop_body27
+; GFX11-FAKE16-NEXT: .LBB9_3: ; %frem.loop_body27
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -6222,14 +5904,22 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_5
-; GFX11-FAKE16-NEXT: ; %bb.6: ; %Flow55
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX11-FAKE16-NEXT: ; %bb.4:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-FAKE16-NEXT: s_branch .LBB9_7
+; GFX11-FAKE16-NEXT: .LBB9_5: ; %frem.else20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x8000, v0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB9_8
+; GFX11-FAKE16-NEXT: .LBB9_6:
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v4
; GFX11-FAKE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -6247,43 +5937,28 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v7, |v3|
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, |v4|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, |v3|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v5, |v4|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v6
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB9_10
-; GFX11-FAKE16-NEXT: ; %bb.9: ; %frem.else
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0x8000, v3
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
-; GFX11-FAKE16-NEXT: s_branch .LBB9_16
-; GFX11-FAKE16-NEXT: .LBB9_10:
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB9_16
-; GFX11-FAKE16-NEXT: .LBB9_11: ; %frem.compute
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v5, v7
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v9, v6
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v5, 11
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v6
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v9, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v5
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB9_13
+; GFX11-FAKE16-NEXT: ; %bb.9: ; %frem.compute
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v6
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v6, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v8
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v6, 11
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v6, v5
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v6, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_div_scale_f32 v10, null, v6, v6, 1.0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v11, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_div_scale_f32 v10, null, v6, v6, 1.0
; GFX11-FAKE16-NEXT: v_not_b32_e32 v9, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v11, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v8
; GFX11-FAKE16-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -6302,12 +5977,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX11-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_14
+; GFX11-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB9_13: ; %frem.loop_body
+; GFX11-FAKE16-NEXT: .LBB9_11: ; %frem.loop_body
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, v7
@@ -6323,14 +5998,22 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_13
-; GFX11-FAKE16-NEXT: ; %bb.14: ; %Flow
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
+; GFX11-FAKE16-NEXT: ; %bb.12:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, s2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v10
+; GFX11-FAKE16-NEXT: s_branch .LBB9_15
+; GFX11-FAKE16-NEXT: .LBB9_13: ; %frem.else
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0x8000, v3
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB9_16
+; GFX11-FAKE16-NEXT: .LBB9_14:
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, v7
; GFX11-FAKE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, -10, v9
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v7, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, -10, v9
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v7, v10, v7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v8, v7, v8
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v8, v8
@@ -6344,7 +6027,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX11-FAKE16-NEXT: v_bfi_b32 v5, 0x7fff, v5, v3
-; GFX11-FAKE16-NEXT: .LBB9_16: ; %Flow54
+; GFX11-FAKE16-NEXT: .LBB9_16:
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
@@ -6375,39 +6058,22 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
; GFX1150-TRUE16-NEXT: s_and_b32 s2, s4, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s5, s3, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s2
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s5, s5
+; GFX1150-TRUE16-NEXT: s_and_b32 s6, s3, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s5, s2
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s6, s5
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_2
-; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.else20
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s6, s5
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s4
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s7
-; GFX1150-TRUE16-NEXT: s_mov_b32 s7, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX1150-TRUE16-NEXT: s_branch .LBB9_7
-; GFX1150-TRUE16-NEXT: .LBB9_2:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s7, -1
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_7
-; GFX1150-TRUE16-NEXT: .LBB9_3: ; %frem.compute19
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
+; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s5, s6
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_5
+; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.compute19
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s5
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v2
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6431,12 +6097,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_6
-; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s5, s6, s5
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_4
+; GFX1150-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s5, s5, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s5, s5, 11
-; GFX1150-TRUE16-NEXT: .LBB9_5: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT: .LBB9_3: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -6452,46 +6118,36 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_5
-; GFX1150-TRUE16-NEXT: .LBB9_6: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX1150-TRUE16-NEXT: .LBB9_4: ; %frem.loop_exit28
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: .LBB9_7:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
+; GFX1150-TRUE16-NEXT: s_branch .LBB9_6
+; GFX1150-TRUE16-NEXT: .LBB9_5: ; %frem.else20
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s5, s6
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s4
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s5, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s5
+; GFX1150-TRUE16-NEXT: .LBB9_6:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s6, s5, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s7, s4
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1150-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_9
-; GFX1150-TRUE16-NEXT: ; %bb.8: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
-; GFX1150-TRUE16-NEXT: s_mov_b32 s8, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_10
-; GFX1150-TRUE16-NEXT: s_branch .LBB9_14
-; GFX1150-TRUE16-NEXT: .LBB9_9:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s8, -1
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_14
-; GFX1150-TRUE16-NEXT: .LBB9_10: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s7
+; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s8, s7
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_11
+; GFX1150-TRUE16-NEXT: ; %bb.7: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s7
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s7
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s7, v4
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6515,12 +6171,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_13
-; GFX1150-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s7, s6
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_10
+; GFX1150-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s6, s7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-TRUE16-NEXT: .LBB9_12: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: .LBB9_9: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -6536,10 +6192,17 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_12
-; GFX1150-TRUE16-NEXT: .LBB9_13: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX1150-TRUE16-NEXT: .LBB9_10: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB9_14: ; %Flow54
+; GFX1150-TRUE16-NEXT: s_branch .LBB9_12
+; GFX1150-TRUE16-NEXT: .LBB9_11: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s8, s7
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s6
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s7
+; GFX1150-TRUE16-NEXT: .LBB9_12:
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -6573,42 +6236,25 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s3, v0
; GFX1150-FAKE16-NEXT: s_and_b32 s2, s4, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s5, s3, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s6, s2
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s5, s5
+; GFX1150-FAKE16-NEXT: s_and_b32 s6, s3, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s5, s2
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s6, s5
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_2
-; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.else20
-; GFX1150-FAKE16-NEXT: s_and_b32 s7, 0x8000, s4
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s6, s5
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v0, s7
-; GFX1150-FAKE16-NEXT: s_mov_b32 s7, 0
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
-; GFX1150-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX1150-FAKE16-NEXT: s_branch .LBB9_8
-; GFX1150-FAKE16-NEXT: .LBB9_2:
-; GFX1150-FAKE16-NEXT: s_mov_b32 s7, -1
-; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_8
-; GFX1150-FAKE16-NEXT: .LBB9_3: ; %frem.compute19
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s5
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s5, s6
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_5
+; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.compute19
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s6
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s5
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v1, v1, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s5, v3
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6630,12 +6276,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_7
-; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s5, s6, s5
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_6
+; GFX1150-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s5, s5, s6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s5, s5, 11
-; GFX1150-FAKE16-NEXT: .LBB9_5: ; %frem.loop_body27
+; GFX1150-FAKE16-NEXT: .LBB9_3: ; %frem.loop_body27
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -6653,14 +6299,24 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_5
-; GFX1150-FAKE16-NEXT: ; %bb.6: ; %Flow55
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX1150-FAKE16-NEXT: ; %bb.4:
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, s5
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-FAKE16-NEXT: s_branch .LBB9_7
+; GFX1150-FAKE16-NEXT: .LBB9_5: ; %frem.else20
+; GFX1150-FAKE16-NEXT: s_and_b32 s7, 0x8000, s4
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s5, s6
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v0, s7
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB9_8
+; GFX1150-FAKE16-NEXT: .LBB9_6:
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1150-FAKE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v2, -10, v4
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v5, v2
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v3, v3
@@ -6680,42 +6336,25 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1150-FAKE16-NEXT: s_lshr_b32 s5, s3, 16
; GFX1150-FAKE16-NEXT: s_and_b32 s4, s6, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s7, s5, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s8, s4
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s7, s7
+; GFX1150-FAKE16-NEXT: s_and_b32 s8, s5, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s7, s4
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s8, s7
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_10
-; GFX1150-FAKE16-NEXT: ; %bb.9: ; %frem.else
-; GFX1150-FAKE16-NEXT: s_and_b32 s9, 0x8000, s6
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s8, s7
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v1, s9
-; GFX1150-FAKE16-NEXT: s_mov_b32 s9, 0
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
-; GFX1150-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
-; GFX1150-FAKE16-NEXT: s_branch .LBB9_16
-; GFX1150-FAKE16-NEXT: .LBB9_10:
-; GFX1150-FAKE16-NEXT: s_mov_b32 s9, -1
-; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_16
-; GFX1150-FAKE16-NEXT: .LBB9_11: ; %frem.compute
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s7
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s8
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s7, s8
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB9_13
+; GFX1150-FAKE16-NEXT: ; %bb.9: ; %frem.compute
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s8
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s7
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s8
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s7, v4
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -6737,12 +6376,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX1150-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s7, s8, s7
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB9_14
+; GFX1150-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s7, s7, s8
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s7, s7, 11
-; GFX1150-FAKE16-NEXT: .LBB9_13: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT: .LBB9_11: ; %frem.loop_body
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -6760,14 +6399,24 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_13
-; GFX1150-FAKE16-NEXT: ; %bb.14: ; %Flow
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
+; GFX1150-FAKE16-NEXT: ; %bb.12:
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, s7
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-FAKE16-NEXT: s_branch .LBB9_15
+; GFX1150-FAKE16-NEXT: .LBB9_13: ; %frem.else
+; GFX1150-FAKE16-NEXT: s_and_b32 s9, 0x8000, s6
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s7, s8
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v1, s9
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB9_16
+; GFX1150-FAKE16-NEXT: .LBB9_14:
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, v3
; GFX1150-FAKE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v3, -10, v5
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v6, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v4, v4
@@ -6783,7 +6432,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s6
-; GFX1150-FAKE16-NEXT: .LBB9_16: ; %Flow54
+; GFX1150-FAKE16-NEXT: .LBB9_16:
; GFX1150-FAKE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -6819,39 +6468,22 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
; GFX1200-TRUE16-NEXT: s_and_b32 s2, s4, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s5, s3, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s2
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s5, s5
+; GFX1200-TRUE16-NEXT: s_and_b32 s6, s3, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s5, s2
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s6, s5
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_2
-; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.else20
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s6, s5
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s4
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s7
-; GFX1200-TRUE16-NEXT: s_mov_b32 s7, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX1200-TRUE16-NEXT: s_branch .LBB9_7
-; GFX1200-TRUE16-NEXT: .LBB9_2:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s7, -1
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_7
-; GFX1200-TRUE16-NEXT: .LBB9_3: ; %frem.compute19
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
+; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s5, s6
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_5
+; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.compute19
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s5
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v2
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6875,12 +6507,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_6
-; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s5, s6, s5
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_4
+; GFX1200-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s5, s5, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s5, s5, 11
-; GFX1200-TRUE16-NEXT: .LBB9_5: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT: .LBB9_3: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -6899,50 +6531,40 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_5
-; GFX1200-TRUE16-NEXT: .LBB9_6: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX1200-TRUE16-NEXT: .LBB9_4: ; %frem.loop_exit28
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: .LBB9_7:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
+; GFX1200-TRUE16-NEXT: s_branch .LBB9_6
+; GFX1200-TRUE16-NEXT: .LBB9_5: ; %frem.else20
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s5, s6
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s4
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s5, -1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s4, v0.l, s5
+; GFX1200-TRUE16-NEXT: .LBB9_6:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
-; GFX1200-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s6, s5, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s4
+; GFX1200-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_9
-; GFX1200-TRUE16-NEXT: ; %bb.8: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
-; GFX1200-TRUE16-NEXT: s_mov_b32 s8, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_10
-; GFX1200-TRUE16-NEXT: s_branch .LBB9_14
-; GFX1200-TRUE16-NEXT: .LBB9_9:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s8, -1
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_14
-; GFX1200-TRUE16-NEXT: .LBB9_10: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s7
+; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s8, s7
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_11
+; GFX1200-TRUE16-NEXT: ; %bb.7: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s7
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s7
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6967,12 +6589,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_13
-; GFX1200-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s7, s6
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_10
+; GFX1200-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s6, s7
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-TRUE16-NEXT: .LBB9_12: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: .LBB9_9: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -6991,10 +6613,18 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_12
-; GFX1200-TRUE16-NEXT: .LBB9_13: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
+; GFX1200-TRUE16-NEXT: .LBB9_10: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB9_14: ; %Flow54
+; GFX1200-TRUE16-NEXT: s_branch .LBB9_12
+; GFX1200-TRUE16-NEXT: .LBB9_11: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s8, s7
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s6
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s7
+; GFX1200-TRUE16-NEXT: .LBB9_12:
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -7029,43 +6659,25 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s3, v0
; GFX1200-FAKE16-NEXT: s_and_b32 s2, s4, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s5, s3, 0x7fff
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s6, s2
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s5, s5
+; GFX1200-FAKE16-NEXT: s_and_b32 s6, s3, 0x7fff
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s5, s2
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s6, s6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s6, s5
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_2
-; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.else20
-; GFX1200-FAKE16-NEXT: s_and_b32 s7, 0x8000, s4
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s6, s5
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, s7
-; GFX1200-FAKE16-NEXT: s_mov_b32 s7, 0
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
-; GFX1200-FAKE16-NEXT: s_branch .LBB9_8
-; GFX1200-FAKE16-NEXT: .LBB9_2:
-; GFX1200-FAKE16-NEXT: s_mov_b32 s7, -1
-; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-FAKE16-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_8
-; GFX1200-FAKE16-NEXT: .LBB9_3: ; %frem.compute19
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s5
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s5, s6
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_5
+; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.compute19
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s6
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s5
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v1, v1, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s5, v3
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -7083,17 +6695,16 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v7, v8, v6
; GFX1200-FAKE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_7
-; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body27.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s5, s6, s5
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_6
+; GFX1200-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body27.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s5, s5, s6
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s5, s5, 11
-; GFX1200-FAKE16-NEXT: .LBB9_5: ; %frem.loop_body27
+; GFX1200-FAKE16-NEXT: .LBB9_3: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -7113,14 +6724,24 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_5
-; GFX1200-FAKE16-NEXT: ; %bb.6: ; %Flow55
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_3
+; GFX1200-FAKE16-NEXT: ; %bb.4:
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, s5
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-FAKE16-NEXT: s_branch .LBB9_7
+; GFX1200-FAKE16-NEXT: .LBB9_5: ; %frem.else20
+; GFX1200-FAKE16-NEXT: s_and_b32 s7, 0x8000, s4
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s5, s6
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, s7
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s4, v0, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB9_8
+; GFX1200-FAKE16-NEXT: .LBB9_6:
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1200-FAKE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v2, -10, v4
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v5, v2
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v3, v3
@@ -7142,45 +6763,27 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_lshr_b32 s5, s3, 16
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 s4, s6, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s7, s5, 0x7fff
+; GFX1200-FAKE16-NEXT: s_and_b32 s8, s5, 0x7fff
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s8, s4
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s7, s7
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s7, s4
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s8, s7
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_10
-; GFX1200-FAKE16-NEXT: ; %bb.9: ; %frem.else
-; GFX1200-FAKE16-NEXT: s_and_b32 s9, 0x8000, s6
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s8, s7
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, s9
-; GFX1200-FAKE16-NEXT: s_mov_b32 s9, 0
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
-; GFX1200-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
-; GFX1200-FAKE16-NEXT: s_branch .LBB9_16
-; GFX1200-FAKE16-NEXT: .LBB9_10:
-; GFX1200-FAKE16-NEXT: s_mov_b32 s9, -1
-; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_16
-; GFX1200-FAKE16-NEXT: .LBB9_11: ; %frem.compute
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s7
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s8
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s7, s8
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB9_13
+; GFX1200-FAKE16-NEXT: ; %bb.9: ; %frem.compute
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s8
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s7
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s7
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s8
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s7, v4
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -7203,12 +6806,12 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX1200-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s7, s8, s7
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB9_14
+; GFX1200-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s7, s7, s8
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s7, s7, 11
-; GFX1200-FAKE16-NEXT: .LBB9_13: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT: .LBB9_11: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -7228,14 +6831,25 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_13
-; GFX1200-FAKE16-NEXT: ; %bb.14: ; %Flow
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB9_11
+; GFX1200-FAKE16-NEXT: ; %bb.12:
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, s7
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1200-FAKE16-NEXT: s_branch .LBB9_15
+; GFX1200-FAKE16-NEXT: .LBB9_13: ; %frem.else
+; GFX1200-FAKE16-NEXT: s_and_b32 s9, 0x8000, s6
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s7, s8
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, s9
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB9_16
+; GFX1200-FAKE16-NEXT: .LBB9_14:
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
; GFX1200-FAKE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v3, -10, v5
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v6, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v4, v4
@@ -7252,7 +6866,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s6
-; GFX1200-FAKE16-NEXT: .LBB9_16: ; %Flow54
+; GFX1200-FAKE16-NEXT: .LBB9_16:
; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-FAKE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -7298,252 +6912,219 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s2, v1
-; SI-NEXT: v_readfirstlane_b32 s3, v0
+; SI-NEXT: v_readfirstlane_b32 s0, v0
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 offset:32
-; SI-NEXT: v_cvt_f32_f16_e64 v3, |s3|
+; SI-NEXT: v_cvt_f32_f16_e64 v4, |s0|
+; SI-NEXT: s_lshr_b32 s3, s0, 16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e64 v2, |v0|
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2
-; SI-NEXT: s_cbranch_vccz .LBB10_3
-; SI-NEXT: ; %bb.1: ; %frem.else86
-; SI-NEXT: s_and_b32 s4, s3, 0xffff8000
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: s_cselect_b32 s4, s4, s3
-; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc1 .LBB10_4
-; SI-NEXT: .LBB10_2:
-; SI-NEXT: v_mov_b32_e32 v3, s4
-; SI-NEXT: s_branch .LBB10_9
-; SI-NEXT: .LBB10_3:
-; SI-NEXT: s_mov_b64 s[0:1], -1
-; SI-NEXT: ; implicit-def: $sgpr4
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc0 .LBB10_2
-; SI-NEXT: .LBB10_4: ; %frem.compute85
-; SI-NEXT: s_mov_b32 s5, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s5
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v3
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v4
-; SI-NEXT: v_frexp_mant_f32_e32 v4, v3
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v2|, s5
-; SI-NEXT: v_frexp_mant_f32_e32 v4, v2
-; SI-NEXT: s_cselect_b32 s4, s0, 0
-; SI-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: v_ldexp_f32_e64 v2, v4, 1
-; SI-NEXT: v_div_scale_f32 v5, s[6:7], v2, v2, 1.0
-; SI-NEXT: v_rcp_f32_e32 v6, v5
-; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
-; SI-NEXT: v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
+; SI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3
+; SI-NEXT: s_cbranch_vccz .LBB10_4
+; SI-NEXT: ; %bb.1: ; %frem.compute85
+; SI-NEXT: s_mov_b32 s1, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s1
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s4, v5
+; SI-NEXT: v_frexp_mant_f32_e32 v5, v4
+; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s1
+; SI-NEXT: v_frexp_mant_f32_e32 v5, v3
+; SI-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
+; SI-NEXT: v_readfirstlane_b32 s1, v3
+; SI-NEXT: v_ldexp_f32_e64 v3, v5, 1
+; SI-NEXT: v_div_scale_f32 v6, s[10:11], v3, v3, 1.0
+; SI-NEXT: v_rcp_f32_e32 v7, v6
+; SI-NEXT: s_cselect_b32 s5, s4, 0
+; SI-NEXT: v_ldexp_f32_e64 v4, v4, 11
+; SI-NEXT: s_and_b64 s[6:7], vcc, exec
+; SI-NEXT: v_div_scale_f32 v5, vcc, 1.0, v3, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT: v_fma_f32 v7, -v5, v6, 1.0
-; SI-NEXT: v_fma_f32 v6, v7, v6, v6
-; SI-NEXT: v_mul_f32_e32 v7, v4, v6
-; SI-NEXT: s_cselect_b32 s5, s0, 0
-; SI-NEXT: v_fma_f32 v8, -v5, v7, v4
-; SI-NEXT: s_add_i32 s0, s5, -1
-; SI-NEXT: v_fma_f32 v7, v8, v6, v7
-; SI-NEXT: s_not_b32 s1, s0
-; SI-NEXT: v_fma_f32 v4, -v5, v7, v4
+; SI-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; SI-NEXT: v_fma_f32 v7, v8, v7, v7
+; SI-NEXT: v_mul_f32_e32 v8, v5, v7
+; SI-NEXT: s_cselect_b32 s6, s1, 0
+; SI-NEXT: v_fma_f32 v9, -v6, v8, v5
+; SI-NEXT: s_add_i32 s1, s6, -1
+; SI-NEXT: v_fma_f32 v8, v9, v7, v8
+; SI-NEXT: s_not_b32 s4, s1
+; SI-NEXT: v_fma_f32 v5, -v6, v8, v5
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT: s_add_i32 s1, s1, s4
-; SI-NEXT: v_div_fmas_f32 v4, v4, v6, v7
-; SI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_8
-; SI-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
-; SI-NEXT: s_sub_i32 s1, s4, s5
-; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB10_6: ; %frem.loop_body93
+; SI-NEXT: s_add_i32 s4, s4, s5
+; SI-NEXT: v_div_fmas_f32 v5, v5, v7, v8
+; SI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; SI-NEXT: s_cmp_lt_i32 s4, 12
+; SI-NEXT: s_cbranch_scc1 .LBB10_5
+; SI-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; SI-NEXT: s_sub_i32 s4, s5, s6
+; SI-NEXT: s_add_i32 s4, s4, 11
+; SI-NEXT: .LBB10_3: ; %frem.loop_body93
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v5, v3
-; SI-NEXT: v_mul_f32_e32 v3, v5, v4
-; SI-NEXT: v_rndne_f32_e32 v3, v3
-; SI-NEXT: v_fma_f32 v3, -v3, v2, v5
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; SI-NEXT: v_add_f32_e32 v6, v3, v2
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; SI-NEXT: s_add_i32 s1, s1, -11
-; SI-NEXT: v_ldexp_f32_e64 v3, v3, 11
-; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_6
-; SI-NEXT: ; %bb.7: ; %Flow133
-; SI-NEXT: v_mov_b32_e32 v3, v5
-; SI-NEXT: .LBB10_8: ; %frem.loop_exit94
-; SI-NEXT: s_add_i32 s1, s1, -10
-; SI-NEXT: v_ldexp_f32_e64 v3, v3, s1
-; SI-NEXT: v_mul_f32_e32 v4, v3, v4
+; SI-NEXT: v_mov_b32_e32 v6, v4
+; SI-NEXT: v_mul_f32_e32 v4, v6, v5
; SI-NEXT: v_rndne_f32_e32 v4, v4
-; SI-NEXT: v_fma_f32 v3, -v4, v2, v3
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; SI-NEXT: v_add_f32_e32 v2, v3, v2
-; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; SI-NEXT: v_ldexp_f32_e64 v2, v2, s0
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NEXT: s_and_b32 s0, s3, 0xffff8000
-; SI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; SI-NEXT: v_or_b32_e32 v3, s0, v2
-; SI-NEXT: .LBB10_9: ; %Flow136
-; SI-NEXT: s_lshr_b32 s4, s2, 16
-; SI-NEXT: s_lshr_b32 s5, s3, 16
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; SI-NEXT: ; %bb.10:
-; SI-NEXT: v_cvt_f32_f16_e64 v6, |s5|
-; SI-NEXT: v_cvt_f32_f16_e64 v5, |v4|
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
-; SI-NEXT: s_cbranch_vccz .LBB10_13
-; SI-NEXT: ; %bb.11: ; %frem.else53
-; SI-NEXT: s_and_b32 s6, s5, 0x8000
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: s_cselect_b32 s6, s6, s5
-; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc1 .LBB10_14
-; SI-NEXT: .LBB10_12:
-; SI-NEXT: v_mov_b32_e32 v5, s6
-; SI-NEXT: s_branch .LBB10_19
-; SI-NEXT: .LBB10_13:
-; SI-NEXT: s_mov_b64 s[0:1], -1
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc0 .LBB10_12
-; SI-NEXT: .LBB10_14: ; %frem.compute52
-; SI-NEXT: s_mov_b32 s7, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v7
-; SI-NEXT: v_frexp_mant_f32_e32 v7, v6
-; SI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s7
-; SI-NEXT: v_frexp_mant_f32_e32 v7, v5
-; SI-NEXT: s_cselect_b32 s6, s0, 0
-; SI-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc
-; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v5
-; SI-NEXT: v_ldexp_f32_e64 v5, v7, 1
-; SI-NEXT: v_div_scale_f32 v8, s[10:11], v5, v5, 1.0
-; SI-NEXT: v_rcp_f32_e32 v9, v8
-; SI-NEXT: v_ldexp_f32_e64 v6, v6, 11
-; SI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; SI-NEXT: v_fma_f32 v4, -v4, v3, v6
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
+; SI-NEXT: v_add_f32_e32 v7, v4, v3
+; SI-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; SI-NEXT: s_add_i32 s4, s4, -11
+; SI-NEXT: v_ldexp_f32_e64 v4, v4, 11
+; SI-NEXT: s_cmp_gt_i32 s4, 11
+; SI-NEXT: s_cbranch_scc1 .LBB10_3
+; SI-NEXT: s_branch .LBB10_6
+; SI-NEXT: .LBB10_4: ; %frem.else86
+; SI-NEXT: s_and_b32 s1, s0, 0xffff8000
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: s_cselect_b32 s1, s1, s0
+; SI-NEXT: v_mov_b32_e32 v3, s1
+; SI-NEXT: s_branch .LBB10_7
+; SI-NEXT: .LBB10_5:
+; SI-NEXT: v_mov_b32_e32 v6, v4
+; SI-NEXT: .LBB10_6: ; %frem.loop_exit94
+; SI-NEXT: s_add_i32 s4, s4, -10
+; SI-NEXT: v_ldexp_f32_e64 v4, v6, s4
+; SI-NEXT: v_mul_f32_e32 v5, v4, v5
+; SI-NEXT: v_rndne_f32_e32 v5, v5
+; SI-NEXT: v_fma_f32 v4, -v5, v3, v4
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
+; SI-NEXT: v_add_f32_e32 v3, v4, v3
+; SI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; SI-NEXT: v_ldexp_f32_e64 v3, v3, s1
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: s_and_b32 s1, s0, 0xffff8000
+; SI-NEXT: v_and_b32_e32 v3, 0x7fff, v3
+; SI-NEXT: v_or_b32_e32 v3, s1, v3
+; SI-NEXT: .LBB10_7:
+; SI-NEXT: v_cvt_f32_f16_e64 v5, |s3|
+; SI-NEXT: v_cvt_f32_f16_e64 v4, |v2|
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
+; SI-NEXT: s_cbranch_vccz .LBB10_11
+; SI-NEXT: ; %bb.8: ; %frem.compute52
+; SI-NEXT: s_mov_b32 s1, 0x7f800000
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s1
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v6, v5
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s4, v6
+; SI-NEXT: v_frexp_mant_f32_e32 v6, v5
+; SI-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s1
+; SI-NEXT: v_frexp_mant_f32_e32 v6, v4
+; SI-NEXT: v_cndmask_b32_e32 v6, v4, v6, vcc
+; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
+; SI-NEXT: v_readfirstlane_b32 s1, v4
+; SI-NEXT: v_ldexp_f32_e64 v4, v6, 1
+; SI-NEXT: v_div_scale_f32 v7, s[10:11], v4, v4, 1.0
+; SI-NEXT: v_rcp_f32_e32 v8, v7
+; SI-NEXT: s_cselect_b32 s5, s4, 0
+; SI-NEXT: v_ldexp_f32_e64 v5, v5, 11
+; SI-NEXT: s_and_b64 s[6:7], vcc, exec
+; SI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT: v_fma_f32 v10, -v8, v9, 1.0
-; SI-NEXT: v_fma_f32 v9, v10, v9, v9
-; SI-NEXT: v_mul_f32_e32 v10, v7, v9
-; SI-NEXT: s_cselect_b32 s7, s0, 0
-; SI-NEXT: v_fma_f32 v11, -v8, v10, v7
-; SI-NEXT: s_add_i32 s0, s7, -1
-; SI-NEXT: v_fma_f32 v10, v11, v9, v10
-; SI-NEXT: s_not_b32 s1, s0
-; SI-NEXT: v_fma_f32 v7, -v8, v10, v7
+; SI-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; SI-NEXT: v_fma_f32 v8, v9, v8, v8
+; SI-NEXT: v_mul_f32_e32 v9, v6, v8
+; SI-NEXT: s_cselect_b32 s6, s1, 0
+; SI-NEXT: v_fma_f32 v10, -v7, v9, v6
+; SI-NEXT: s_add_i32 s1, s6, -1
+; SI-NEXT: v_fma_f32 v9, v10, v8, v9
+; SI-NEXT: s_not_b32 s4, s1
+; SI-NEXT: v_fma_f32 v6, -v7, v9, v6
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT: s_add_i32 s1, s1, s6
-; SI-NEXT: v_div_fmas_f32 v7, v7, v9, v10
-; SI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_18
-; SI-NEXT: ; %bb.15: ; %frem.loop_body60.preheader
-; SI-NEXT: s_sub_i32 s1, s6, s7
-; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB10_16: ; %frem.loop_body60
+; SI-NEXT: s_add_i32 s4, s4, s5
+; SI-NEXT: v_div_fmas_f32 v6, v6, v8, v9
+; SI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
+; SI-NEXT: s_cmp_lt_i32 s4, 12
+; SI-NEXT: s_cbranch_scc1 .LBB10_12
+; SI-NEXT: ; %bb.9: ; %frem.loop_body60.preheader
+; SI-NEXT: s_sub_i32 s4, s5, s6
+; SI-NEXT: s_add_i32 s4, s4, 11
+; SI-NEXT: .LBB10_10: ; %frem.loop_body60
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v8, v6
-; SI-NEXT: v_mul_f32_e32 v6, v8, v7
+; SI-NEXT: v_mov_b32_e32 v7, v5
+; SI-NEXT: v_mul_f32_e32 v5, v7, v6
+; SI-NEXT: v_rndne_f32_e32 v5, v5
+; SI-NEXT: v_fma_f32 v5, -v5, v4, v7
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; SI-NEXT: v_add_f32_e32 v8, v5, v4
+; SI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; SI-NEXT: s_add_i32 s4, s4, -11
+; SI-NEXT: v_ldexp_f32_e64 v5, v5, 11
+; SI-NEXT: s_cmp_gt_i32 s4, 11
+; SI-NEXT: s_cbranch_scc1 .LBB10_10
+; SI-NEXT: s_branch .LBB10_13
+; SI-NEXT: .LBB10_11: ; %frem.else53
+; SI-NEXT: s_and_b32 s1, s3, 0x8000
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: s_cselect_b32 s1, s1, s3
+; SI-NEXT: v_mov_b32_e32 v5, s1
+; SI-NEXT: s_branch .LBB10_14
+; SI-NEXT: .LBB10_12:
+; SI-NEXT: v_mov_b32_e32 v7, v5
+; SI-NEXT: .LBB10_13: ; %frem.loop_exit61
+; SI-NEXT: s_add_i32 s4, s4, -10
+; SI-NEXT: v_ldexp_f32_e64 v5, v7, s4
+; SI-NEXT: v_mul_f32_e32 v6, v5, v6
; SI-NEXT: v_rndne_f32_e32 v6, v6
-; SI-NEXT: v_fma_f32 v6, -v6, v5, v8
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; SI-NEXT: v_add_f32_e32 v9, v6, v5
-; SI-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
-; SI-NEXT: s_add_i32 s1, s1, -11
-; SI-NEXT: v_ldexp_f32_e64 v6, v6, 11
-; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_16
-; SI-NEXT: ; %bb.17: ; %Flow129
-; SI-NEXT: v_mov_b32_e32 v6, v8
-; SI-NEXT: .LBB10_18: ; %frem.loop_exit61
-; SI-NEXT: s_add_i32 s1, s1, -10
-; SI-NEXT: v_ldexp_f32_e64 v6, v6, s1
-; SI-NEXT: v_mul_f32_e32 v7, v6, v7
-; SI-NEXT: v_rndne_f32_e32 v7, v7
-; SI-NEXT: v_fma_f32 v6, -v7, v5, v6
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
-; SI-NEXT: v_add_f32_e32 v5, v6, v5
-; SI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
-; SI-NEXT: v_ldexp_f32_e64 v5, v5, s0
-; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; SI-NEXT: s_and_b32 s0, s5, 0x8000
-; SI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
-; SI-NEXT: v_or_b32_e32 v5, s0, v5
-; SI-NEXT: .LBB10_19:
+; SI-NEXT: v_fma_f32 v5, -v6, v4, v5
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
+; SI-NEXT: v_add_f32_e32 v4, v5, v4
+; SI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
+; SI-NEXT: v_ldexp_f32_e64 v4, v4, s1
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT: s_and_b32 s1, s3, 0x8000
+; SI-NEXT: v_and_b32_e32 v4, 0x7fff, v4
+; SI-NEXT: v_or_b32_e32 v5, s1, v4
+; SI-NEXT: .LBB10_14:
; SI-NEXT: v_cvt_f32_f16_e64 v7, |s2|
; SI-NEXT: v_cvt_f32_f16_e64 v6, |v1|
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
-; SI-NEXT: s_cbranch_vccz .LBB10_22
-; SI-NEXT: ; %bb.20: ; %frem.else20
-; SI-NEXT: s_and_b32 s6, s2, 0xffff8000
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: s_cselect_b32 s6, s6, s2
-; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc1 .LBB10_23
-; SI-NEXT: .LBB10_21:
-; SI-NEXT: v_mov_b32_e32 v6, s6
-; SI-NEXT: s_branch .LBB10_28
-; SI-NEXT: .LBB10_22:
-; SI-NEXT: s_mov_b64 s[0:1], -1
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc0 .LBB10_21
-; SI-NEXT: .LBB10_23: ; %frem.compute19
-; SI-NEXT: s_mov_b32 s7, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s7
+; SI-NEXT: s_lshr_b32 s4, s2, 16
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6
+; SI-NEXT: s_cbranch_vccz .LBB10_18
+; SI-NEXT: ; %bb.15: ; %frem.compute19
+; SI-NEXT: s_mov_b32 s1, 0x7f800000
; SI-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v8
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s1
+; SI-NEXT: v_readfirstlane_b32 s5, v8
; SI-NEXT: v_frexp_mant_f32_e32 v8, v7
+; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s1
; SI-NEXT: v_frexp_mant_f32_e32 v8, v6
-; SI-NEXT: s_cselect_b32 s6, s0, 0
; SI-NEXT: v_cndmask_b32_e32 v8, v6, v8, vcc
; SI-NEXT: v_frexp_exp_i32_f32_e32 v6, v6
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v6
+; SI-NEXT: v_readfirstlane_b32 s1, v6
; SI-NEXT: v_ldexp_f32_e64 v6, v8, 1
; SI-NEXT: v_div_scale_f32 v9, s[10:11], v6, v6, 1.0
; SI-NEXT: v_rcp_f32_e32 v10, v9
+; SI-NEXT: s_cselect_b32 s6, s5, 0
; SI-NEXT: v_ldexp_f32_e64 v7, v7, 11
+; SI-NEXT: s_and_b64 s[10:11], vcc, exec
; SI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; SI-NEXT: v_fma_f32 v10, v11, v10, v10
; SI-NEXT: v_mul_f32_e32 v11, v8, v10
-; SI-NEXT: s_cselect_b32 s7, s0, 0
+; SI-NEXT: s_cselect_b32 s7, s1, 0
; SI-NEXT: v_fma_f32 v12, -v9, v11, v8
-; SI-NEXT: s_add_i32 s0, s7, -1
+; SI-NEXT: s_add_i32 s1, s7, -1
; SI-NEXT: v_fma_f32 v11, v12, v10, v11
-; SI-NEXT: s_not_b32 s1, s0
+; SI-NEXT: s_not_b32 s5, s1
; SI-NEXT: v_fma_f32 v8, -v9, v11, v8
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT: s_add_i32 s1, s1, s6
+; SI-NEXT: s_add_i32 s5, s5, s6
; SI-NEXT: v_div_fmas_f32 v8, v8, v10, v11
; SI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_27
-; SI-NEXT: ; %bb.24: ; %frem.loop_body27.preheader
-; SI-NEXT: s_sub_i32 s1, s6, s7
-; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB10_25: ; %frem.loop_body27
+; SI-NEXT: s_cmp_lt_i32 s5, 12
+; SI-NEXT: s_cbranch_scc1 .LBB10_19
+; SI-NEXT: ; %bb.16: ; %frem.loop_body27.preheader
+; SI-NEXT: s_sub_i32 s5, s6, s7
+; SI-NEXT: s_add_i32 s5, s5, 11
+; SI-NEXT: .LBB10_17: ; %frem.loop_body27
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v9, v7
; SI-NEXT: v_mul_f32_e32 v7, v9, v8
@@ -7552,87 +7133,79 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
; SI-NEXT: v_add_f32_e32 v10, v7, v6
; SI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
-; SI-NEXT: s_add_i32 s1, s1, -11
+; SI-NEXT: s_add_i32 s5, s5, -11
; SI-NEXT: v_ldexp_f32_e64 v7, v7, 11
-; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_25
-; SI-NEXT: ; %bb.26: ; %Flow125
-; SI-NEXT: v_mov_b32_e32 v7, v9
-; SI-NEXT: .LBB10_27: ; %frem.loop_exit28
-; SI-NEXT: s_add_i32 s1, s1, -10
-; SI-NEXT: v_ldexp_f32_e64 v7, v7, s1
+; SI-NEXT: s_cmp_gt_i32 s5, 11
+; SI-NEXT: s_cbranch_scc1 .LBB10_17
+; SI-NEXT: s_branch .LBB10_20
+; SI-NEXT: .LBB10_18: ; %frem.else20
+; SI-NEXT: s_and_b32 s1, s2, 0xffff8000
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
+; SI-NEXT: s_and_b64 s[6:7], vcc, exec
+; SI-NEXT: s_cselect_b32 s1, s1, s2
+; SI-NEXT: v_mov_b32_e32 v6, s1
+; SI-NEXT: s_branch .LBB10_21
+; SI-NEXT: .LBB10_19:
+; SI-NEXT: v_mov_b32_e32 v9, v7
+; SI-NEXT: .LBB10_20: ; %frem.loop_exit28
+; SI-NEXT: s_add_i32 s5, s5, -10
+; SI-NEXT: v_ldexp_f32_e64 v7, v9, s5
; SI-NEXT: v_mul_f32_e32 v8, v7, v8
; SI-NEXT: v_rndne_f32_e32 v8, v8
; SI-NEXT: v_fma_f32 v7, -v8, v6, v7
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
; SI-NEXT: v_add_f32_e32 v6, v7, v6
; SI-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
-; SI-NEXT: v_ldexp_f32_e64 v6, v6, s0
+; SI-NEXT: v_ldexp_f32_e64 v6, v6, s1
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
-; SI-NEXT: s_and_b32 s0, s2, 0xffff8000
+; SI-NEXT: s_and_b32 s1, s2, 0xffff8000
; SI-NEXT: v_and_b32_e32 v6, 0x7fff, v6
-; SI-NEXT: v_or_b32_e32 v6, s0, v6
-; SI-NEXT: .LBB10_28:
+; SI-NEXT: v_or_b32_e32 v6, s1, v6
+; SI-NEXT: .LBB10_21:
; SI-NEXT: v_cvt_f32_f16_e64 v8, |s4|
-; SI-NEXT: v_cvt_f32_f16_e64 v7, |v2|
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, v8, v7
-; SI-NEXT: s_cbranch_vccz .LBB10_31
-; SI-NEXT: ; %bb.29: ; %frem.else
-; SI-NEXT: s_and_b32 s6, s4, 0x8000
-; SI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: s_cselect_b32 s6, s6, s4
-; SI-NEXT: s_mov_b64 s[0:1], 0
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc1 .LBB10_32
-; SI-NEXT: .LBB10_30:
-; SI-NEXT: v_mov_b32_e32 v7, s6
-; SI-NEXT: s_branch .LBB10_37
-; SI-NEXT: .LBB10_31:
-; SI-NEXT: s_mov_b64 s[0:1], -1
-; SI-NEXT: ; implicit-def: $sgpr6
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cbranch_scc0 .LBB10_30
-; SI-NEXT: .LBB10_32: ; %frem.compute
-; SI-NEXT: s_mov_b32 s7, 0x7f800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s7
+; SI-NEXT: v_cvt_f32_f16_e64 v7, |v4|
+; SI-NEXT: v_cmp_gt_f32_e32 vcc, v8, v7
+; SI-NEXT: s_cbranch_vccz .LBB10_25
+; SI-NEXT: ; %bb.22: ; %frem.compute
+; SI-NEXT: s_mov_b32 s1, 0x7f800000
; SI-NEXT: v_frexp_exp_i32_f32_e32 v9, v8
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v9
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s1
+; SI-NEXT: v_readfirstlane_b32 s5, v9
; SI-NEXT: v_frexp_mant_f32_e32 v9, v8
+; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s7
+; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s1
; SI-NEXT: v_frexp_mant_f32_e32 v9, v7
-; SI-NEXT: s_cselect_b32 s6, s0, 0
; SI-NEXT: v_cndmask_b32_e32 v9, v7, v9, vcc
; SI-NEXT: v_frexp_exp_i32_f32_e32 v7, v7
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s0, v7
+; SI-NEXT: v_readfirstlane_b32 s1, v7
; SI-NEXT: v_ldexp_f32_e64 v7, v9, 1
; SI-NEXT: v_div_scale_f32 v10, s[10:11], v7, v7, 1.0
; SI-NEXT: v_rcp_f32_e32 v11, v10
+; SI-NEXT: s_cselect_b32 s6, s5, 0
; SI-NEXT: v_ldexp_f32_e64 v8, v8, 11
+; SI-NEXT: s_and_b64 s[10:11], vcc, exec
; SI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v7, 1.0
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; SI-NEXT: v_fma_f32 v12, -v10, v11, 1.0
; SI-NEXT: v_fma_f32 v11, v12, v11, v11
; SI-NEXT: v_mul_f32_e32 v12, v9, v11
-; SI-NEXT: s_cselect_b32 s7, s0, 0
+; SI-NEXT: s_cselect_b32 s7, s1, 0
; SI-NEXT: v_fma_f32 v13, -v10, v12, v9
-; SI-NEXT: s_add_i32 s0, s7, -1
+; SI-NEXT: s_add_i32 s1, s7, -1
; SI-NEXT: v_fma_f32 v12, v13, v11, v12
-; SI-NEXT: s_not_b32 s1, s0
+; SI-NEXT: s_not_b32 s5, s1
; SI-NEXT: v_fma_f32 v9, -v10, v12, v9
; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT: s_add_i32 s1, s1, s6
+; SI-NEXT: s_add_i32 s5, s5, s6
; SI-NEXT: v_div_fmas_f32 v9, v9, v11, v12
; SI-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
-; SI-NEXT: s_cmp_lt_i32 s1, 12
-; SI-NEXT: s_cbranch_scc1 .LBB10_36
-; SI-NEXT: ; %bb.33: ; %frem.loop_body.preheader
-; SI-NEXT: s_sub_i32 s1, s6, s7
-; SI-NEXT: s_add_i32 s1, s1, 11
-; SI-NEXT: .LBB10_34: ; %frem.loop_body
+; SI-NEXT: s_cmp_lt_i32 s5, 12
+; SI-NEXT: s_cbranch_scc1 .LBB10_26
+; SI-NEXT: ; %bb.23: ; %frem.loop_body.preheader
+; SI-NEXT: s_sub_i32 s5, s6, s7
+; SI-NEXT: s_add_i32 s5, s5, 11
+; SI-NEXT: .LBB10_24: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v10, v8
; SI-NEXT: v_mul_f32_e32 v8, v10, v9
@@ -7641,59 +7214,67 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
; SI-NEXT: v_add_f32_e32 v11, v8, v7
; SI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
-; SI-NEXT: s_add_i32 s1, s1, -11
+; SI-NEXT: s_add_i32 s5, s5, -11
; SI-NEXT: v_ldexp_f32_e64 v8, v8, 11
-; SI-NEXT: s_cmp_gt_i32 s1, 11
-; SI-NEXT: s_cbranch_scc1 .LBB10_34
-; SI-NEXT: ; %bb.35: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v8, v10
-; SI-NEXT: .LBB10_36: ; %frem.loop_exit
-; SI-NEXT: s_add_i32 s1, s1, -10
-; SI-NEXT: v_ldexp_f32_e64 v8, v8, s1
+; SI-NEXT: s_cmp_gt_i32 s5, 11
+; SI-NEXT: s_cbranch_scc1 .LBB10_24
+; SI-NEXT: s_branch .LBB10_27
+; SI-NEXT: .LBB10_25: ; %frem.else
+; SI-NEXT: s_and_b32 s1, s4, 0x8000
+; SI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
+; SI-NEXT: s_and_b64 s[6:7], vcc, exec
+; SI-NEXT: s_cselect_b32 s1, s1, s4
+; SI-NEXT: v_mov_b32_e32 v7, s1
+; SI-NEXT: s_branch .LBB10_28
+; SI-NEXT: .LBB10_26:
+; SI-NEXT: v_mov_b32_e32 v10, v8
+; SI-NEXT: .LBB10_27: ; %frem.loop_exit
+; SI-NEXT: s_add_i32 s5, s5, -10
+; SI-NEXT: v_ldexp_f32_e64 v8, v10, s5
; SI-NEXT: v_mul_f32_e32 v9, v8, v9
; SI-NEXT: v_rndne_f32_e32 v9, v9
; SI-NEXT: v_fma_f32 v8, -v9, v7, v8
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
; SI-NEXT: v_add_f32_e32 v7, v8, v7
; SI-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
-; SI-NEXT: v_ldexp_f32_e64 v7, v7, s0
+; SI-NEXT: v_ldexp_f32_e64 v7, v7, s1
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
-; SI-NEXT: s_and_b32 s0, s4, 0x8000
+; SI-NEXT: s_and_b32 s1, s4, 0x8000
; SI-NEXT: v_and_b32_e32 v7, 0x7fff, v7
-; SI-NEXT: v_or_b32_e32 v7, s0, v7
-; SI-NEXT: .LBB10_37: ; %Flow124
+; SI-NEXT: v_or_b32_e32 v7, s1, v7
+; SI-NEXT: .LBB10_28:
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: s_mov_b32 s5, 0x7f800000
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0
-; SI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
-; SI-NEXT: s_mov_b32 s3, 0x7f800000
+; SI-NEXT: v_cvt_f32_f16_e64 v0, |s0|
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1
-; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v0
+; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v0
; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
; SI-NEXT: v_mov_b32_e32 v0, 0x7e00
; SI-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
-; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
-; SI-NEXT: v_cvt_f32_f16_e64 v4, |s5|
-; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v4
+; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
+; SI-NEXT: v_cvt_f32_f16_e64 v2, |s3|
+; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v2
; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; SI-NEXT: v_cndmask_b32_e32 v4, v0, v5, vcc
+; SI-NEXT: v_cndmask_b32_e32 v2, v0, v5, vcc
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; SI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
-; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v1
+; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v1
; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
; SI-NEXT: v_cndmask_b32_e32 v1, v0, v6, vcc
-; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
-; SI-NEXT: v_cvt_f32_f16_e64 v2, |s4|
+; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
+; SI-NEXT: v_cvt_f32_f16_e64 v4, |s4|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v2
+; SI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v4
; SI-NEXT: s_and_b64 vcc, s[0:1], vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v1, v1, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
@@ -7713,237 +7294,212 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: s_mov_b32 s7, s3
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_readfirstlane_b32 s2, v1
-; CI-NEXT: v_readfirstlane_b32 s3, v0
+; CI-NEXT: v_readfirstlane_b32 s0, v0
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 offset:32
-; CI-NEXT: v_cvt_f32_f16_e64 v3, |s3|
+; CI-NEXT: v_cvt_f32_f16_e64 v4, |s0|
+; CI-NEXT: s_lshr_b32 s3, s0, 16
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |v0|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2
-; CI-NEXT: s_cbranch_vccz .LBB10_3
-; CI-NEXT: ; %bb.1: ; %frem.else86
-; CI-NEXT: s_and_b32 s4, s3, 0xffff8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2
-; CI-NEXT: s_and_b64 s[0:1], vcc, exec
-; CI-NEXT: s_cselect_b32 s4, s4, s3
-; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc1 .LBB10_4
-; CI-NEXT: .LBB10_2:
-; CI-NEXT: v_mov_b32_e32 v3, s4
-; CI-NEXT: s_branch .LBB10_9
-; CI-NEXT: .LBB10_3:
-; CI-NEXT: s_mov_b64 s[0:1], -1
-; CI-NEXT: ; implicit-def: $sgpr4
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc0 .LBB10_2
-; CI-NEXT: .LBB10_4: ; %frem.compute85
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v3
-; CI-NEXT: v_frexp_mant_f32_e32 v3, v3
-; CI-NEXT: v_ldexp_f32_e64 v5, v3, 11
-; CI-NEXT: v_frexp_mant_f32_e32 v3, v2
-; CI-NEXT: v_ldexp_f32_e64 v3, v3, 1
-; CI-NEXT: v_div_scale_f32 v9, s[0:1], v3, v3, 1.0
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v2
-; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8
-; CI-NEXT: v_not_b32_e32 v4, v2
-; CI-NEXT: v_add_i32_e32 v4, vcc, v4, v7
-; CI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
-; CI-NEXT: v_rcp_f32_e32 v10, v9
+; CI-NEXT: v_cvt_f32_f16_e64 v3, |v0|
+; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3
+; CI-NEXT: s_cbranch_vccz .LBB10_4
+; CI-NEXT: ; %bb.1: ; %frem.compute85
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v4
+; CI-NEXT: v_frexp_mant_f32_e32 v4, v4
+; CI-NEXT: v_ldexp_f32_e64 v7, v4, 11
+; CI-NEXT: v_frexp_mant_f32_e32 v4, v3
+; CI-NEXT: v_ldexp_f32_e64 v4, v4, 1
+; CI-NEXT: v_div_scale_f32 v10, s[4:5], v4, v4, 1.0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v9, v3
+; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v9
+; CI-NEXT: v_not_b32_e32 v5, v3
+; CI-NEXT: v_add_i32_e32 v5, vcc, v5, v8
+; CI-NEXT: v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
+; CI-NEXT: v_rcp_f32_e32 v11, v10
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v11, -v9, v10, 1.0
-; CI-NEXT: v_fma_f32 v10, v11, v10, v10
-; CI-NEXT: v_mul_f32_e32 v11, v6, v10
-; CI-NEXT: v_fma_f32 v12, -v9, v11, v6
-; CI-NEXT: v_fma_f32 v11, v12, v10, v11
-; CI-NEXT: v_fma_f32 v6, -v9, v11, v6
+; CI-NEXT: v_fma_f32 v12, -v10, v11, 1.0
+; CI-NEXT: v_fma_f32 v11, v12, v11, v11
+; CI-NEXT: v_mul_f32_e32 v12, v6, v11
+; CI-NEXT: v_fma_f32 v13, -v10, v12, v6
+; CI-NEXT: v_fma_f32 v12, v13, v11, v12
+; CI-NEXT: v_fma_f32 v6, -v10, v12, v6
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v6, v6, v10, v11
-; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v4
-; CI-NEXT: v_div_fixup_f32 v6, v6, v3, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_8
-; CI-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
-; CI-NEXT: v_sub_i32_e32 v4, vcc, v7, v8
-; CI-NEXT: v_add_i32_e32 v4, vcc, 11, v4
-; CI-NEXT: .LBB10_6: ; %frem.loop_body93
+; CI-NEXT: v_div_fmas_f32 v6, v6, v11, v12
+; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v5
+; CI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB10_5
+; CI-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; CI-NEXT: v_sub_i32_e32 v5, vcc, v8, v9
+; CI-NEXT: v_add_i32_e32 v5, vcc, 11, v5
+; CI-NEXT: .LBB10_3: ; %frem.loop_body93
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v5
-; CI-NEXT: v_mul_f32_e32 v5, v7, v6
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v5, -v5, v3, v7
+; CI-NEXT: v_mov_b32_e32 v8, v7
+; CI-NEXT: v_mul_f32_e32 v7, v8, v6
+; CI-NEXT: v_rndne_f32_e32 v7, v7
+; CI-NEXT: v_fma_f32 v7, -v7, v4, v8
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
+; CI-NEXT: v_add_f32_e32 v9, v7, v4
+; CI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; CI-NEXT: v_add_i32_e32 v5, vcc, -11, v5
+; CI-NEXT: v_ldexp_f32_e64 v7, v7, 11
+; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v5
+; CI-NEXT: s_cbranch_vccnz .LBB10_3
+; CI-NEXT: s_branch .LBB10_6
+; CI-NEXT: .LBB10_4: ; %frem.else86
+; CI-NEXT: s_and_b32 s1, s0, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3
+; CI-NEXT: s_and_b64 s[4:5], vcc, exec
+; CI-NEXT: s_cselect_b32 s1, s1, s0
+; CI-NEXT: v_mov_b32_e32 v3, s1
+; CI-NEXT: s_branch .LBB10_7
+; CI-NEXT: .LBB10_5:
+; CI-NEXT: v_mov_b32_e32 v8, v7
+; CI-NEXT: .LBB10_6: ; %frem.loop_exit94
+; CI-NEXT: v_add_i32_e32 v5, vcc, -10, v5
+; CI-NEXT: v_ldexp_f32_e32 v5, v8, v5
+; CI-NEXT: v_mul_f32_e32 v6, v5, v6
+; CI-NEXT: v_rndne_f32_e32 v6, v6
+; CI-NEXT: v_fma_f32 v5, -v6, v4, v5
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; CI-NEXT: v_add_f32_e32 v8, v5, v3
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
-; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4
-; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11
-; CI-NEXT: s_cbranch_vccnz .LBB10_6
-; CI-NEXT: ; %bb.7: ; %Flow133
-; CI-NEXT: v_mov_b32_e32 v5, v7
-; CI-NEXT: .LBB10_8: ; %frem.loop_exit94
-; CI-NEXT: v_add_i32_e32 v4, vcc, -10, v4
-; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
-; CI-NEXT: v_mul_f32_e32 v5, v4, v6
-; CI-NEXT: v_rndne_f32_e32 v5, v5
-; CI-NEXT: v_fma_f32 v4, -v5, v3, v4
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4
-; CI-NEXT: v_add_f32_e32 v3, v4, v3
-; CI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: s_and_b32 s0, s3, 0xffff8000
-; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
-; CI-NEXT: v_or_b32_e32 v3, s0, v2
-; CI-NEXT: .LBB10_9: ; %Flow136
-; CI-NEXT: s_lshr_b32 s4, s2, 16
-; CI-NEXT: s_lshr_b32 s5, s3, 16
-; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; CI-NEXT: ; %bb.10:
-; CI-NEXT: v_cvt_f32_f16_e64 v6, |s5|
-; CI-NEXT: v_cvt_f32_f16_e64 v5, |v4|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
-; CI-NEXT: s_cbranch_vccz .LBB10_13
-; CI-NEXT: ; %bb.11: ; %frem.else53
-; CI-NEXT: s_and_b32 s6, s5, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
-; CI-NEXT: s_and_b64 s[0:1], vcc, exec
-; CI-NEXT: s_cselect_b32 s6, s6, s5
-; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc1 .LBB10_14
-; CI-NEXT: .LBB10_12:
-; CI-NEXT: v_mov_b32_e32 v5, s6
-; CI-NEXT: s_branch .LBB10_19
-; CI-NEXT: .LBB10_13:
-; CI-NEXT: s_mov_b64 s[0:1], -1
-; CI-NEXT: ; implicit-def: $sgpr6
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc0 .LBB10_12
-; CI-NEXT: .LBB10_14: ; %frem.compute52
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v6
-; CI-NEXT: v_frexp_mant_f32_e32 v6, v6
-; CI-NEXT: v_ldexp_f32_e64 v8, v6, 11
-; CI-NEXT: v_frexp_mant_f32_e32 v6, v5
-; CI-NEXT: v_ldexp_f32_e64 v6, v6, 1
-; CI-NEXT: v_div_scale_f32 v12, s[0:1], v6, v6, 1.0
-; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v5
-; CI-NEXT: v_add_i32_e32 v5, vcc, -1, v11
-; CI-NEXT: v_not_b32_e32 v7, v5
-; CI-NEXT: v_add_i32_e32 v7, vcc, v7, v10
-; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
-; CI-NEXT: v_rcp_f32_e32 v13, v12
+; CI-NEXT: v_add_f32_e32 v4, v5, v4
+; CI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
+; CI-NEXT: v_ldexp_f32_e32 v3, v4, v3
+; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT: s_and_b32 s1, s0, 0xffff8000
+; CI-NEXT: v_and_b32_e32 v3, 0x7fff, v3
+; CI-NEXT: v_or_b32_e32 v3, s1, v3
+; CI-NEXT: .LBB10_7:
+; CI-NEXT: v_cvt_f32_f16_e64 v5, |s3|
+; CI-NEXT: v_cvt_f32_f16_e64 v4, |v2|
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
+; CI-NEXT: s_cbranch_vccz .LBB10_11
+; CI-NEXT: ; %bb.8: ; %frem.compute52
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v9, v5
+; CI-NEXT: v_frexp_mant_f32_e32 v5, v5
+; CI-NEXT: v_ldexp_f32_e64 v8, v5, 11
+; CI-NEXT: v_frexp_mant_f32_e32 v5, v4
+; CI-NEXT: v_ldexp_f32_e64 v5, v5, 1
+; CI-NEXT: v_div_scale_f32 v11, s[4:5], v5, v5, 1.0
+; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v4
+; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v10
+; CI-NEXT: v_not_b32_e32 v6, v4
+; CI-NEXT: v_add_i32_e32 v6, vcc, v6, v9
+; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; CI-NEXT: v_rcp_f32_e32 v12, v11
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT: v_fma_f32 v14, -v12, v13, 1.0
-; CI-NEXT: v_fma_f32 v13, v14, v13, v13
-; CI-NEXT: v_mul_f32_e32 v14, v9, v13
-; CI-NEXT: v_fma_f32 v15, -v12, v14, v9
-; CI-NEXT: v_fma_f32 v14, v15, v13, v14
-; CI-NEXT: v_fma_f32 v9, -v12, v14, v9
+; CI-NEXT: v_fma_f32 v13, -v11, v12, 1.0
+; CI-NEXT: v_fma_f32 v12, v13, v12, v12
+; CI-NEXT: v_mul_f32_e32 v13, v7, v12
+; CI-NEXT: v_fma_f32 v14, -v11, v13, v7
+; CI-NEXT: v_fma_f32 v13, v14, v12, v13
+; CI-NEXT: v_fma_f32 v7, -v11, v13, v7
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
-; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v7
-; CI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_18
-; CI-NEXT: ; %bb.15: ; %frem.loop_body60.preheader
-; CI-NEXT: v_sub_i32_e32 v7, vcc, v10, v11
-; CI-NEXT: v_add_i32_e32 v7, vcc, 11, v7
-; CI-NEXT: .LBB10_16: ; %frem.loop_body60
+; CI-NEXT: v_div_fmas_f32 v7, v7, v12, v13
+; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
+; CI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB10_12
+; CI-NEXT: ; %bb.9: ; %frem.loop_body60.preheader
+; CI-NEXT: v_sub_i32_e32 v6, vcc, v9, v10
+; CI-NEXT: v_add_i32_e32 v6, vcc, 11, v6
+; CI-NEXT: .LBB10_10: ; %frem.loop_body60
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v10, v8
-; CI-NEXT: v_mul_f32_e32 v8, v10, v9
+; CI-NEXT: v_mov_b32_e32 v9, v8
+; CI-NEXT: v_mul_f32_e32 v8, v9, v7
; CI-NEXT: v_rndne_f32_e32 v8, v8
-; CI-NEXT: v_fma_f32 v8, -v8, v6, v10
+; CI-NEXT: v_fma_f32 v8, -v8, v5, v9
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; CI-NEXT: v_add_f32_e32 v11, v8, v6
-; CI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
-; CI-NEXT: v_add_i32_e32 v7, vcc, -11, v7
-; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v7
+; CI-NEXT: v_add_f32_e32 v10, v8, v5
+; CI-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; CI-NEXT: v_add_i32_e32 v6, vcc, -11, v6
; CI-NEXT: v_ldexp_f32_e64 v8, v8, 11
-; CI-NEXT: s_cbranch_vccnz .LBB10_16
-; CI-NEXT: ; %bb.17: ; %Flow129
-; CI-NEXT: v_mov_b32_e32 v8, v10
-; CI-NEXT: .LBB10_18: ; %frem.loop_exit61
-; CI-NEXT: v_add_i32_e32 v7, vcc, -10, v7
-; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
-; CI-NEXT: v_mul_f32_e32 v8, v7, v9
-; CI-NEXT: v_rndne_f32_e32 v8, v8
-; CI-NEXT: v_fma_f32 v7, -v8, v6, v7
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; CI-NEXT: v_add_f32_e32 v6, v7, v6
-; CI-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
-; CI-NEXT: v_ldexp_f32_e32 v5, v6, v5
-; CI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; CI-NEXT: s_and_b32 s0, s5, 0x8000
-; CI-NEXT: v_and_b32_e32 v5, 0x7fff, v5
-; CI-NEXT: v_or_b32_e32 v5, s0, v5
-; CI-NEXT: .LBB10_19:
+; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
+; CI-NEXT: s_cbranch_vccnz .LBB10_10
+; CI-NEXT: s_branch .LBB10_13
+; CI-NEXT: .LBB10_11: ; %frem.else53
+; CI-NEXT: s_and_b32 s1, s3, 0x8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
+; CI-NEXT: s_and_b64 s[4:5], vcc, exec
+; CI-NEXT: s_cselect_b32 s1, s1, s3
+; CI-NEXT: v_mov_b32_e32 v5, s1
+; CI-NEXT: s_branch .LBB10_14
+; CI-NEXT: .LBB10_12:
+; CI-NEXT: v_mov_b32_e32 v9, v8
+; CI-NEXT: .LBB10_13: ; %frem.loop_exit61
+; CI-NEXT: v_add_i32_e32 v6, vcc, -10, v6
+; CI-NEXT: v_ldexp_f32_e32 v6, v9, v6
+; CI-NEXT: v_mul_f32_e32 v7, v6, v7
+; CI-NEXT: v_rndne_f32_e32 v7, v7
+; CI-NEXT: v_fma_f32 v6, -v7, v5, v6
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
+; CI-NEXT: v_add_f32_e32 v5, v6, v5
+; CI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
+; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
+; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
+; CI-NEXT: s_and_b32 s1, s3, 0x8000
+; CI-NEXT: v_and_b32_e32 v4, 0x7fff, v4
+; CI-NEXT: v_or_b32_e32 v5, s1, v4
+; CI-NEXT: .LBB10_14:
; CI-NEXT: v_cvt_f32_f16_e64 v7, |s2|
; CI-NEXT: v_cvt_f32_f16_e64 v6, |v1|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v7, v6
-; CI-NEXT: s_cbranch_vccz .LBB10_22
-; CI-NEXT: ; %bb.20: ; %frem.else20
-; CI-NEXT: s_and_b32 s6, s2, 0xffff8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
-; CI-NEXT: s_and_b64 s[0:1], vcc, exec
-; CI-NEXT: s_cselect_b32 s6, s6, s2
-; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc1 .LBB10_23
-; CI-NEXT: .LBB10_21:
-; CI-NEXT: v_mov_b32_e32 v6, s6
-; CI-NEXT: s_branch .LBB10_28
-; CI-NEXT: .LBB10_22:
-; CI-NEXT: s_mov_b64 s[0:1], -1
-; CI-NEXT: ; implicit-def: $sgpr6
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc0 .LBB10_21
-; CI-NEXT: .LBB10_23: ; %frem.compute19
+; CI-NEXT: s_lshr_b32 s4, s2, 16
+; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6
+; CI-NEXT: s_cbranch_vccz .LBB10_18
+; CI-NEXT: ; %bb.15: ; %frem.compute19
; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v7
; CI-NEXT: v_frexp_mant_f32_e32 v7, v7
-; CI-NEXT: v_ldexp_f32_e64 v9, v7, 11
+; CI-NEXT: v_ldexp_f32_e64 v10, v7, 11
; CI-NEXT: v_frexp_mant_f32_e32 v7, v6
; CI-NEXT: v_ldexp_f32_e64 v7, v7, 1
-; CI-NEXT: v_div_scale_f32 v13, s[0:1], v7, v7, 1.0
+; CI-NEXT: v_div_scale_f32 v13, s[6:7], v7, v7, 1.0
; CI-NEXT: v_frexp_exp_i32_f32_e32 v12, v6
; CI-NEXT: v_add_i32_e32 v6, vcc, -1, v12
; CI-NEXT: v_not_b32_e32 v8, v6
; CI-NEXT: v_add_i32_e32 v8, vcc, v8, v11
-; CI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v7, 1.0
+; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v7, 1.0
; CI-NEXT: v_rcp_f32_e32 v14, v13
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v15, -v13, v14, 1.0
; CI-NEXT: v_fma_f32 v14, v15, v14, v14
-; CI-NEXT: v_mul_f32_e32 v15, v10, v14
-; CI-NEXT: v_fma_f32 v16, -v13, v15, v10
+; CI-NEXT: v_mul_f32_e32 v15, v9, v14
+; CI-NEXT: v_fma_f32 v16, -v13, v15, v9
; CI-NEXT: v_fma_f32 v15, v16, v14, v15
-; CI-NEXT: v_fma_f32 v10, -v13, v15, v10
+; CI-NEXT: v_fma_f32 v9, -v13, v15, v9
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v10, v10, v14, v15
+; CI-NEXT: v_div_fmas_f32 v9, v9, v14, v15
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v8
-; CI-NEXT: v_div_fixup_f32 v10, v10, v7, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_27
-; CI-NEXT: ; %bb.24: ; %frem.loop_body27.preheader
+; CI-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB10_19
+; CI-NEXT: ; %bb.16: ; %frem.loop_body27.preheader
; CI-NEXT: v_sub_i32_e32 v8, vcc, v11, v12
; CI-NEXT: v_add_i32_e32 v8, vcc, 11, v8
-; CI-NEXT: .LBB10_25: ; %frem.loop_body27
+; CI-NEXT: .LBB10_17: ; %frem.loop_body27
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v11, v9
-; CI-NEXT: v_mul_f32_e32 v9, v11, v10
-; CI-NEXT: v_rndne_f32_e32 v9, v9
-; CI-NEXT: v_fma_f32 v9, -v9, v7, v11
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
-; CI-NEXT: v_add_f32_e32 v12, v9, v7
-; CI-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
+; CI-NEXT: v_mov_b32_e32 v11, v10
+; CI-NEXT: v_mul_f32_e32 v10, v11, v9
+; CI-NEXT: v_rndne_f32_e32 v10, v10
+; CI-NEXT: v_fma_f32 v10, -v10, v7, v11
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
+; CI-NEXT: v_add_f32_e32 v12, v10, v7
+; CI-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
; CI-NEXT: v_add_i32_e32 v8, vcc, -11, v8
+; CI-NEXT: v_ldexp_f32_e64 v10, v10, 11
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v8
-; CI-NEXT: v_ldexp_f32_e64 v9, v9, 11
-; CI-NEXT: s_cbranch_vccnz .LBB10_25
-; CI-NEXT: ; %bb.26: ; %Flow125
-; CI-NEXT: v_mov_b32_e32 v9, v11
-; CI-NEXT: .LBB10_27: ; %frem.loop_exit28
+; CI-NEXT: s_cbranch_vccnz .LBB10_17
+; CI-NEXT: s_branch .LBB10_20
+; CI-NEXT: .LBB10_18: ; %frem.else20
+; CI-NEXT: s_and_b32 s1, s2, 0xffff8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
+; CI-NEXT: s_and_b64 s[6:7], vcc, exec
+; CI-NEXT: s_cselect_b32 s1, s1, s2
+; CI-NEXT: v_mov_b32_e32 v6, s1
+; CI-NEXT: s_branch .LBB10_21
+; CI-NEXT: .LBB10_19:
+; CI-NEXT: v_mov_b32_e32 v11, v10
+; CI-NEXT: .LBB10_20: ; %frem.loop_exit28
; CI-NEXT: v_add_i32_e32 v8, vcc, -10, v8
-; CI-NEXT: v_ldexp_f32_e32 v8, v9, v8
-; CI-NEXT: v_mul_f32_e32 v9, v8, v10
+; CI-NEXT: v_ldexp_f32_e32 v8, v11, v8
+; CI-NEXT: v_mul_f32_e32 v9, v8, v9
; CI-NEXT: v_rndne_f32_e32 v9, v9
; CI-NEXT: v_fma_f32 v8, -v9, v7, v8
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
@@ -7951,77 +7507,69 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
; CI-NEXT: v_ldexp_f32_e32 v6, v7, v6
; CI-NEXT: v_cvt_f16_f32_e32 v6, v6
-; CI-NEXT: s_and_b32 s0, s2, 0xffff8000
+; CI-NEXT: s_and_b32 s1, s2, 0xffff8000
; CI-NEXT: v_and_b32_e32 v6, 0x7fff, v6
-; CI-NEXT: v_or_b32_e32 v6, s0, v6
-; CI-NEXT: .LBB10_28:
+; CI-NEXT: v_or_b32_e32 v6, s1, v6
+; CI-NEXT: .LBB10_21:
; CI-NEXT: v_cvt_f32_f16_e64 v8, |s4|
-; CI-NEXT: v_cvt_f32_f16_e64 v7, |v2|
-; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v8, v7
-; CI-NEXT: s_cbranch_vccz .LBB10_31
-; CI-NEXT: ; %bb.29: ; %frem.else
-; CI-NEXT: s_and_b32 s6, s4, 0x8000
-; CI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
-; CI-NEXT: s_and_b64 s[0:1], vcc, exec
-; CI-NEXT: s_cselect_b32 s6, s6, s4
-; CI-NEXT: s_mov_b64 s[0:1], 0
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc1 .LBB10_32
-; CI-NEXT: .LBB10_30:
-; CI-NEXT: v_mov_b32_e32 v7, s6
-; CI-NEXT: s_branch .LBB10_37
-; CI-NEXT: .LBB10_31:
-; CI-NEXT: s_mov_b64 s[0:1], -1
-; CI-NEXT: ; implicit-def: $sgpr6
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cbranch_scc0 .LBB10_30
-; CI-NEXT: .LBB10_32: ; %frem.compute
+; CI-NEXT: v_cvt_f32_f16_e64 v7, |v4|
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, v8, v7
+; CI-NEXT: s_cbranch_vccz .LBB10_25
+; CI-NEXT: ; %bb.22: ; %frem.compute
; CI-NEXT: v_frexp_exp_i32_f32_e32 v12, v8
; CI-NEXT: v_frexp_mant_f32_e32 v8, v8
-; CI-NEXT: v_ldexp_f32_e64 v10, v8, 11
+; CI-NEXT: v_ldexp_f32_e64 v11, v8, 11
; CI-NEXT: v_frexp_mant_f32_e32 v8, v7
; CI-NEXT: v_ldexp_f32_e64 v8, v8, 1
-; CI-NEXT: v_div_scale_f32 v14, s[0:1], v8, v8, 1.0
+; CI-NEXT: v_div_scale_f32 v14, s[6:7], v8, v8, 1.0
; CI-NEXT: v_frexp_exp_i32_f32_e32 v13, v7
; CI-NEXT: v_add_i32_e32 v7, vcc, -1, v13
; CI-NEXT: v_not_b32_e32 v9, v7
; CI-NEXT: v_add_i32_e32 v9, vcc, v9, v12
-; CI-NEXT: v_div_scale_f32 v11, vcc, 1.0, v8, 1.0
+; CI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v8, 1.0
; CI-NEXT: v_rcp_f32_e32 v15, v14
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v16, -v14, v15, 1.0
; CI-NEXT: v_fma_f32 v15, v16, v15, v15
-; CI-NEXT: v_mul_f32_e32 v16, v11, v15
-; CI-NEXT: v_fma_f32 v17, -v14, v16, v11
+; CI-NEXT: v_mul_f32_e32 v16, v10, v15
+; CI-NEXT: v_fma_f32 v17, -v14, v16, v10
; CI-NEXT: v_fma_f32 v16, v17, v15, v16
-; CI-NEXT: v_fma_f32 v11, -v14, v16, v11
+; CI-NEXT: v_fma_f32 v10, -v14, v16, v10
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v11, v11, v15, v16
+; CI-NEXT: v_div_fmas_f32 v10, v10, v15, v16
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v9
-; CI-NEXT: v_div_fixup_f32 v11, v11, v8, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB10_36
-; CI-NEXT: ; %bb.33: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB10_26
+; CI-NEXT: ; %bb.23: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v9, vcc, v12, v13
; CI-NEXT: v_add_i32_e32 v9, vcc, 11, v9
-; CI-NEXT: .LBB10_34: ; %frem.loop_body
+; CI-NEXT: .LBB10_24: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v12, v10
-; CI-NEXT: v_mul_f32_e32 v10, v12, v11
-; CI-NEXT: v_rndne_f32_e32 v10, v10
-; CI-NEXT: v_fma_f32 v10, -v10, v8, v12
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
-; CI-NEXT: v_add_f32_e32 v13, v10, v8
-; CI-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
+; CI-NEXT: v_mov_b32_e32 v12, v11
+; CI-NEXT: v_mul_f32_e32 v11, v12, v10
+; CI-NEXT: v_rndne_f32_e32 v11, v11
+; CI-NEXT: v_fma_f32 v11, -v11, v8, v12
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
+; CI-NEXT: v_add_f32_e32 v13, v11, v8
+; CI-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
; CI-NEXT: v_add_i32_e32 v9, vcc, -11, v9
+; CI-NEXT: v_ldexp_f32_e64 v11, v11, 11
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v9
-; CI-NEXT: v_ldexp_f32_e64 v10, v10, 11
-; CI-NEXT: s_cbranch_vccnz .LBB10_34
-; CI-NEXT: ; %bb.35: ; %Flow
-; CI-NEXT: v_mov_b32_e32 v10, v12
-; CI-NEXT: .LBB10_36: ; %frem.loop_exit
+; CI-NEXT: s_cbranch_vccnz .LBB10_24
+; CI-NEXT: s_branch .LBB10_27
+; CI-NEXT: .LBB10_25: ; %frem.else
+; CI-NEXT: s_and_b32 s1, s4, 0x8000
+; CI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
+; CI-NEXT: s_and_b64 s[6:7], vcc, exec
+; CI-NEXT: s_cselect_b32 s1, s1, s4
+; CI-NEXT: v_mov_b32_e32 v7, s1
+; CI-NEXT: s_branch .LBB10_28
+; CI-NEXT: .LBB10_26:
+; CI-NEXT: v_mov_b32_e32 v12, v11
+; CI-NEXT: .LBB10_27: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v9, vcc, -10, v9
-; CI-NEXT: v_ldexp_f32_e32 v9, v10, v9
-; CI-NEXT: v_mul_f32_e32 v10, v9, v11
+; CI-NEXT: v_ldexp_f32_e32 v9, v12, v9
+; CI-NEXT: v_mul_f32_e32 v10, v9, v10
; CI-NEXT: v_rndne_f32_e32 v10, v10
; CI-NEXT: v_fma_f32 v9, -v10, v8, v9
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
@@ -8029,42 +7577,42 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
; CI-NEXT: v_cvt_f16_f32_e32 v7, v7
-; CI-NEXT: s_and_b32 s0, s4, 0x8000
+; CI-NEXT: s_and_b32 s1, s4, 0x8000
; CI-NEXT: v_and_b32_e32 v7, 0x7fff, v7
-; CI-NEXT: v_or_b32_e32 v7, s0, v7
-; CI-NEXT: .LBB10_37: ; %Flow124
+; CI-NEXT: v_or_b32_e32 v7, s1, v7
+; CI-NEXT: .LBB10_28:
; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; CI-NEXT: s_mov_b32 s5, 0x7f800000
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v0, |s3|
-; CI-NEXT: s_mov_b32 s3, 0x7f800000
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |s0|
+; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
; CI-NEXT: s_mov_b32 s11, 0xf000
; CI-NEXT: s_mov_b32 s10, -1
-; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v0
+; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v0
; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
; CI-NEXT: v_mov_b32_e32 v0, 0x7e00
; CI-NEXT: v_cndmask_b32_e32 v3, v0, v3, vcc
-; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
-; CI-NEXT: v_cvt_f32_f16_e64 v4, |s5|
-; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v4
+; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
+; CI-NEXT: v_cvt_f32_f16_e64 v2, |s3|
+; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v2
; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
-; CI-NEXT: v_cndmask_b32_e32 v4, v0, v5, vcc
+; CI-NEXT: v_cndmask_b32_e32 v2, v0, v5, vcc
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
; CI-NEXT: v_cvt_f32_f16_e64 v1, |s2|
-; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v1
+; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v1
; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
; CI-NEXT: v_cndmask_b32_e32 v1, v0, v6, vcc
-; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |s4|
+; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
+; CI-NEXT: v_cvt_f32_f16_e64 v4, |s4|
; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s3, v2
+; CI-NEXT: v_cmp_nle_f32_e64 s[0:1], s5, v4
; CI-NEXT: s_and_b64 vcc, s[0:1], vcc
; CI-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; CI-NEXT: v_or_b32_e32 v1, v1, v0
-; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
+; CI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; CI-NEXT: v_and_b32_e32 v2, 0xffff, v3
; CI-NEXT: v_or_b32_e32 v0, v2, v0
; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
@@ -8084,71 +7632,64 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_cvt_f32_f16_e64 v6, |v0|
+; VI-NEXT: v_cvt_f32_f16_e64 v5, |v0|
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e64 v5, |v2|
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
-; VI-NEXT: s_cbranch_vccz .LBB10_2
-; VI-NEXT: ; %bb.1: ; %frem.else86
-; VI-NEXT: v_and_b32_e32 v4, 0x8000, v0
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
-; VI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB10_3
-; VI-NEXT: s_branch .LBB10_8
-; VI-NEXT: .LBB10_2:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr4
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB10_8
-; VI-NEXT: .LBB10_3: ; %frem.compute85
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v9, v6
-; VI-NEXT: v_frexp_mant_f32_e32 v4, v6
-; VI-NEXT: v_frexp_mant_f32_e32 v6, v5
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v5
-; VI-NEXT: v_ldexp_f32 v5, v6, 1
+; VI-NEXT: v_cvt_f32_f16_e64 v4, |v2|
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
+; VI-NEXT: s_cbranch_vccz .LBB10_4
+; VI-NEXT: ; %bb.1: ; %frem.compute85
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v9, v5
+; VI-NEXT: v_frexp_mant_f32_e32 v5, v5
+; VI-NEXT: v_ldexp_f32 v8, v5, 11
+; VI-NEXT: v_frexp_mant_f32_e32 v5, v4
+; VI-NEXT: v_ldexp_f32 v5, v5, 1
; VI-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
-; VI-NEXT: v_ldexp_f32 v7, v4, 11
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, -1, v10
; VI-NEXT: v_not_b32_e32 v6, v4
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v9
-; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
; VI-NEXT: v_rcp_f32_e32 v12, v11
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; VI-NEXT: v_fma_f32 v12, v13, v12, v12
-; VI-NEXT: v_mul_f32_e32 v13, v8, v12
-; VI-NEXT: v_fma_f32 v14, -v11, v13, v8
+; VI-NEXT: v_mul_f32_e32 v13, v7, v12
+; VI-NEXT: v_fma_f32 v14, -v11, v13, v7
; VI-NEXT: v_fma_f32 v13, v14, v12, v13
-; VI-NEXT: v_fma_f32 v8, -v11, v13, v8
+; VI-NEXT: v_fma_f32 v7, -v11, v13, v7
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v8, v8, v12, v13
+; VI-NEXT: v_div_fmas_f32 v7, v7, v12, v13
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
-; VI-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_7
-; VI-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
+; VI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB10_5
+; VI-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
; VI-NEXT: v_sub_u32_e32 v6, vcc, v9, v10
; VI-NEXT: v_add_u32_e32 v6, vcc, 11, v6
-; VI-NEXT: .LBB10_5: ; %frem.loop_body93
+; VI-NEXT: .LBB10_3: ; %frem.loop_body93
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v9, v7
-; VI-NEXT: v_mul_f32_e32 v7, v9, v8
-; VI-NEXT: v_rndne_f32_e32 v7, v7
-; VI-NEXT: v_fma_f32 v7, -v7, v5, v9
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; VI-NEXT: v_add_f32_e32 v10, v7, v5
-; VI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; VI-NEXT: v_mov_b32_e32 v9, v8
+; VI-NEXT: v_mul_f32_e32 v8, v9, v7
+; VI-NEXT: v_rndne_f32_e32 v8, v8
+; VI-NEXT: v_fma_f32 v8, -v8, v5, v9
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; VI-NEXT: v_add_f32_e32 v10, v8, v5
+; VI-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, -11, v6
+; VI-NEXT: v_ldexp_f32 v8, v8, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
-; VI-NEXT: v_ldexp_f32 v7, v7, 11
-; VI-NEXT: s_cbranch_vccnz .LBB10_5
-; VI-NEXT: ; %bb.6: ; %Flow133
-; VI-NEXT: v_mov_b32_e32 v7, v9
-; VI-NEXT: .LBB10_7: ; %frem.loop_exit94
+; VI-NEXT: s_cbranch_vccnz .LBB10_3
+; VI-NEXT: s_branch .LBB10_6
+; VI-NEXT: .LBB10_4: ; %frem.else86
+; VI-NEXT: v_and_b32_e32 v6, 0x8000, v0
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
+; VI-NEXT: v_cndmask_b32_e32 v4, v0, v6, vcc
+; VI-NEXT: s_branch .LBB10_7
+; VI-NEXT: .LBB10_5:
+; VI-NEXT: v_mov_b32_e32 v9, v8
+; VI-NEXT: .LBB10_6: ; %frem.loop_exit94
; VI-NEXT: v_add_u32_e32 v6, vcc, -10, v6
-; VI-NEXT: v_ldexp_f32 v6, v7, v6
-; VI-NEXT: v_mul_f32_e32 v7, v6, v8
+; VI-NEXT: v_ldexp_f32 v6, v9, v6
+; VI-NEXT: v_mul_f32_e32 v7, v6, v7
; VI-NEXT: v_rndne_f32_e32 v7, v7
; VI-NEXT: v_fma_f32 v6, -v7, v5, v6
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -8158,73 +7699,66 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cvt_f16_f32_e32 v4, v4
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; VI-NEXT: .LBB10_8:
+; VI-NEXT: .LBB10_7:
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; VI-NEXT: v_cvt_f32_f16_e64 v9, |v5|
-; VI-NEXT: v_cvt_f32_f16_e64 v8, |v6|
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v9, v8
-; VI-NEXT: s_cbranch_vccz .LBB10_10
-; VI-NEXT: ; %bb.9: ; %frem.else53
-; VI-NEXT: v_and_b32_e32 v7, 0x8000, v5
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v9, v8
-; VI-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB10_11
-; VI-NEXT: s_branch .LBB10_16
-; VI-NEXT: .LBB10_10:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr7
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB10_16
-; VI-NEXT: .LBB10_11: ; %frem.compute52
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v12, v9
-; VI-NEXT: v_frexp_mant_f32_e32 v7, v9
-; VI-NEXT: v_frexp_mant_f32_e32 v9, v8
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v8
-; VI-NEXT: v_ldexp_f32 v8, v9, 1
+; VI-NEXT: v_cvt_f32_f16_e64 v8, |v5|
+; VI-NEXT: v_cvt_f32_f16_e64 v7, |v6|
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, v8, v7
+; VI-NEXT: s_cbranch_vccz .LBB10_11
+; VI-NEXT: ; %bb.8: ; %frem.compute52
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v12, v8
+; VI-NEXT: v_frexp_mant_f32_e32 v8, v8
+; VI-NEXT: v_ldexp_f32 v11, v8, 11
+; VI-NEXT: v_frexp_mant_f32_e32 v8, v7
+; VI-NEXT: v_ldexp_f32 v8, v8, 1
; VI-NEXT: v_div_scale_f32 v14, s[2:3], v8, v8, 1.0
-; VI-NEXT: v_ldexp_f32 v10, v7, 11
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, -1, v13
; VI-NEXT: v_not_b32_e32 v9, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v12
-; VI-NEXT: v_div_scale_f32 v11, vcc, 1.0, v8, 1.0
+; VI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v8, 1.0
; VI-NEXT: v_rcp_f32_e32 v15, v14
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v16, -v14, v15, 1.0
; VI-NEXT: v_fma_f32 v15, v16, v15, v15
-; VI-NEXT: v_mul_f32_e32 v16, v11, v15
-; VI-NEXT: v_fma_f32 v17, -v14, v16, v11
+; VI-NEXT: v_mul_f32_e32 v16, v10, v15
+; VI-NEXT: v_fma_f32 v17, -v14, v16, v10
; VI-NEXT: v_fma_f32 v16, v17, v15, v16
-; VI-NEXT: v_fma_f32 v11, -v14, v16, v11
+; VI-NEXT: v_fma_f32 v10, -v14, v16, v10
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v11, v11, v15, v16
+; VI-NEXT: v_div_fmas_f32 v10, v10, v15, v16
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v9
-; VI-NEXT: v_div_fixup_f32 v11, v11, v8, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_15
-; VI-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
+; VI-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB10_12
+; VI-NEXT: ; %bb.9: ; %frem.loop_body60.preheader
; VI-NEXT: v_sub_u32_e32 v9, vcc, v12, v13
; VI-NEXT: v_add_u32_e32 v9, vcc, 11, v9
-; VI-NEXT: .LBB10_13: ; %frem.loop_body60
+; VI-NEXT: .LBB10_10: ; %frem.loop_body60
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v12, v10
-; VI-NEXT: v_mul_f32_e32 v10, v12, v11
-; VI-NEXT: v_rndne_f32_e32 v10, v10
-; VI-NEXT: v_fma_f32 v10, -v10, v8, v12
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
-; VI-NEXT: v_add_f32_e32 v13, v10, v8
-; VI-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
+; VI-NEXT: v_mov_b32_e32 v12, v11
+; VI-NEXT: v_mul_f32_e32 v11, v12, v10
+; VI-NEXT: v_rndne_f32_e32 v11, v11
+; VI-NEXT: v_fma_f32 v11, -v11, v8, v12
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
+; VI-NEXT: v_add_f32_e32 v13, v11, v8
+; VI-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
; VI-NEXT: v_add_u32_e32 v9, vcc, -11, v9
+; VI-NEXT: v_ldexp_f32 v11, v11, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v9
-; VI-NEXT: v_ldexp_f32 v10, v10, 11
-; VI-NEXT: s_cbranch_vccnz .LBB10_13
-; VI-NEXT: ; %bb.14: ; %Flow129
-; VI-NEXT: v_mov_b32_e32 v10, v12
-; VI-NEXT: .LBB10_15: ; %frem.loop_exit61
+; VI-NEXT: s_cbranch_vccnz .LBB10_10
+; VI-NEXT: s_branch .LBB10_13
+; VI-NEXT: .LBB10_11: ; %frem.else53
+; VI-NEXT: v_and_b32_e32 v9, 0x8000, v5
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
+; VI-NEXT: v_cndmask_b32_e32 v7, v5, v9, vcc
+; VI-NEXT: s_branch .LBB10_14
+; VI-NEXT: .LBB10_12:
+; VI-NEXT: v_mov_b32_e32 v12, v11
+; VI-NEXT: .LBB10_13: ; %frem.loop_exit61
; VI-NEXT: v_add_u32_e32 v9, vcc, -10, v9
-; VI-NEXT: v_ldexp_f32 v9, v10, v9
-; VI-NEXT: v_mul_f32_e32 v10, v9, v11
+; VI-NEXT: v_ldexp_f32 v9, v12, v9
+; VI-NEXT: v_mul_f32_e32 v10, v9, v10
; VI-NEXT: v_rndne_f32_e32 v10, v10
; VI-NEXT: v_fma_f32 v9, -v10, v8, v9
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
@@ -8234,71 +7768,64 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cvt_f16_f32_e32 v7, v7
; VI-NEXT: s_movk_i32 s2, 0x7fff
; VI-NEXT: v_bfi_b32 v7, s2, v7, v5
-; VI-NEXT: .LBB10_16:
-; VI-NEXT: v_cvt_f32_f16_e64 v10, |v1|
-; VI-NEXT: v_cvt_f32_f16_e64 v9, |v3|
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v10, v9
+; VI-NEXT: .LBB10_14:
+; VI-NEXT: v_cvt_f32_f16_e64 v9, |v1|
+; VI-NEXT: v_cvt_f32_f16_e64 v8, |v3|
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, v9, v8
; VI-NEXT: s_cbranch_vccz .LBB10_18
-; VI-NEXT: ; %bb.17: ; %frem.else20
-; VI-NEXT: v_and_b32_e32 v8, 0x8000, v1
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v10, v9
-; VI-NEXT: v_cndmask_b32_e32 v8, v1, v8, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB10_19
-; VI-NEXT: s_branch .LBB10_24
-; VI-NEXT: .LBB10_18:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr8
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB10_24
-; VI-NEXT: .LBB10_19: ; %frem.compute19
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v10
-; VI-NEXT: v_frexp_mant_f32_e32 v8, v10
-; VI-NEXT: v_frexp_mant_f32_e32 v10, v9
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v14, v9
-; VI-NEXT: v_ldexp_f32 v9, v10, 1
+; VI-NEXT: ; %bb.15: ; %frem.compute19
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v9
+; VI-NEXT: v_frexp_mant_f32_e32 v9, v9
+; VI-NEXT: v_ldexp_f32 v12, v9, 11
+; VI-NEXT: v_frexp_mant_f32_e32 v9, v8
+; VI-NEXT: v_ldexp_f32 v9, v9, 1
; VI-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
-; VI-NEXT: v_ldexp_f32 v11, v8, 11
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v14, v8
; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v14
; VI-NEXT: v_not_b32_e32 v10, v8
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v13
-; VI-NEXT: v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
+; VI-NEXT: v_div_scale_f32 v11, vcc, 1.0, v9, 1.0
; VI-NEXT: v_rcp_f32_e32 v16, v15
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v17, -v15, v16, 1.0
; VI-NEXT: v_fma_f32 v16, v17, v16, v16
-; VI-NEXT: v_mul_f32_e32 v17, v12, v16
-; VI-NEXT: v_fma_f32 v18, -v15, v17, v12
+; VI-NEXT: v_mul_f32_e32 v17, v11, v16
+; VI-NEXT: v_fma_f32 v18, -v15, v17, v11
; VI-NEXT: v_fma_f32 v17, v18, v16, v17
-; VI-NEXT: v_fma_f32 v12, -v15, v17, v12
+; VI-NEXT: v_fma_f32 v11, -v15, v17, v11
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v12, v12, v16, v17
+; VI-NEXT: v_div_fmas_f32 v11, v11, v16, v17
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v10
-; VI-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_23
-; VI-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
+; VI-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB10_19
+; VI-NEXT: ; %bb.16: ; %frem.loop_body27.preheader
; VI-NEXT: v_sub_u32_e32 v10, vcc, v13, v14
; VI-NEXT: v_add_u32_e32 v10, vcc, 11, v10
-; VI-NEXT: .LBB10_21: ; %frem.loop_body27
+; VI-NEXT: .LBB10_17: ; %frem.loop_body27
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v13, v11
-; VI-NEXT: v_mul_f32_e32 v11, v13, v12
-; VI-NEXT: v_rndne_f32_e32 v11, v11
-; VI-NEXT: v_fma_f32 v11, -v11, v9, v13
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
-; VI-NEXT: v_add_f32_e32 v14, v11, v9
-; VI-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
+; VI-NEXT: v_mov_b32_e32 v13, v12
+; VI-NEXT: v_mul_f32_e32 v12, v13, v11
+; VI-NEXT: v_rndne_f32_e32 v12, v12
+; VI-NEXT: v_fma_f32 v12, -v12, v9, v13
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
+; VI-NEXT: v_add_f32_e32 v14, v12, v9
+; VI-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, -11, v10
+; VI-NEXT: v_ldexp_f32 v12, v12, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v10
-; VI-NEXT: v_ldexp_f32 v11, v11, 11
-; VI-NEXT: s_cbranch_vccnz .LBB10_21
-; VI-NEXT: ; %bb.22: ; %Flow125
-; VI-NEXT: v_mov_b32_e32 v11, v13
-; VI-NEXT: .LBB10_23: ; %frem.loop_exit28
+; VI-NEXT: s_cbranch_vccnz .LBB10_17
+; VI-NEXT: s_branch .LBB10_20
+; VI-NEXT: .LBB10_18: ; %frem.else20
+; VI-NEXT: v_and_b32_e32 v10, 0x8000, v1
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v9, v8
+; VI-NEXT: v_cndmask_b32_e32 v9, v1, v10, vcc
+; VI-NEXT: s_branch .LBB10_21
+; VI-NEXT: .LBB10_19:
+; VI-NEXT: v_mov_b32_e32 v13, v12
+; VI-NEXT: .LBB10_20: ; %frem.loop_exit28
; VI-NEXT: v_add_u32_e32 v10, vcc, -10, v10
-; VI-NEXT: v_ldexp_f32 v10, v11, v10
-; VI-NEXT: v_mul_f32_e32 v11, v10, v12
+; VI-NEXT: v_ldexp_f32 v10, v13, v10
+; VI-NEXT: v_mul_f32_e32 v11, v10, v11
; VI-NEXT: v_rndne_f32_e32 v11, v11
; VI-NEXT: v_fma_f32 v10, -v11, v9, v10
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
@@ -8307,74 +7834,67 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v8, v9, v8
; VI-NEXT: v_cvt_f16_f32_e32 v8, v8
; VI-NEXT: s_movk_i32 s2, 0x7fff
-; VI-NEXT: v_bfi_b32 v8, s2, v8, v1
-; VI-NEXT: .LBB10_24:
-; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; VI-NEXT: v_bfi_b32 v9, s2, v8, v1
+; VI-NEXT: .LBB10_21:
+; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v3
-; VI-NEXT: v_cvt_f32_f16_e64 v13, |v9|
-; VI-NEXT: v_cvt_f32_f16_e64 v12, |v10|
-; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v13, v12
-; VI-NEXT: s_cbranch_vccz .LBB10_26
-; VI-NEXT: ; %bb.25: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v11, 0x8000, v9
-; VI-NEXT: v_cmp_eq_f32_e32 vcc, v13, v12
-; VI-NEXT: v_cndmask_b32_e32 v11, v9, v11, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB10_27
-; VI-NEXT: s_branch .LBB10_32
-; VI-NEXT: .LBB10_26:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr11
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB10_32
-; VI-NEXT: .LBB10_27: ; %frem.compute
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v16, v13
-; VI-NEXT: v_frexp_mant_f32_e32 v11, v13
-; VI-NEXT: v_frexp_mant_f32_e32 v13, v12
-; VI-NEXT: v_frexp_exp_i32_f32_e32 v17, v12
-; VI-NEXT: v_ldexp_f32 v12, v13, 1
+; VI-NEXT: v_cvt_f32_f16_e64 v12, |v8|
+; VI-NEXT: v_cvt_f32_f16_e64 v11, |v10|
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, v12, v11
+; VI-NEXT: s_cbranch_vccz .LBB10_25
+; VI-NEXT: ; %bb.22: ; %frem.compute
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v16, v12
+; VI-NEXT: v_frexp_mant_f32_e32 v12, v12
+; VI-NEXT: v_ldexp_f32 v15, v12, 11
+; VI-NEXT: v_frexp_mant_f32_e32 v12, v11
+; VI-NEXT: v_ldexp_f32 v12, v12, 1
; VI-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
-; VI-NEXT: v_ldexp_f32 v14, v11, 11
+; VI-NEXT: v_frexp_exp_i32_f32_e32 v17, v11
; VI-NEXT: v_add_u32_e32 v11, vcc, -1, v17
; VI-NEXT: v_not_b32_e32 v13, v11
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v16
-; VI-NEXT: v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
+; VI-NEXT: v_div_scale_f32 v14, vcc, 1.0, v12, 1.0
; VI-NEXT: v_rcp_f32_e32 v19, v18
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v20, -v18, v19, 1.0
; VI-NEXT: v_fma_f32 v19, v20, v19, v19
-; VI-NEXT: v_mul_f32_e32 v20, v15, v19
-; VI-NEXT: v_fma_f32 v21, -v18, v20, v15
+; VI-NEXT: v_mul_f32_e32 v20, v14, v19
+; VI-NEXT: v_fma_f32 v21, -v18, v20, v14
; VI-NEXT: v_fma_f32 v20, v21, v19, v20
-; VI-NEXT: v_fma_f32 v15, -v18, v20, v15
+; VI-NEXT: v_fma_f32 v14, -v18, v20, v14
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v15, v15, v19, v20
+; VI-NEXT: v_div_fmas_f32 v14, v14, v19, v20
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 12, v13
-; VI-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB10_31
-; VI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB10_26
+; VI-NEXT: ; %bb.23: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v13, vcc, v16, v17
; VI-NEXT: v_add_u32_e32 v13, vcc, 11, v13
-; VI-NEXT: .LBB10_29: ; %frem.loop_body
+; VI-NEXT: .LBB10_24: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v16, v14
-; VI-NEXT: v_mul_f32_e32 v14, v16, v15
-; VI-NEXT: v_rndne_f32_e32 v14, v14
-; VI-NEXT: v_fma_f32 v14, -v14, v12, v16
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
-; VI-NEXT: v_add_f32_e32 v17, v14, v12
-; VI-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
+; VI-NEXT: v_mov_b32_e32 v16, v15
+; VI-NEXT: v_mul_f32_e32 v15, v16, v14
+; VI-NEXT: v_rndne_f32_e32 v15, v15
+; VI-NEXT: v_fma_f32 v15, -v15, v12, v16
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v15
+; VI-NEXT: v_add_f32_e32 v17, v15, v12
+; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
; VI-NEXT: v_add_u32_e32 v13, vcc, -11, v13
+; VI-NEXT: v_ldexp_f32 v15, v15, 11
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v13
-; VI-NEXT: v_ldexp_f32 v14, v14, 11
-; VI-NEXT: s_cbranch_vccnz .LBB10_29
-; VI-NEXT: ; %bb.30: ; %Flow
-; VI-NEXT: v_mov_b32_e32 v14, v16
-; VI-NEXT: .LBB10_31: ; %frem.loop_exit
+; VI-NEXT: s_cbranch_vccnz .LBB10_24
+; VI-NEXT: s_branch .LBB10_27
+; VI-NEXT: .LBB10_25: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v13, 0x8000, v8
+; VI-NEXT: v_cmp_eq_f32_e32 vcc, v12, v11
+; VI-NEXT: v_cndmask_b32_e32 v11, v8, v13, vcc
+; VI-NEXT: s_branch .LBB10_28
+; VI-NEXT: .LBB10_26:
+; VI-NEXT: v_mov_b32_e32 v16, v15
+; VI-NEXT: .LBB10_27: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v13, vcc, -10, v13
-; VI-NEXT: v_ldexp_f32 v13, v14, v13
-; VI-NEXT: v_mul_f32_e32 v14, v13, v15
+; VI-NEXT: v_ldexp_f32 v13, v16, v13
+; VI-NEXT: v_mul_f32_e32 v14, v13, v14
; VI-NEXT: v_rndne_f32_e32 v14, v14
; VI-NEXT: v_fma_f32 v13, -v14, v12, v13
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
@@ -8383,8 +7903,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v11, v12, v11
; VI-NEXT: v_cvt_f16_f32_e32 v11, v11
; VI-NEXT: s_movk_i32 s2, 0x7fff
-; VI-NEXT: v_bfi_b32 v11, s2, v11, v9
-; VI-NEXT: .LBB10_32: ; %Flow124
+; VI-NEXT: v_bfi_b32 v11, s2, v11, v8
+; VI-NEXT: .LBB10_28:
; VI-NEXT: s_movk_i32 s4, 0x7c00
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v2
; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |v0|, s4
@@ -8398,11 +7918,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v3
; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], |v1|, s4
; VI-NEXT: s_and_b64 vcc, s[2:3], vcc
-; VI-NEXT: v_cndmask_b32_e32 v3, v2, v8, vcc
+; VI-NEXT: v_cndmask_b32_e32 v3, v2, v9, vcc
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_cmp_lg_f16_e32 vcc, 0, v10
-; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |v9|, s4
+; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |v8|, s4
; VI-NEXT: s_and_b64 vcc, s[0:1], vcc
; VI-NEXT: v_cndmask_b32_sdwa v2, v2, v11, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
@@ -8419,33 +7939,20 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7] offset:32
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v6, |v2|
+; GFX9-NEXT: v_cvt_f32_f16_e64 v5, |v2|
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cvt_f32_f16_e64 v5, |v0|
-; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v6, v5
-; GFX9-NEXT: s_cbranch_vccz .LBB10_2
-; GFX9-NEXT: ; %bb.1: ; %frem.else86
-; GFX9-NEXT: v_and_b32_e32 v4, 0x8000, v2
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v6, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX9-NEXT: s_branch .LBB10_8
-; GFX9-NEXT: .LBB10_2:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr4
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB10_8
-; GFX9-NEXT: .LBB10_3: ; %frem.compute85
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v6
-; GFX9-NEXT: v_frexp_mant_f32_e32 v4, v6
-; GFX9-NEXT: v_frexp_mant_f32_e32 v6, v5
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v5
-; GFX9-NEXT: v_ldexp_f32 v5, v6, 1
+; GFX9-NEXT: v_cvt_f32_f16_e64 v4, |v0|
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v5, v4
+; GFX9-NEXT: s_cbranch_vccz .LBB10_4
+; GFX9-NEXT: ; %bb.1: ; %frem.compute85
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v5
+; GFX9-NEXT: v_frexp_mant_f32_e32 v5, v5
+; GFX9-NEXT: v_ldexp_f32 v8, v5, 11
+; GFX9-NEXT: v_frexp_mant_f32_e32 v5, v4
+; GFX9-NEXT: v_ldexp_f32 v5, v5, 1
; GFX9-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
-; GFX9-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
-; GFX9-NEXT: v_ldexp_f32 v7, v4, 11
+; GFX9-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v4
; GFX9-NEXT: v_add_u32_e32 v4, -1, v10
; GFX9-NEXT: v_not_b32_e32 v6, v4
; GFX9-NEXT: v_add_u32_e32 v6, v6, v9
@@ -8453,37 +7960,43 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; GFX9-NEXT: v_fma_f32 v12, v13, v12, v12
-; GFX9-NEXT: v_mul_f32_e32 v13, v8, v12
-; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v8
+; GFX9-NEXT: v_mul_f32_e32 v13, v7, v12
+; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v7
; GFX9-NEXT: v_fma_f32 v13, v14, v12, v13
-; GFX9-NEXT: v_fma_f32 v8, -v11, v13, v8
+; GFX9-NEXT: v_fma_f32 v7, -v11, v13, v7
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v8, v8, v12, v13
+; GFX9-NEXT: v_div_fmas_f32 v7, v7, v12, v13
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v6
-; GFX9-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_7
-; GFX9-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
+; GFX9-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_5
+; GFX9-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
; GFX9-NEXT: v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT: v_add_u32_e32 v6, 11, v6
-; GFX9-NEXT: .LBB10_5: ; %frem.loop_body93
+; GFX9-NEXT: .LBB10_3: ; %frem.loop_body93
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v9, v7
-; GFX9-NEXT: v_mul_f32_e32 v7, v9, v8
-; GFX9-NEXT: v_rndne_f32_e32 v7, v7
-; GFX9-NEXT: v_fma_f32 v7, -v7, v5, v9
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; GFX9-NEXT: v_add_f32_e32 v10, v7, v5
+; GFX9-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-NEXT: v_mul_f32_e32 v8, v9, v7
+; GFX9-NEXT: v_rndne_f32_e32 v8, v8
+; GFX9-NEXT: v_fma_f32 v8, -v8, v5, v9
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; GFX9-NEXT: v_add_f32_e32 v10, v8, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GFX9-NEXT: v_add_u32_e32 v6, -11, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; GFX9-NEXT: v_ldexp_f32 v8, v8, 11
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v6
-; GFX9-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_5
-; GFX9-NEXT: ; %bb.6: ; %Flow133
-; GFX9-NEXT: v_mov_b32_e32 v7, v9
-; GFX9-NEXT: .LBB10_7: ; %frem.loop_exit94
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_3
+; GFX9-NEXT: s_branch .LBB10_6
+; GFX9-NEXT: .LBB10_4: ; %frem.else86
+; GFX9-NEXT: v_and_b32_e32 v6, 0x8000, v2
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
+; GFX9-NEXT: s_branch .LBB10_7
+; GFX9-NEXT: .LBB10_5:
+; GFX9-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-NEXT: .LBB10_6: ; %frem.loop_exit94
; GFX9-NEXT: v_add_u32_e32 v6, -10, v6
-; GFX9-NEXT: v_ldexp_f32 v6, v7, v6
-; GFX9-NEXT: v_mul_f32_e32 v7, v6, v8
+; GFX9-NEXT: v_ldexp_f32 v6, v9, v6
+; GFX9-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX9-NEXT: v_rndne_f32_e32 v7, v7
; GFX9-NEXT: v_fma_f32 v6, -v7, v5, v6
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -8493,34 +8006,21 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v2
-; GFX9-NEXT: .LBB10_8:
+; GFX9-NEXT: .LBB10_7:
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX9-NEXT: v_cvt_f32_f16_e64 v8, |v5|
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v7, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v8, v7
-; GFX9-NEXT: s_cbranch_vccz .LBB10_10
-; GFX9-NEXT: ; %bb.9: ; %frem.else53
-; GFX9-NEXT: v_and_b32_e32 v6, 0x8000, v5
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB10_11
-; GFX9-NEXT: s_branch .LBB10_16
-; GFX9-NEXT: .LBB10_10:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr6
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB10_16
-; GFX9-NEXT: .LBB10_11: ; %frem.compute52
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v11, v8
-; GFX9-NEXT: v_frexp_mant_f32_e32 v6, v8
-; GFX9-NEXT: v_frexp_mant_f32_e32 v8, v7
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v12, v7
-; GFX9-NEXT: v_ldexp_f32 v7, v8, 1
+; GFX9-NEXT: v_cvt_f32_f16_e64 v7, |v5|
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v6, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v7, v6
+; GFX9-NEXT: s_cbranch_vccz .LBB10_11
+; GFX9-NEXT: ; %bb.8: ; %frem.compute52
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v11, v7
+; GFX9-NEXT: v_frexp_mant_f32_e32 v7, v7
+; GFX9-NEXT: v_ldexp_f32 v10, v7, 11
+; GFX9-NEXT: v_frexp_mant_f32_e32 v7, v6
+; GFX9-NEXT: v_ldexp_f32 v7, v7, 1
; GFX9-NEXT: v_div_scale_f32 v13, s[2:3], v7, v7, 1.0
-; GFX9-NEXT: v_div_scale_f32 v10, vcc, 1.0, v7, 1.0
-; GFX9-NEXT: v_ldexp_f32 v9, v6, 11
+; GFX9-NEXT: v_div_scale_f32 v9, vcc, 1.0, v7, 1.0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v12, v6
; GFX9-NEXT: v_add_u32_e32 v6, -1, v12
; GFX9-NEXT: v_not_b32_e32 v8, v6
; GFX9-NEXT: v_add_u32_e32 v8, v8, v11
@@ -8528,37 +8028,43 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v15, -v13, v14, 1.0
; GFX9-NEXT: v_fma_f32 v14, v15, v14, v14
-; GFX9-NEXT: v_mul_f32_e32 v15, v10, v14
-; GFX9-NEXT: v_fma_f32 v16, -v13, v15, v10
+; GFX9-NEXT: v_mul_f32_e32 v15, v9, v14
+; GFX9-NEXT: v_fma_f32 v16, -v13, v15, v9
; GFX9-NEXT: v_fma_f32 v15, v16, v14, v15
-; GFX9-NEXT: v_fma_f32 v10, -v13, v15, v10
+; GFX9-NEXT: v_fma_f32 v9, -v13, v15, v9
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v10, v10, v14, v15
+; GFX9-NEXT: v_div_fmas_f32 v9, v9, v14, v15
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v8
-; GFX9-NEXT: v_div_fixup_f32 v10, v10, v7, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX9-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
+; GFX9-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_12
+; GFX9-NEXT: ; %bb.9: ; %frem.loop_body60.preheader
; GFX9-NEXT: v_sub_u32_e32 v8, v11, v12
; GFX9-NEXT: v_add_u32_e32 v8, 11, v8
-; GFX9-NEXT: .LBB10_13: ; %frem.loop_body60
+; GFX9-NEXT: .LBB10_10: ; %frem.loop_body60
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v11, v9
-; GFX9-NEXT: v_mul_f32_e32 v9, v11, v10
-; GFX9-NEXT: v_rndne_f32_e32 v9, v9
-; GFX9-NEXT: v_fma_f32 v9, -v9, v7, v11
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
-; GFX9-NEXT: v_add_f32_e32 v12, v9, v7
+; GFX9-NEXT: v_mov_b32_e32 v11, v10
+; GFX9-NEXT: v_mul_f32_e32 v10, v11, v9
+; GFX9-NEXT: v_rndne_f32_e32 v10, v10
+; GFX9-NEXT: v_fma_f32 v10, -v10, v7, v11
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
+; GFX9-NEXT: v_add_f32_e32 v12, v10, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc
; GFX9-NEXT: v_add_u32_e32 v8, -11, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
+; GFX9-NEXT: v_ldexp_f32 v10, v10, 11
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v8
-; GFX9-NEXT: v_ldexp_f32 v9, v9, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_13
-; GFX9-NEXT: ; %bb.14: ; %Flow129
-; GFX9-NEXT: v_mov_b32_e32 v9, v11
-; GFX9-NEXT: .LBB10_15: ; %frem.loop_exit61
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_10
+; GFX9-NEXT: s_branch .LBB10_13
+; GFX9-NEXT: .LBB10_11: ; %frem.else53
+; GFX9-NEXT: v_and_b32_e32 v8, 0x8000, v5
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v7, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
+; GFX9-NEXT: s_branch .LBB10_14
+; GFX9-NEXT: .LBB10_12:
+; GFX9-NEXT: v_mov_b32_e32 v11, v10
+; GFX9-NEXT: .LBB10_13: ; %frem.loop_exit61
; GFX9-NEXT: v_add_u32_e32 v8, -10, v8
-; GFX9-NEXT: v_ldexp_f32 v8, v9, v8
-; GFX9-NEXT: v_mul_f32_e32 v9, v8, v10
+; GFX9-NEXT: v_ldexp_f32 v8, v11, v8
+; GFX9-NEXT: v_mul_f32_e32 v9, v8, v9
; GFX9-NEXT: v_rndne_f32_e32 v9, v9
; GFX9-NEXT: v_fma_f32 v8, -v9, v7, v8
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
@@ -8568,33 +8074,20 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v6, s2, v6, v5
-; GFX9-NEXT: .LBB10_16:
-; GFX9-NEXT: v_cvt_f32_f16_e64 v9, |v3|
-; GFX9-NEXT: v_cvt_f32_f16_e64 v8, |v1|
-; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v9, v8
+; GFX9-NEXT: .LBB10_14:
+; GFX9-NEXT: v_cvt_f32_f16_e64 v8, |v3|
+; GFX9-NEXT: v_cvt_f32_f16_e64 v7, |v1|
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v8, v7
; GFX9-NEXT: s_cbranch_vccz .LBB10_18
-; GFX9-NEXT: ; %bb.17: ; %frem.else20
-; GFX9-NEXT: v_and_b32_e32 v7, 0x8000, v3
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v9, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v7, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX9-NEXT: s_branch .LBB10_24
-; GFX9-NEXT: .LBB10_18:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr7
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB10_24
-; GFX9-NEXT: .LBB10_19: ; %frem.compute19
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v12, v9
-; GFX9-NEXT: v_frexp_mant_f32_e32 v7, v9
-; GFX9-NEXT: v_frexp_mant_f32_e32 v9, v8
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v13, v8
-; GFX9-NEXT: v_ldexp_f32 v8, v9, 1
+; GFX9-NEXT: ; %bb.15: ; %frem.compute19
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v12, v8
+; GFX9-NEXT: v_frexp_mant_f32_e32 v8, v8
+; GFX9-NEXT: v_ldexp_f32 v11, v8, 11
+; GFX9-NEXT: v_frexp_mant_f32_e32 v8, v7
+; GFX9-NEXT: v_ldexp_f32 v8, v8, 1
; GFX9-NEXT: v_div_scale_f32 v14, s[2:3], v8, v8, 1.0
-; GFX9-NEXT: v_div_scale_f32 v11, vcc, 1.0, v8, 1.0
-; GFX9-NEXT: v_ldexp_f32 v10, v7, 11
+; GFX9-NEXT: v_div_scale_f32 v10, vcc, 1.0, v8, 1.0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v13, v7
; GFX9-NEXT: v_add_u32_e32 v7, -1, v13
; GFX9-NEXT: v_not_b32_e32 v9, v7
; GFX9-NEXT: v_add_u32_e32 v9, v9, v12
@@ -8602,37 +8095,43 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v16, -v14, v15, 1.0
; GFX9-NEXT: v_fma_f32 v15, v16, v15, v15
-; GFX9-NEXT: v_mul_f32_e32 v16, v11, v15
-; GFX9-NEXT: v_fma_f32 v17, -v14, v16, v11
+; GFX9-NEXT: v_mul_f32_e32 v16, v10, v15
+; GFX9-NEXT: v_fma_f32 v17, -v14, v16, v10
; GFX9-NEXT: v_fma_f32 v16, v17, v15, v16
-; GFX9-NEXT: v_fma_f32 v11, -v14, v16, v11
+; GFX9-NEXT: v_fma_f32 v10, -v14, v16, v10
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v11, v11, v15, v16
+; GFX9-NEXT: v_div_fmas_f32 v10, v10, v15, v16
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v9
-; GFX9-NEXT: v_div_fixup_f32 v11, v11, v8, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX9-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
+; GFX9-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_19
+; GFX9-NEXT: ; %bb.16: ; %frem.loop_body27.preheader
; GFX9-NEXT: v_sub_u32_e32 v9, v12, v13
; GFX9-NEXT: v_add_u32_e32 v9, 11, v9
-; GFX9-NEXT: .LBB10_21: ; %frem.loop_body27
+; GFX9-NEXT: .LBB10_17: ; %frem.loop_body27
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v12, v10
-; GFX9-NEXT: v_mul_f32_e32 v10, v12, v11
-; GFX9-NEXT: v_rndne_f32_e32 v10, v10
-; GFX9-NEXT: v_fma_f32 v10, -v10, v8, v12
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
-; GFX9-NEXT: v_add_f32_e32 v13, v10, v8
+; GFX9-NEXT: v_mov_b32_e32 v12, v11
+; GFX9-NEXT: v_mul_f32_e32 v11, v12, v10
+; GFX9-NEXT: v_rndne_f32_e32 v11, v11
+; GFX9-NEXT: v_fma_f32 v11, -v11, v8, v12
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
+; GFX9-NEXT: v_add_f32_e32 v13, v11, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
; GFX9-NEXT: v_add_u32_e32 v9, -11, v9
-; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
+; GFX9-NEXT: v_ldexp_f32 v11, v11, 11
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v9
-; GFX9-NEXT: v_ldexp_f32 v10, v10, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_21
-; GFX9-NEXT: ; %bb.22: ; %Flow125
-; GFX9-NEXT: v_mov_b32_e32 v10, v12
-; GFX9-NEXT: .LBB10_23: ; %frem.loop_exit28
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX9-NEXT: s_branch .LBB10_20
+; GFX9-NEXT: .LBB10_18: ; %frem.else20
+; GFX9-NEXT: v_and_b32_e32 v9, 0x8000, v3
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v8, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
+; GFX9-NEXT: s_branch .LBB10_21
+; GFX9-NEXT: .LBB10_19:
+; GFX9-NEXT: v_mov_b32_e32 v12, v11
+; GFX9-NEXT: .LBB10_20: ; %frem.loop_exit28
; GFX9-NEXT: v_add_u32_e32 v9, -10, v9
-; GFX9-NEXT: v_ldexp_f32 v9, v10, v9
-; GFX9-NEXT: v_mul_f32_e32 v10, v9, v11
+; GFX9-NEXT: v_ldexp_f32 v9, v12, v9
+; GFX9-NEXT: v_mul_f32_e32 v10, v9, v10
; GFX9-NEXT: v_rndne_f32_e32 v10, v10
; GFX9-NEXT: v_fma_f32 v9, -v10, v8, v9
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
@@ -8642,34 +8141,21 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v7, v7
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v7, s2, v7, v3
-; GFX9-NEXT: .LBB10_24:
+; GFX9-NEXT: .LBB10_21:
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX9-NEXT: v_cvt_f32_f16_e64 v11, |v8|
-; GFX9-NEXT: v_cvt_f32_f16_sdwa v10, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v11, v10
-; GFX9-NEXT: s_cbranch_vccz .LBB10_26
-; GFX9-NEXT: ; %bb.25: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v9, 0x8000, v8
-; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v11, v10
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX9-NEXT: s_branch .LBB10_32
-; GFX9-NEXT: .LBB10_26:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr9
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB10_32
-; GFX9-NEXT: .LBB10_27: ; %frem.compute
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v14, v11
-; GFX9-NEXT: v_frexp_mant_f32_e32 v9, v11
-; GFX9-NEXT: v_frexp_mant_f32_e32 v11, v10
-; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v15, v10
-; GFX9-NEXT: v_ldexp_f32 v10, v11, 1
+; GFX9-NEXT: v_cvt_f32_f16_e64 v10, |v8|
+; GFX9-NEXT: v_cvt_f32_f16_sdwa v9, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v10, v9
+; GFX9-NEXT: s_cbranch_vccz .LBB10_25
+; GFX9-NEXT: ; %bb.22: ; %frem.compute
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v14, v10
+; GFX9-NEXT: v_frexp_mant_f32_e32 v10, v10
+; GFX9-NEXT: v_ldexp_f32 v13, v10, 11
+; GFX9-NEXT: v_frexp_mant_f32_e32 v10, v9
+; GFX9-NEXT: v_ldexp_f32 v10, v10, 1
; GFX9-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
-; GFX9-NEXT: v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
-; GFX9-NEXT: v_ldexp_f32 v12, v9, 11
+; GFX9-NEXT: v_div_scale_f32 v12, vcc, 1.0, v10, 1.0
+; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v15, v9
; GFX9-NEXT: v_add_u32_e32 v9, -1, v15
; GFX9-NEXT: v_not_b32_e32 v11, v9
; GFX9-NEXT: v_add_u32_e32 v11, v11, v14
@@ -8677,37 +8163,43 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; GFX9-NEXT: v_fma_f32 v17, v18, v17, v17
-; GFX9-NEXT: v_mul_f32_e32 v18, v13, v17
-; GFX9-NEXT: v_fma_f32 v19, -v16, v18, v13
+; GFX9-NEXT: v_mul_f32_e32 v18, v12, v17
+; GFX9-NEXT: v_fma_f32 v19, -v16, v18, v12
; GFX9-NEXT: v_fma_f32 v18, v19, v17, v18
-; GFX9-NEXT: v_fma_f32 v13, -v16, v18, v13
+; GFX9-NEXT: v_fma_f32 v12, -v16, v18, v12
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v13, v13, v17, v18
+; GFX9-NEXT: v_div_fmas_f32 v12, v12, v17, v18
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 12, v11
-; GFX9-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX9-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX9-NEXT: ; %bb.23: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v11, v14, v15
; GFX9-NEXT: v_add_u32_e32 v11, 11, v11
-; GFX9-NEXT: .LBB10_29: ; %frem.loop_body
+; GFX9-NEXT: .LBB10_24: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v14, v12
-; GFX9-NEXT: v_mul_f32_e32 v12, v14, v13
-; GFX9-NEXT: v_rndne_f32_e32 v12, v12
-; GFX9-NEXT: v_fma_f32 v12, -v12, v10, v14
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
-; GFX9-NEXT: v_add_f32_e32 v15, v12, v10
+; GFX9-NEXT: v_mov_b32_e32 v14, v13
+; GFX9-NEXT: v_mul_f32_e32 v13, v14, v12
+; GFX9-NEXT: v_rndne_f32_e32 v13, v13
+; GFX9-NEXT: v_fma_f32 v13, -v13, v10, v14
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
+; GFX9-NEXT: v_add_f32_e32 v15, v13, v10
+; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
; GFX9-NEXT: v_add_u32_e32 v11, -11, v11
-; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
+; GFX9-NEXT: v_ldexp_f32 v13, v13, 11
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 11, v11
-; GFX9-NEXT: v_ldexp_f32 v12, v12, 11
-; GFX9-NEXT: s_cbranch_vccnz .LBB10_29
-; GFX9-NEXT: ; %bb.30: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v12, v14
-; GFX9-NEXT: .LBB10_31: ; %frem.loop_exit
+; GFX9-NEXT: s_cbranch_vccnz .LBB10_24
+; GFX9-NEXT: s_branch .LBB10_27
+; GFX9-NEXT: .LBB10_25: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v11, 0x8000, v8
+; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v10, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v8, v11, vcc
+; GFX9-NEXT: s_branch .LBB10_28
+; GFX9-NEXT: .LBB10_26:
+; GFX9-NEXT: v_mov_b32_e32 v14, v13
+; GFX9-NEXT: .LBB10_27: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v11, -10, v11
-; GFX9-NEXT: v_ldexp_f32 v11, v12, v11
-; GFX9-NEXT: v_mul_f32_e32 v12, v11, v13
+; GFX9-NEXT: v_ldexp_f32 v11, v14, v11
+; GFX9-NEXT: v_mul_f32_e32 v12, v11, v12
; GFX9-NEXT: v_rndne_f32_e32 v12, v12
; GFX9-NEXT: v_fma_f32 v11, -v12, v10, v11
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
@@ -8717,7 +8209,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cvt_f16_f32_e32 v9, v9
; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_bfi_b32 v9, s2, v9, v8
-; GFX9-NEXT: .LBB10_32: ; %Flow124
+; GFX9-NEXT: .LBB10_28:
; GFX9-NEXT: s_movk_i32 s6, 0x7c00
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v0
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v2|, s6
@@ -8728,7 +8220,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cmp_nge_f16_e64 s[4:5], |v5|, s6
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[2:3]
-; GFX9-NEXT: v_cndmask_b32_sdwa v0, v2, v6, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc
; GFX9-NEXT: v_cmp_lg_f16_e32 vcc, 0, v1
; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], |v3|, s6
; GFX9-NEXT: s_and_b64 vcc, s[2:3], vcc
@@ -8737,6 +8229,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v3, v2, v7, vcc
; GFX9-NEXT: s_and_b64 vcc, s[4:5], s[2:3]
; GFX9-NEXT: v_cndmask_b32_sdwa v1, v2, v9, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: global_store_dwordx2 v10, v[0:1], s[0:1]
@@ -8753,37 +8246,24 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[6:7] offset:32
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v6, |v2|
+; GFX10-NEXT: v_cvt_f32_f16_e64 v5, |v2|
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cvt_f32_f16_e64 v5, |v0|
-; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v6, v5
-; GFX10-NEXT: s_cbranch_vccz .LBB10_2
-; GFX10-NEXT: ; %bb.1: ; %frem.else86
-; GFX10-NEXT: v_and_b32_e32 v4, 0x8000, v2
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v2, v4, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX10-NEXT: s_branch .LBB10_8
-; GFX10-NEXT: .LBB10_2:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB10_8
-; GFX10-NEXT: .LBB10_3: ; %frem.compute85
-; GFX10-NEXT: v_frexp_mant_f32_e32 v4, v6
-; GFX10-NEXT: v_frexp_mant_f32_e32 v8, v5
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
-; GFX10-NEXT: v_ldexp_f32 v6, v4, 11
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v4, v5
-; GFX10-NEXT: v_ldexp_f32 v5, v8, 1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v4, |v0|
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
+; GFX10-NEXT: s_cbranch_vccz .LBB10_5
+; GFX10-NEXT: ; %bb.1: ; %frem.compute85
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v5
+; GFX10-NEXT: v_frexp_mant_f32_e32 v5, v5
; GFX10-NEXT: v_readfirstlane_b32 s2, v7
+; GFX10-NEXT: v_ldexp_f32 v6, v5, 11
+; GFX10-NEXT: v_frexp_mant_f32_e32 v5, v4
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
+; GFX10-NEXT: v_ldexp_f32 v5, v5, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v4
-; GFX10-NEXT: v_div_scale_f32 v9, s4, v5, v5, 1.0
; GFX10-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX10-NEXT: v_rcp_f32_e32 v10, v9
+; GFX10-NEXT: v_div_scale_f32 v9, s4, v5, v5, 1.0
; GFX10-NEXT: v_not_b32_e32 v8, v4
+; GFX10-NEXT: v_rcp_f32_e32 v10, v9
; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX10-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -8797,11 +8277,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v7, v7, v10, v11
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX10-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_7
-; GFX10-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_6
+; GFX10-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_5: ; %frem.loop_body93
+; GFX10-NEXT: .LBB10_3: ; %frem.loop_body93
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -8813,13 +8293,20 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v8, v6, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v6, v6, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_5
-; GFX10-NEXT: ; %bb.6: ; %Flow133
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX10-NEXT: ; %bb.4:
; GFX10-NEXT: v_mov_b32_e32 v8, s2
-; GFX10-NEXT: v_mov_b32_e32 v6, v9
+; GFX10-NEXT: s_branch .LBB10_7
+; GFX10-NEXT: .LBB10_5: ; %frem.else86
+; GFX10-NEXT: v_and_b32_e32 v6, 0x8000, v2
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc_lo
+; GFX10-NEXT: s_branch .LBB10_8
+; GFX10-NEXT: .LBB10_6:
+; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX10-NEXT: v_add_nc_u32_e32 v8, -10, v8
-; GFX10-NEXT: v_ldexp_f32 v6, v6, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v6, -10, v8
+; GFX10-NEXT: v_ldexp_f32 v6, v9, v6
; GFX10-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX10-NEXT: v_rndne_f32_e32 v7, v7
; GFX10-NEXT: v_fma_f32 v6, -v7, v5, v6
@@ -8831,36 +8318,23 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_bfi_b32 v4, 0x7fff, v4, v2
; GFX10-NEXT: .LBB10_8:
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v7, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e64 v8, |v5|
-; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v8, v7
-; GFX10-NEXT: s_cbranch_vccz .LBB10_10
-; GFX10-NEXT: ; %bb.9: ; %frem.else53
-; GFX10-NEXT: v_and_b32_e32 v6, 0x8000, v5
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_11
-; GFX10-NEXT: s_branch .LBB10_16
-; GFX10-NEXT: .LBB10_10:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr6
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB10_16
-; GFX10-NEXT: .LBB10_11: ; %frem.compute52
-; GFX10-NEXT: v_frexp_mant_f32_e32 v6, v8
-; GFX10-NEXT: v_frexp_mant_f32_e32 v10, v7
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v9, v8
-; GFX10-NEXT: v_ldexp_f32 v8, v6, 11
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v6, v7
-; GFX10-NEXT: v_ldexp_f32 v7, v10, 1
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v6, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v7, |v5|
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v6
+; GFX10-NEXT: s_cbranch_vccz .LBB10_13
+; GFX10-NEXT: ; %bb.9: ; %frem.compute52
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v9, v7
+; GFX10-NEXT: v_frexp_mant_f32_e32 v7, v7
; GFX10-NEXT: v_readfirstlane_b32 s2, v9
+; GFX10-NEXT: v_ldexp_f32 v8, v7, 11
+; GFX10-NEXT: v_frexp_mant_f32_e32 v7, v6
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v6, v6
+; GFX10-NEXT: v_ldexp_f32 v7, v7, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v6
-; GFX10-NEXT: v_div_scale_f32 v11, s4, v7, v7, 1.0
; GFX10-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX10-NEXT: v_rcp_f32_e32 v12, v11
+; GFX10-NEXT: v_div_scale_f32 v11, s4, v7, v7, 1.0
; GFX10-NEXT: v_not_b32_e32 v10, v6
+; GFX10-NEXT: v_rcp_f32_e32 v12, v11
; GFX10-NEXT: v_add_nc_u32_e32 v10, v10, v9
; GFX10-NEXT: v_div_scale_f32 v9, vcc_lo, 1.0, v7, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -8874,11 +8348,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v9, v9, v12, v13
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v10
; GFX10-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX10-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_14
+; GFX10-NEXT: ; %bb.10: ; %frem.loop_body60.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_13: ; %frem.loop_body60
+; GFX10-NEXT: .LBB10_11: ; %frem.loop_body60
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v11, v8
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -8890,13 +8364,20 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v10, v8, v7
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_13
-; GFX10-NEXT: ; %bb.14: ; %Flow129
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_11
+; GFX10-NEXT: ; %bb.12:
; GFX10-NEXT: v_mov_b32_e32 v10, s2
-; GFX10-NEXT: v_mov_b32_e32 v8, v11
+; GFX10-NEXT: s_branch .LBB10_15
+; GFX10-NEXT: .LBB10_13: ; %frem.else53
+; GFX10-NEXT: v_and_b32_e32 v8, 0x8000, v5
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc_lo
+; GFX10-NEXT: s_branch .LBB10_16
+; GFX10-NEXT: .LBB10_14:
+; GFX10-NEXT: v_mov_b32_e32 v11, v8
; GFX10-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX10-NEXT: v_add_nc_u32_e32 v10, -10, v10
-; GFX10-NEXT: v_ldexp_f32 v8, v8, v10
+; GFX10-NEXT: v_add_nc_u32_e32 v8, -10, v10
+; GFX10-NEXT: v_ldexp_f32 v8, v11, v8
; GFX10-NEXT: v_mul_f32_e32 v9, v8, v9
; GFX10-NEXT: v_rndne_f32_e32 v9, v9
; GFX10-NEXT: v_fma_f32 v8, -v9, v7, v8
@@ -8907,36 +8388,23 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX10-NEXT: v_bfi_b32 v6, 0x7fff, v6, v5
; GFX10-NEXT: .LBB10_16:
-; GFX10-NEXT: v_cvt_f32_f16_e64 v9, |v3|
-; GFX10-NEXT: v_cvt_f32_f16_e64 v8, |v1|
-; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
-; GFX10-NEXT: s_cbranch_vccz .LBB10_18
-; GFX10-NEXT: ; %bb.17: ; %frem.else20
-; GFX10-NEXT: v_and_b32_e32 v7, 0x8000, v3
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v7, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX10-NEXT: s_branch .LBB10_24
-; GFX10-NEXT: .LBB10_18:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr7
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB10_24
-; GFX10-NEXT: .LBB10_19: ; %frem.compute19
-; GFX10-NEXT: v_frexp_mant_f32_e32 v7, v9
-; GFX10-NEXT: v_frexp_mant_f32_e32 v11, v8
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
-; GFX10-NEXT: v_ldexp_f32 v9, v7, 11
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v8
-; GFX10-NEXT: v_ldexp_f32 v8, v11, 1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v8, |v3|
+; GFX10-NEXT: v_cvt_f32_f16_e64 v7, |v1|
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7
+; GFX10-NEXT: s_cbranch_vccz .LBB10_21
+; GFX10-NEXT: ; %bb.17: ; %frem.compute19
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v10, v8
+; GFX10-NEXT: v_frexp_mant_f32_e32 v8, v8
; GFX10-NEXT: v_readfirstlane_b32 s2, v10
+; GFX10-NEXT: v_ldexp_f32 v9, v8, 11
+; GFX10-NEXT: v_frexp_mant_f32_e32 v8, v7
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v7
+; GFX10-NEXT: v_ldexp_f32 v8, v8, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v7
-; GFX10-NEXT: v_div_scale_f32 v12, s4, v8, v8, 1.0
; GFX10-NEXT: v_add_nc_u32_e32 v7, -1, v7
-; GFX10-NEXT: v_rcp_f32_e32 v13, v12
+; GFX10-NEXT: v_div_scale_f32 v12, s4, v8, v8, 1.0
; GFX10-NEXT: v_not_b32_e32 v11, v7
+; GFX10-NEXT: v_rcp_f32_e32 v13, v12
; GFX10-NEXT: v_add_nc_u32_e32 v11, v11, v10
; GFX10-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -8950,11 +8418,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v10, v10, v13, v14
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
; GFX10-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX10-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_22
+; GFX10-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_21: ; %frem.loop_body27
+; GFX10-NEXT: .LBB10_19: ; %frem.loop_body27
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v12, v9
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -8966,13 +8434,20 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v11, v9, v8
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v9, v9, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_21
-; GFX10-NEXT: ; %bb.22: ; %Flow125
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX10-NEXT: ; %bb.20:
; GFX10-NEXT: v_mov_b32_e32 v11, s2
-; GFX10-NEXT: v_mov_b32_e32 v9, v12
+; GFX10-NEXT: s_branch .LBB10_23
+; GFX10-NEXT: .LBB10_21: ; %frem.else20
+; GFX10-NEXT: v_and_b32_e32 v9, 0x8000, v3
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc_lo
+; GFX10-NEXT: s_branch .LBB10_24
+; GFX10-NEXT: .LBB10_22:
+; GFX10-NEXT: v_mov_b32_e32 v12, v9
; GFX10-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX10-NEXT: v_add_nc_u32_e32 v11, -10, v11
-; GFX10-NEXT: v_ldexp_f32 v9, v9, v11
+; GFX10-NEXT: v_add_nc_u32_e32 v9, -10, v11
+; GFX10-NEXT: v_ldexp_f32 v9, v12, v9
; GFX10-NEXT: v_mul_f32_e32 v10, v9, v10
; GFX10-NEXT: v_rndne_f32_e32 v10, v10
; GFX10-NEXT: v_fma_f32 v9, -v10, v8, v9
@@ -8984,36 +8459,23 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_bfi_b32 v7, 0x7fff, v7, v3
; GFX10-NEXT: .LBB10_24:
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX10-NEXT: v_cvt_f32_f16_sdwa v10, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_f16_e64 v11, |v8|
-; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v11, v10
-; GFX10-NEXT: s_cbranch_vccz .LBB10_26
-; GFX10-NEXT: ; %bb.25: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v9, 0x8000, v8
-; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v11, v10
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX10-NEXT: s_branch .LBB10_32
-; GFX10-NEXT: .LBB10_26:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr9
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB10_32
-; GFX10-NEXT: .LBB10_27: ; %frem.compute
-; GFX10-NEXT: v_frexp_mant_f32_e32 v9, v11
-; GFX10-NEXT: v_frexp_mant_f32_e32 v13, v10
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v12, v11
-; GFX10-NEXT: v_ldexp_f32 v11, v9, 11
-; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v9, v10
-; GFX10-NEXT: v_ldexp_f32 v10, v13, 1
+; GFX10-NEXT: v_cvt_f32_f16_sdwa v9, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_f16_e64 v10, |v8|
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v9
+; GFX10-NEXT: s_cbranch_vccz .LBB10_29
+; GFX10-NEXT: ; %bb.25: ; %frem.compute
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v12, v10
+; GFX10-NEXT: v_frexp_mant_f32_e32 v10, v10
; GFX10-NEXT: v_readfirstlane_b32 s2, v12
+; GFX10-NEXT: v_ldexp_f32 v11, v10, 11
+; GFX10-NEXT: v_frexp_mant_f32_e32 v10, v9
+; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v9, v9
+; GFX10-NEXT: v_ldexp_f32 v10, v10, 1
; GFX10-NEXT: v_readfirstlane_b32 s3, v9
-; GFX10-NEXT: v_div_scale_f32 v14, s4, v10, v10, 1.0
; GFX10-NEXT: v_add_nc_u32_e32 v9, -1, v9
-; GFX10-NEXT: v_rcp_f32_e32 v15, v14
+; GFX10-NEXT: v_div_scale_f32 v14, s4, v10, v10, 1.0
; GFX10-NEXT: v_not_b32_e32 v13, v9
+; GFX10-NEXT: v_rcp_f32_e32 v15, v14
; GFX10-NEXT: v_add_nc_u32_e32 v13, v13, v12
; GFX10-NEXT: v_div_scale_f32 v12, vcc_lo, 1.0, v10, 1.0
; GFX10-NEXT: s_denorm_mode 15
@@ -9027,11 +8489,11 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v12, v12, v15, v16
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v13
; GFX10-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX10-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB10_30
+; GFX10-NEXT: ; %bb.26: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 11
-; GFX10-NEXT: .LBB10_29: ; %frem.loop_body
+; GFX10-NEXT: .LBB10_27: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v14, v11
; GFX10-NEXT: s_add_i32 s2, s2, -11
@@ -9043,13 +8505,20 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v13, v11, v10
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX10-NEXT: s_cbranch_scc1 .LBB10_29
-; GFX10-NEXT: ; %bb.30: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX10-NEXT: ; %bb.28:
; GFX10-NEXT: v_mov_b32_e32 v13, s2
-; GFX10-NEXT: v_mov_b32_e32 v11, v14
+; GFX10-NEXT: s_branch .LBB10_31
+; GFX10-NEXT: .LBB10_29: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v11, 0x8000, v8
+; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v11, vcc_lo
+; GFX10-NEXT: s_branch .LBB10_32
+; GFX10-NEXT: .LBB10_30:
+; GFX10-NEXT: v_mov_b32_e32 v14, v11
; GFX10-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v13, -10, v13
-; GFX10-NEXT: v_ldexp_f32 v11, v11, v13
+; GFX10-NEXT: v_add_nc_u32_e32 v11, -10, v13
+; GFX10-NEXT: v_ldexp_f32 v11, v14, v11
; GFX10-NEXT: v_mul_f32_e32 v12, v11, v12
; GFX10-NEXT: v_rndne_f32_e32 v12, v12
; GFX10-NEXT: v_fma_f32 v11, -v12, v10, v11
@@ -9059,7 +8528,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_ldexp_f32 v9, v10, v9
; GFX10-NEXT: v_cvt_f16_f32_e32 v9, v9
; GFX10-NEXT: v_bfi_b32 v9, 0x7fff, v9, v8
-; GFX10-NEXT: .LBB10_32: ; %Flow124
+; GFX10-NEXT: .LBB10_32:
; GFX10-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v2|
; GFX10-NEXT: v_cmp_nle_f16_e64 s3, 0x7c00, |v5|
@@ -9094,43 +8563,27 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v2, s[4:5] offset:32
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v4, |v0.l|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v5, |v2.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v6, v5
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else86
-; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX11-TRUE16-NEXT: s_branch .LBB10_7
-; GFX11-TRUE16-NEXT: .LBB10_2:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB10_7
-; GFX11-TRUE16-NEXT: .LBB10_3: ; %frem.compute85
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v6
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v5
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_5
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.compute85
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v5
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v7
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, v4
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, -1, v5
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v6, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v7, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v7, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, null, v5, v5, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v6, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v5, 1.0
@@ -9149,12 +8602,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v5, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_6
-; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_4
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_5: ; %frem.loop_body93
+; GFX11-TRUE16-NEXT: .LBB10_3: ; %frem.loop_body93
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v4, v6
@@ -9169,49 +8622,39 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_5
-; GFX11-TRUE16-NEXT: .LBB10_6: ; %frem.loop_exit94
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX11-TRUE16-NEXT: .LBB10_4: ; %frem.loop_exit94
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
-; GFX11-TRUE16-NEXT: .LBB10_7:
+; GFX11-TRUE16-NEXT: s_branch .LBB10_6
+; GFX11-TRUE16-NEXT: .LBB10_5: ; %frem.else86
+; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: .LBB10_6:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, |v5.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, |v5.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, |v6.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_9
-; GFX11-TRUE16-NEXT: ; %bb.8: ; %frem.else53
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_10
-; GFX11-TRUE16-NEXT: s_branch .LBB10_14
-; GFX11-TRUE16-NEXT: .LBB10_9:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB10_14
-; GFX11-TRUE16-NEXT: .LBB10_10: ; %frem.compute52
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v9
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v9, v8
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v8
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_11
+; GFX11-TRUE16-NEXT: ; %bb.7: ; %frem.compute52
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v10, v8
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v10
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v9, v7
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v8
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v9, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v9, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v10, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v9
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v10, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v11, null, v8, v8, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v9, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v10, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v12, v11
; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, vcc_lo, 1.0, v8, 1.0
@@ -9230,12 +8673,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v9, v9, v12, v13
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v10
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v9, v9, v8, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_13
-; GFX11-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body60.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_10
+; GFX11-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body60.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_12: ; %frem.loop_body60
+; GFX11-TRUE16-NEXT: .LBB10_9: ; %frem.loop_body60
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v7, v9
@@ -9250,46 +8693,36 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_12
-; GFX11-TRUE16-NEXT: .LBB10_13: ; %frem.loop_exit61
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX11-TRUE16-NEXT: .LBB10_10: ; %frem.loop_exit61
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-TRUE16-NEXT: .LBB10_14:
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v10, |v1.l|
+; GFX11-TRUE16-NEXT: s_branch .LBB10_12
+; GFX11-TRUE16-NEXT: .LBB10_11: ; %frem.else53
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: .LBB10_12:
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, |v1.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, |v3.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v10, v9
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_16
-; GFX11-TRUE16-NEXT: ; %bb.15: ; %frem.else20
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_17
-; GFX11-TRUE16-NEXT: s_branch .LBB10_21
-; GFX11-TRUE16-NEXT: .LBB10_16:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB10_21
-; GFX11-TRUE16-NEXT: .LBB10_17: ; %frem.compute19
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v10
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v10, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_17
+; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.compute19
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v9
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v11
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v8
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, -1, v9
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v10, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v10, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v11, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v10
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v11, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v12, null, v9, v9, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v10, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v13, v12
; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v9, 1.0
@@ -9308,12 +8741,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v10, v10, v13, v14
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v10, v10, v9, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_20
-; GFX11-TRUE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_16
+; GFX11-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_19: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v8, v10
@@ -9328,49 +8761,39 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX11-TRUE16-NEXT: .LBB10_20: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX11-TRUE16-NEXT: .LBB10_16: ; %frem.loop_exit28
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-TRUE16-NEXT: .LBB10_21:
+; GFX11-TRUE16-NEXT: s_branch .LBB10_18
+; GFX11-TRUE16-NEXT: .LBB10_17: ; %frem.else20
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: .LBB10_18:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v13, |v9.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v11, |v9.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v12, |v10.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v13, v12
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_23
-; GFX11-TRUE16-NEXT: ; %bb.22: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v13, v12
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX11-TRUE16-NEXT: s_branch .LBB10_28
-; GFX11-TRUE16-NEXT: .LBB10_23:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB10_28
-; GFX11-TRUE16-NEXT: .LBB10_24: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v13
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v13
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v13, v12
+; GFX11-TRUE16-NEXT: ; %bb.19: ; %frem.compute
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v14, v12
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v12, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v14
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v13, v11
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, -1, v12
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v12, v13, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v12, v14, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v13
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v14, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_scale_f32 v15, null, v12, v12, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v13, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v14, v13
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v16, v15
; GFX11-TRUE16-NEXT: v_div_scale_f32 v13, vcc_lo, 1.0, v12, 1.0
@@ -9389,12 +8812,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v13, v13, v16, v17
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v14
; GFX11-TRUE16-NEXT: v_div_fixup_f32 v13, v13, v12, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_27
-; GFX11-TRUE16-NEXT: ; %bb.25: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_22
+; GFX11-TRUE16-NEXT: ; %bb.20: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_26: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB10_21: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v11, v13
@@ -9409,10 +8832,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_26
-; GFX11-TRUE16-NEXT: .LBB10_27: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_21
+; GFX11-TRUE16-NEXT: .LBB10_22: ; %frem.loop_exit
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-TRUE16-NEXT: .LBB10_28: ; %Flow124
+; GFX11-TRUE16-NEXT: s_branch .LBB10_24
+; GFX11-TRUE16-NEXT: .LBB10_23: ; %frem.else
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v11, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: .LBB10_24:
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
@@ -9445,44 +8874,29 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-FAKE16-NEXT: global_load_b64 v[2:3], v2, s[4:5] offset:32
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v6, |v0|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v5, |v0|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v5, |v2|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v4, |v2|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v6, v5
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_2
-; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.else86
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0x8000, v0
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX11-FAKE16-NEXT: s_branch .LBB10_8
-; GFX11-FAKE16-NEXT: .LBB10_2:
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB10_8
-; GFX11-FAKE16-NEXT: .LBB10_3: ; %frem.compute85
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, v6
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v8, v5
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v4, 11
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v5
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, v8, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_5
+; GFX11-FAKE16-NEXT: ; %bb.1: ; %frem.compute85
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v5
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v7
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v5, 11
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v5, v4
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v5, v5, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_div_scale_f32 v9, null, v5, v5, 1.0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v10, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_div_scale_f32 v9, null, v5, v5, 1.0
; GFX11-FAKE16-NEXT: v_not_b32_e32 v8, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
; GFX11-FAKE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -9501,12 +8915,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_7
-; GFX11-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_6
+; GFX11-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_5: ; %frem.loop_body93
+; GFX11-FAKE16-NEXT: .LBB10_3: ; %frem.loop_body93
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v6
@@ -9522,14 +8936,22 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v6, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_5
-; GFX11-FAKE16-NEXT: ; %bb.6: ; %Flow133
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX11-FAKE16-NEXT: ; %bb.4:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v9
+; GFX11-FAKE16-NEXT: s_branch .LBB10_7
+; GFX11-FAKE16-NEXT: .LBB10_5: ; %frem.else86
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0x8000, v0
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v0, v6, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB10_8
+; GFX11-FAKE16-NEXT: .LBB10_6:
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v6
; GFX11-FAKE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, -10, v8
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v6, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v8
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v6, v9, v6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v7, v7
@@ -9547,43 +8969,28 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, |v5|
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v8, |v6|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v8, |v5|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v7, |v6|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_10
-; GFX11-FAKE16-NEXT: ; %bb.9: ; %frem.else53
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0x8000, v5
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
-; GFX11-FAKE16-NEXT: s_branch .LBB10_16
-; GFX11-FAKE16-NEXT: .LBB10_10:
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB10_16
-; GFX11-FAKE16-NEXT: .LBB10_11: ; %frem.compute52
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v7, v9
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v11, v8
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v7, 11
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v8
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v8, v11, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v7
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_13
+; GFX11-FAKE16-NEXT: ; %bb.9: ; %frem.compute52
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v8
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v8, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v10
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v8, 11
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v8, v8, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_div_scale_f32 v12, null, v8, v8, 1.0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, -1, v7
-; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v13, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_div_scale_f32 v12, null, v8, v8, 1.0
; GFX11-FAKE16-NEXT: v_not_b32_e32 v11, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v13, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v10
; GFX11-FAKE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -9602,12 +9009,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX11-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_14
+; GFX11-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body60.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_13: ; %frem.loop_body60
+; GFX11-FAKE16-NEXT: .LBB10_11: ; %frem.loop_body60
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v12, v9
@@ -9623,14 +9030,22 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v9, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_13
-; GFX11-FAKE16-NEXT: ; %bb.14: ; %Flow129
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
+; GFX11-FAKE16-NEXT: ; %bb.12:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, s2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v12
+; GFX11-FAKE16-NEXT: s_branch .LBB10_15
+; GFX11-FAKE16-NEXT: .LBB10_13: ; %frem.else53
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0x8000, v5
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v5, v9, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB10_16
+; GFX11-FAKE16-NEXT: .LBB10_14:
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v12, v9
; GFX11-FAKE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, -10, v11
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v9, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, -10, v11
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v12, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v10, v9, v10
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v10, v10
@@ -9645,43 +9060,28 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v7, v7
; GFX11-FAKE16-NEXT: v_bfi_b32 v7, 0x7fff, v7, v5
; GFX11-FAKE16-NEXT: .LBB10_16:
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v10, |v1|
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, |v3|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v9, |v1|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v8, |v3|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v10, v9
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_18
-; GFX11-FAKE16-NEXT: ; %bb.17: ; %frem.else20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0x8000, v1
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v1, v8, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX11-FAKE16-NEXT: s_branch .LBB10_24
-; GFX11-FAKE16-NEXT: .LBB10_18:
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB10_24
-; GFX11-FAKE16-NEXT: .LBB10_19: ; %frem.compute19
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v8, v10
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v12, v9
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v8, 11
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v9
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v12, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_21
+; GFX11-FAKE16-NEXT: ; %bb.17: ; %frem.compute19
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v9
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v9, v9
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v11
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v9, 11
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v9, v8
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v9, v9, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_div_scale_f32 v13, null, v9, v9, 1.0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, -1, v8
-; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v14, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_div_scale_f32 v13, null, v9, v9, 1.0
; GFX11-FAKE16-NEXT: v_not_b32_e32 v12, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v11
; GFX11-FAKE16-NEXT: v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -9700,12 +9100,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v12
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX11-FAKE16-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_22
+; GFX11-FAKE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_21: ; %frem.loop_body27
+; GFX11-FAKE16-NEXT: .LBB10_19: ; %frem.loop_body27
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, v10
@@ -9721,14 +9121,22 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v10, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_21
-; GFX11-FAKE16-NEXT: ; %bb.22: ; %Flow125
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX11-FAKE16-NEXT: ; %bb.20:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v12, s2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, v13
+; GFX11-FAKE16-NEXT: s_branch .LBB10_23
+; GFX11-FAKE16-NEXT: .LBB10_21: ; %frem.else20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0x8000, v1
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v1, v10, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB10_24
+; GFX11-FAKE16-NEXT: .LBB10_22:
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, v10
; GFX11-FAKE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, -10, v12
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v10, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, -10, v12
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v10, v13, v10
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v11, v10, v11
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v11, v11
@@ -9746,43 +9154,28 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v13, |v9|
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v12, |v10|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v12, |v9|
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e64 v11, |v10|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v13, v12
-; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_26
-; GFX11-FAKE16-NEXT: ; %bb.25: ; %frem.else
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0x8000, v9
-; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v13, v12
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, 0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v11, vcc_lo
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX11-FAKE16-NEXT: s_branch .LBB10_32
-; GFX11-FAKE16-NEXT: .LBB10_26:
-; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB10_32
-; GFX11-FAKE16-NEXT: .LBB10_27: ; %frem.compute
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v11, v13
-; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v15, v12
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v13
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v11, 11
-; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v12
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v12, v15, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v11
+; GFX11-FAKE16-NEXT: s_cbranch_vccz .LBB10_29
+; GFX11-FAKE16-NEXT: ; %bb.25: ; %frem.compute
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v12
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v12, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v14
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v12, 11
+; GFX11-FAKE16-NEXT: v_frexp_mant_f32_e32 v12, v11
+; GFX11-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v12, v12, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_div_scale_f32 v16, null, v12, v12, 1.0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, -1, v11
-; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v17, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_div_scale_f32 v16, null, v12, v12, 1.0
; GFX11-FAKE16-NEXT: v_not_b32_e32 v15, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v17, v16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v14
; GFX11-FAKE16-NEXT: v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
; GFX11-FAKE16-NEXT: s_denorm_mode 15
@@ -9801,12 +9194,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX11-FAKE16-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB10_30
+; GFX11-FAKE16-NEXT: ; %bb.26: ; %frem.loop_body.preheader
; GFX11-FAKE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-FAKE16-NEXT: .LBB10_29: ; %frem.loop_body
+; GFX11-FAKE16-NEXT: .LBB10_27: ; %frem.loop_body
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v16, v13
@@ -9822,14 +9215,22 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v13, 11
-; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_29
-; GFX11-FAKE16-NEXT: ; %bb.30: ; %Flow
+; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX11-FAKE16-NEXT: ; %bb.28:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v15, s2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v13, v16
+; GFX11-FAKE16-NEXT: s_branch .LBB10_31
+; GFX11-FAKE16-NEXT: .LBB10_29: ; %frem.else
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0x8000, v9
+; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v12, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v13, vcc_lo
+; GFX11-FAKE16-NEXT: s_branch .LBB10_32
+; GFX11-FAKE16-NEXT: .LBB10_30:
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v16, v13
; GFX11-FAKE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, -10, v15
-; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v13, v15
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, -10, v15
+; GFX11-FAKE16-NEXT: v_ldexp_f32 v13, v16, v13
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mul_f32_e32 v14, v13, v14
; GFX11-FAKE16-NEXT: v_rndne_f32_e32 v14, v14
@@ -9843,7 +9244,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v11, v11
; GFX11-FAKE16-NEXT: v_bfi_b32 v11, 0x7fff, v11, v9
-; GFX11-FAKE16-NEXT: .LBB10_32: ; %Flow124
+; GFX11-FAKE16-NEXT: .LBB10_32:
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
; GFX11-FAKE16-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -9882,42 +9283,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[8:9] offset:32
; GFX1150-TRUE16-NEXT: s_and_b32 s3, s5, 0x7fff
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s3
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s3
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1150-TRUE16-NEXT: s_and_b32 s6, s4, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1150-TRUE16-NEXT: s_and_b32 s8, s4, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s8, s6
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_2
-; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.else86
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s8, s6
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s5
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s9
-; GFX1150-TRUE16-NEXT: s_mov_b32 s9, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_7
-; GFX1150-TRUE16-NEXT: .LBB10_2:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s9, -1
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_7
-; GFX1150-TRUE16-NEXT: .LBB10_3: ; %frem.compute85
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s8
+; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s6, s8
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_5
+; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.compute85
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v2
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9941,12 +9325,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_6
-; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s8, s6
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_4
+; GFX1150-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s6, s8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-TRUE16-NEXT: .LBB10_5: ; %frem.loop_body93
+; GFX1150-TRUE16-NEXT: .LBB10_3: ; %frem.loop_body93
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -9962,46 +9346,36 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_5
-; GFX1150-TRUE16-NEXT: .LBB10_6: ; %frem.loop_exit94
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX1150-TRUE16-NEXT: .LBB10_4: ; %frem.loop_exit94
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: .LBB10_7:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_6
+; GFX1150-TRUE16-NEXT: .LBB10_5: ; %frem.else86
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s6, s8
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s5
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s6, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s6
+; GFX1150-TRUE16-NEXT: .LBB10_6:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s8, s6, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s5
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1150-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_9
-; GFX1150-TRUE16-NEXT: ; %bb.8: ; %frem.else53
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
-; GFX1150-TRUE16-NEXT: s_mov_b32 s10, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_10
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_14
-; GFX1150-TRUE16-NEXT: .LBB10_9:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s10, -1
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_14
-; GFX1150-TRUE16-NEXT: .LBB10_10: ; %frem.compute52
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s9
+; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s10, s9
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_11
+; GFX1150-TRUE16-NEXT: ; %bb.7: ; %frem.compute52
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s10
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s10
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v4
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -10025,12 +9399,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_13
-; GFX1150-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body60.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s8, s9, s8
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_10
+; GFX1150-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body60.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s8, s8, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s8, s8, 11
-; GFX1150-TRUE16-NEXT: .LBB10_12: ; %frem.loop_body60
+; GFX1150-TRUE16-NEXT: .LBB10_9: ; %frem.loop_body60
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -10046,44 +9420,34 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_12
-; GFX1150-TRUE16-NEXT: .LBB10_13: ; %frem.loop_exit61
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX1150-TRUE16-NEXT: .LBB10_10: ; %frem.loop_exit61
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB10_14:
-; GFX1150-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s8
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_16
-; GFX1150-TRUE16-NEXT: ; %bb.15: ; %frem.else20
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_12
+; GFX1150-TRUE16-NEXT: .LBB10_11: ; %frem.else53
; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
-; GFX1150-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_17
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_21
-; GFX1150-TRUE16-NEXT: .LBB10_16:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s11, -1
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_21
-; GFX1150-TRUE16-NEXT: .LBB10_17: ; %frem.compute19
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
+; GFX1150-TRUE16-NEXT: .LBB10_12:
+; GFX1150-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s10, s2, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s8
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s9, s10
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_17
+; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.compute19
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s10
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v4
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -10107,12 +9471,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_20
-; GFX1150-TRUE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s10, s9
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_16
+; GFX1150-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s9, s10
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-TRUE16-NEXT: .LBB10_19: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -10128,46 +9492,36 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX1150-TRUE16-NEXT: .LBB10_20: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX1150-TRUE16-NEXT: .LBB10_16: ; %frem.loop_exit28
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB10_21:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_18
+; GFX1150-TRUE16-NEXT: .LBB10_17: ; %frem.else20
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s9, s10
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s9
+; GFX1150-TRUE16-NEXT: .LBB10_18:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s10, s9, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s11, s7
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1150-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
+; GFX1150-TRUE16-NEXT: s_cmp_gt_f32 s12, s11
; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_23
-; GFX1150-TRUE16-NEXT: ; %bb.22: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
-; GFX1150-TRUE16-NEXT: s_mov_b32 s12, 0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_28
-; GFX1150-TRUE16-NEXT: .LBB10_23:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s12, -1
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_28
-; GFX1150-TRUE16-NEXT: .LBB10_24: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s11
+; GFX1150-TRUE16-NEXT: ; %bb.19: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s12
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s12
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s11, v6
; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s11, v5
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v4, v4, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -10191,12 +9545,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_27
-; GFX1150-TRUE16-NEXT: ; %bb.25: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s10, s11, s10
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_22
+; GFX1150-TRUE16-NEXT: ; %bb.20: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s10, s10, s11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s10, s10, 11
-; GFX1150-TRUE16-NEXT: .LBB10_26: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: .LBB10_21: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
@@ -10212,10 +9566,17 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_26
-; GFX1150-TRUE16-NEXT: .LBB10_27: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_21
+; GFX1150-TRUE16-NEXT: .LBB10_22: ; %frem.loop_exit
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-TRUE16-NEXT: .LBB10_28: ; %Flow124
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_24
+; GFX1150-TRUE16-NEXT: .LBB10_23: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s12, s11
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s11
+; GFX1150-TRUE16-NEXT: .LBB10_24:
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1150-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -10262,45 +9623,28 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: global_load_b64 v[0:1], v2, s[8:9] offset:32
; GFX1150-FAKE16-NEXT: s_and_b32 s3, s5, 0x7fff
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s8, s3
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s6, s3
; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1150-FAKE16-NEXT: s_and_b32 s6, s4, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1150-FAKE16-NEXT: s_and_b32 s8, s4, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s8, s6
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_2
-; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.else86
-; GFX1150-FAKE16-NEXT: s_and_b32 s9, 0x8000, s5
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s8, s6
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v0, s9
-; GFX1150-FAKE16-NEXT: s_mov_b32 s9, 0
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
-; GFX1150-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_8
-; GFX1150-FAKE16-NEXT: .LBB10_2:
-; GFX1150-FAKE16-NEXT: s_mov_b32 s9, -1
-; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_8
-; GFX1150-FAKE16-NEXT: .LBB10_3: ; %frem.compute85
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s8
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s6, s8
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_5
+; GFX1150-FAKE16-NEXT: ; %bb.1: ; %frem.compute85
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v1, v1, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s8
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s8, v0
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10322,12 +9666,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_7
-; GFX1150-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s6, s8, s6
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_6
+; GFX1150-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s6, s6, s8
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-FAKE16-NEXT: .LBB10_5: ; %frem.loop_body93
+; GFX1150-FAKE16-NEXT: .LBB10_3: ; %frem.loop_body93
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -10345,14 +9689,24 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_5
-; GFX1150-FAKE16-NEXT: ; %bb.6: ; %Flow133
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX1150-FAKE16-NEXT: ; %bb.4:
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, s6
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_7
+; GFX1150-FAKE16-NEXT: .LBB10_5: ; %frem.else86
+; GFX1150-FAKE16-NEXT: s_and_b32 s9, 0x8000, s5
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s6, s8
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v0, s9
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_8
+; GFX1150-FAKE16-NEXT: .LBB10_6:
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1150-FAKE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v2, -10, v4
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v5, v2
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v3, v3
@@ -10372,42 +9726,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1150-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1150-FAKE16-NEXT: s_and_b32 s5, s8, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s9, s6, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s10, s5
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
+; GFX1150-FAKE16-NEXT: s_and_b32 s10, s6, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s9, s5
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s10, s10
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_10
-; GFX1150-FAKE16-NEXT: ; %bb.9: ; %frem.else53
-; GFX1150-FAKE16-NEXT: s_and_b32 s11, 0x8000, s8
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v1, s11
-; GFX1150-FAKE16-NEXT: s_mov_b32 s11, 0
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
-; GFX1150-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_16
-; GFX1150-FAKE16-NEXT: .LBB10_10:
-; GFX1150-FAKE16-NEXT: s_mov_b32 s11, -1
-; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_16
-; GFX1150-FAKE16-NEXT: .LBB10_11: ; %frem.compute52
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s9
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s10
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s9, s10
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_13
+; GFX1150-FAKE16-NEXT: ; %bb.9: ; %frem.compute52
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s10
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s9
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v2, v2, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s10
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s9, v4
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s9, v1
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s10, v1
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10429,12 +9766,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX1150-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s9, s10, s9
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_14
+; GFX1150-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body60.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s9, s9, s10
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-FAKE16-NEXT: .LBB10_13: ; %frem.loop_body60
+; GFX1150-FAKE16-NEXT: .LBB10_11: ; %frem.loop_body60
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -10452,14 +9789,24 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_13
-; GFX1150-FAKE16-NEXT: ; %bb.14: ; %Flow129
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
+; GFX1150-FAKE16-NEXT: ; %bb.12:
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, s9
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_15
+; GFX1150-FAKE16-NEXT: .LBB10_13: ; %frem.else53
+; GFX1150-FAKE16-NEXT: s_and_b32 s11, 0x8000, s8
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s9, s10
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v1, s11
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_16
+; GFX1150-FAKE16-NEXT: .LBB10_14:
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, v3
; GFX1150-FAKE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v3, -10, v5
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v6, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v4, v4
@@ -10477,42 +9824,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s8
; GFX1150-FAKE16-NEXT: .LBB10_16:
; GFX1150-FAKE16-NEXT: s_and_b32 s8, s7, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s9, s2, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s10, s8
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
+; GFX1150-FAKE16-NEXT: s_and_b32 s10, s2, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s9, s8
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s10, s10
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_18
-; GFX1150-FAKE16-NEXT: ; %bb.17: ; %frem.else20
-; GFX1150-FAKE16-NEXT: s_and_b32 s11, 0x8000, s7
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, s11
-; GFX1150-FAKE16-NEXT: s_mov_b32 s11, 0
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
-; GFX1150-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_24
-; GFX1150-FAKE16-NEXT: .LBB10_18:
-; GFX1150-FAKE16-NEXT: s_mov_b32 s11, -1
-; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_24
-; GFX1150-FAKE16-NEXT: .LBB10_19: ; %frem.compute19
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s9
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
+; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s9, s10
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_21
+; GFX1150-FAKE16-NEXT: ; %bb.17: ; %frem.compute19
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s10
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s9
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s10
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s9, v5
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s9, v2
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s10, v2
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10534,12 +9864,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX1150-FAKE16-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s9, s10, s9
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_22
+; GFX1150-FAKE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s9, s9, s10
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-FAKE16-NEXT: .LBB10_21: ; %frem.loop_body27
+; GFX1150-FAKE16-NEXT: .LBB10_19: ; %frem.loop_body27
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -10557,14 +9887,24 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_21
-; GFX1150-FAKE16-NEXT: ; %bb.22: ; %Flow125
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX1150-FAKE16-NEXT: ; %bb.20:
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v6, s9
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_23
+; GFX1150-FAKE16-NEXT: .LBB10_21: ; %frem.else20
+; GFX1150-FAKE16-NEXT: s_and_b32 s11, 0x8000, s7
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s9, s10
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v2, s11
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_24
+; GFX1150-FAKE16-NEXT: .LBB10_22:
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1150-FAKE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -10584,42 +9924,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1150-FAKE16-NEXT: s_lshr_b32 s9, s2, 16
; GFX1150-FAKE16-NEXT: s_and_b32 s7, s10, 0x7fff
-; GFX1150-FAKE16-NEXT: s_and_b32 s11, s9, 0x7fff
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s12, s7
-; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s11, s11
+; GFX1150-FAKE16-NEXT: s_and_b32 s12, s9, 0x7fff
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s11, s7
+; GFX1150-FAKE16-NEXT: s_cvt_f32_f16 s12, s12
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-FAKE16-NEXT: s_cmp_ngt_f32 s12, s11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_26
-; GFX1150-FAKE16-NEXT: ; %bb.25: ; %frem.else
-; GFX1150-FAKE16-NEXT: s_and_b32 s13, 0x8000, s10
-; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s12, s11
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, s13
-; GFX1150-FAKE16-NEXT: s_mov_b32 s13, 0
-; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
-; GFX1150-FAKE16-NEXT: s_and_b32 s13, s13, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX1150-FAKE16-NEXT: s_branch .LBB10_32
-; GFX1150-FAKE16-NEXT: .LBB10_26:
-; GFX1150-FAKE16-NEXT: s_mov_b32 s13, -1
-; GFX1150-FAKE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-FAKE16-NEXT: s_and_b32 s13, s13, exec_lo
-; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_32
-; GFX1150-FAKE16-NEXT: .LBB10_27: ; %frem.compute
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, s11
-; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s12
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
+; GFX1150-FAKE16-NEXT: s_cmp_gt_f32 s11, s12
+; GFX1150-FAKE16-NEXT: s_cbranch_scc0 .LBB10_29
+; GFX1150-FAKE16-NEXT: ; %bb.25: ; %frem.compute
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, s12
+; GFX1150-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s11
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s11
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v4, v4, 1
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v5, v3, 11
-; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1150-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s12
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s12, v6
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s11, v6
; GFX1150-FAKE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s11, v3
+; GFX1150-FAKE16-NEXT: v_readfirstlane_b32 s12, v3
; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v9, v8
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -10641,12 +9964,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1150-FAKE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX1150-FAKE16-NEXT: ; %bb.28: ; %frem.loop_body.preheader
-; GFX1150-FAKE16-NEXT: s_sub_i32 s11, s12, s11
+; GFX1150-FAKE16-NEXT: s_cbranch_vccnz .LBB10_30
+; GFX1150-FAKE16-NEXT: ; %bb.26: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: s_add_i32 s11, s11, 11
-; GFX1150-FAKE16-NEXT: .LBB10_29: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT: .LBB10_27: ; %frem.loop_body
; GFX1150-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v8, v5
@@ -10664,14 +9987,24 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_29
-; GFX1150-FAKE16-NEXT: ; %bb.30: ; %Flow
+; GFX1150-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX1150-FAKE16-NEXT: ; %bb.28:
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v7, s11
-; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v5, v8
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_31
+; GFX1150-FAKE16-NEXT: .LBB10_29: ; %frem.else
+; GFX1150-FAKE16-NEXT: s_and_b32 s13, 0x8000, s10
+; GFX1150-FAKE16-NEXT: s_cmp_eq_f32 s11, s12
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v3, s13
+; GFX1150-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
+; GFX1150-FAKE16-NEXT: s_branch .LBB10_32
+; GFX1150-FAKE16-NEXT: .LBB10_30:
+; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v8, v5
; GFX1150-FAKE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
-; GFX1150-FAKE16-NEXT: v_ldexp_f32 v5, v5, v7
+; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v7
+; GFX1150-FAKE16-NEXT: v_ldexp_f32 v5, v8, v5
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1150-FAKE16-NEXT: v_rndne_f32_e32 v6, v6
@@ -10687,7 +10020,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-FAKE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, s10
-; GFX1150-FAKE16-NEXT: .LBB10_32: ; %Flow124
+; GFX1150-FAKE16-NEXT: .LBB10_32:
; GFX1150-FAKE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1150-FAKE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1150-FAKE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -10738,42 +10071,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[8:9] offset:32
; GFX1200-TRUE16-NEXT: s_and_b32 s3, s5, 0x7fff
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s3
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s3
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1200-TRUE16-NEXT: s_and_b32 s6, s4, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1200-TRUE16-NEXT: s_and_b32 s8, s4, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s8, s6
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_2
-; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.else86
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s8, s6
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s5
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s9
-; GFX1200-TRUE16-NEXT: s_mov_b32 s9, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_7
-; GFX1200-TRUE16-NEXT: .LBB10_2:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s9, -1
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_7
-; GFX1200-TRUE16-NEXT: .LBB10_3: ; %frem.compute85
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s8
+; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s6, s8
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_5
+; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.compute85
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v2
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -10797,12 +10113,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_6
-; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s8, s6
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_4
+; GFX1200-TRUE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s6, s8
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-TRUE16-NEXT: .LBB10_5: ; %frem.loop_body93
+; GFX1200-TRUE16-NEXT: .LBB10_3: ; %frem.loop_body93
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
@@ -10821,50 +10137,39 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_5
-; GFX1200-TRUE16-NEXT: .LBB10_6: ; %frem.loop_exit94
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX1200-TRUE16-NEXT: .LBB10_4: ; %frem.loop_exit94
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: .LBB10_7:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_6
+; GFX1200-TRUE16-NEXT: .LBB10_5: ; %frem.else86
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s6, s8
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s5
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s6, -1, 0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s5, v0.l, s6
+; GFX1200-TRUE16-NEXT: .LBB10_6:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
-; GFX1200-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s8, s6, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s5
+; GFX1200-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_9
-; GFX1200-TRUE16-NEXT: ; %bb.8: ; %frem.else53
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
-; GFX1200-TRUE16-NEXT: s_mov_b32 s10, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_10
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_14
-; GFX1200-TRUE16-NEXT: .LBB10_9:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s10, -1
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_14
-; GFX1200-TRUE16-NEXT: .LBB10_10: ; %frem.compute52
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s9
+; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s10, s9
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_11
+; GFX1200-TRUE16-NEXT: ; %bb.7: ; %frem.compute52
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s10
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s10
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v4
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -10889,12 +10194,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_13
-; GFX1200-TRUE16-NEXT: ; %bb.11: ; %frem.loop_body60.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s8, s9, s8
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_10
+; GFX1200-TRUE16-NEXT: ; %bb.8: ; %frem.loop_body60.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s8, s8, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s8, s8, 11
-; GFX1200-TRUE16-NEXT: .LBB10_12: ; %frem.loop_body60
+; GFX1200-TRUE16-NEXT: .LBB10_9: ; %frem.loop_body60
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
@@ -10913,47 +10218,37 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_12
-; GFX1200-TRUE16-NEXT: .LBB10_13: ; %frem.loop_exit61
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
+; GFX1200-TRUE16-NEXT: .LBB10_10: ; %frem.loop_exit61
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB10_14:
-; GFX1200-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s8
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_16
-; GFX1200-TRUE16-NEXT: ; %bb.15: ; %frem.else20
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_12
+; GFX1200-TRUE16-NEXT: .LBB10_11: ; %frem.else53
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
-; GFX1200-TRUE16-NEXT: s_mov_b32 s11, 0
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
+; GFX1200-TRUE16-NEXT: .LBB10_12:
+; GFX1200-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s10, s2, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_17
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_21
-; GFX1200-TRUE16-NEXT: .LBB10_16:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s11, -1
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s8
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_21
-; GFX1200-TRUE16-NEXT: .LBB10_17: ; %frem.compute19
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s10
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s9, s10
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_17
+; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.compute19
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s10
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v4
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -10978,12 +10273,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_20
-; GFX1200-TRUE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_16
+; GFX1200-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s9, s10
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-TRUE16-NEXT: .LBB10_19: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
@@ -11002,50 +10297,40 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX1200-TRUE16-NEXT: .LBB10_20: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX1200-TRUE16-NEXT: .LBB10_16: ; %frem.loop_exit28
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB10_21:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_18
+; GFX1200-TRUE16-NEXT: .LBB10_17: ; %frem.else20
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s9, s10
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s9
+; GFX1200-TRUE16-NEXT: .LBB10_18:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX1200-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s10, s9, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s7
+; GFX1200-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
+; GFX1200-TRUE16-NEXT: s_cmp_gt_f32 s12, s11
; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_23
-; GFX1200-TRUE16-NEXT: ; %bb.22: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
-; GFX1200-TRUE16-NEXT: s_mov_b32 s12, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_28
-; GFX1200-TRUE16-NEXT: .LBB10_23:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s12, -1
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_28
-; GFX1200-TRUE16-NEXT: .LBB10_24: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s11
+; GFX1200-TRUE16-NEXT: ; %bb.19: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s12
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s12
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s11, v6
; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s11, v5
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v4, v4, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -11070,12 +10355,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_27
-; GFX1200-TRUE16-NEXT: ; %bb.25: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s10, s11, s10
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_22
+; GFX1200-TRUE16-NEXT: ; %bb.20: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s10, s10, s11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s10, s10, 11
-; GFX1200-TRUE16-NEXT: .LBB10_26: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: .LBB10_21: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
@@ -11094,10 +10379,18 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_26
-; GFX1200-TRUE16-NEXT: .LBB10_27: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_21
+; GFX1200-TRUE16-NEXT: .LBB10_22: ; %frem.loop_exit
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-TRUE16-NEXT: .LBB10_28: ; %Flow124
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_24
+; GFX1200-TRUE16-NEXT: .LBB10_23: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s12, s11
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s11
+; GFX1200-TRUE16-NEXT: .LBB10_24:
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -11147,46 +10440,28 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: global_load_b64 v[0:1], v2, s[8:9] offset:32
; GFX1200-FAKE16-NEXT: s_and_b32 s3, s5, 0x7fff
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s8, s3
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s6, s3
; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s4, v0
; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1200-FAKE16-NEXT: s_and_b32 s6, s4, 0x7fff
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1200-FAKE16-NEXT: s_and_b32 s8, s4, 0x7fff
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s8, s8
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s8, s6
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_2
-; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.else86
-; GFX1200-FAKE16-NEXT: s_and_b32 s9, 0x8000, s5
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s8, s6
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, s9
-; GFX1200-FAKE16-NEXT: s_mov_b32 s9, 0
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_8
-; GFX1200-FAKE16-NEXT: .LBB10_2:
-; GFX1200-FAKE16-NEXT: s_mov_b32 s9, -1
-; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-FAKE16-NEXT: s_and_b32 s9, s9, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_8
-; GFX1200-FAKE16-NEXT: .LBB10_3: ; %frem.compute85
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s8
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s6, s8
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_5
+; GFX1200-FAKE16-NEXT: ; %bb.1: ; %frem.compute85
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v0, s6
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v1, v1, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v0, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s8
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s8, v0
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v6, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -11204,17 +10479,16 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v7, v8, v6
; GFX1200-FAKE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-FAKE16-NEXT: s_denorm_mode 12
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_7
-; GFX1200-FAKE16-NEXT: ; %bb.4: ; %frem.loop_body93.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s6, s8, s6
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_6
+; GFX1200-FAKE16-NEXT: ; %bb.2: ; %frem.loop_body93.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s6, s6, s8
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-FAKE16-NEXT: .LBB10_5: ; %frem.loop_body93
+; GFX1200-FAKE16-NEXT: .LBB10_3: ; %frem.loop_body93
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
@@ -11234,14 +10508,24 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_5
-; GFX1200-FAKE16-NEXT: ; %bb.6: ; %Flow133
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_3
+; GFX1200-FAKE16-NEXT: ; %bb.4:
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, s6
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_7
+; GFX1200-FAKE16-NEXT: .LBB10_5: ; %frem.else86
+; GFX1200-FAKE16-NEXT: s_and_b32 s9, 0x8000, s5
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s6, s8
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v0, s9
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_8
+; GFX1200-FAKE16-NEXT: .LBB10_6:
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1200-FAKE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v2, -10, v4
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v5, v2
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v3, v3
@@ -11263,45 +10547,27 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 s5, s8, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s9, s6, 0x7fff
+; GFX1200-FAKE16-NEXT: s_and_b32 s10, s6, 0x7fff
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s10, s5
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s9, s5
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s10, s10
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_10
-; GFX1200-FAKE16-NEXT: ; %bb.9: ; %frem.else53
-; GFX1200-FAKE16-NEXT: s_and_b32 s11, 0x8000, s8
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, s11
-; GFX1200-FAKE16-NEXT: s_mov_b32 s11, 0
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
-; GFX1200-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_16
-; GFX1200-FAKE16-NEXT: .LBB10_10:
-; GFX1200-FAKE16-NEXT: s_mov_b32 s11, -1
-; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_16
-; GFX1200-FAKE16-NEXT: .LBB10_11: ; %frem.compute52
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s9
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s10
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s9, s10
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_13
+; GFX1200-FAKE16-NEXT: ; %bb.9: ; %frem.compute52
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s10
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v1, s9
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s9
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v2, v2, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v1, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s10
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s9, v4
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s9, v1
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s10, v1
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v7, v6
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -11324,12 +10590,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX1200-FAKE16-NEXT: ; %bb.12: ; %frem.loop_body60.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s10, s9
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_14
+; GFX1200-FAKE16-NEXT: ; %bb.10: ; %frem.loop_body60.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s9, s10
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-FAKE16-NEXT: .LBB10_13: ; %frem.loop_body60
+; GFX1200-FAKE16-NEXT: .LBB10_11: ; %frem.loop_body60
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
@@ -11349,14 +10615,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_13
-; GFX1200-FAKE16-NEXT: ; %bb.14: ; %Flow129
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_11
+; GFX1200-FAKE16-NEXT: ; %bb.12:
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, s9
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_15
+; GFX1200-FAKE16-NEXT: .LBB10_13: ; %frem.else53
+; GFX1200-FAKE16-NEXT: s_and_b32 s11, 0x8000, s8
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s9, s10
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v1, s11
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v1, s8, v1, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_16
+; GFX1200-FAKE16-NEXT: .LBB10_14:
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, v3
; GFX1200-FAKE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v3, -10, v5
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v6, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v4, v4
@@ -11375,46 +10652,27 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, s8
; GFX1200-FAKE16-NEXT: .LBB10_16:
; GFX1200-FAKE16-NEXT: s_and_b32 s8, s7, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s9, s2, 0x7fff
+; GFX1200-FAKE16-NEXT: s_and_b32 s10, s2, 0x7fff
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s10, s8
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s9, s9
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s9, s8
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s10, s10
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_18
-; GFX1200-FAKE16-NEXT: ; %bb.17: ; %frem.else20
-; GFX1200-FAKE16-NEXT: s_and_b32 s11, 0x8000, s7
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s10, s9
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, s11
-; GFX1200-FAKE16-NEXT: s_mov_b32 s11, 0
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
-; GFX1200-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_24
-; GFX1200-FAKE16-NEXT: .LBB10_18:
-; GFX1200-FAKE16-NEXT: s_mov_b32 s11, -1
-; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_24
-; GFX1200-FAKE16-NEXT: .LBB10_19: ; %frem.compute19
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s9
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
+; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s9, s10
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_21
+; GFX1200-FAKE16-NEXT: ; %bb.17: ; %frem.compute19
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s10
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s9
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s10
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s9, v5
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s9, v2
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s10, v2
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v8, v7
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -11437,12 +10695,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX1200-FAKE16-NEXT: ; %bb.20: ; %frem.loop_body27.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s10, s9
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_22
+; GFX1200-FAKE16-NEXT: ; %bb.18: ; %frem.loop_body27.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s9, s9, s10
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-FAKE16-NEXT: .LBB10_21: ; %frem.loop_body27
+; GFX1200-FAKE16-NEXT: .LBB10_19: ; %frem.loop_body27
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
@@ -11462,14 +10720,26 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_21
-; GFX1200-FAKE16-NEXT: ; %bb.22: ; %Flow125
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_19
+; GFX1200-FAKE16-NEXT: ; %bb.20:
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v6, s9
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_23
+; GFX1200-FAKE16-NEXT: .LBB10_21: ; %frem.else20
+; GFX1200-FAKE16-NEXT: s_and_b32 s11, 0x8000, s7
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s9, s10
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v2, s11
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_24
+; GFX1200-FAKE16-NEXT: .LBB10_22:
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-FAKE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v4, -10, v6
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v7, v4
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v5, v5
@@ -11491,45 +10761,27 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_lshr_b32 s9, s2, 16
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_and_b32 s7, s10, 0x7fff
-; GFX1200-FAKE16-NEXT: s_and_b32 s11, s9, 0x7fff
+; GFX1200-FAKE16-NEXT: s_and_b32 s12, s9, 0x7fff
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s12, s7
-; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s11, s11
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s11, s7
+; GFX1200-FAKE16-NEXT: s_cvt_f32_f16 s12, s12
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-FAKE16-NEXT: s_cmp_ngt_f32 s12, s11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_26
-; GFX1200-FAKE16-NEXT: ; %bb.25: ; %frem.else
-; GFX1200-FAKE16-NEXT: s_and_b32 s13, 0x8000, s10
-; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s12, s11
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, s13
-; GFX1200-FAKE16-NEXT: s_mov_b32 s13, 0
-; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
-; GFX1200-FAKE16-NEXT: s_and_b32 s13, s13, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
-; GFX1200-FAKE16-NEXT: s_branch .LBB10_32
-; GFX1200-FAKE16-NEXT: .LBB10_26:
-; GFX1200-FAKE16-NEXT: s_mov_b32 s13, -1
-; GFX1200-FAKE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-FAKE16-NEXT: s_and_b32 s13, s13, exec_lo
-; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_32
-; GFX1200-FAKE16-NEXT: .LBB10_27: ; %frem.compute
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, s11
-; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s12
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
+; GFX1200-FAKE16-NEXT: s_cmp_gt_f32 s11, s12
+; GFX1200-FAKE16-NEXT: s_cbranch_scc0 .LBB10_29
+; GFX1200-FAKE16-NEXT: ; %bb.25: ; %frem.compute
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v4, s12
+; GFX1200-FAKE16-NEXT: v_frexp_mant_f32_e32 v3, s11
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s11
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v4, v4, 1
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v3, 11
-; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1200-FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s12
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s12, v6
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s11, v6
; GFX1200-FAKE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s11, v3
+; GFX1200-FAKE16-NEXT: v_readfirstlane_b32 s12, v3
; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v9, v8
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -11552,12 +10804,12 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
; GFX1200-FAKE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX1200-FAKE16-NEXT: ; %bb.28: ; %frem.loop_body.preheader
-; GFX1200-FAKE16-NEXT: s_sub_co_i32 s11, s12, s11
+; GFX1200-FAKE16-NEXT: s_cbranch_vccnz .LBB10_30
+; GFX1200-FAKE16-NEXT: ; %bb.26: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-FAKE16-NEXT: s_add_co_i32 s11, s11, 11
-; GFX1200-FAKE16-NEXT: .LBB10_29: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT: .LBB10_27: ; %frem.loop_body
; GFX1200-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v8, v5
@@ -11577,14 +10829,25 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_29
-; GFX1200-FAKE16-NEXT: ; %bb.30: ; %Flow
+; GFX1200-FAKE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX1200-FAKE16-NEXT: ; %bb.28:
; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v7, s11
-; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v5, v8
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_31
+; GFX1200-FAKE16-NEXT: .LBB10_29: ; %frem.else
+; GFX1200-FAKE16-NEXT: s_and_b32 s13, 0x8000, s10
+; GFX1200-FAKE16-NEXT: s_cmp_eq_f32 s11, s12
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v3, s13
+; GFX1200-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_cndmask_b32_e32 v3, s10, v3, vcc_lo
+; GFX1200-FAKE16-NEXT: s_branch .LBB10_32
+; GFX1200-FAKE16-NEXT: .LBB10_30:
+; GFX1200-FAKE16-NEXT: v_mov_b32_e32 v8, v5
; GFX1200-FAKE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
-; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v5, v7
+; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT: v_add_nc_u32_e32 v5, -10, v7
+; GFX1200-FAKE16-NEXT: v_ldexp_f32 v5, v8, v5
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1200-FAKE16-NEXT: v_rndne_f32_e32 v6, v6
@@ -11601,7 +10864,7 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-FAKE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, s10
-; GFX1200-FAKE16-NEXT: .LBB10_32: ; %Flow124
+; GFX1200-FAKE16-NEXT: .LBB10_32:
; GFX1200-FAKE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1200-FAKE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-FAKE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -11665,23 +10928,9 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0 offset:32
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
-; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB11_2
-; SI-NEXT: ; %bb.1: ; %frem.else16
-; SI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
-; SI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
-; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc1 .LBB11_3
-; SI-NEXT: s_branch .LBB11_8
-; SI-NEXT: .LBB11_2:
-; SI-NEXT: s_mov_b64 s[2:3], -1
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc0 .LBB11_8
-; SI-NEXT: .LBB11_3: ; %frem.compute15
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v2|
+; SI-NEXT: s_cbranch_vccz .LBB11_4
+; SI-NEXT: ; %bb.1: ; %frem.compute15
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v4, v0
@@ -11716,11 +10965,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v6, v6, v8, v9
; SI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB11_7
-; SI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB11_6
+; SI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB11_5: ; %frem.loop_body23
+; SI-NEXT: .LBB11_3: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v7, v5
; SI-NEXT: v_mul_f32_e32 v5, v7, v6
@@ -11732,12 +10981,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v5, v5, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB11_5
-; SI-NEXT: ; %bb.6: ; %Flow51
-; SI-NEXT: v_mov_b32_e32 v5, v7
+; SI-NEXT: s_cbranch_scc1 .LBB11_3
+; SI-NEXT: s_branch .LBB11_7
+; SI-NEXT: .LBB11_4: ; %frem.else16
+; SI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; SI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
+; SI-NEXT: s_cbranch_vccnz .LBB11_8
+; SI-NEXT: .LBB11_5: ; %frem.else
+; SI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; SI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
+; SI-NEXT: s_branch .LBB11_13
+; SI-NEXT: .LBB11_6:
+; SI-NEXT: v_mov_b32_e32 v7, v5
; SI-NEXT: .LBB11_7: ; %frem.loop_exit24
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v5, v5, s3
+; SI-NEXT: v_ldexp_f32_e64 v5, v7, s3
; SI-NEXT: v_mul_f32_e32 v6, v5, v6
; SI-NEXT: v_rndne_f32_e32 v6, v6
; SI-NEXT: v_fma_f32 v5, -v6, v4, v5
@@ -11747,24 +11008,9 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v4, v4, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; SI-NEXT: .LBB11_8:
-; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
-; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB11_10
-; SI-NEXT: ; %bb.9: ; %frem.else
-; SI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
-; SI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
-; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc1 .LBB11_11
-; SI-NEXT: s_branch .LBB11_16
-; SI-NEXT: .LBB11_10:
-; SI-NEXT: s_mov_b64 s[2:3], -1
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc0 .LBB11_16
-; SI-NEXT: .LBB11_11: ; %frem.compute
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
+; SI-NEXT: s_cbranch_vccz .LBB11_5
+; SI-NEXT: .LBB11_8: ; %frem.compute
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v5, v1
@@ -11799,11 +11045,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v7, v7, v9, v10
; SI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB11_15
-; SI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB11_11
+; SI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB11_13: ; %frem.loop_body
+; SI-NEXT: .LBB11_10: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v8, v6
; SI-NEXT: v_mul_f32_e32 v6, v8, v7
@@ -11815,12 +11061,13 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v6, v6, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB11_13
-; SI-NEXT: ; %bb.14: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v6, v8
-; SI-NEXT: .LBB11_15: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB11_10
+; SI-NEXT: s_branch .LBB11_12
+; SI-NEXT: .LBB11_11:
+; SI-NEXT: v_mov_b32_e32 v8, v6
+; SI-NEXT: .LBB11_12: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v6, v6, s3
+; SI-NEXT: v_ldexp_f32_e64 v6, v8, s3
; SI-NEXT: v_mul_f32_e32 v7, v6, v7
; SI-NEXT: v_rndne_f32_e32 v7, v7
; SI-NEXT: v_fma_f32 v6, -v7, v5, v6
@@ -11830,7 +11077,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v5, v5, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; SI-NEXT: .LBB11_16: ; %Flow50
+; SI-NEXT: .LBB11_13:
; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; SI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -11860,69 +11107,67 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; CI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0 offset:32
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB11_2
-; CI-NEXT: ; %bb.1: ; %frem.else16
-; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
-; CI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB11_3
-; CI-NEXT: s_branch .LBB11_8
-; CI-NEXT: .LBB11_2:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr4
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB11_8
-; CI-NEXT: .LBB11_3: ; %frem.compute15
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v2|
+; CI-NEXT: s_cbranch_vccz .LBB11_4
+; CI-NEXT: ; %bb.1: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; CI-NEXT: v_ldexp_f32_e64 v5, v5, 1
; CI-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v2
-; CI-NEXT: v_ldexp_f32_e64 v7, v4, 12
+; CI-NEXT: v_ldexp_f32_e64 v8, v4, 12
; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v10
; CI-NEXT: v_frexp_exp_i32_f32_e32 v9, v0
; CI-NEXT: v_not_b32_e32 v6, v4
; CI-NEXT: v_add_i32_e32 v6, vcc, v6, v9
-; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
; CI-NEXT: v_rcp_f32_e32 v12, v11
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; CI-NEXT: v_fma_f32 v12, v13, v12, v12
-; CI-NEXT: v_mul_f32_e32 v13, v8, v12
-; CI-NEXT: v_fma_f32 v14, -v11, v13, v8
+; CI-NEXT: v_mul_f32_e32 v13, v7, v12
+; CI-NEXT: v_fma_f32 v14, -v11, v13, v7
; CI-NEXT: v_fma_f32 v13, v14, v12, v13
-; CI-NEXT: v_fma_f32 v8, -v11, v13, v8
+; CI-NEXT: v_fma_f32 v7, -v11, v13, v7
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v8, v8, v12, v13
+; CI-NEXT: v_div_fmas_f32 v7, v7, v12, v13
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v6
-; CI-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB11_7
-; CI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; CI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB11_6
+; CI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; CI-NEXT: v_sub_i32_e32 v6, vcc, v9, v10
; CI-NEXT: v_add_i32_e32 v6, vcc, 12, v6
-; CI-NEXT: .LBB11_5: ; %frem.loop_body23
+; CI-NEXT: .LBB11_3: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v9, v7
-; CI-NEXT: v_mul_f32_e32 v7, v9, v8
-; CI-NEXT: v_rndne_f32_e32 v7, v7
-; CI-NEXT: v_fma_f32 v7, -v7, v5, v9
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; CI-NEXT: v_add_f32_e32 v10, v7, v5
-; CI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; CI-NEXT: v_mov_b32_e32 v9, v8
+; CI-NEXT: v_mul_f32_e32 v8, v9, v7
+; CI-NEXT: v_rndne_f32_e32 v8, v8
+; CI-NEXT: v_fma_f32 v8, -v8, v5, v9
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; CI-NEXT: v_add_f32_e32 v10, v8, v5
+; CI-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; CI-NEXT: v_add_i32_e32 v6, vcc, -12, v6
+; CI-NEXT: v_ldexp_f32_e64 v8, v8, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v6
-; CI-NEXT: v_ldexp_f32_e64 v7, v7, 12
-; CI-NEXT: s_cbranch_vccnz .LBB11_5
-; CI-NEXT: ; %bb.6: ; %Flow51
-; CI-NEXT: v_mov_b32_e32 v7, v9
+; CI-NEXT: s_cbranch_vccnz .LBB11_3
+; CI-NEXT: s_branch .LBB11_7
+; CI-NEXT: .LBB11_4: ; %frem.else16
+; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; CI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
+; CI-NEXT: s_cbranch_vccnz .LBB11_8
+; CI-NEXT: .LBB11_5: ; %frem.else
+; CI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; CI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
+; CI-NEXT: s_branch .LBB11_13
+; CI-NEXT: .LBB11_6:
+; CI-NEXT: v_mov_b32_e32 v9, v8
; CI-NEXT: .LBB11_7: ; %frem.loop_exit24
; CI-NEXT: v_add_i32_e32 v6, vcc, -11, v6
-; CI-NEXT: v_ldexp_f32_e32 v6, v7, v6
-; CI-NEXT: v_mul_f32_e32 v7, v6, v8
+; CI-NEXT: v_ldexp_f32_e32 v6, v9, v6
+; CI-NEXT: v_mul_f32_e32 v7, v6, v7
; CI-NEXT: v_rndne_f32_e32 v7, v7
; CI-NEXT: v_fma_f32 v6, -v7, v5, v6
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -11931,70 +11176,56 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v4, v5, v4
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; CI-NEXT: .LBB11_8:
-; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB11_10
-; CI-NEXT: ; %bb.9: ; %frem.else
-; CI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
-; CI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB11_11
-; CI-NEXT: s_branch .LBB11_16
-; CI-NEXT: .LBB11_10:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr5
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB11_16
-; CI-NEXT: .LBB11_11: ; %frem.compute
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
+; CI-NEXT: s_cbranch_vccz .LBB11_5
+; CI-NEXT: .LBB11_8: ; %frem.compute
; CI-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; CI-NEXT: v_ldexp_f32_e64 v6, v6, 1
; CI-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v11, v3
-; CI-NEXT: v_ldexp_f32_e64 v8, v5, 12
+; CI-NEXT: v_ldexp_f32_e64 v9, v5, 12
; CI-NEXT: v_add_i32_e32 v5, vcc, -1, v11
; CI-NEXT: v_frexp_exp_i32_f32_e32 v10, v1
; CI-NEXT: v_not_b32_e32 v7, v5
; CI-NEXT: v_add_i32_e32 v7, vcc, v7, v10
-; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
; CI-NEXT: v_rcp_f32_e32 v13, v12
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; CI-NEXT: v_fma_f32 v13, v14, v13, v13
-; CI-NEXT: v_mul_f32_e32 v14, v9, v13
-; CI-NEXT: v_fma_f32 v15, -v12, v14, v9
+; CI-NEXT: v_mul_f32_e32 v14, v8, v13
+; CI-NEXT: v_fma_f32 v15, -v12, v14, v8
; CI-NEXT: v_fma_f32 v14, v15, v13, v14
-; CI-NEXT: v_fma_f32 v9, -v12, v14, v9
+; CI-NEXT: v_fma_f32 v8, -v12, v14, v8
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
+; CI-NEXT: v_div_fmas_f32 v8, v8, v13, v14
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v7
-; CI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB11_15
-; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB11_11
+; CI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v7, vcc, v10, v11
; CI-NEXT: v_add_i32_e32 v7, vcc, 12, v7
-; CI-NEXT: .LBB11_13: ; %frem.loop_body
+; CI-NEXT: .LBB11_10: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v10, v8
-; CI-NEXT: v_mul_f32_e32 v8, v10, v9
-; CI-NEXT: v_rndne_f32_e32 v8, v8
-; CI-NEXT: v_fma_f32 v8, -v8, v6, v10
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; CI-NEXT: v_add_f32_e32 v11, v8, v6
-; CI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; CI-NEXT: v_mov_b32_e32 v10, v9
+; CI-NEXT: v_mul_f32_e32 v9, v10, v8
+; CI-NEXT: v_rndne_f32_e32 v9, v9
+; CI-NEXT: v_fma_f32 v9, -v9, v6, v10
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
+; CI-NEXT: v_add_f32_e32 v11, v9, v6
+; CI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; CI-NEXT: v_add_i32_e32 v7, vcc, -12, v7
+; CI-NEXT: v_ldexp_f32_e64 v9, v9, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v7
-; CI-NEXT: v_ldexp_f32_e64 v8, v8, 12
-; CI-NEXT: s_cbranch_vccnz .LBB11_13
-; CI-NEXT: ; %bb.14: ; %Flow
-; CI-NEXT: v_mov_b32_e32 v8, v10
-; CI-NEXT: .LBB11_15: ; %frem.loop_exit
+; CI-NEXT: s_cbranch_vccnz .LBB11_10
+; CI-NEXT: s_branch .LBB11_12
+; CI-NEXT: .LBB11_11:
+; CI-NEXT: v_mov_b32_e32 v10, v9
+; CI-NEXT: .LBB11_12: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v7, vcc, -11, v7
-; CI-NEXT: v_ldexp_f32_e32 v7, v8, v7
-; CI-NEXT: v_mul_f32_e32 v8, v7, v9
+; CI-NEXT: v_ldexp_f32_e32 v7, v10, v7
+; CI-NEXT: v_mul_f32_e32 v8, v7, v8
; CI-NEXT: v_rndne_f32_e32 v8, v8
; CI-NEXT: v_fma_f32 v7, -v8, v6, v7
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
@@ -12003,7 +11234,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v5, v6, v5
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; CI-NEXT: .LBB11_16: ; %Flow50
+; CI-NEXT: .LBB11_13:
; CI-NEXT: s_mov_b32 s4, 0x7f800000
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -12033,69 +11264,67 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB11_2
-; VI-NEXT: ; %bb.1: ; %frem.else16
-; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
-; VI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB11_3
-; VI-NEXT: s_branch .LBB11_8
-; VI-NEXT: .LBB11_2:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr4
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB11_8
-; VI-NEXT: .LBB11_3: ; %frem.compute15
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v2|
+; VI-NEXT: s_cbranch_vccz .LBB11_4
+; VI-NEXT: ; %bb.1: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; VI-NEXT: v_ldexp_f32 v5, v5, 1
; VI-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v2
-; VI-NEXT: v_ldexp_f32 v7, v4, 12
+; VI-NEXT: v_ldexp_f32 v8, v4, 12
; VI-NEXT: v_add_u32_e32 v4, vcc, -1, v10
; VI-NEXT: v_frexp_exp_i32_f32_e32 v9, v0
; VI-NEXT: v_not_b32_e32 v6, v4
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v9
-; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
; VI-NEXT: v_rcp_f32_e32 v12, v11
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; VI-NEXT: v_fma_f32 v12, v13, v12, v12
-; VI-NEXT: v_mul_f32_e32 v13, v8, v12
-; VI-NEXT: v_fma_f32 v14, -v11, v13, v8
+; VI-NEXT: v_mul_f32_e32 v13, v7, v12
+; VI-NEXT: v_fma_f32 v14, -v11, v13, v7
; VI-NEXT: v_fma_f32 v13, v14, v12, v13
-; VI-NEXT: v_fma_f32 v8, -v11, v13, v8
+; VI-NEXT: v_fma_f32 v7, -v11, v13, v7
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v8, v8, v12, v13
+; VI-NEXT: v_div_fmas_f32 v7, v7, v12, v13
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v6
-; VI-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB11_7
-; VI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; VI-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB11_6
+; VI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; VI-NEXT: v_sub_u32_e32 v6, vcc, v9, v10
; VI-NEXT: v_add_u32_e32 v6, vcc, 12, v6
-; VI-NEXT: .LBB11_5: ; %frem.loop_body23
+; VI-NEXT: .LBB11_3: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v9, v7
-; VI-NEXT: v_mul_f32_e32 v7, v9, v8
-; VI-NEXT: v_rndne_f32_e32 v7, v7
-; VI-NEXT: v_fma_f32 v7, -v7, v5, v9
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; VI-NEXT: v_add_f32_e32 v10, v7, v5
-; VI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; VI-NEXT: v_mov_b32_e32 v9, v8
+; VI-NEXT: v_mul_f32_e32 v8, v9, v7
+; VI-NEXT: v_rndne_f32_e32 v8, v8
+; VI-NEXT: v_fma_f32 v8, -v8, v5, v9
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; VI-NEXT: v_add_f32_e32 v10, v8, v5
+; VI-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, -12, v6
+; VI-NEXT: v_ldexp_f32 v8, v8, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v6
-; VI-NEXT: v_ldexp_f32 v7, v7, 12
-; VI-NEXT: s_cbranch_vccnz .LBB11_5
-; VI-NEXT: ; %bb.6: ; %Flow51
-; VI-NEXT: v_mov_b32_e32 v7, v9
+; VI-NEXT: s_cbranch_vccnz .LBB11_3
+; VI-NEXT: s_branch .LBB11_7
+; VI-NEXT: .LBB11_4: ; %frem.else16
+; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; VI-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
+; VI-NEXT: s_cbranch_vccnz .LBB11_8
+; VI-NEXT: .LBB11_5: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; VI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
+; VI-NEXT: s_branch .LBB11_13
+; VI-NEXT: .LBB11_6:
+; VI-NEXT: v_mov_b32_e32 v9, v8
; VI-NEXT: .LBB11_7: ; %frem.loop_exit24
; VI-NEXT: v_add_u32_e32 v6, vcc, -11, v6
-; VI-NEXT: v_ldexp_f32 v6, v7, v6
-; VI-NEXT: v_mul_f32_e32 v7, v6, v8
+; VI-NEXT: v_ldexp_f32 v6, v9, v6
+; VI-NEXT: v_mul_f32_e32 v7, v6, v7
; VI-NEXT: v_rndne_f32_e32 v7, v7
; VI-NEXT: v_fma_f32 v6, -v7, v5, v6
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -12104,70 +11333,56 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v4, v5, v4
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v4, s2, v4, v0
-; VI-NEXT: .LBB11_8:
-; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB11_10
-; VI-NEXT: ; %bb.9: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
-; VI-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB11_11
-; VI-NEXT: s_branch .LBB11_16
-; VI-NEXT: .LBB11_10:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr5
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB11_16
-; VI-NEXT: .LBB11_11: ; %frem.compute
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
+; VI-NEXT: s_cbranch_vccz .LBB11_5
+; VI-NEXT: .LBB11_8: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; VI-NEXT: v_ldexp_f32 v6, v6, 1
; VI-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v11, v3
-; VI-NEXT: v_ldexp_f32 v8, v5, 12
+; VI-NEXT: v_ldexp_f32 v9, v5, 12
; VI-NEXT: v_add_u32_e32 v5, vcc, -1, v11
; VI-NEXT: v_frexp_exp_i32_f32_e32 v10, v1
; VI-NEXT: v_not_b32_e32 v7, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v10
-; VI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
; VI-NEXT: v_rcp_f32_e32 v13, v12
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; VI-NEXT: v_fma_f32 v13, v14, v13, v13
-; VI-NEXT: v_mul_f32_e32 v14, v9, v13
-; VI-NEXT: v_fma_f32 v15, -v12, v14, v9
+; VI-NEXT: v_mul_f32_e32 v14, v8, v13
+; VI-NEXT: v_fma_f32 v15, -v12, v14, v8
; VI-NEXT: v_fma_f32 v14, v15, v13, v14
-; VI-NEXT: v_fma_f32 v9, -v12, v14, v9
+; VI-NEXT: v_fma_f32 v8, -v12, v14, v8
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v9, v9, v13, v14
+; VI-NEXT: v_div_fmas_f32 v8, v8, v13, v14
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v7
-; VI-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB11_15
-; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB11_11
+; VI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v7, vcc, v10, v11
; VI-NEXT: v_add_u32_e32 v7, vcc, 12, v7
-; VI-NEXT: .LBB11_13: ; %frem.loop_body
+; VI-NEXT: .LBB11_10: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v10, v8
-; VI-NEXT: v_mul_f32_e32 v8, v10, v9
-; VI-NEXT: v_rndne_f32_e32 v8, v8
-; VI-NEXT: v_fma_f32 v8, -v8, v6, v10
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; VI-NEXT: v_add_f32_e32 v11, v8, v6
-; VI-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; VI-NEXT: v_mov_b32_e32 v10, v9
+; VI-NEXT: v_mul_f32_e32 v9, v10, v8
+; VI-NEXT: v_rndne_f32_e32 v9, v9
+; VI-NEXT: v_fma_f32 v9, -v9, v6, v10
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
+; VI-NEXT: v_add_f32_e32 v11, v9, v6
+; VI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; VI-NEXT: v_add_u32_e32 v7, vcc, -12, v7
+; VI-NEXT: v_ldexp_f32 v9, v9, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v7
-; VI-NEXT: v_ldexp_f32 v8, v8, 12
-; VI-NEXT: s_cbranch_vccnz .LBB11_13
-; VI-NEXT: ; %bb.14: ; %Flow
-; VI-NEXT: v_mov_b32_e32 v8, v10
-; VI-NEXT: .LBB11_15: ; %frem.loop_exit
+; VI-NEXT: s_cbranch_vccnz .LBB11_10
+; VI-NEXT: s_branch .LBB11_12
+; VI-NEXT: .LBB11_11:
+; VI-NEXT: v_mov_b32_e32 v10, v9
+; VI-NEXT: .LBB11_12: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v7, vcc, -11, v7
-; VI-NEXT: v_ldexp_f32 v7, v8, v7
-; VI-NEXT: v_mul_f32_e32 v8, v7, v9
+; VI-NEXT: v_ldexp_f32 v7, v10, v7
+; VI-NEXT: v_mul_f32_e32 v8, v7, v8
; VI-NEXT: v_rndne_f32_e32 v8, v8
; VI-NEXT: v_fma_f32 v7, -v8, v6, v7
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
@@ -12176,7 +11391,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v5, v6, v5
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; VI-NEXT: .LBB11_16: ; %Flow50
+; VI-NEXT: .LBB11_13:
; VI-NEXT: s_mov_b32 s4, 0x7f800000
; VI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -12201,30 +11416,16 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7] offset:32
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB11_2
-; GFX9-NEXT: ; %bb.1: ; %frem.else16
-; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB11_3
-; GFX9-NEXT: s_branch .LBB11_8
-; GFX9-NEXT: .LBB11_2:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr4
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB11_8
-; GFX9-NEXT: .LBB11_3: ; %frem.compute15
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v2|
+; GFX9-NEXT: s_cbranch_vccz .LBB11_4
+; GFX9-NEXT: ; %bb.1: ; %frem.compute15
; GFX9-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; GFX9-NEXT: v_ldexp_f32 v5, v5, 1
; GFX9-NEXT: v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
-; GFX9-NEXT: v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; GFX9-NEXT: v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v9, v0
-; GFX9-NEXT: v_ldexp_f32 v7, v4, 12
+; GFX9-NEXT: v_ldexp_f32 v8, v4, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v2
; GFX9-NEXT: v_add_u32_e32 v4, -1, v10
; GFX9-NEXT: v_not_b32_e32 v6, v4
@@ -12233,37 +11434,49 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v13, -v11, v12, 1.0
; GFX9-NEXT: v_fma_f32 v12, v13, v12, v12
-; GFX9-NEXT: v_mul_f32_e32 v13, v8, v12
-; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v8
+; GFX9-NEXT: v_mul_f32_e32 v13, v7, v12
+; GFX9-NEXT: v_fma_f32 v14, -v11, v13, v7
; GFX9-NEXT: v_fma_f32 v13, v14, v12, v13
-; GFX9-NEXT: v_fma_f32 v8, -v11, v13, v8
+; GFX9-NEXT: v_fma_f32 v7, -v11, v13, v7
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v8, v8, v12, v13
+; GFX9-NEXT: v_div_fmas_f32 v7, v7, v12, v13
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v6
-; GFX9-NEXT: v_div_fixup_f32 v8, v8, v5, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_7
-; GFX9-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX9-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_6
+; GFX9-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX9-NEXT: v_sub_u32_e32 v6, v9, v10
; GFX9-NEXT: v_add_u32_e32 v6, 12, v6
-; GFX9-NEXT: .LBB11_5: ; %frem.loop_body23
+; GFX9-NEXT: .LBB11_3: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v9, v7
-; GFX9-NEXT: v_mul_f32_e32 v7, v9, v8
-; GFX9-NEXT: v_rndne_f32_e32 v7, v7
-; GFX9-NEXT: v_fma_f32 v7, -v7, v5, v9
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
-; GFX9-NEXT: v_add_f32_e32 v10, v7, v5
+; GFX9-NEXT: v_mov_b32_e32 v9, v8
+; GFX9-NEXT: v_mul_f32_e32 v8, v9, v7
+; GFX9-NEXT: v_rndne_f32_e32 v8, v8
+; GFX9-NEXT: v_fma_f32 v8, -v8, v5, v9
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
+; GFX9-NEXT: v_add_f32_e32 v10, v8, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GFX9-NEXT: v_add_u32_e32 v6, -12, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; GFX9-NEXT: v_ldexp_f32 v8, v8, 12
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v6
-; GFX9-NEXT: v_ldexp_f32 v7, v7, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_5
-; GFX9-NEXT: ; %bb.6: ; %Flow51
-; GFX9-NEXT: v_mov_b32_e32 v7, v9
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_3
+; GFX9-NEXT: s_branch .LBB11_7
+; GFX9-NEXT: .LBB11_4: ; %frem.else16
+; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_8
+; GFX9-NEXT: .LBB11_5: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
+; GFX9-NEXT: s_branch .LBB11_13
+; GFX9-NEXT: .LBB11_6:
+; GFX9-NEXT: v_mov_b32_e32 v9, v8
; GFX9-NEXT: .LBB11_7: ; %frem.loop_exit24
; GFX9-NEXT: v_add_u32_e32 v6, -11, v6
-; GFX9-NEXT: v_ldexp_f32 v6, v7, v6
-; GFX9-NEXT: v_mul_f32_e32 v7, v6, v8
+; GFX9-NEXT: v_ldexp_f32 v6, v9, v6
+; GFX9-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX9-NEXT: v_rndne_f32_e32 v7, v7
; GFX9-NEXT: v_fma_f32 v6, -v7, v5, v6
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6
@@ -12272,31 +11485,16 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v4, v5, v4
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v0
-; GFX9-NEXT: .LBB11_8:
-; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB11_10
-; GFX9-NEXT: ; %bb.9: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v3|
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB11_11
-; GFX9-NEXT: s_branch .LBB11_16
-; GFX9-NEXT: .LBB11_10:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr5
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB11_16
-; GFX9-NEXT: .LBB11_11: ; %frem.compute
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v3|
+; GFX9-NEXT: s_cbranch_vccz .LBB11_5
+; GFX9-NEXT: .LBB11_8: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; GFX9-NEXT: v_ldexp_f32 v6, v6, 1
; GFX9-NEXT: v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
-; GFX9-NEXT: v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; GFX9-NEXT: v_div_scale_f32 v8, vcc, 1.0, v6, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v10, v1
-; GFX9-NEXT: v_ldexp_f32 v8, v5, 12
+; GFX9-NEXT: v_ldexp_f32 v9, v5, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v11, v3
; GFX9-NEXT: v_add_u32_e32 v5, -1, v11
; GFX9-NEXT: v_not_b32_e32 v7, v5
@@ -12305,37 +11503,38 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; GFX9-NEXT: v_fma_f32 v13, v14, v13, v13
-; GFX9-NEXT: v_mul_f32_e32 v14, v9, v13
-; GFX9-NEXT: v_fma_f32 v15, -v12, v14, v9
+; GFX9-NEXT: v_mul_f32_e32 v14, v8, v13
+; GFX9-NEXT: v_fma_f32 v15, -v12, v14, v8
; GFX9-NEXT: v_fma_f32 v14, v15, v13, v14
-; GFX9-NEXT: v_fma_f32 v9, -v12, v14, v9
+; GFX9-NEXT: v_fma_f32 v8, -v12, v14, v8
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v9, v9, v13, v14
+; GFX9-NEXT: v_div_fmas_f32 v8, v8, v13, v14
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v7
-; GFX9-NEXT: v_div_fixup_f32 v9, v9, v6, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_15
-; GFX9-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_11
+; GFX9-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v7, v10, v11
; GFX9-NEXT: v_add_u32_e32 v7, 12, v7
-; GFX9-NEXT: .LBB11_13: ; %frem.loop_body
+; GFX9-NEXT: .LBB11_10: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v10, v8
-; GFX9-NEXT: v_mul_f32_e32 v8, v10, v9
-; GFX9-NEXT: v_rndne_f32_e32 v8, v8
-; GFX9-NEXT: v_fma_f32 v8, -v8, v6, v10
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v8
-; GFX9-NEXT: v_add_f32_e32 v11, v8, v6
+; GFX9-NEXT: v_mov_b32_e32 v10, v9
+; GFX9-NEXT: v_mul_f32_e32 v9, v10, v8
+; GFX9-NEXT: v_rndne_f32_e32 v9, v9
+; GFX9-NEXT: v_fma_f32 v9, -v9, v6, v10
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v9
+; GFX9-NEXT: v_add_f32_e32 v11, v9, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GFX9-NEXT: v_add_u32_e32 v7, -12, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; GFX9-NEXT: v_ldexp_f32 v9, v9, 12
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v7
-; GFX9-NEXT: v_ldexp_f32 v8, v8, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB11_13
-; GFX9-NEXT: ; %bb.14: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v8, v10
-; GFX9-NEXT: .LBB11_15: ; %frem.loop_exit
+; GFX9-NEXT: s_cbranch_vccnz .LBB11_10
+; GFX9-NEXT: s_branch .LBB11_12
+; GFX9-NEXT: .LBB11_11:
+; GFX9-NEXT: v_mov_b32_e32 v10, v9
+; GFX9-NEXT: .LBB11_12: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v7, -11, v7
-; GFX9-NEXT: v_ldexp_f32 v7, v8, v7
-; GFX9-NEXT: v_mul_f32_e32 v8, v7, v9
+; GFX9-NEXT: v_ldexp_f32 v7, v10, v7
+; GFX9-NEXT: v_mul_f32_e32 v8, v7, v8
; GFX9-NEXT: v_rndne_f32_e32 v8, v8
; GFX9-NEXT: v_fma_f32 v7, -v8, v6, v7
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7
@@ -12344,7 +11543,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v5, v6, v5
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v1
-; GFX9-NEXT: .LBB11_16: ; %Flow50
+; GFX9-NEXT: .LBB11_13:
; GFX9-NEXT: s_mov_b32 s4, 0x7f800000
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, 0, v2
; GFX9-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -12370,23 +11569,9 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7] offset:32
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v2|
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB11_2
-; GFX10-NEXT: ; %bb.1: ; %frem.else16
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB11_3
-; GFX10-NEXT: s_branch .LBB11_8
-; GFX10-NEXT: .LBB11_2:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr4
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB11_8
-; GFX10-NEXT: .LBB11_3: ; %frem.compute15
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v2|
+; GFX10-NEXT: s_cbranch_vccz .LBB11_5
+; GFX10-NEXT: ; %bb.1: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; GFX10-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
@@ -12413,10 +11598,10 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v8
; GFX10-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
; GFX10-NEXT: s_cbranch_vccnz .LBB11_7
-; GFX10-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX10-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB11_5: ; %frem.loop_body23
+; GFX10-NEXT: .LBB11_3: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v9, v6
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -12428,13 +11613,26 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v8, v6, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v6, v6, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB11_5
-; GFX10-NEXT: ; %bb.6: ; %Flow51
+; GFX10-NEXT: s_cbranch_scc1 .LBB11_3
+; GFX10-NEXT: ; %bb.4:
; GFX10-NEXT: v_mov_b32_e32 v8, s2
-; GFX10-NEXT: v_mov_b32_e32 v6, v9
-; GFX10-NEXT: .LBB11_7: ; %frem.loop_exit24
-; GFX10-NEXT: v_add_nc_u32_e32 v8, -11, v8
-; GFX10-NEXT: v_ldexp_f32 v6, v6, v8
+; GFX10-NEXT: s_branch .LBB11_8
+; GFX10-NEXT: .LBB11_5: ; %frem.else16
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v3|
+; GFX10-NEXT: s_cbranch_vccnz .LBB11_9
+; GFX10-NEXT: .LBB11_6: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc_lo
+; GFX10-NEXT: s_branch .LBB11_15
+; GFX10-NEXT: .LBB11_7:
+; GFX10-NEXT: v_mov_b32_e32 v9, v6
+; GFX10-NEXT: .LBB11_8: ; %frem.loop_exit24
+; GFX10-NEXT: v_add_nc_u32_e32 v6, -11, v8
+; GFX10-NEXT: v_ldexp_f32 v6, v9, v6
; GFX10-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX10-NEXT: v_rndne_f32_e32 v7, v7
; GFX10-NEXT: v_fma_f32 v6, -v7, v5, v6
@@ -12443,24 +11641,9 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v4, v5, v4
; GFX10-NEXT: v_bfi_b32 v4, 0x7fffffff, v4, v0
-; GFX10-NEXT: .LBB11_8:
-; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v3|
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB11_10
-; GFX10-NEXT: ; %bb.9: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB11_11
-; GFX10-NEXT: s_branch .LBB11_16
-; GFX10-NEXT: .LBB11_10:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr5
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB11_16
-; GFX10-NEXT: .LBB11_11: ; %frem.compute
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v3|
+; GFX10-NEXT: s_cbranch_vccz .LBB11_6
+; GFX10-NEXT: .LBB11_9: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; GFX10-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
@@ -12486,11 +11669,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v8, v8, v11, v12
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v9
; GFX10-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB11_15
-; GFX10-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB11_13
+; GFX10-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB11_13: ; %frem.loop_body
+; GFX10-NEXT: .LBB11_11: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v10, v7
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -12502,13 +11685,15 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v9, v7, v6
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v7, v7, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB11_13
-; GFX10-NEXT: ; %bb.14: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB11_11
+; GFX10-NEXT: ; %bb.12:
; GFX10-NEXT: v_mov_b32_e32 v9, s2
-; GFX10-NEXT: v_mov_b32_e32 v7, v10
-; GFX10-NEXT: .LBB11_15: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v9, -11, v9
-; GFX10-NEXT: v_ldexp_f32 v7, v7, v9
+; GFX10-NEXT: s_branch .LBB11_14
+; GFX10-NEXT: .LBB11_13:
+; GFX10-NEXT: v_mov_b32_e32 v10, v7
+; GFX10-NEXT: .LBB11_14: ; %frem.loop_exit
+; GFX10-NEXT: v_add_nc_u32_e32 v7, -11, v9
+; GFX10-NEXT: v_ldexp_f32 v7, v10, v7
; GFX10-NEXT: v_mul_f32_e32 v8, v7, v8
; GFX10-NEXT: v_rndne_f32_e32 v8, v8
; GFX10-NEXT: v_fma_f32 v7, -v8, v6, v7
@@ -12517,7 +11702,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v5, v6, v5
; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX10-NEXT: .LBB11_16: ; %Flow50
+; GFX10-NEXT: .LBB11_15:
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
@@ -12541,24 +11726,9 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-NEXT: global_load_b64 v[2:3], v2, s[4:5] offset:32
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v2|
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB11_2
-; GFX11-NEXT: ; %bb.1: ; %frem.else16
-; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB11_3
-; GFX11-NEXT: s_branch .LBB11_8
-; GFX11-NEXT: .LBB11_2:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB11_8
-; GFX11-NEXT: .LBB11_3: ; %frem.compute15
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v2|
+; GFX11-NEXT: s_cbranch_vccz .LBB11_5
+; GFX11-NEXT: ; %bb.1: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f32_e64 v5, |v2|
; GFX11-NEXT: v_frexp_mant_f32_e64 v4, |v0|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
@@ -12594,11 +11764,11 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
; GFX11-NEXT: s_cbranch_vccnz .LBB11_7
-; GFX11-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX11-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB11_5: ; %frem.loop_body23
+; GFX11-NEXT: .LBB11_3: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v9, v6
@@ -12614,14 +11784,29 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v6, v6, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB11_5
-; GFX11-NEXT: ; %bb.6: ; %Flow51
+; GFX11-NEXT: s_cbranch_scc1 .LBB11_3
+; GFX11-NEXT: ; %bb.4:
; GFX11-NEXT: v_mov_b32_e32 v8, s2
-; GFX11-NEXT: v_mov_b32_e32 v6, v9
-; GFX11-NEXT: .LBB11_7: ; %frem.loop_exit24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v8, -11, v8
-; GFX11-NEXT: v_ldexp_f32 v6, v6, v8
+; GFX11-NEXT: s_branch .LBB11_8
+; GFX11-NEXT: .LBB11_5: ; %frem.else16
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v0
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc_lo
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v3|
+; GFX11-NEXT: s_cbranch_vccnz .LBB11_9
+; GFX11-NEXT: .LBB11_6: ; %frem.else
+; GFX11-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc_lo
+; GFX11-NEXT: s_branch .LBB11_15
+; GFX11-NEXT: .LBB11_7:
+; GFX11-NEXT: v_mov_b32_e32 v9, v6
+; GFX11-NEXT: .LBB11_8: ; %frem.loop_exit24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v6, -11, v8
+; GFX11-NEXT: v_ldexp_f32 v6, v9, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v7, v6, v7
; GFX11-NEXT: v_rndne_f32_e32 v7, v7
@@ -12634,25 +11819,9 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v4, v5, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v4, 0x7fffffff, v4, v0
-; GFX11-NEXT: .LBB11_8:
-; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v3|
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB11_10
-; GFX11-NEXT: ; %bb.9: ; %frem.else
-; GFX11-NEXT: v_and_b32_e32 v5, 0x80000000, v1
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB11_11
-; GFX11-NEXT: s_branch .LBB11_16
-; GFX11-NEXT: .LBB11_10:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB11_16
-; GFX11-NEXT: .LBB11_11: ; %frem.compute
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v3|
+; GFX11-NEXT: s_cbranch_vccz .LBB11_6
+; GFX11-NEXT: .LBB11_9: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f32_e64 v6, |v3|
; GFX11-NEXT: v_frexp_mant_f32_e64 v5, |v1|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v8, v1
@@ -12687,12 +11856,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB11_15
-; GFX11-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB11_13
+; GFX11-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB11_13: ; %frem.loop_body
+; GFX11-NEXT: .LBB11_11: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v10, v7
@@ -12708,14 +11877,16 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v7, v7, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB11_13
-; GFX11-NEXT: ; %bb.14: ; %Flow
+; GFX11-NEXT: s_cbranch_scc1 .LBB11_11
+; GFX11-NEXT: ; %bb.12:
; GFX11-NEXT: v_mov_b32_e32 v9, s2
-; GFX11-NEXT: v_mov_b32_e32 v7, v10
-; GFX11-NEXT: .LBB11_15: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v9, -11, v9
-; GFX11-NEXT: v_ldexp_f32 v7, v7, v9
+; GFX11-NEXT: s_branch .LBB11_14
+; GFX11-NEXT: .LBB11_13:
+; GFX11-NEXT: v_mov_b32_e32 v10, v7
+; GFX11-NEXT: .LBB11_14: ; %frem.loop_exit
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v7, -11, v9
+; GFX11-NEXT: v_ldexp_f32 v7, v10, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v8, v7, v8
; GFX11-NEXT: v_rndne_f32_e32 v8, v8
@@ -12728,7 +11899,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v5, v6, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX11-NEXT: .LBB11_16: ; %Flow50
+; GFX11-NEXT: .LBB11_15:
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
@@ -12759,26 +11930,9 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_readfirstlane_b32 s2, v2
; GFX1150-NEXT: s_and_b32 s7, s4, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_ngt_f32 s3, s7
-; GFX1150-NEXT: s_cbranch_scc0 .LBB11_2
-; GFX1150-NEXT: ; %bb.1: ; %frem.else16
-; GFX1150-NEXT: s_and_b32 s8, 0x80000000, s6
-; GFX1150-NEXT: s_cmp_eq_f32 s3, s7
-; GFX1150-NEXT: v_mov_b32_e32 v0, s8
-; GFX1150-NEXT: s_mov_b32 s7, 0
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v0, s6, v0, vcc_lo
-; GFX1150-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB11_3
-; GFX1150-NEXT: s_branch .LBB11_8
-; GFX1150-NEXT: .LBB11_2:
-; GFX1150-NEXT: s_mov_b32 s7, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr0
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB11_8
-; GFX1150-NEXT: .LBB11_3: ; %frem.compute15
+; GFX1150-NEXT: s_cmp_gt_f32 s3, s7
+; GFX1150-NEXT: s_cbranch_scc0 .LBB11_5
+; GFX1150-NEXT: ; %bb.1: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s4|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v0, |s6|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
@@ -12812,12 +11966,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1150-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB11_7
-; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB11_6
+; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_sub_i32 s7, s7, s8
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s7, s7, 12
-; GFX1150-NEXT: .LBB11_5: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB11_3: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v5, v2
@@ -12835,14 +11989,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v2, v2, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB11_5
-; GFX1150-NEXT: ; %bb.6: ; %Flow51
+; GFX1150-NEXT: s_cbranch_scc1 .LBB11_3
+; GFX1150-NEXT: ; %bb.4:
; GFX1150-NEXT: v_mov_b32_e32 v4, s7
-; GFX1150-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-NEXT: s_branch .LBB11_7
+; GFX1150-NEXT: .LBB11_5: ; %frem.else16
+; GFX1150-NEXT: s_and_b32 s8, 0x80000000, s6
+; GFX1150-NEXT: s_cmp_eq_f32 s3, s7
+; GFX1150-NEXT: v_mov_b32_e32 v0, s8
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v0, s6, v0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB11_8
+; GFX1150-NEXT: .LBB11_6:
+; GFX1150-NEXT: v_mov_b32_e32 v5, v2
; GFX1150-NEXT: .LBB11_7: ; %frem.loop_exit24
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v4, -11, v4
-; GFX1150-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v2, -11, v4
+; GFX1150-NEXT: v_ldexp_f32 v2, v5, v2
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-NEXT: v_rndne_f32_e32 v3, v3
@@ -12860,26 +12024,9 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_and_b32 s6, s5, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s7, s2, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_ngt_f32 s6, s7
-; GFX1150-NEXT: s_cbranch_scc0 .LBB11_10
-; GFX1150-NEXT: ; %bb.9: ; %frem.else
-; GFX1150-NEXT: s_and_b32 s8, 0x80000000, s5
-; GFX1150-NEXT: s_cmp_eq_f32 s6, s7
-; GFX1150-NEXT: v_mov_b32_e32 v1, s8
-; GFX1150-NEXT: s_mov_b32 s7, 0
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
-; GFX1150-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB11_11
-; GFX1150-NEXT: s_branch .LBB11_16
-; GFX1150-NEXT: .LBB11_10:
-; GFX1150-NEXT: s_mov_b32 s7, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr1
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB11_16
-; GFX1150-NEXT: .LBB11_11: ; %frem.compute
+; GFX1150-NEXT: s_cmp_gt_f32 s6, s7
+; GFX1150-NEXT: s_cbranch_scc0 .LBB11_13
+; GFX1150-NEXT: ; %bb.9: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f32_e64 v2, |s2|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s5|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v4, s5
@@ -12913,12 +12060,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1150-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB11_15
-; GFX1150-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB11_14
+; GFX1150-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s7, s7, s8
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s7, s7, 12
-; GFX1150-NEXT: .LBB11_13: ; %frem.loop_body
+; GFX1150-NEXT: .LBB11_11: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v6, v3
@@ -12936,14 +12083,24 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB11_13
-; GFX1150-NEXT: ; %bb.14: ; %Flow
+; GFX1150-NEXT: s_cbranch_scc1 .LBB11_11
+; GFX1150-NEXT: ; %bb.12:
; GFX1150-NEXT: v_mov_b32_e32 v5, s7
-; GFX1150-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-NEXT: s_branch .LBB11_15
+; GFX1150-NEXT: .LBB11_13: ; %frem.else
+; GFX1150-NEXT: s_and_b32 s8, 0x80000000, s5
+; GFX1150-NEXT: s_cmp_eq_f32 s6, s7
+; GFX1150-NEXT: v_mov_b32_e32 v1, s8
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
+; GFX1150-NEXT: s_branch .LBB11_16
+; GFX1150-NEXT: .LBB11_14:
+; GFX1150-NEXT: v_mov_b32_e32 v6, v3
; GFX1150-NEXT: .LBB11_15: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v5, -11, v5
-; GFX1150-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v3, -11, v5
+; GFX1150-NEXT: v_ldexp_f32 v3, v6, v3
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-NEXT: v_rndne_f32_e32 v4, v4
@@ -12957,7 +12114,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1150-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s5
-; GFX1150-NEXT: .LBB11_16: ; %Flow50
+; GFX1150-NEXT: .LBB11_16:
; GFX1150-NEXT: s_cmp_lg_f32 s4, 0
; GFX1150-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-NEXT: s_cselect_b32 s4, -1, 0
@@ -12994,26 +12151,9 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_readfirstlane_b32 s2, v2
; GFX1200-NEXT: s_and_b32 s7, s4, 0x7fffffff
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_cmp_ngt_f32 s3, s7
-; GFX1200-NEXT: s_cbranch_scc0 .LBB11_3
-; GFX1200-NEXT: ; %bb.1: ; %frem.else16
-; GFX1200-NEXT: s_and_b32 s8, 0x80000000, s6
-; GFX1200-NEXT: s_cmp_eq_f32 s3, s7
-; GFX1200-NEXT: s_cselect_b32 s7, s8, s6
-; GFX1200-NEXT: s_mov_b32 s8, 0
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB11_4
-; GFX1200-NEXT: .LBB11_2:
-; GFX1200-NEXT: v_mov_b32_e32 v0, s7
-; GFX1200-NEXT: s_branch .LBB11_9
-; GFX1200-NEXT: .LBB11_3:
-; GFX1200-NEXT: s_mov_b32 s8, -1
-; GFX1200-NEXT: ; implicit-def: $sgpr7
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB11_2
-; GFX1200-NEXT: .LBB11_4: ; %frem.compute15
+; GFX1200-NEXT: s_cmp_gt_f32 s3, s7
+; GFX1200-NEXT: s_cbranch_scc0 .LBB11_5
+; GFX1200-NEXT: ; %bb.1: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s4|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v0, |s6|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
@@ -13047,12 +12187,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1200-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB11_8
-; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB11_6
+; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_sub_co_i32 s7, s7, s8
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s7, s7, 12
-; GFX1200-NEXT: .LBB11_6: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB11_3: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v2
@@ -13072,14 +12212,23 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v2, v2, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB11_6
-; GFX1200-NEXT: ; %bb.7: ; %Flow51
+; GFX1200-NEXT: s_cbranch_scc1 .LBB11_3
+; GFX1200-NEXT: ; %bb.4:
; GFX1200-NEXT: v_mov_b32_e32 v4, s7
-; GFX1200-NEXT: v_mov_b32_e32 v2, v5
-; GFX1200-NEXT: .LBB11_8: ; %frem.loop_exit24
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v4, -11, v4
-; GFX1200-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1200-NEXT: s_branch .LBB11_7
+; GFX1200-NEXT: .LBB11_5: ; %frem.else16
+; GFX1200-NEXT: s_and_b32 s8, 0x80000000, s6
+; GFX1200-NEXT: s_cmp_eq_f32 s3, s7
+; GFX1200-NEXT: s_cselect_b32 s6, s8, s6
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: v_mov_b32_e32 v0, s6
+; GFX1200-NEXT: s_branch .LBB11_8
+; GFX1200-NEXT: .LBB11_6:
+; GFX1200-NEXT: v_mov_b32_e32 v5, v2
+; GFX1200-NEXT: .LBB11_7: ; %frem.loop_exit24
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v2, -11, v4
+; GFX1200-NEXT: v_ldexp_f32 v2, v5, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-NEXT: v_rndne_f32_e32 v3, v3
@@ -13094,31 +12243,13 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1200-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s6
-; GFX1200-NEXT: .LBB11_9:
+; GFX1200-NEXT: .LBB11_8:
; GFX1200-NEXT: s_and_b32 s6, s5, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s7, s2, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cmp_ngt_f32 s6, s7
-; GFX1200-NEXT: s_cbranch_scc0 .LBB11_12
-; GFX1200-NEXT: ; %bb.10: ; %frem.else
-; GFX1200-NEXT: s_and_b32 s8, 0x80000000, s5
-; GFX1200-NEXT: s_cmp_eq_f32 s6, s7
-; GFX1200-NEXT: s_cselect_b32 s7, s8, s5
-; GFX1200-NEXT: s_mov_b32 s8, 0
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB11_13
-; GFX1200-NEXT: .LBB11_11:
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v1, s7
-; GFX1200-NEXT: s_branch .LBB11_18
-; GFX1200-NEXT: .LBB11_12:
-; GFX1200-NEXT: s_mov_b32 s8, -1
-; GFX1200-NEXT: ; implicit-def: $sgpr7
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB11_11
-; GFX1200-NEXT: .LBB11_13: ; %frem.compute
+; GFX1200-NEXT: s_cmp_gt_f32 s6, s7
+; GFX1200-NEXT: s_cbranch_scc0 .LBB11_13
+; GFX1200-NEXT: ; %bb.9: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f32_e64 v2, |s2|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s5|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v4, s5
@@ -13153,13 +12284,12 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1200-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB11_17
-; GFX1200-NEXT: ; %bb.14: ; %frem.loop_body.preheader
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_cbranch_vccnz .LBB11_14
+; GFX1200-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s7, s7, s8
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s7, s7, 12
-; GFX1200-NEXT: .LBB11_15: ; %frem.loop_body
+; GFX1200-NEXT: .LBB11_11: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v6, v3
@@ -13179,14 +12309,23 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB11_15
-; GFX1200-NEXT: ; %bb.16: ; %Flow
+; GFX1200-NEXT: s_cbranch_scc1 .LBB11_11
+; GFX1200-NEXT: ; %bb.12:
; GFX1200-NEXT: v_mov_b32_e32 v5, s7
-; GFX1200-NEXT: v_mov_b32_e32 v3, v6
-; GFX1200-NEXT: .LBB11_17: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v5, -11, v5
-; GFX1200-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1200-NEXT: s_branch .LBB11_15
+; GFX1200-NEXT: .LBB11_13: ; %frem.else
+; GFX1200-NEXT: s_and_b32 s8, 0x80000000, s5
+; GFX1200-NEXT: s_cmp_eq_f32 s6, s7
+; GFX1200-NEXT: s_cselect_b32 s5, s8, s5
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v1, s5
+; GFX1200-NEXT: s_branch .LBB11_16
+; GFX1200-NEXT: .LBB11_14:
+; GFX1200-NEXT: v_mov_b32_e32 v6, v3
+; GFX1200-NEXT: .LBB11_15: ; %frem.loop_exit
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v3, -11, v5
+; GFX1200-NEXT: v_ldexp_f32 v3, v6, v3
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-NEXT: v_rndne_f32_e32 v4, v4
@@ -13201,7 +12340,7 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1200-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s5
-; GFX1200-NEXT: .LBB11_18: ; %Flow50
+; GFX1200-NEXT: .LBB11_16:
; GFX1200-NEXT: s_cmp_lg_f32 s4, 0
; GFX1200-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-NEXT: s_cselect_b32 s4, -1, 0
@@ -13245,23 +12384,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:64
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
-; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB12_2
-; SI-NEXT: ; %bb.1: ; %frem.else78
-; SI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
-; SI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
-; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc1 .LBB12_3
-; SI-NEXT: s_branch .LBB12_8
-; SI-NEXT: .LBB12_2:
-; SI-NEXT: s_mov_b64 s[2:3], -1
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc0 .LBB12_8
-; SI-NEXT: .LBB12_3: ; %frem.compute77
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v4|
+; SI-NEXT: s_cbranch_vccz .LBB12_4
+; SI-NEXT: ; %bb.1: ; %frem.compute77
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v8, v0
@@ -13296,11 +12421,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v10, v10, v12, v13
; SI-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_7
-; SI-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_8
+; SI-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_5: ; %frem.loop_body85
+; SI-NEXT: .LBB12_3: ; %frem.loop_body85
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v11, v9
; SI-NEXT: v_mul_f32_e32 v9, v11, v10
@@ -13312,12 +12437,36 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v9, v9, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_5
-; SI-NEXT: ; %bb.6: ; %Flow125
-; SI-NEXT: v_mov_b32_e32 v9, v11
-; SI-NEXT: .LBB12_7: ; %frem.loop_exit86
+; SI-NEXT: s_cbranch_scc1 .LBB12_3
+; SI-NEXT: s_branch .LBB12_9
+; SI-NEXT: .LBB12_4: ; %frem.else78
+; SI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; SI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
+; SI-NEXT: s_cbranch_vccnz .LBB12_10
+; SI-NEXT: .LBB12_5: ; %frem.else47
+; SI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; SI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
+; SI-NEXT: s_cbranch_vccnz .LBB12_15
+; SI-NEXT: .LBB12_6: ; %frem.else16
+; SI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; SI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
+; SI-NEXT: s_cbranch_vccnz .LBB12_20
+; SI-NEXT: .LBB12_7: ; %frem.else
+; SI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; SI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
+; SI-NEXT: s_branch .LBB12_25
+; SI-NEXT: .LBB12_8:
+; SI-NEXT: v_mov_b32_e32 v11, v9
+; SI-NEXT: .LBB12_9: ; %frem.loop_exit86
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v9, v9, s3
+; SI-NEXT: v_ldexp_f32_e64 v9, v11, s3
; SI-NEXT: v_mul_f32_e32 v10, v9, v10
; SI-NEXT: v_rndne_f32_e32 v10, v10
; SI-NEXT: v_fma_f32 v9, -v10, v8, v9
@@ -13327,24 +12476,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v8, v8, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v8, s2, v8, v0
-; SI-NEXT: .LBB12_8:
-; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
-; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB12_10
-; SI-NEXT: ; %bb.9: ; %frem.else47
-; SI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
-; SI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
-; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc1 .LBB12_11
-; SI-NEXT: s_branch .LBB12_16
-; SI-NEXT: .LBB12_10:
-; SI-NEXT: s_mov_b64 s[2:3], -1
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc0 .LBB12_16
-; SI-NEXT: .LBB12_11: ; %frem.compute46
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
+; SI-NEXT: s_cbranch_vccz .LBB12_5
+; SI-NEXT: .LBB12_10: ; %frem.compute46
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v9, v1
@@ -13379,11 +12513,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v11, v11, v13, v14
; SI-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_15
-; SI-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_13
+; SI-NEXT: ; %bb.11: ; %frem.loop_body54.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_13: ; %frem.loop_body54
+; SI-NEXT: .LBB12_12: ; %frem.loop_body54
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v12, v10
; SI-NEXT: v_mul_f32_e32 v10, v12, v11
@@ -13395,12 +12529,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v10, v10, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_13
-; SI-NEXT: ; %bb.14: ; %Flow121
-; SI-NEXT: v_mov_b32_e32 v10, v12
-; SI-NEXT: .LBB12_15: ; %frem.loop_exit55
+; SI-NEXT: s_cbranch_scc1 .LBB12_12
+; SI-NEXT: s_branch .LBB12_14
+; SI-NEXT: .LBB12_13:
+; SI-NEXT: v_mov_b32_e32 v12, v10
+; SI-NEXT: .LBB12_14: ; %frem.loop_exit55
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v10, v10, s3
+; SI-NEXT: v_ldexp_f32_e64 v10, v12, s3
; SI-NEXT: v_mul_f32_e32 v11, v10, v11
; SI-NEXT: v_rndne_f32_e32 v11, v11
; SI-NEXT: v_fma_f32 v10, -v11, v9, v10
@@ -13410,24 +12545,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v9, v9, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; SI-NEXT: .LBB12_16:
-; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
-; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB12_18
-; SI-NEXT: ; %bb.17: ; %frem.else16
-; SI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
-; SI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
-; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc1 .LBB12_19
-; SI-NEXT: s_branch .LBB12_24
-; SI-NEXT: .LBB12_18:
-; SI-NEXT: s_mov_b64 s[2:3], -1
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc0 .LBB12_24
-; SI-NEXT: .LBB12_19: ; %frem.compute15
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
+; SI-NEXT: s_cbranch_vccz .LBB12_6
+; SI-NEXT: .LBB12_15: ; %frem.compute15
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v2|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v10, v2
@@ -13462,11 +12582,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v12, v12, v14, v15
; SI-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_23
-; SI-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_18
+; SI-NEXT: ; %bb.16: ; %frem.loop_body23.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_21: ; %frem.loop_body23
+; SI-NEXT: .LBB12_17: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v13, v11
; SI-NEXT: v_mul_f32_e32 v11, v13, v12
@@ -13478,12 +12598,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v11, v11, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_21
-; SI-NEXT: ; %bb.22: ; %Flow117
-; SI-NEXT: v_mov_b32_e32 v11, v13
-; SI-NEXT: .LBB12_23: ; %frem.loop_exit24
+; SI-NEXT: s_cbranch_scc1 .LBB12_17
+; SI-NEXT: s_branch .LBB12_19
+; SI-NEXT: .LBB12_18:
+; SI-NEXT: v_mov_b32_e32 v13, v11
+; SI-NEXT: .LBB12_19: ; %frem.loop_exit24
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v11, v11, s3
+; SI-NEXT: v_ldexp_f32_e64 v11, v13, s3
; SI-NEXT: v_mul_f32_e32 v12, v11, v12
; SI-NEXT: v_rndne_f32_e32 v12, v12
; SI-NEXT: v_fma_f32 v11, -v12, v10, v11
@@ -13493,24 +12614,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v10, v10, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v10, s2, v10, v2
-; SI-NEXT: .LBB12_24:
-; SI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
-; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; SI-NEXT: s_cbranch_vccz .LBB12_26
-; SI-NEXT: ; %bb.25: ; %frem.else
-; SI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; SI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
-; SI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
-; SI-NEXT: s_mov_b64 s[2:3], 0
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc1 .LBB12_27
-; SI-NEXT: s_branch .LBB12_32
-; SI-NEXT: .LBB12_26:
-; SI-NEXT: s_mov_b64 s[2:3], -1
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; SI-NEXT: s_cbranch_scc0 .LBB12_32
-; SI-NEXT: .LBB12_27: ; %frem.compute
+; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
+; SI-NEXT: s_cbranch_vccz .LBB12_7
+; SI-NEXT: .LBB12_20: ; %frem.compute
; SI-NEXT: s_mov_b32 s6, 0x7f800000
; SI-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, s6
; SI-NEXT: v_frexp_exp_i32_f32_e32 v11, v3
@@ -13545,11 +12651,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f32 v13, v13, v15, v16
; SI-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
; SI-NEXT: s_cmp_lt_i32 s3, 13
-; SI-NEXT: s_cbranch_scc1 .LBB12_31
-; SI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB12_23
+; SI-NEXT: ; %bb.21: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s3, s4, s5
; SI-NEXT: s_add_i32 s3, s3, 12
-; SI-NEXT: .LBB12_29: ; %frem.loop_body
+; SI-NEXT: .LBB12_22: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: v_mov_b32_e32 v14, v12
; SI-NEXT: v_mul_f32_e32 v12, v14, v13
@@ -13561,12 +12667,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_add_i32 s3, s3, -12
; SI-NEXT: v_ldexp_f32_e64 v12, v12, 12
; SI-NEXT: s_cmp_gt_i32 s3, 12
-; SI-NEXT: s_cbranch_scc1 .LBB12_29
-; SI-NEXT: ; %bb.30: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v12, v14
-; SI-NEXT: .LBB12_31: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB12_22
+; SI-NEXT: s_branch .LBB12_24
+; SI-NEXT: .LBB12_23:
+; SI-NEXT: v_mov_b32_e32 v14, v12
+; SI-NEXT: .LBB12_24: ; %frem.loop_exit
; SI-NEXT: s_add_i32 s3, s3, -11
-; SI-NEXT: v_ldexp_f32_e64 v12, v12, s3
+; SI-NEXT: v_ldexp_f32_e64 v12, v14, s3
; SI-NEXT: v_mul_f32_e32 v13, v12, v13
; SI-NEXT: v_rndne_f32_e32 v13, v13
; SI-NEXT: v_fma_f32 v12, -v13, v11, v12
@@ -13576,7 +12683,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f32_e64 v11, v11, s2
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; SI-NEXT: .LBB12_32: ; %Flow116
+; SI-NEXT: .LBB12_25:
; SI-NEXT: s_mov_b32 s4, 0x7f800000
; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; SI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -13614,141 +12721,137 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; CI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:64
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB12_2
-; CI-NEXT: ; %bb.1: ; %frem.else78
-; CI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
-; CI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB12_3
-; CI-NEXT: s_branch .LBB12_8
-; CI-NEXT: .LBB12_2:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr8
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB12_8
-; CI-NEXT: .LBB12_3: ; %frem.compute77
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v4|
+; CI-NEXT: s_cbranch_vccz .LBB12_4
+; CI-NEXT: ; %bb.1: ; %frem.compute77
; CI-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; CI-NEXT: v_ldexp_f32_e64 v9, v9, 1
; CI-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v14, v4
-; CI-NEXT: v_ldexp_f32_e64 v11, v8, 12
+; CI-NEXT: v_ldexp_f32_e64 v12, v8, 12
; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v14
; CI-NEXT: v_frexp_exp_i32_f32_e32 v13, v0
; CI-NEXT: v_not_b32_e32 v10, v8
; CI-NEXT: v_add_i32_e32 v10, vcc, v10, v13
-; CI-NEXT: v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
+; CI-NEXT: v_div_scale_f32 v11, vcc, 1.0, v9, 1.0
; CI-NEXT: v_rcp_f32_e32 v16, v15
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v17, -v15, v16, 1.0
; CI-NEXT: v_fma_f32 v16, v17, v16, v16
-; CI-NEXT: v_mul_f32_e32 v17, v12, v16
-; CI-NEXT: v_fma_f32 v18, -v15, v17, v12
+; CI-NEXT: v_mul_f32_e32 v17, v11, v16
+; CI-NEXT: v_fma_f32 v18, -v15, v17, v11
; CI-NEXT: v_fma_f32 v17, v18, v16, v17
-; CI-NEXT: v_fma_f32 v12, -v15, v17, v12
+; CI-NEXT: v_fma_f32 v11, -v15, v17, v11
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v12, v12, v16, v17
+; CI-NEXT: v_div_fmas_f32 v11, v11, v16, v17
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v10
-; CI-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_7
-; CI-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
+; CI-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB12_8
+; CI-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
; CI-NEXT: v_sub_i32_e32 v10, vcc, v13, v14
; CI-NEXT: v_add_i32_e32 v10, vcc, 12, v10
-; CI-NEXT: .LBB12_5: ; %frem.loop_body85
+; CI-NEXT: .LBB12_3: ; %frem.loop_body85
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v13, v11
-; CI-NEXT: v_mul_f32_e32 v11, v13, v12
-; CI-NEXT: v_rndne_f32_e32 v11, v11
-; CI-NEXT: v_fma_f32 v11, -v11, v9, v13
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
-; CI-NEXT: v_add_f32_e32 v14, v11, v9
-; CI-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
+; CI-NEXT: v_mov_b32_e32 v13, v12
+; CI-NEXT: v_mul_f32_e32 v12, v13, v11
+; CI-NEXT: v_rndne_f32_e32 v12, v12
+; CI-NEXT: v_fma_f32 v12, -v12, v9, v13
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
+; CI-NEXT: v_add_f32_e32 v14, v12, v9
+; CI-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc
; CI-NEXT: v_add_i32_e32 v10, vcc, -12, v10
+; CI-NEXT: v_ldexp_f32_e64 v12, v12, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v10
-; CI-NEXT: v_ldexp_f32_e64 v11, v11, 12
-; CI-NEXT: s_cbranch_vccnz .LBB12_5
-; CI-NEXT: ; %bb.6: ; %Flow125
-; CI-NEXT: v_mov_b32_e32 v11, v13
-; CI-NEXT: .LBB12_7: ; %frem.loop_exit86
-; CI-NEXT: v_add_i32_e32 v10, vcc, -11, v10
-; CI-NEXT: v_ldexp_f32_e32 v10, v11, v10
-; CI-NEXT: v_mul_f32_e32 v11, v10, v12
-; CI-NEXT: v_rndne_f32_e32 v11, v11
-; CI-NEXT: v_fma_f32 v10, -v11, v9, v10
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
-; CI-NEXT: v_add_f32_e32 v9, v10, v9
+; CI-NEXT: s_cbranch_vccnz .LBB12_3
+; CI-NEXT: s_branch .LBB12_9
+; CI-NEXT: .LBB12_4: ; %frem.else78
+; CI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; CI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
+; CI-NEXT: s_cbranch_vccnz .LBB12_10
+; CI-NEXT: .LBB12_5: ; %frem.else47
+; CI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; CI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
+; CI-NEXT: s_cbranch_vccnz .LBB12_15
+; CI-NEXT: .LBB12_6: ; %frem.else16
+; CI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; CI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
+; CI-NEXT: s_cbranch_vccnz .LBB12_20
+; CI-NEXT: .LBB12_7: ; %frem.else
+; CI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; CI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
+; CI-NEXT: s_branch .LBB12_25
+; CI-NEXT: .LBB12_8:
+; CI-NEXT: v_mov_b32_e32 v13, v12
+; CI-NEXT: .LBB12_9: ; %frem.loop_exit86
+; CI-NEXT: v_add_i32_e32 v10, vcc, -11, v10
+; CI-NEXT: v_ldexp_f32_e32 v10, v13, v10
+; CI-NEXT: v_mul_f32_e32 v11, v10, v11
+; CI-NEXT: v_rndne_f32_e32 v11, v11
+; CI-NEXT: v_fma_f32 v10, -v11, v9, v10
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
+; CI-NEXT: v_add_f32_e32 v9, v10, v9
; CI-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc
; CI-NEXT: v_ldexp_f32_e32 v8, v9, v8
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v8, s2, v8, v0
-; CI-NEXT: .LBB12_8:
-; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB12_10
-; CI-NEXT: ; %bb.9: ; %frem.else47
-; CI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
-; CI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB12_11
-; CI-NEXT: s_branch .LBB12_16
-; CI-NEXT: .LBB12_10:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr9
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB12_16
-; CI-NEXT: .LBB12_11: ; %frem.compute46
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
+; CI-NEXT: s_cbranch_vccz .LBB12_5
+; CI-NEXT: .LBB12_10: ; %frem.compute46
; CI-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; CI-NEXT: v_ldexp_f32_e64 v10, v10, 1
; CI-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v9, |v1|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v15, v5
-; CI-NEXT: v_ldexp_f32_e64 v12, v9, 12
+; CI-NEXT: v_ldexp_f32_e64 v13, v9, 12
; CI-NEXT: v_add_i32_e32 v9, vcc, -1, v15
; CI-NEXT: v_frexp_exp_i32_f32_e32 v14, v1
; CI-NEXT: v_not_b32_e32 v11, v9
; CI-NEXT: v_add_i32_e32 v11, vcc, v11, v14
-; CI-NEXT: v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
+; CI-NEXT: v_div_scale_f32 v12, vcc, 1.0, v10, 1.0
; CI-NEXT: v_rcp_f32_e32 v17, v16
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; CI-NEXT: v_fma_f32 v17, v18, v17, v17
-; CI-NEXT: v_mul_f32_e32 v18, v13, v17
-; CI-NEXT: v_fma_f32 v19, -v16, v18, v13
+; CI-NEXT: v_mul_f32_e32 v18, v12, v17
+; CI-NEXT: v_fma_f32 v19, -v16, v18, v12
; CI-NEXT: v_fma_f32 v18, v19, v17, v18
-; CI-NEXT: v_fma_f32 v13, -v16, v18, v13
+; CI-NEXT: v_fma_f32 v12, -v16, v18, v12
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v13, v13, v17, v18
+; CI-NEXT: v_div_fmas_f32 v12, v12, v17, v18
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v11
-; CI-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_15
-; CI-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
+; CI-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB12_13
+; CI-NEXT: ; %bb.11: ; %frem.loop_body54.preheader
; CI-NEXT: v_sub_i32_e32 v11, vcc, v14, v15
; CI-NEXT: v_add_i32_e32 v11, vcc, 12, v11
-; CI-NEXT: .LBB12_13: ; %frem.loop_body54
+; CI-NEXT: .LBB12_12: ; %frem.loop_body54
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v14, v12
-; CI-NEXT: v_mul_f32_e32 v12, v14, v13
-; CI-NEXT: v_rndne_f32_e32 v12, v12
-; CI-NEXT: v_fma_f32 v12, -v12, v10, v14
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
-; CI-NEXT: v_add_f32_e32 v15, v12, v10
-; CI-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
+; CI-NEXT: v_mov_b32_e32 v14, v13
+; CI-NEXT: v_mul_f32_e32 v13, v14, v12
+; CI-NEXT: v_rndne_f32_e32 v13, v13
+; CI-NEXT: v_fma_f32 v13, -v13, v10, v14
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
+; CI-NEXT: v_add_f32_e32 v15, v13, v10
+; CI-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
; CI-NEXT: v_add_i32_e32 v11, vcc, -12, v11
+; CI-NEXT: v_ldexp_f32_e64 v13, v13, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v11
-; CI-NEXT: v_ldexp_f32_e64 v12, v12, 12
-; CI-NEXT: s_cbranch_vccnz .LBB12_13
-; CI-NEXT: ; %bb.14: ; %Flow121
-; CI-NEXT: v_mov_b32_e32 v12, v14
-; CI-NEXT: .LBB12_15: ; %frem.loop_exit55
+; CI-NEXT: s_cbranch_vccnz .LBB12_12
+; CI-NEXT: s_branch .LBB12_14
+; CI-NEXT: .LBB12_13:
+; CI-NEXT: v_mov_b32_e32 v14, v13
+; CI-NEXT: .LBB12_14: ; %frem.loop_exit55
; CI-NEXT: v_add_i32_e32 v11, vcc, -11, v11
-; CI-NEXT: v_ldexp_f32_e32 v11, v12, v11
-; CI-NEXT: v_mul_f32_e32 v12, v11, v13
+; CI-NEXT: v_ldexp_f32_e32 v11, v14, v11
+; CI-NEXT: v_mul_f32_e32 v12, v11, v12
; CI-NEXT: v_rndne_f32_e32 v12, v12
; CI-NEXT: v_fma_f32 v11, -v12, v10, v11
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
@@ -13757,70 +12860,56 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v9, v10, v9
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; CI-NEXT: .LBB12_16:
-; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB12_18
-; CI-NEXT: ; %bb.17: ; %frem.else16
-; CI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
-; CI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB12_19
-; CI-NEXT: s_branch .LBB12_24
-; CI-NEXT: .LBB12_18:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr10
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB12_24
-; CI-NEXT: .LBB12_19: ; %frem.compute15
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
+; CI-NEXT: s_cbranch_vccz .LBB12_6
+; CI-NEXT: .LBB12_15: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; CI-NEXT: v_ldexp_f32_e64 v11, v11, 1
; CI-NEXT: v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v16, v6
-; CI-NEXT: v_ldexp_f32_e64 v13, v10, 12
+; CI-NEXT: v_ldexp_f32_e64 v14, v10, 12
; CI-NEXT: v_add_i32_e32 v10, vcc, -1, v16
; CI-NEXT: v_frexp_exp_i32_f32_e32 v15, v2
; CI-NEXT: v_not_b32_e32 v12, v10
; CI-NEXT: v_add_i32_e32 v12, vcc, v12, v15
-; CI-NEXT: v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
+; CI-NEXT: v_div_scale_f32 v13, vcc, 1.0, v11, 1.0
; CI-NEXT: v_rcp_f32_e32 v18, v17
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v19, -v17, v18, 1.0
; CI-NEXT: v_fma_f32 v18, v19, v18, v18
-; CI-NEXT: v_mul_f32_e32 v19, v14, v18
-; CI-NEXT: v_fma_f32 v20, -v17, v19, v14
+; CI-NEXT: v_mul_f32_e32 v19, v13, v18
+; CI-NEXT: v_fma_f32 v20, -v17, v19, v13
; CI-NEXT: v_fma_f32 v19, v20, v18, v19
-; CI-NEXT: v_fma_f32 v14, -v17, v19, v14
+; CI-NEXT: v_fma_f32 v13, -v17, v19, v13
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v14, v14, v18, v19
+; CI-NEXT: v_div_fmas_f32 v13, v13, v18, v19
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v12
-; CI-NEXT: v_div_fixup_f32 v14, v14, v11, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_23
-; CI-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
+; CI-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB12_18
+; CI-NEXT: ; %bb.16: ; %frem.loop_body23.preheader
; CI-NEXT: v_sub_i32_e32 v12, vcc, v15, v16
; CI-NEXT: v_add_i32_e32 v12, vcc, 12, v12
-; CI-NEXT: .LBB12_21: ; %frem.loop_body23
+; CI-NEXT: .LBB12_17: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v15, v13
-; CI-NEXT: v_mul_f32_e32 v13, v15, v14
-; CI-NEXT: v_rndne_f32_e32 v13, v13
-; CI-NEXT: v_fma_f32 v13, -v13, v11, v15
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
-; CI-NEXT: v_add_f32_e32 v16, v13, v11
-; CI-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc
+; CI-NEXT: v_mov_b32_e32 v15, v14
+; CI-NEXT: v_mul_f32_e32 v14, v15, v13
+; CI-NEXT: v_rndne_f32_e32 v14, v14
+; CI-NEXT: v_fma_f32 v14, -v14, v11, v15
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
+; CI-NEXT: v_add_f32_e32 v16, v14, v11
+; CI-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
; CI-NEXT: v_add_i32_e32 v12, vcc, -12, v12
+; CI-NEXT: v_ldexp_f32_e64 v14, v14, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v12
-; CI-NEXT: v_ldexp_f32_e64 v13, v13, 12
-; CI-NEXT: s_cbranch_vccnz .LBB12_21
-; CI-NEXT: ; %bb.22: ; %Flow117
-; CI-NEXT: v_mov_b32_e32 v13, v15
-; CI-NEXT: .LBB12_23: ; %frem.loop_exit24
+; CI-NEXT: s_cbranch_vccnz .LBB12_17
+; CI-NEXT: s_branch .LBB12_19
+; CI-NEXT: .LBB12_18:
+; CI-NEXT: v_mov_b32_e32 v15, v14
+; CI-NEXT: .LBB12_19: ; %frem.loop_exit24
; CI-NEXT: v_add_i32_e32 v12, vcc, -11, v12
-; CI-NEXT: v_ldexp_f32_e32 v12, v13, v12
-; CI-NEXT: v_mul_f32_e32 v13, v12, v14
+; CI-NEXT: v_ldexp_f32_e32 v12, v15, v12
+; CI-NEXT: v_mul_f32_e32 v13, v12, v13
; CI-NEXT: v_rndne_f32_e32 v13, v13
; CI-NEXT: v_fma_f32 v12, -v13, v11, v12
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
@@ -13829,70 +12918,56 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v10, v11, v10
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v10, s2, v10, v2
-; CI-NEXT: .LBB12_24:
-; CI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB12_26
-; CI-NEXT: ; %bb.25: ; %frem.else
-; CI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; CI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
-; CI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB12_27
-; CI-NEXT: s_branch .LBB12_32
-; CI-NEXT: .LBB12_26:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr11
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB12_32
-; CI-NEXT: .LBB12_27: ; %frem.compute
+; CI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
+; CI-NEXT: s_cbranch_vccz .LBB12_7
+; CI-NEXT: .LBB12_20: ; %frem.compute
; CI-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; CI-NEXT: v_ldexp_f32_e64 v12, v12, 1
; CI-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
; CI-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; CI-NEXT: v_frexp_exp_i32_f32_e32 v17, v7
-; CI-NEXT: v_ldexp_f32_e64 v14, v11, 12
+; CI-NEXT: v_ldexp_f32_e64 v15, v11, 12
; CI-NEXT: v_add_i32_e32 v11, vcc, -1, v17
; CI-NEXT: v_frexp_exp_i32_f32_e32 v16, v3
; CI-NEXT: v_not_b32_e32 v13, v11
; CI-NEXT: v_add_i32_e32 v13, vcc, v13, v16
-; CI-NEXT: v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
+; CI-NEXT: v_div_scale_f32 v14, vcc, 1.0, v12, 1.0
; CI-NEXT: v_rcp_f32_e32 v19, v18
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; CI-NEXT: v_fma_f32 v20, -v18, v19, 1.0
; CI-NEXT: v_fma_f32 v19, v20, v19, v19
-; CI-NEXT: v_mul_f32_e32 v20, v15, v19
-; CI-NEXT: v_fma_f32 v21, -v18, v20, v15
+; CI-NEXT: v_mul_f32_e32 v20, v14, v19
+; CI-NEXT: v_fma_f32 v21, -v18, v20, v14
; CI-NEXT: v_fma_f32 v20, v21, v19, v20
-; CI-NEXT: v_fma_f32 v15, -v18, v20, v15
+; CI-NEXT: v_fma_f32 v14, -v18, v20, v14
; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT: v_div_fmas_f32 v15, v15, v19, v20
+; CI-NEXT: v_div_fmas_f32 v14, v14, v19, v20
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v13
-; CI-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB12_31
-; CI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; CI-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB12_23
+; CI-NEXT: ; %bb.21: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v13, vcc, v16, v17
; CI-NEXT: v_add_i32_e32 v13, vcc, 12, v13
-; CI-NEXT: .LBB12_29: ; %frem.loop_body
+; CI-NEXT: .LBB12_22: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v16, v14
-; CI-NEXT: v_mul_f32_e32 v14, v16, v15
-; CI-NEXT: v_rndne_f32_e32 v14, v14
-; CI-NEXT: v_fma_f32 v14, -v14, v12, v16
-; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
-; CI-NEXT: v_add_f32_e32 v17, v14, v12
-; CI-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
+; CI-NEXT: v_mov_b32_e32 v16, v15
+; CI-NEXT: v_mul_f32_e32 v15, v16, v14
+; CI-NEXT: v_rndne_f32_e32 v15, v15
+; CI-NEXT: v_fma_f32 v15, -v15, v12, v16
+; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v15
+; CI-NEXT: v_add_f32_e32 v17, v15, v12
+; CI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
; CI-NEXT: v_add_i32_e32 v13, vcc, -12, v13
+; CI-NEXT: v_ldexp_f32_e64 v15, v15, 12
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v13
-; CI-NEXT: v_ldexp_f32_e64 v14, v14, 12
-; CI-NEXT: s_cbranch_vccnz .LBB12_29
-; CI-NEXT: ; %bb.30: ; %Flow
-; CI-NEXT: v_mov_b32_e32 v14, v16
-; CI-NEXT: .LBB12_31: ; %frem.loop_exit
+; CI-NEXT: s_cbranch_vccnz .LBB12_22
+; CI-NEXT: s_branch .LBB12_24
+; CI-NEXT: .LBB12_23:
+; CI-NEXT: v_mov_b32_e32 v16, v15
+; CI-NEXT: .LBB12_24: ; %frem.loop_exit
; CI-NEXT: v_add_i32_e32 v13, vcc, -11, v13
-; CI-NEXT: v_ldexp_f32_e32 v13, v14, v13
-; CI-NEXT: v_mul_f32_e32 v14, v13, v15
+; CI-NEXT: v_ldexp_f32_e32 v13, v16, v13
+; CI-NEXT: v_mul_f32_e32 v14, v13, v14
; CI-NEXT: v_rndne_f32_e32 v14, v14
; CI-NEXT: v_fma_f32 v13, -v14, v12, v13
; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
@@ -13901,7 +12976,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f32_e32 v11, v12, v11
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; CI-NEXT: .LBB12_32: ; %Flow116
+; CI-NEXT: .LBB12_25:
; CI-NEXT: s_mov_b32 s4, 0x7f800000
; CI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; CI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -13939,69 +13014,79 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB12_2
-; VI-NEXT: ; %bb.1: ; %frem.else78
-; VI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
-; VI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB12_3
-; VI-NEXT: s_branch .LBB12_8
-; VI-NEXT: .LBB12_2:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr8
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB12_8
-; VI-NEXT: .LBB12_3: ; %frem.compute77
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v4|
+; VI-NEXT: s_cbranch_vccz .LBB12_4
+; VI-NEXT: ; %bb.1: ; %frem.compute77
; VI-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; VI-NEXT: v_ldexp_f32 v9, v9, 1
; VI-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v14, v4
-; VI-NEXT: v_ldexp_f32 v11, v8, 12
+; VI-NEXT: v_ldexp_f32 v12, v8, 12
; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v14
; VI-NEXT: v_frexp_exp_i32_f32_e32 v13, v0
; VI-NEXT: v_not_b32_e32 v10, v8
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v13
-; VI-NEXT: v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
+; VI-NEXT: v_div_scale_f32 v11, vcc, 1.0, v9, 1.0
; VI-NEXT: v_rcp_f32_e32 v16, v15
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v17, -v15, v16, 1.0
; VI-NEXT: v_fma_f32 v16, v17, v16, v16
-; VI-NEXT: v_mul_f32_e32 v17, v12, v16
-; VI-NEXT: v_fma_f32 v18, -v15, v17, v12
+; VI-NEXT: v_mul_f32_e32 v17, v11, v16
+; VI-NEXT: v_fma_f32 v18, -v15, v17, v11
; VI-NEXT: v_fma_f32 v17, v18, v16, v17
-; VI-NEXT: v_fma_f32 v12, -v15, v17, v12
+; VI-NEXT: v_fma_f32 v11, -v15, v17, v11
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v12, v12, v16, v17
+; VI-NEXT: v_div_fmas_f32 v11, v11, v16, v17
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v10
-; VI-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_7
-; VI-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
+; VI-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB12_8
+; VI-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
; VI-NEXT: v_sub_u32_e32 v10, vcc, v13, v14
; VI-NEXT: v_add_u32_e32 v10, vcc, 12, v10
-; VI-NEXT: .LBB12_5: ; %frem.loop_body85
+; VI-NEXT: .LBB12_3: ; %frem.loop_body85
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v13, v11
-; VI-NEXT: v_mul_f32_e32 v11, v13, v12
-; VI-NEXT: v_rndne_f32_e32 v11, v11
-; VI-NEXT: v_fma_f32 v11, -v11, v9, v13
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
-; VI-NEXT: v_add_f32_e32 v14, v11, v9
-; VI-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
+; VI-NEXT: v_mov_b32_e32 v13, v12
+; VI-NEXT: v_mul_f32_e32 v12, v13, v11
+; VI-NEXT: v_rndne_f32_e32 v12, v12
+; VI-NEXT: v_fma_f32 v12, -v12, v9, v13
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
+; VI-NEXT: v_add_f32_e32 v14, v12, v9
+; VI-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, -12, v10
+; VI-NEXT: v_ldexp_f32 v12, v12, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v10
-; VI-NEXT: v_ldexp_f32 v11, v11, 12
-; VI-NEXT: s_cbranch_vccnz .LBB12_5
-; VI-NEXT: ; %bb.6: ; %Flow125
-; VI-NEXT: v_mov_b32_e32 v11, v13
-; VI-NEXT: .LBB12_7: ; %frem.loop_exit86
+; VI-NEXT: s_cbranch_vccnz .LBB12_3
+; VI-NEXT: s_branch .LBB12_9
+; VI-NEXT: .LBB12_4: ; %frem.else78
+; VI-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; VI-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
+; VI-NEXT: s_cbranch_vccnz .LBB12_10
+; VI-NEXT: .LBB12_5: ; %frem.else47
+; VI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; VI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
+; VI-NEXT: s_cbranch_vccnz .LBB12_15
+; VI-NEXT: .LBB12_6: ; %frem.else16
+; VI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; VI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
+; VI-NEXT: s_cbranch_vccnz .LBB12_20
+; VI-NEXT: .LBB12_7: ; %frem.else
+; VI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; VI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
+; VI-NEXT: s_branch .LBB12_25
+; VI-NEXT: .LBB12_8:
+; VI-NEXT: v_mov_b32_e32 v13, v12
+; VI-NEXT: .LBB12_9: ; %frem.loop_exit86
; VI-NEXT: v_add_u32_e32 v10, vcc, -11, v10
-; VI-NEXT: v_ldexp_f32 v10, v11, v10
-; VI-NEXT: v_mul_f32_e32 v11, v10, v12
+; VI-NEXT: v_ldexp_f32 v10, v13, v10
+; VI-NEXT: v_mul_f32_e32 v11, v10, v11
; VI-NEXT: v_rndne_f32_e32 v11, v11
; VI-NEXT: v_fma_f32 v10, -v11, v9, v10
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
@@ -14010,70 +13095,56 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v8, v9, v8
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v8, s2, v8, v0
-; VI-NEXT: .LBB12_8:
-; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB12_10
-; VI-NEXT: ; %bb.9: ; %frem.else47
-; VI-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
-; VI-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB12_11
-; VI-NEXT: s_branch .LBB12_16
-; VI-NEXT: .LBB12_10:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr9
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB12_16
-; VI-NEXT: .LBB12_11: ; %frem.compute46
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
+; VI-NEXT: s_cbranch_vccz .LBB12_5
+; VI-NEXT: .LBB12_10: ; %frem.compute46
; VI-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; VI-NEXT: v_ldexp_f32 v10, v10, 1
; VI-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v9, |v1|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v15, v5
-; VI-NEXT: v_ldexp_f32 v12, v9, 12
+; VI-NEXT: v_ldexp_f32 v13, v9, 12
; VI-NEXT: v_add_u32_e32 v9, vcc, -1, v15
; VI-NEXT: v_frexp_exp_i32_f32_e32 v14, v1
; VI-NEXT: v_not_b32_e32 v11, v9
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v14
-; VI-NEXT: v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
+; VI-NEXT: v_div_scale_f32 v12, vcc, 1.0, v10, 1.0
; VI-NEXT: v_rcp_f32_e32 v17, v16
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; VI-NEXT: v_fma_f32 v17, v18, v17, v17
-; VI-NEXT: v_mul_f32_e32 v18, v13, v17
-; VI-NEXT: v_fma_f32 v19, -v16, v18, v13
+; VI-NEXT: v_mul_f32_e32 v18, v12, v17
+; VI-NEXT: v_fma_f32 v19, -v16, v18, v12
; VI-NEXT: v_fma_f32 v18, v19, v17, v18
-; VI-NEXT: v_fma_f32 v13, -v16, v18, v13
+; VI-NEXT: v_fma_f32 v12, -v16, v18, v12
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v13, v13, v17, v18
+; VI-NEXT: v_div_fmas_f32 v12, v12, v17, v18
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v11
-; VI-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_15
-; VI-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
+; VI-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB12_13
+; VI-NEXT: ; %bb.11: ; %frem.loop_body54.preheader
; VI-NEXT: v_sub_u32_e32 v11, vcc, v14, v15
; VI-NEXT: v_add_u32_e32 v11, vcc, 12, v11
-; VI-NEXT: .LBB12_13: ; %frem.loop_body54
+; VI-NEXT: .LBB12_12: ; %frem.loop_body54
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v14, v12
-; VI-NEXT: v_mul_f32_e32 v12, v14, v13
-; VI-NEXT: v_rndne_f32_e32 v12, v12
-; VI-NEXT: v_fma_f32 v12, -v12, v10, v14
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
-; VI-NEXT: v_add_f32_e32 v15, v12, v10
-; VI-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
+; VI-NEXT: v_mov_b32_e32 v14, v13
+; VI-NEXT: v_mul_f32_e32 v13, v14, v12
+; VI-NEXT: v_rndne_f32_e32 v13, v13
+; VI-NEXT: v_fma_f32 v13, -v13, v10, v14
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
+; VI-NEXT: v_add_f32_e32 v15, v13, v10
+; VI-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
; VI-NEXT: v_add_u32_e32 v11, vcc, -12, v11
+; VI-NEXT: v_ldexp_f32 v13, v13, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v11
-; VI-NEXT: v_ldexp_f32 v12, v12, 12
-; VI-NEXT: s_cbranch_vccnz .LBB12_13
-; VI-NEXT: ; %bb.14: ; %Flow121
-; VI-NEXT: v_mov_b32_e32 v12, v14
-; VI-NEXT: .LBB12_15: ; %frem.loop_exit55
+; VI-NEXT: s_cbranch_vccnz .LBB12_12
+; VI-NEXT: s_branch .LBB12_14
+; VI-NEXT: .LBB12_13:
+; VI-NEXT: v_mov_b32_e32 v14, v13
+; VI-NEXT: .LBB12_14: ; %frem.loop_exit55
; VI-NEXT: v_add_u32_e32 v11, vcc, -11, v11
-; VI-NEXT: v_ldexp_f32 v11, v12, v11
-; VI-NEXT: v_mul_f32_e32 v12, v11, v13
+; VI-NEXT: v_ldexp_f32 v11, v14, v11
+; VI-NEXT: v_mul_f32_e32 v12, v11, v12
; VI-NEXT: v_rndne_f32_e32 v12, v12
; VI-NEXT: v_fma_f32 v11, -v12, v10, v11
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
@@ -14082,70 +13153,56 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v9, v10, v9
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; VI-NEXT: .LBB12_16:
-; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB12_18
-; VI-NEXT: ; %bb.17: ; %frem.else16
-; VI-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
-; VI-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB12_19
-; VI-NEXT: s_branch .LBB12_24
-; VI-NEXT: .LBB12_18:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr10
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB12_24
-; VI-NEXT: .LBB12_19: ; %frem.compute15
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
+; VI-NEXT: s_cbranch_vccz .LBB12_6
+; VI-NEXT: .LBB12_15: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; VI-NEXT: v_ldexp_f32 v11, v11, 1
; VI-NEXT: v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v16, v6
-; VI-NEXT: v_ldexp_f32 v13, v10, 12
+; VI-NEXT: v_ldexp_f32 v14, v10, 12
; VI-NEXT: v_add_u32_e32 v10, vcc, -1, v16
; VI-NEXT: v_frexp_exp_i32_f32_e32 v15, v2
; VI-NEXT: v_not_b32_e32 v12, v10
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v15
-; VI-NEXT: v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
+; VI-NEXT: v_div_scale_f32 v13, vcc, 1.0, v11, 1.0
; VI-NEXT: v_rcp_f32_e32 v18, v17
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v19, -v17, v18, 1.0
; VI-NEXT: v_fma_f32 v18, v19, v18, v18
-; VI-NEXT: v_mul_f32_e32 v19, v14, v18
-; VI-NEXT: v_fma_f32 v20, -v17, v19, v14
+; VI-NEXT: v_mul_f32_e32 v19, v13, v18
+; VI-NEXT: v_fma_f32 v20, -v17, v19, v13
; VI-NEXT: v_fma_f32 v19, v20, v18, v19
-; VI-NEXT: v_fma_f32 v14, -v17, v19, v14
+; VI-NEXT: v_fma_f32 v13, -v17, v19, v13
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v14, v14, v18, v19
+; VI-NEXT: v_div_fmas_f32 v13, v13, v18, v19
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v12
-; VI-NEXT: v_div_fixup_f32 v14, v14, v11, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_23
-; VI-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
+; VI-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB12_18
+; VI-NEXT: ; %bb.16: ; %frem.loop_body23.preheader
; VI-NEXT: v_sub_u32_e32 v12, vcc, v15, v16
; VI-NEXT: v_add_u32_e32 v12, vcc, 12, v12
-; VI-NEXT: .LBB12_21: ; %frem.loop_body23
+; VI-NEXT: .LBB12_17: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v15, v13
-; VI-NEXT: v_mul_f32_e32 v13, v15, v14
-; VI-NEXT: v_rndne_f32_e32 v13, v13
-; VI-NEXT: v_fma_f32 v13, -v13, v11, v15
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
-; VI-NEXT: v_add_f32_e32 v16, v13, v11
-; VI-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc
+; VI-NEXT: v_mov_b32_e32 v15, v14
+; VI-NEXT: v_mul_f32_e32 v14, v15, v13
+; VI-NEXT: v_rndne_f32_e32 v14, v14
+; VI-NEXT: v_fma_f32 v14, -v14, v11, v15
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
+; VI-NEXT: v_add_f32_e32 v16, v14, v11
+; VI-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
; VI-NEXT: v_add_u32_e32 v12, vcc, -12, v12
+; VI-NEXT: v_ldexp_f32 v14, v14, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v12
-; VI-NEXT: v_ldexp_f32 v13, v13, 12
-; VI-NEXT: s_cbranch_vccnz .LBB12_21
-; VI-NEXT: ; %bb.22: ; %Flow117
-; VI-NEXT: v_mov_b32_e32 v13, v15
-; VI-NEXT: .LBB12_23: ; %frem.loop_exit24
+; VI-NEXT: s_cbranch_vccnz .LBB12_17
+; VI-NEXT: s_branch .LBB12_19
+; VI-NEXT: .LBB12_18:
+; VI-NEXT: v_mov_b32_e32 v15, v14
+; VI-NEXT: .LBB12_19: ; %frem.loop_exit24
; VI-NEXT: v_add_u32_e32 v12, vcc, -11, v12
-; VI-NEXT: v_ldexp_f32 v12, v13, v12
-; VI-NEXT: v_mul_f32_e32 v13, v12, v14
+; VI-NEXT: v_ldexp_f32 v12, v15, v12
+; VI-NEXT: v_mul_f32_e32 v13, v12, v13
; VI-NEXT: v_rndne_f32_e32 v13, v13
; VI-NEXT: v_fma_f32 v12, -v13, v11, v12
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
@@ -14154,70 +13211,56 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v10, v11, v10
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v10, s2, v10, v2
-; VI-NEXT: .LBB12_24:
-; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB12_26
-; VI-NEXT: ; %bb.25: ; %frem.else
-; VI-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; VI-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
-; VI-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB12_27
-; VI-NEXT: s_branch .LBB12_32
-; VI-NEXT: .LBB12_26:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr11
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB12_32
-; VI-NEXT: .LBB12_27: ; %frem.compute
+; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
+; VI-NEXT: s_cbranch_vccz .LBB12_7
+; VI-NEXT: .LBB12_20: ; %frem.compute
; VI-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; VI-NEXT: v_ldexp_f32 v12, v12, 1
; VI-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
; VI-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; VI-NEXT: v_frexp_exp_i32_f32_e32 v17, v7
-; VI-NEXT: v_ldexp_f32 v14, v11, 12
+; VI-NEXT: v_ldexp_f32 v15, v11, 12
; VI-NEXT: v_add_u32_e32 v11, vcc, -1, v17
; VI-NEXT: v_frexp_exp_i32_f32_e32 v16, v3
; VI-NEXT: v_not_b32_e32 v13, v11
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v16
-; VI-NEXT: v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
+; VI-NEXT: v_div_scale_f32 v14, vcc, 1.0, v12, 1.0
; VI-NEXT: v_rcp_f32_e32 v19, v18
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; VI-NEXT: v_fma_f32 v20, -v18, v19, 1.0
; VI-NEXT: v_fma_f32 v19, v20, v19, v19
-; VI-NEXT: v_mul_f32_e32 v20, v15, v19
-; VI-NEXT: v_fma_f32 v21, -v18, v20, v15
+; VI-NEXT: v_mul_f32_e32 v20, v14, v19
+; VI-NEXT: v_fma_f32 v21, -v18, v20, v14
; VI-NEXT: v_fma_f32 v20, v21, v19, v20
-; VI-NEXT: v_fma_f32 v15, -v18, v20, v15
+; VI-NEXT: v_fma_f32 v14, -v18, v20, v14
; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT: v_div_fmas_f32 v15, v15, v19, v20
+; VI-NEXT: v_div_fmas_f32 v14, v14, v19, v20
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 13, v13
-; VI-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB12_31
-; VI-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; VI-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB12_23
+; VI-NEXT: ; %bb.21: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v13, vcc, v16, v17
; VI-NEXT: v_add_u32_e32 v13, vcc, 12, v13
-; VI-NEXT: .LBB12_29: ; %frem.loop_body
+; VI-NEXT: .LBB12_22: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v16, v14
-; VI-NEXT: v_mul_f32_e32 v14, v16, v15
-; VI-NEXT: v_rndne_f32_e32 v14, v14
-; VI-NEXT: v_fma_f32 v14, -v14, v12, v16
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
-; VI-NEXT: v_add_f32_e32 v17, v14, v12
-; VI-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
+; VI-NEXT: v_mov_b32_e32 v16, v15
+; VI-NEXT: v_mul_f32_e32 v15, v16, v14
+; VI-NEXT: v_rndne_f32_e32 v15, v15
+; VI-NEXT: v_fma_f32 v15, -v15, v12, v16
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v15
+; VI-NEXT: v_add_f32_e32 v17, v15, v12
+; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
; VI-NEXT: v_add_u32_e32 v13, vcc, -12, v13
+; VI-NEXT: v_ldexp_f32 v15, v15, 12
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v13
-; VI-NEXT: v_ldexp_f32 v14, v14, 12
-; VI-NEXT: s_cbranch_vccnz .LBB12_29
-; VI-NEXT: ; %bb.30: ; %Flow
-; VI-NEXT: v_mov_b32_e32 v14, v16
-; VI-NEXT: .LBB12_31: ; %frem.loop_exit
+; VI-NEXT: s_cbranch_vccnz .LBB12_22
+; VI-NEXT: s_branch .LBB12_24
+; VI-NEXT: .LBB12_23:
+; VI-NEXT: v_mov_b32_e32 v16, v15
+; VI-NEXT: .LBB12_24: ; %frem.loop_exit
; VI-NEXT: v_add_u32_e32 v13, vcc, -11, v13
-; VI-NEXT: v_ldexp_f32 v13, v14, v13
-; VI-NEXT: v_mul_f32_e32 v14, v13, v15
+; VI-NEXT: v_ldexp_f32 v13, v16, v13
+; VI-NEXT: v_mul_f32_e32 v14, v13, v14
; VI-NEXT: v_rndne_f32_e32 v14, v14
; VI-NEXT: v_fma_f32 v13, -v14, v12, v13
; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
@@ -14226,7 +13269,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f32 v11, v12, v11
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; VI-NEXT: .LBB12_32: ; %Flow116
+; VI-NEXT: .LBB12_25:
; VI-NEXT: s_mov_b32 s4, 0x7f800000
; VI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -14259,30 +13302,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3]
; GFX9-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB12_2
-; GFX9-NEXT: ; %bb.1: ; %frem.else78
-; GFX9-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB12_3
-; GFX9-NEXT: s_branch .LBB12_8
-; GFX9-NEXT: .LBB12_2:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr8
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB12_8
-; GFX9-NEXT: .LBB12_3: ; %frem.compute77
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, |v4|
+; GFX9-NEXT: s_cbranch_vccz .LBB12_4
+; GFX9-NEXT: ; %bb.1: ; %frem.compute77
; GFX9-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; GFX9-NEXT: v_ldexp_f32 v9, v9, 1
; GFX9-NEXT: v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
-; GFX9-NEXT: v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
+; GFX9-NEXT: v_div_scale_f32 v11, vcc, 1.0, v9, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v13, v0
-; GFX9-NEXT: v_ldexp_f32 v11, v8, 12
+; GFX9-NEXT: v_ldexp_f32 v12, v8, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v14, v4
; GFX9-NEXT: v_add_u32_e32 v8, -1, v14
; GFX9-NEXT: v_not_b32_e32 v10, v8
@@ -14291,37 +13320,61 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v17, -v15, v16, 1.0
; GFX9-NEXT: v_fma_f32 v16, v17, v16, v16
-; GFX9-NEXT: v_mul_f32_e32 v17, v12, v16
-; GFX9-NEXT: v_fma_f32 v18, -v15, v17, v12
+; GFX9-NEXT: v_mul_f32_e32 v17, v11, v16
+; GFX9-NEXT: v_fma_f32 v18, -v15, v17, v11
; GFX9-NEXT: v_fma_f32 v17, v18, v16, v17
-; GFX9-NEXT: v_fma_f32 v12, -v15, v17, v12
+; GFX9-NEXT: v_fma_f32 v11, -v15, v17, v11
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v12, v12, v16, v17
+; GFX9-NEXT: v_div_fmas_f32 v11, v11, v16, v17
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v10
-; GFX9-NEXT: v_div_fixup_f32 v12, v12, v9, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_7
-; GFX9-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
+; GFX9-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_8
+; GFX9-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
; GFX9-NEXT: v_sub_u32_e32 v10, v13, v14
; GFX9-NEXT: v_add_u32_e32 v10, 12, v10
-; GFX9-NEXT: .LBB12_5: ; %frem.loop_body85
+; GFX9-NEXT: .LBB12_3: ; %frem.loop_body85
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v13, v11
-; GFX9-NEXT: v_mul_f32_e32 v11, v13, v12
-; GFX9-NEXT: v_rndne_f32_e32 v11, v11
-; GFX9-NEXT: v_fma_f32 v11, -v11, v9, v13
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
-; GFX9-NEXT: v_add_f32_e32 v14, v11, v9
+; GFX9-NEXT: v_mov_b32_e32 v13, v12
+; GFX9-NEXT: v_mul_f32_e32 v12, v13, v11
+; GFX9-NEXT: v_rndne_f32_e32 v12, v12
+; GFX9-NEXT: v_fma_f32 v12, -v12, v9, v13
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
+; GFX9-NEXT: v_add_f32_e32 v14, v12, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc
; GFX9-NEXT: v_add_u32_e32 v10, -12, v10
-; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
+; GFX9-NEXT: v_ldexp_f32 v12, v12, 12
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v10
-; GFX9-NEXT: v_ldexp_f32 v11, v11, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_5
-; GFX9-NEXT: ; %bb.6: ; %Flow125
-; GFX9-NEXT: v_mov_b32_e32 v11, v13
-; GFX9-NEXT: .LBB12_7: ; %frem.loop_exit86
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_3
+; GFX9-NEXT: s_branch .LBB12_9
+; GFX9-NEXT: .LBB12_4: ; %frem.else78
+; GFX9-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_10
+; GFX9-NEXT: .LBB12_5: ; %frem.else47
+; GFX9-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_15
+; GFX9-NEXT: .LBB12_6: ; %frem.else16
+; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_20
+; GFX9-NEXT: .LBB12_7: ; %frem.else
+; GFX9-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
+; GFX9-NEXT: s_branch .LBB12_25
+; GFX9-NEXT: .LBB12_8:
+; GFX9-NEXT: v_mov_b32_e32 v13, v12
+; GFX9-NEXT: .LBB12_9: ; %frem.loop_exit86
; GFX9-NEXT: v_add_u32_e32 v10, -11, v10
-; GFX9-NEXT: v_ldexp_f32 v10, v11, v10
-; GFX9-NEXT: v_mul_f32_e32 v11, v10, v12
+; GFX9-NEXT: v_ldexp_f32 v10, v13, v10
+; GFX9-NEXT: v_mul_f32_e32 v11, v10, v11
; GFX9-NEXT: v_rndne_f32_e32 v11, v11
; GFX9-NEXT: v_fma_f32 v10, -v11, v9, v10
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v10
@@ -14330,31 +13383,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v8, v9, v8
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v8, s2, v8, v0
-; GFX9-NEXT: .LBB12_8:
-; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB12_10
-; GFX9-NEXT: ; %bb.9: ; %frem.else47
-; GFX9-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v1|, |v5|
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB12_11
-; GFX9-NEXT: s_branch .LBB12_16
-; GFX9-NEXT: .LBB12_10:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr9
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB12_16
-; GFX9-NEXT: .LBB12_11: ; %frem.compute46
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, |v5|
+; GFX9-NEXT: s_cbranch_vccz .LBB12_5
+; GFX9-NEXT: .LBB12_10: ; %frem.compute46
; GFX9-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; GFX9-NEXT: v_ldexp_f32 v10, v10, 1
; GFX9-NEXT: v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
-; GFX9-NEXT: v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
+; GFX9-NEXT: v_div_scale_f32 v12, vcc, 1.0, v10, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v9, |v1|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v14, v1
-; GFX9-NEXT: v_ldexp_f32 v12, v9, 12
+; GFX9-NEXT: v_ldexp_f32 v13, v9, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v15, v5
; GFX9-NEXT: v_add_u32_e32 v9, -1, v15
; GFX9-NEXT: v_not_b32_e32 v11, v9
@@ -14363,37 +13401,38 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; GFX9-NEXT: v_fma_f32 v17, v18, v17, v17
-; GFX9-NEXT: v_mul_f32_e32 v18, v13, v17
-; GFX9-NEXT: v_fma_f32 v19, -v16, v18, v13
+; GFX9-NEXT: v_mul_f32_e32 v18, v12, v17
+; GFX9-NEXT: v_fma_f32 v19, -v16, v18, v12
; GFX9-NEXT: v_fma_f32 v18, v19, v17, v18
-; GFX9-NEXT: v_fma_f32 v13, -v16, v18, v13
+; GFX9-NEXT: v_fma_f32 v12, -v16, v18, v12
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v13, v13, v17, v18
+; GFX9-NEXT: v_div_fmas_f32 v12, v12, v17, v18
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v11
-; GFX9-NEXT: v_div_fixup_f32 v13, v13, v10, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_15
-; GFX9-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
+; GFX9-NEXT: v_div_fixup_f32 v12, v12, v10, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_13
+; GFX9-NEXT: ; %bb.11: ; %frem.loop_body54.preheader
; GFX9-NEXT: v_sub_u32_e32 v11, v14, v15
; GFX9-NEXT: v_add_u32_e32 v11, 12, v11
-; GFX9-NEXT: .LBB12_13: ; %frem.loop_body54
+; GFX9-NEXT: .LBB12_12: ; %frem.loop_body54
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v14, v12
-; GFX9-NEXT: v_mul_f32_e32 v12, v14, v13
-; GFX9-NEXT: v_rndne_f32_e32 v12, v12
-; GFX9-NEXT: v_fma_f32 v12, -v12, v10, v14
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
-; GFX9-NEXT: v_add_f32_e32 v15, v12, v10
+; GFX9-NEXT: v_mov_b32_e32 v14, v13
+; GFX9-NEXT: v_mul_f32_e32 v13, v14, v12
+; GFX9-NEXT: v_rndne_f32_e32 v13, v13
+; GFX9-NEXT: v_fma_f32 v13, -v13, v10, v14
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
+; GFX9-NEXT: v_add_f32_e32 v15, v13, v10
+; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
; GFX9-NEXT: v_add_u32_e32 v11, -12, v11
-; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc
+; GFX9-NEXT: v_ldexp_f32 v13, v13, 12
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v11
-; GFX9-NEXT: v_ldexp_f32 v12, v12, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_13
-; GFX9-NEXT: ; %bb.14: ; %Flow121
-; GFX9-NEXT: v_mov_b32_e32 v12, v14
-; GFX9-NEXT: .LBB12_15: ; %frem.loop_exit55
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_12
+; GFX9-NEXT: s_branch .LBB12_14
+; GFX9-NEXT: .LBB12_13:
+; GFX9-NEXT: v_mov_b32_e32 v14, v13
+; GFX9-NEXT: .LBB12_14: ; %frem.loop_exit55
; GFX9-NEXT: v_add_u32_e32 v11, -11, v11
-; GFX9-NEXT: v_ldexp_f32 v11, v12, v11
-; GFX9-NEXT: v_mul_f32_e32 v12, v11, v13
+; GFX9-NEXT: v_ldexp_f32 v11, v14, v11
+; GFX9-NEXT: v_mul_f32_e32 v12, v11, v12
; GFX9-NEXT: v_rndne_f32_e32 v12, v12
; GFX9-NEXT: v_fma_f32 v11, -v12, v10, v11
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v11
@@ -14402,31 +13441,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v9, v10, v9
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v9, s2, v9, v1
-; GFX9-NEXT: .LBB12_16:
-; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB12_18
-; GFX9-NEXT: ; %bb.17: ; %frem.else16
-; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v2|, |v6|
-; GFX9-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB12_19
-; GFX9-NEXT: s_branch .LBB12_24
-; GFX9-NEXT: .LBB12_18:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr10
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB12_24
-; GFX9-NEXT: .LBB12_19: ; %frem.compute15
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v2|, |v6|
+; GFX9-NEXT: s_cbranch_vccz .LBB12_6
+; GFX9-NEXT: .LBB12_15: ; %frem.compute15
; GFX9-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; GFX9-NEXT: v_ldexp_f32 v11, v11, 1
; GFX9-NEXT: v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
-; GFX9-NEXT: v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
+; GFX9-NEXT: v_div_scale_f32 v13, vcc, 1.0, v11, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v15, v2
-; GFX9-NEXT: v_ldexp_f32 v13, v10, 12
+; GFX9-NEXT: v_ldexp_f32 v14, v10, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v16, v6
; GFX9-NEXT: v_add_u32_e32 v10, -1, v16
; GFX9-NEXT: v_not_b32_e32 v12, v10
@@ -14435,37 +13459,38 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v19, -v17, v18, 1.0
; GFX9-NEXT: v_fma_f32 v18, v19, v18, v18
-; GFX9-NEXT: v_mul_f32_e32 v19, v14, v18
-; GFX9-NEXT: v_fma_f32 v20, -v17, v19, v14
+; GFX9-NEXT: v_mul_f32_e32 v19, v13, v18
+; GFX9-NEXT: v_fma_f32 v20, -v17, v19, v13
; GFX9-NEXT: v_fma_f32 v19, v20, v18, v19
-; GFX9-NEXT: v_fma_f32 v14, -v17, v19, v14
+; GFX9-NEXT: v_fma_f32 v13, -v17, v19, v13
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v14, v14, v18, v19
+; GFX9-NEXT: v_div_fmas_f32 v13, v13, v18, v19
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v12
-; GFX9-NEXT: v_div_fixup_f32 v14, v14, v11, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_23
-; GFX9-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
+; GFX9-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_18
+; GFX9-NEXT: ; %bb.16: ; %frem.loop_body23.preheader
; GFX9-NEXT: v_sub_u32_e32 v12, v15, v16
; GFX9-NEXT: v_add_u32_e32 v12, 12, v12
-; GFX9-NEXT: .LBB12_21: ; %frem.loop_body23
+; GFX9-NEXT: .LBB12_17: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v15, v13
-; GFX9-NEXT: v_mul_f32_e32 v13, v15, v14
-; GFX9-NEXT: v_rndne_f32_e32 v13, v13
-; GFX9-NEXT: v_fma_f32 v13, -v13, v11, v15
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
-; GFX9-NEXT: v_add_f32_e32 v16, v13, v11
+; GFX9-NEXT: v_mov_b32_e32 v15, v14
+; GFX9-NEXT: v_mul_f32_e32 v14, v15, v13
+; GFX9-NEXT: v_rndne_f32_e32 v14, v14
+; GFX9-NEXT: v_fma_f32 v14, -v14, v11, v15
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
+; GFX9-NEXT: v_add_f32_e32 v16, v14, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
; GFX9-NEXT: v_add_u32_e32 v12, -12, v12
-; GFX9-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc
+; GFX9-NEXT: v_ldexp_f32 v14, v14, 12
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v12
-; GFX9-NEXT: v_ldexp_f32 v13, v13, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_21
-; GFX9-NEXT: ; %bb.22: ; %Flow117
-; GFX9-NEXT: v_mov_b32_e32 v13, v15
-; GFX9-NEXT: .LBB12_23: ; %frem.loop_exit24
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_17
+; GFX9-NEXT: s_branch .LBB12_19
+; GFX9-NEXT: .LBB12_18:
+; GFX9-NEXT: v_mov_b32_e32 v15, v14
+; GFX9-NEXT: .LBB12_19: ; %frem.loop_exit24
; GFX9-NEXT: v_add_u32_e32 v12, -11, v12
-; GFX9-NEXT: v_ldexp_f32 v12, v13, v12
-; GFX9-NEXT: v_mul_f32_e32 v13, v12, v14
+; GFX9-NEXT: v_ldexp_f32 v12, v15, v12
+; GFX9-NEXT: v_mul_f32_e32 v13, v12, v13
; GFX9-NEXT: v_rndne_f32_e32 v13, v13
; GFX9-NEXT: v_fma_f32 v12, -v13, v11, v12
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v12
@@ -14474,31 +13499,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v10, v11, v10
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v10, s2, v10, v2
-; GFX9-NEXT: .LBB12_24:
-; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB12_26
-; GFX9-NEXT: ; %bb.25: ; %frem.else
-; GFX9-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; GFX9-NEXT: v_cmp_eq_f32_e64 vcc, |v3|, |v7|
-; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB12_27
-; GFX9-NEXT: s_branch .LBB12_32
-; GFX9-NEXT: .LBB12_26:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr11
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB12_32
-; GFX9-NEXT: .LBB12_27: ; %frem.compute
+; GFX9-NEXT: v_cmp_gt_f32_e64 vcc, |v3|, |v7|
+; GFX9-NEXT: s_cbranch_vccz .LBB12_7
+; GFX9-NEXT: .LBB12_20: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; GFX9-NEXT: v_ldexp_f32 v12, v12, 1
; GFX9-NEXT: v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
-; GFX9-NEXT: v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
+; GFX9-NEXT: v_div_scale_f32 v14, vcc, 1.0, v12, 1.0
; GFX9-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v16, v3
-; GFX9-NEXT: v_ldexp_f32 v14, v11, 12
+; GFX9-NEXT: v_ldexp_f32 v15, v11, 12
; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v17, v7
; GFX9-NEXT: v_add_u32_e32 v11, -1, v17
; GFX9-NEXT: v_not_b32_e32 v13, v11
@@ -14507,37 +13517,38 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
; GFX9-NEXT: v_fma_f32 v20, -v18, v19, 1.0
; GFX9-NEXT: v_fma_f32 v19, v20, v19, v19
-; GFX9-NEXT: v_mul_f32_e32 v20, v15, v19
-; GFX9-NEXT: v_fma_f32 v21, -v18, v20, v15
+; GFX9-NEXT: v_mul_f32_e32 v20, v14, v19
+; GFX9-NEXT: v_fma_f32 v21, -v18, v20, v14
; GFX9-NEXT: v_fma_f32 v20, v21, v19, v20
-; GFX9-NEXT: v_fma_f32 v15, -v18, v20, v15
+; GFX9-NEXT: v_fma_f32 v14, -v18, v20, v14
; GFX9-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT: v_div_fmas_f32 v15, v15, v19, v20
+; GFX9-NEXT: v_div_fmas_f32 v14, v14, v19, v20
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 13, v13
-; GFX9-NEXT: v_div_fixup_f32 v15, v15, v12, 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_31
-; GFX9-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_23
+; GFX9-NEXT: ; %bb.21: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v13, v16, v17
; GFX9-NEXT: v_add_u32_e32 v13, 12, v13
-; GFX9-NEXT: .LBB12_29: ; %frem.loop_body
+; GFX9-NEXT: .LBB12_22: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v16, v14
-; GFX9-NEXT: v_mul_f32_e32 v14, v16, v15
-; GFX9-NEXT: v_rndne_f32_e32 v14, v14
-; GFX9-NEXT: v_fma_f32 v14, -v14, v12, v16
-; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v14
-; GFX9-NEXT: v_add_f32_e32 v17, v14, v12
+; GFX9-NEXT: v_mov_b32_e32 v16, v15
+; GFX9-NEXT: v_mul_f32_e32 v15, v16, v14
+; GFX9-NEXT: v_rndne_f32_e32 v15, v15
+; GFX9-NEXT: v_fma_f32 v15, -v15, v12, v16
+; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v15
+; GFX9-NEXT: v_add_f32_e32 v17, v15, v12
+; GFX9-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
; GFX9-NEXT: v_add_u32_e32 v13, -12, v13
-; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
+; GFX9-NEXT: v_ldexp_f32 v15, v15, 12
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 12, v13
-; GFX9-NEXT: v_ldexp_f32 v14, v14, 12
-; GFX9-NEXT: s_cbranch_vccnz .LBB12_29
-; GFX9-NEXT: ; %bb.30: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v14, v16
-; GFX9-NEXT: .LBB12_31: ; %frem.loop_exit
+; GFX9-NEXT: s_cbranch_vccnz .LBB12_22
+; GFX9-NEXT: s_branch .LBB12_24
+; GFX9-NEXT: .LBB12_23:
+; GFX9-NEXT: v_mov_b32_e32 v16, v15
+; GFX9-NEXT: .LBB12_24: ; %frem.loop_exit
; GFX9-NEXT: v_add_u32_e32 v13, -11, v13
-; GFX9-NEXT: v_ldexp_f32 v13, v14, v13
-; GFX9-NEXT: v_mul_f32_e32 v14, v13, v15
+; GFX9-NEXT: v_ldexp_f32 v13, v16, v13
+; GFX9-NEXT: v_mul_f32_e32 v14, v13, v14
; GFX9-NEXT: v_rndne_f32_e32 v14, v14
; GFX9-NEXT: v_fma_f32 v13, -v14, v12, v13
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v13
@@ -14546,7 +13557,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_ldexp_f32 v11, v12, v11
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_bfi_b32 v11, s2, v11, v3
-; GFX9-NEXT: .LBB12_32: ; %Flow116
+; GFX9-NEXT: .LBB12_25:
; GFX9-NEXT: s_mov_b32 s4, 0x7f800000
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, 0, v4
; GFX9-NEXT: v_cmp_nge_f32_e64 s[2:3], |v0|, s4
@@ -14580,23 +13591,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3]
; GFX10-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v4|
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB12_2
-; GFX10-NEXT: ; %bb.1: ; %frem.else78
-; GFX10-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_3
-; GFX10-NEXT: s_branch .LBB12_8
-; GFX10-NEXT: .LBB12_2:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr8
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB12_8
-; GFX10-NEXT: .LBB12_3: ; %frem.compute77
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v4|
+; GFX10-NEXT: s_cbranch_vccz .LBB12_5
+; GFX10-NEXT: ; %bb.1: ; %frem.compute77
; GFX10-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; GFX10-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v11, v0
@@ -14622,11 +13619,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v11, v11, v14, v15
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v12
; GFX10-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_7
-; GFX10-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_9
+; GFX10-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_5: ; %frem.loop_body85
+; GFX10-NEXT: .LBB12_3: ; %frem.loop_body85
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v13, v10
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -14638,13 +13635,38 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v12, v10, v9
; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v10, v10, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_5
-; GFX10-NEXT: ; %bb.6: ; %Flow125
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_3
+; GFX10-NEXT: ; %bb.4:
; GFX10-NEXT: v_mov_b32_e32 v12, s2
-; GFX10-NEXT: v_mov_b32_e32 v10, v13
-; GFX10-NEXT: .LBB12_7: ; %frem.loop_exit86
-; GFX10-NEXT: v_add_nc_u32_e32 v12, -11, v12
-; GFX10-NEXT: v_ldexp_f32 v10, v10, v12
+; GFX10-NEXT: s_branch .LBB12_10
+; GFX10-NEXT: .LBB12_5: ; %frem.else78
+; GFX10-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v5|
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_11
+; GFX10-NEXT: .LBB12_6: ; %frem.else47
+; GFX10-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v2|, |v6|
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_17
+; GFX10-NEXT: .LBB12_7: ; %frem.else16
+; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v3|, |v7|
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_23
+; GFX10-NEXT: .LBB12_8: ; %frem.else
+; GFX10-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc_lo
+; GFX10-NEXT: s_branch .LBB12_29
+; GFX10-NEXT: .LBB12_9:
+; GFX10-NEXT: v_mov_b32_e32 v13, v10
+; GFX10-NEXT: .LBB12_10: ; %frem.loop_exit86
+; GFX10-NEXT: v_add_nc_u32_e32 v10, -11, v12
+; GFX10-NEXT: v_ldexp_f32 v10, v13, v10
; GFX10-NEXT: v_mul_f32_e32 v11, v10, v11
; GFX10-NEXT: v_rndne_f32_e32 v11, v11
; GFX10-NEXT: v_fma_f32 v10, -v11, v9, v10
@@ -14653,23 +13675,8 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v8, v9, v8
; GFX10-NEXT: v_bfi_b32 v8, 0x7fffffff, v8, v0
-; GFX10-NEXT: .LBB12_8:
-; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v5|
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB12_10
-; GFX10-NEXT: ; %bb.9: ; %frem.else47
-; GFX10-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_11
-; GFX10-NEXT: s_branch .LBB12_16
-; GFX10-NEXT: .LBB12_10:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr9
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB12_16
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v5|
+; GFX10-NEXT: s_cbranch_vccz .LBB12_6
; GFX10-NEXT: .LBB12_11: ; %frem.compute46
; GFX10-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; GFX10-NEXT: v_frexp_mant_f32_e64 v9, |v1|
@@ -14713,12 +13720,14 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v11, v11, 12
; GFX10-NEXT: s_cbranch_scc1 .LBB12_13
-; GFX10-NEXT: ; %bb.14: ; %Flow121
+; GFX10-NEXT: ; %bb.14:
; GFX10-NEXT: v_mov_b32_e32 v13, s2
-; GFX10-NEXT: v_mov_b32_e32 v11, v14
-; GFX10-NEXT: .LBB12_15: ; %frem.loop_exit55
-; GFX10-NEXT: v_add_nc_u32_e32 v13, -11, v13
-; GFX10-NEXT: v_ldexp_f32 v11, v11, v13
+; GFX10-NEXT: s_branch .LBB12_16
+; GFX10-NEXT: .LBB12_15:
+; GFX10-NEXT: v_mov_b32_e32 v14, v11
+; GFX10-NEXT: .LBB12_16: ; %frem.loop_exit55
+; GFX10-NEXT: v_add_nc_u32_e32 v11, -11, v13
+; GFX10-NEXT: v_ldexp_f32 v11, v14, v11
; GFX10-NEXT: v_mul_f32_e32 v12, v11, v12
; GFX10-NEXT: v_rndne_f32_e32 v12, v12
; GFX10-NEXT: v_fma_f32 v11, -v12, v10, v11
@@ -14727,24 +13736,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v9, v10, v9
; GFX10-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX10-NEXT: .LBB12_16:
-; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v2|, |v6|
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB12_18
-; GFX10-NEXT: ; %bb.17: ; %frem.else16
-; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_19
-; GFX10-NEXT: s_branch .LBB12_24
-; GFX10-NEXT: .LBB12_18:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr10
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB12_24
-; GFX10-NEXT: .LBB12_19: ; %frem.compute15
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v2|, |v6|
+; GFX10-NEXT: s_cbranch_vccz .LBB12_7
+; GFX10-NEXT: .LBB12_17: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; GFX10-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v13, v2
@@ -14770,11 +13764,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v13, v13, v16, v17
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v14
; GFX10-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_23
-; GFX10-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_21
+; GFX10-NEXT: ; %bb.18: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_21: ; %frem.loop_body23
+; GFX10-NEXT: .LBB12_19: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v15, v12
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -14786,13 +13780,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v14, v12, v11
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v12, v12, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_21
-; GFX10-NEXT: ; %bb.22: ; %Flow117
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_19
+; GFX10-NEXT: ; %bb.20:
; GFX10-NEXT: v_mov_b32_e32 v14, s2
-; GFX10-NEXT: v_mov_b32_e32 v12, v15
-; GFX10-NEXT: .LBB12_23: ; %frem.loop_exit24
-; GFX10-NEXT: v_add_nc_u32_e32 v14, -11, v14
-; GFX10-NEXT: v_ldexp_f32 v12, v12, v14
+; GFX10-NEXT: s_branch .LBB12_22
+; GFX10-NEXT: .LBB12_21:
+; GFX10-NEXT: v_mov_b32_e32 v15, v12
+; GFX10-NEXT: .LBB12_22: ; %frem.loop_exit24
+; GFX10-NEXT: v_add_nc_u32_e32 v12, -11, v14
+; GFX10-NEXT: v_ldexp_f32 v12, v15, v12
; GFX10-NEXT: v_mul_f32_e32 v13, v12, v13
; GFX10-NEXT: v_rndne_f32_e32 v13, v13
; GFX10-NEXT: v_fma_f32 v12, -v13, v11, v12
@@ -14801,24 +13797,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v11, v12, v11, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v10, v11, v10
; GFX10-NEXT: v_bfi_b32 v10, 0x7fffffff, v10, v2
-; GFX10-NEXT: .LBB12_24:
-; GFX10-NEXT: v_cmp_ngt_f32_e64 s2, |v3|, |v7|
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB12_26
-; GFX10-NEXT: ; %bb.25: ; %frem.else
-; GFX10-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; GFX10-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_27
-; GFX10-NEXT: s_branch .LBB12_32
-; GFX10-NEXT: .LBB12_26:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr11
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB12_32
-; GFX10-NEXT: .LBB12_27: ; %frem.compute
+; GFX10-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v3|, |v7|
+; GFX10-NEXT: s_cbranch_vccz .LBB12_8
+; GFX10-NEXT: .LBB12_23: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; GFX10-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v14, v3
@@ -14844,11 +13825,11 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_div_fmas_f32 v14, v14, v17, v18
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v15
; GFX10-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB12_31
-; GFX10-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB12_27
+; GFX10-NEXT: ; %bb.24: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 12
-; GFX10-NEXT: .LBB12_29: ; %frem.loop_body
+; GFX10-NEXT: .LBB12_25: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: v_mov_b32_e32 v16, v13
; GFX10-NEXT: s_add_i32 s2, s2, -12
@@ -14860,13 +13841,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_add_f32_e32 v15, v13, v12
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v13, v13, 12
-; GFX10-NEXT: s_cbranch_scc1 .LBB12_29
-; GFX10-NEXT: ; %bb.30: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB12_25
+; GFX10-NEXT: ; %bb.26:
; GFX10-NEXT: v_mov_b32_e32 v15, s2
-; GFX10-NEXT: v_mov_b32_e32 v13, v16
-; GFX10-NEXT: .LBB12_31: ; %frem.loop_exit
-; GFX10-NEXT: v_add_nc_u32_e32 v15, -11, v15
-; GFX10-NEXT: v_ldexp_f32 v13, v13, v15
+; GFX10-NEXT: s_branch .LBB12_28
+; GFX10-NEXT: .LBB12_27:
+; GFX10-NEXT: v_mov_b32_e32 v16, v13
+; GFX10-NEXT: .LBB12_28: ; %frem.loop_exit
+; GFX10-NEXT: v_add_nc_u32_e32 v13, -11, v15
+; GFX10-NEXT: v_ldexp_f32 v13, v16, v13
; GFX10-NEXT: v_mul_f32_e32 v14, v13, v14
; GFX10-NEXT: v_rndne_f32_e32 v14, v14
; GFX10-NEXT: v_fma_f32 v13, -v14, v12, v13
@@ -14875,7 +13858,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc_lo
; GFX10-NEXT: v_ldexp_f32 v11, v12, v11
; GFX10-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX10-NEXT: .LBB12_32: ; %Flow116
+; GFX10-NEXT: .LBB12_29:
; GFX10-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX10-NEXT: v_mov_b32_e32 v4, 0
@@ -14907,24 +13890,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: global_load_b128 v[0:3], v4, s[2:3]
; GFX11-NEXT: global_load_b128 v[4:7], v4, s[4:5] offset:64
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v0|, |v4|
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB12_2
-; GFX11-NEXT: ; %bb.1: ; %frem.else78
-; GFX11-NEXT: v_and_b32_e32 v8, 0x80000000, v0
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_3
-; GFX11-NEXT: s_branch .LBB12_8
-; GFX11-NEXT: .LBB12_2:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr8
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB12_8
-; GFX11-NEXT: .LBB12_3: ; %frem.compute77
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v0|, |v4|
+; GFX11-NEXT: s_cbranch_vccz .LBB12_5
+; GFX11-NEXT: ; %bb.1: ; %frem.compute77
; GFX11-NEXT: v_frexp_mant_f32_e64 v9, |v4|
; GFX11-NEXT: v_frexp_mant_f32_e64 v8, |v0|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v11, v0
@@ -14959,12 +13927,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_7
-; GFX11-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_9
+; GFX11-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_5: ; %frem.loop_body85
+; GFX11-NEXT: .LBB12_3: ; %frem.loop_body85
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v13, v10
@@ -14980,14 +13948,43 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v10, v10, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_5
-; GFX11-NEXT: ; %bb.6: ; %Flow125
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_3
+; GFX11-NEXT: ; %bb.4:
; GFX11-NEXT: v_mov_b32_e32 v12, s2
-; GFX11-NEXT: v_mov_b32_e32 v10, v13
-; GFX11-NEXT: .LBB12_7: ; %frem.loop_exit86
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v12, -11, v12
-; GFX11-NEXT: v_ldexp_f32 v10, v10, v12
+; GFX11-NEXT: s_branch .LBB12_10
+; GFX11-NEXT: .LBB12_5: ; %frem.else78
+; GFX11-NEXT: v_and_b32_e32 v8, 0x80000000, v0
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v0, v8, vcc_lo
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v5|
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_11
+; GFX11-NEXT: .LBB12_6: ; %frem.else47
+; GFX11-NEXT: v_and_b32_e32 v9, 0x80000000, v1
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc_lo
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v2|, |v6|
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_17
+; GFX11-NEXT: .LBB12_7: ; %frem.else16
+; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v2
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc_lo
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v3|, |v7|
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_23
+; GFX11-NEXT: .LBB12_8: ; %frem.else
+; GFX11-NEXT: v_and_b32_e32 v11, 0x80000000, v3
+; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc_lo
+; GFX11-NEXT: s_branch .LBB12_29
+; GFX11-NEXT: .LBB12_9:
+; GFX11-NEXT: v_mov_b32_e32 v13, v10
+; GFX11-NEXT: .LBB12_10: ; %frem.loop_exit86
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v10, -11, v12
+; GFX11-NEXT: v_ldexp_f32 v10, v13, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v11, v10, v11
; GFX11-NEXT: v_rndne_f32_e32 v11, v11
@@ -15000,24 +13997,8 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v8, v9, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v8, 0x7fffffff, v8, v0
-; GFX11-NEXT: .LBB12_8:
-; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v1|, |v5|
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB12_10
-; GFX11-NEXT: ; %bb.9: ; %frem.else47
-; GFX11-NEXT: v_and_b32_e32 v9, 0x80000000, v1
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v9, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_11
-; GFX11-NEXT: s_branch .LBB12_16
-; GFX11-NEXT: .LBB12_10:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr9
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB12_16
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v1|, |v5|
+; GFX11-NEXT: s_cbranch_vccz .LBB12_6
; GFX11-NEXT: .LBB12_11: ; %frem.compute46
; GFX11-NEXT: v_frexp_mant_f32_e64 v10, |v5|
; GFX11-NEXT: v_frexp_mant_f32_e64 v9, |v1|
@@ -15075,13 +14056,15 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v11, v11, 12
; GFX11-NEXT: s_cbranch_scc1 .LBB12_13
-; GFX11-NEXT: ; %bb.14: ; %Flow121
+; GFX11-NEXT: ; %bb.14:
; GFX11-NEXT: v_mov_b32_e32 v13, s2
-; GFX11-NEXT: v_mov_b32_e32 v11, v14
-; GFX11-NEXT: .LBB12_15: ; %frem.loop_exit55
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v13, -11, v13
-; GFX11-NEXT: v_ldexp_f32 v11, v11, v13
+; GFX11-NEXT: s_branch .LBB12_16
+; GFX11-NEXT: .LBB12_15:
+; GFX11-NEXT: v_mov_b32_e32 v14, v11
+; GFX11-NEXT: .LBB12_16: ; %frem.loop_exit55
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v11, -11, v13
+; GFX11-NEXT: v_ldexp_f32 v11, v14, v11
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v12, v11, v12
; GFX11-NEXT: v_rndne_f32_e32 v12, v12
@@ -15094,25 +14077,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v9, v10, v9
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX11-NEXT: .LBB12_16:
-; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v2|, |v6|
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB12_18
-; GFX11-NEXT: ; %bb.17: ; %frem.else16
-; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v2
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v10, v2, v10, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_19
-; GFX11-NEXT: s_branch .LBB12_24
-; GFX11-NEXT: .LBB12_18:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr10
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB12_24
-; GFX11-NEXT: .LBB12_19: ; %frem.compute15
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v2|, |v6|
+; GFX11-NEXT: s_cbranch_vccz .LBB12_7
+; GFX11-NEXT: .LBB12_17: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f32_e64 v11, |v6|
; GFX11-NEXT: v_frexp_mant_f32_e64 v10, |v2|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v13, v2
@@ -15147,12 +14114,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v13, v13, v11, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_23
-; GFX11-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_21
+; GFX11-NEXT: ; %bb.18: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_21: ; %frem.loop_body23
+; GFX11-NEXT: .LBB12_19: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v15, v12
@@ -15168,14 +14135,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v12, v12, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_21
-; GFX11-NEXT: ; %bb.22: ; %Flow117
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_19
+; GFX11-NEXT: ; %bb.20:
; GFX11-NEXT: v_mov_b32_e32 v14, s2
-; GFX11-NEXT: v_mov_b32_e32 v12, v15
-; GFX11-NEXT: .LBB12_23: ; %frem.loop_exit24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v14, -11, v14
-; GFX11-NEXT: v_ldexp_f32 v12, v12, v14
+; GFX11-NEXT: s_branch .LBB12_22
+; GFX11-NEXT: .LBB12_21:
+; GFX11-NEXT: v_mov_b32_e32 v15, v12
+; GFX11-NEXT: .LBB12_22: ; %frem.loop_exit24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v12, -11, v14
+; GFX11-NEXT: v_ldexp_f32 v12, v15, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v13, v12, v13
; GFX11-NEXT: v_rndne_f32_e32 v13, v13
@@ -15188,25 +14157,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v10, v11, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v10, 0x7fffffff, v10, v2
-; GFX11-NEXT: .LBB12_24:
-; GFX11-NEXT: v_cmp_ngt_f32_e64 s2, |v3|, |v7|
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB12_26
-; GFX11-NEXT: ; %bb.25: ; %frem.else
-; GFX11-NEXT: v_and_b32_e32 v11, 0x80000000, v3
-; GFX11-NEXT: v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: v_cndmask_b32_e32 v11, v3, v11, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_27
-; GFX11-NEXT: s_branch .LBB12_32
-; GFX11-NEXT: .LBB12_26:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr11
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB12_32
-; GFX11-NEXT: .LBB12_27: ; %frem.compute
+; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, |v3|, |v7|
+; GFX11-NEXT: s_cbranch_vccz .LBB12_8
+; GFX11-NEXT: .LBB12_23: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f32_e64 v12, |v7|
; GFX11-NEXT: v_frexp_mant_f32_e64 v11, |v3|
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v14, v3
@@ -15241,12 +14194,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v15
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB12_31
-; GFX11-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB12_27
+; GFX11-NEXT: ; %bb.24: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 12
-; GFX11-NEXT: .LBB12_29: ; %frem.loop_body
+; GFX11-NEXT: .LBB12_25: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v16, v13
@@ -15262,14 +14215,16 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX11-NEXT: v_ldexp_f32 v13, v13, 12
-; GFX11-NEXT: s_cbranch_scc1 .LBB12_29
-; GFX11-NEXT: ; %bb.30: ; %Flow
+; GFX11-NEXT: s_cbranch_scc1 .LBB12_25
+; GFX11-NEXT: ; %bb.26:
; GFX11-NEXT: v_mov_b32_e32 v15, s2
-; GFX11-NEXT: v_mov_b32_e32 v13, v16
-; GFX11-NEXT: .LBB12_31: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v15, -11, v15
-; GFX11-NEXT: v_ldexp_f32 v13, v13, v15
+; GFX11-NEXT: s_branch .LBB12_28
+; GFX11-NEXT: .LBB12_27:
+; GFX11-NEXT: v_mov_b32_e32 v16, v13
+; GFX11-NEXT: .LBB12_28: ; %frem.loop_exit
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v13, -11, v15
+; GFX11-NEXT: v_ldexp_f32 v13, v16, v13
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v14, v13, v14
; GFX11-NEXT: v_rndne_f32_e32 v14, v14
@@ -15282,7 +14237,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f32 v11, v12, v11
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX11-NEXT: .LBB12_32: ; %Flow116
+; GFX11-NEXT: .LBB12_29:
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
; GFX11-NEXT: v_mov_b32_e32 v4, 0
@@ -15325,26 +14280,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_readfirstlane_b32 s2, v4
; GFX1150-NEXT: s_and_b32 s11, s6, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_ngt_f32 s5, s11
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_2
-; GFX1150-NEXT: ; %bb.1: ; %frem.else78
-; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s8
-; GFX1150-NEXT: s_cmp_eq_f32 s5, s11
-; GFX1150-NEXT: v_mov_b32_e32 v0, s12
-; GFX1150-NEXT: s_mov_b32 s11, 0
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
-; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_3
-; GFX1150-NEXT: s_branch .LBB12_8
-; GFX1150-NEXT: .LBB12_2:
-; GFX1150-NEXT: s_mov_b32 s11, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr0
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_8
-; GFX1150-NEXT: .LBB12_3: ; %frem.compute77
+; GFX1150-NEXT: s_cmp_gt_f32 s5, s11
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_5
+; GFX1150-NEXT: ; %bb.1: ; %frem.compute77
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s6|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v0, |s8|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
@@ -15378,12 +14316,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1150-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_7
-; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body85.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_6
+; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_5: ; %frem.loop_body85
+; GFX1150-NEXT: .LBB12_3: ; %frem.loop_body85
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v5, v2
@@ -15401,14 +14339,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v2, v2, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_5
-; GFX1150-NEXT: ; %bb.6: ; %Flow125
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_3
+; GFX1150-NEXT: ; %bb.4:
; GFX1150-NEXT: v_mov_b32_e32 v4, s11
-; GFX1150-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-NEXT: s_branch .LBB12_7
+; GFX1150-NEXT: .LBB12_5: ; %frem.else78
+; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s8
+; GFX1150-NEXT: s_cmp_eq_f32 s5, s11
+; GFX1150-NEXT: v_mov_b32_e32 v0, s12
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v0, s8, v0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB12_8
+; GFX1150-NEXT: .LBB12_6:
+; GFX1150-NEXT: v_mov_b32_e32 v5, v2
; GFX1150-NEXT: .LBB12_7: ; %frem.loop_exit86
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v4, -11, v4
-; GFX1150-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v2, -11, v4
+; GFX1150-NEXT: v_ldexp_f32 v2, v5, v2
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-NEXT: v_rndne_f32_e32 v3, v3
@@ -15426,26 +14374,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_and_b32 s8, s10, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s11, s4, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_ngt_f32 s8, s11
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_10
-; GFX1150-NEXT: ; %bb.9: ; %frem.else47
-; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s10
-; GFX1150-NEXT: s_cmp_eq_f32 s8, s11
-; GFX1150-NEXT: v_mov_b32_e32 v1, s12
-; GFX1150-NEXT: s_mov_b32 s11, 0
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v1, s10, v1, vcc_lo
-; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_11
-; GFX1150-NEXT: s_branch .LBB12_16
-; GFX1150-NEXT: .LBB12_10:
-; GFX1150-NEXT: s_mov_b32 s11, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr1
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_16
-; GFX1150-NEXT: .LBB12_11: ; %frem.compute46
+; GFX1150-NEXT: s_cmp_gt_f32 s8, s11
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_13
+; GFX1150-NEXT: ; %bb.9: ; %frem.compute46
; GFX1150-NEXT: v_frexp_mant_f32_e64 v2, |s4|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v1, |s10|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
@@ -15479,12 +14410,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1150-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_15
-; GFX1150-NEXT: ; %bb.12: ; %frem.loop_body54.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_14
+; GFX1150-NEXT: ; %bb.10: ; %frem.loop_body54.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_13: ; %frem.loop_body54
+; GFX1150-NEXT: .LBB12_11: ; %frem.loop_body54
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v6, v3
@@ -15502,14 +14433,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_13
-; GFX1150-NEXT: ; %bb.14: ; %Flow121
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_11
+; GFX1150-NEXT: ; %bb.12:
; GFX1150-NEXT: v_mov_b32_e32 v5, s11
-; GFX1150-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-NEXT: s_branch .LBB12_15
+; GFX1150-NEXT: .LBB12_13: ; %frem.else47
+; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s10
+; GFX1150-NEXT: s_cmp_eq_f32 s8, s11
+; GFX1150-NEXT: v_mov_b32_e32 v1, s12
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v1, s10, v1, vcc_lo
+; GFX1150-NEXT: s_branch .LBB12_16
+; GFX1150-NEXT: .LBB12_14:
+; GFX1150-NEXT: v_mov_b32_e32 v6, v3
; GFX1150-NEXT: .LBB12_15: ; %frem.loop_exit55
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v5, -11, v5
-; GFX1150-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v3, -11, v5
+; GFX1150-NEXT: v_ldexp_f32 v3, v6, v3
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-NEXT: v_rndne_f32_e32 v4, v4
@@ -15527,26 +14468,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_and_b32 s10, s9, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s11, s3, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_ngt_f32 s10, s11
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_18
-; GFX1150-NEXT: ; %bb.17: ; %frem.else16
-; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s9
-; GFX1150-NEXT: s_cmp_eq_f32 s10, s11
-; GFX1150-NEXT: v_mov_b32_e32 v2, s12
-; GFX1150-NEXT: s_mov_b32 s11, 0
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v2, s9, v2, vcc_lo
-; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_19
-; GFX1150-NEXT: s_branch .LBB12_24
-; GFX1150-NEXT: .LBB12_18:
-; GFX1150-NEXT: s_mov_b32 s11, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr2
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_24
-; GFX1150-NEXT: .LBB12_19: ; %frem.compute15
+; GFX1150-NEXT: s_cmp_gt_f32 s10, s11
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_21
+; GFX1150-NEXT: ; %bb.17: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f32_e64 v3, |s3|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v2, |s9|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
@@ -15580,12 +14504,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX1150-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_23
-; GFX1150-NEXT: ; %bb.20: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_22
+; GFX1150-NEXT: ; %bb.18: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_21: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB12_19: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v7, v4
@@ -15603,14 +14527,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_21
-; GFX1150-NEXT: ; %bb.22: ; %Flow117
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_19
+; GFX1150-NEXT: ; %bb.20:
; GFX1150-NEXT: v_mov_b32_e32 v6, s11
-; GFX1150-NEXT: v_mov_b32_e32 v4, v7
+; GFX1150-NEXT: s_branch .LBB12_23
+; GFX1150-NEXT: .LBB12_21: ; %frem.else16
+; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s9
+; GFX1150-NEXT: s_cmp_eq_f32 s10, s11
+; GFX1150-NEXT: v_mov_b32_e32 v2, s12
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v2, s9, v2, vcc_lo
+; GFX1150-NEXT: s_branch .LBB12_24
+; GFX1150-NEXT: .LBB12_22:
+; GFX1150-NEXT: v_mov_b32_e32 v7, v4
; GFX1150-NEXT: .LBB12_23: ; %frem.loop_exit24
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v6, -11, v6
-; GFX1150-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v4, -11, v6
+; GFX1150-NEXT: v_ldexp_f32 v4, v7, v4
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-NEXT: v_rndne_f32_e32 v5, v5
@@ -15628,26 +14562,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_and_b32 s9, s7, 0x7fffffff
; GFX1150-NEXT: s_and_b32 s11, s2, 0x7fffffff
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_cmp_ngt_f32 s9, s11
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_26
-; GFX1150-NEXT: ; %bb.25: ; %frem.else
-; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s7
-; GFX1150-NEXT: s_cmp_eq_f32 s9, s11
-; GFX1150-NEXT: v_mov_b32_e32 v3, s12
-; GFX1150-NEXT: s_mov_b32 s11, 0
-; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v3, s7, v3, vcc_lo
-; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_27
-; GFX1150-NEXT: s_branch .LBB12_32
-; GFX1150-NEXT: .LBB12_26:
-; GFX1150-NEXT: s_mov_b32 s11, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr3
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s11, s11, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB12_32
-; GFX1150-NEXT: .LBB12_27: ; %frem.compute
+; GFX1150-NEXT: s_cmp_gt_f32 s9, s11
+; GFX1150-NEXT: s_cbranch_scc0 .LBB12_29
+; GFX1150-NEXT: ; %bb.25: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f32_e64 v4, |s2|
; GFX1150-NEXT: v_frexp_mant_f32_e64 v3, |s7|
; GFX1150-NEXT: v_frexp_exp_i32_f32_e32 v6, s7
@@ -15681,12 +14598,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1150-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB12_31
-; GFX1150-NEXT: ; %bb.28: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB12_30
+; GFX1150-NEXT: ; %bb.26: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s11, s11, s12
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s11, s11, 12
-; GFX1150-NEXT: .LBB12_29: ; %frem.loop_body
+; GFX1150-NEXT: .LBB12_27: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v8, v5
@@ -15704,14 +14621,24 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1150-NEXT: s_cbranch_scc1 .LBB12_29
-; GFX1150-NEXT: ; %bb.30: ; %Flow
+; GFX1150-NEXT: s_cbranch_scc1 .LBB12_27
+; GFX1150-NEXT: ; %bb.28:
; GFX1150-NEXT: v_mov_b32_e32 v7, s11
-; GFX1150-NEXT: v_mov_b32_e32 v5, v8
+; GFX1150-NEXT: s_branch .LBB12_31
+; GFX1150-NEXT: .LBB12_29: ; %frem.else
+; GFX1150-NEXT: s_and_b32 s12, 0x80000000, s7
+; GFX1150-NEXT: s_cmp_eq_f32 s9, s11
+; GFX1150-NEXT: v_mov_b32_e32 v3, s12
+; GFX1150-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v3, s7, v3, vcc_lo
+; GFX1150-NEXT: s_branch .LBB12_32
+; GFX1150-NEXT: .LBB12_30:
+; GFX1150-NEXT: v_mov_b32_e32 v8, v5
; GFX1150-NEXT: .LBB12_31: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_add_nc_u32_e32 v7, -11, v7
-; GFX1150-NEXT: v_ldexp_f32 v5, v5, v7
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_add_nc_u32_e32 v5, -11, v7
+; GFX1150-NEXT: v_ldexp_f32 v5, v8, v5
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1150-NEXT: v_rndne_f32_e32 v6, v6
@@ -15725,7 +14652,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f32 v3, v4, v3
; GFX1150-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, s7
-; GFX1150-NEXT: .LBB12_32: ; %Flow116
+; GFX1150-NEXT: .LBB12_32:
; GFX1150-NEXT: s_cmp_lg_f32 s6, 0
; GFX1150-NEXT: v_mov_b32_e32 v4, 0
; GFX1150-NEXT: s_cselect_b32 s6, -1, 0
@@ -15780,26 +14707,9 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_readfirstlane_b32 s2, v4
; GFX1200-NEXT: s_and_b32 s11, s6, 0x7fffffff
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_cmp_ngt_f32 s5, s11
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_3
-; GFX1200-NEXT: ; %bb.1: ; %frem.else78
-; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s8
-; GFX1200-NEXT: s_cmp_eq_f32 s5, s11
-; GFX1200-NEXT: s_cselect_b32 s11, s12, s8
-; GFX1200-NEXT: s_mov_b32 s12, 0
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_4
-; GFX1200-NEXT: .LBB12_2:
-; GFX1200-NEXT: v_mov_b32_e32 v0, s11
-; GFX1200-NEXT: s_branch .LBB12_9
-; GFX1200-NEXT: .LBB12_3:
-; GFX1200-NEXT: s_mov_b32 s12, -1
-; GFX1200-NEXT: ; implicit-def: $sgpr11
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_2
-; GFX1200-NEXT: .LBB12_4: ; %frem.compute77
+; GFX1200-NEXT: s_cmp_gt_f32 s5, s11
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_5
+; GFX1200-NEXT: ; %bb.1: ; %frem.compute77
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s6|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v0, |s8|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
@@ -15833,12 +14743,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v3, v3, v6, v7
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
; GFX1200-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_8
-; GFX1200-NEXT: ; %bb.5: ; %frem.loop_body85.preheader
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_6
+; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body85.preheader
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_6: ; %frem.loop_body85
+; GFX1200-NEXT: .LBB12_3: ; %frem.loop_body85
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1200-NEXT: v_mov_b32_e32 v5, v2
@@ -15857,14 +14767,23 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v2, v2, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_6
-; GFX1200-NEXT: ; %bb.7: ; %Flow125
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_3
+; GFX1200-NEXT: ; %bb.4:
; GFX1200-NEXT: v_mov_b32_e32 v4, s11
-; GFX1200-NEXT: v_mov_b32_e32 v2, v5
-; GFX1200-NEXT: .LBB12_8: ; %frem.loop_exit86
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v4, -11, v4
-; GFX1200-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1200-NEXT: s_branch .LBB12_7
+; GFX1200-NEXT: .LBB12_5: ; %frem.else78
+; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s8
+; GFX1200-NEXT: s_cmp_eq_f32 s5, s11
+; GFX1200-NEXT: s_cselect_b32 s8, s12, s8
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: v_mov_b32_e32 v0, s8
+; GFX1200-NEXT: s_branch .LBB12_8
+; GFX1200-NEXT: .LBB12_6:
+; GFX1200-NEXT: v_mov_b32_e32 v5, v2
+; GFX1200-NEXT: .LBB12_7: ; %frem.loop_exit86
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v2, -11, v4
+; GFX1200-NEXT: v_ldexp_f32 v2, v5, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-NEXT: v_rndne_f32_e32 v3, v3
@@ -15879,31 +14798,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v0, v1, v0
; GFX1200-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, s8
-; GFX1200-NEXT: .LBB12_9:
+; GFX1200-NEXT: .LBB12_8:
; GFX1200-NEXT: s_and_b32 s8, s10, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s11, s4, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cmp_ngt_f32 s8, s11
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_12
-; GFX1200-NEXT: ; %bb.10: ; %frem.else47
-; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s10
-; GFX1200-NEXT: s_cmp_eq_f32 s8, s11
-; GFX1200-NEXT: s_cselect_b32 s11, s12, s10
-; GFX1200-NEXT: s_mov_b32 s12, 0
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_13
-; GFX1200-NEXT: .LBB12_11:
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v1, s11
-; GFX1200-NEXT: s_branch .LBB12_18
-; GFX1200-NEXT: .LBB12_12:
-; GFX1200-NEXT: s_mov_b32 s12, -1
-; GFX1200-NEXT: ; implicit-def: $sgpr11
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_11
-; GFX1200-NEXT: .LBB12_13: ; %frem.compute46
+; GFX1200-NEXT: s_cmp_gt_f32 s8, s11
+; GFX1200-NEXT: s_cbranch_scc0 .LBB12_13
+; GFX1200-NEXT: ; %bb.9: ; %frem.compute46
; GFX1200-NEXT: v_frexp_mant_f32_e64 v2, |s4|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v1, |s10|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
@@ -15938,13 +14839,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v4, v4, v7, v8
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v5
; GFX1200-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_17
-; GFX1200-NEXT: ; %bb.14: ; %frem.loop_body54.preheader
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_14
+; GFX1200-NEXT: ; %bb.10: ; %frem.loop_body54.preheader
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_15: ; %frem.loop_body54
+; GFX1200-NEXT: .LBB12_11: ; %frem.loop_body54
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v6, v3
@@ -15964,14 +14864,23 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v3, v3, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_15
-; GFX1200-NEXT: ; %bb.16: ; %Flow121
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_11
+; GFX1200-NEXT: ; %bb.12:
; GFX1200-NEXT: v_mov_b32_e32 v5, s11
-; GFX1200-NEXT: v_mov_b32_e32 v3, v6
-; GFX1200-NEXT: .LBB12_17: ; %frem.loop_exit55
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v5, -11, v5
-; GFX1200-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1200-NEXT: s_branch .LBB12_15
+; GFX1200-NEXT: .LBB12_13: ; %frem.else47
+; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s10
+; GFX1200-NEXT: s_cmp_eq_f32 s8, s11
+; GFX1200-NEXT: s_cselect_b32 s10, s12, s10
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v1, s10
+; GFX1200-NEXT: s_branch .LBB12_16
+; GFX1200-NEXT: .LBB12_14:
+; GFX1200-NEXT: v_mov_b32_e32 v6, v3
+; GFX1200-NEXT: .LBB12_15: ; %frem.loop_exit55
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v3, -11, v5
+; GFX1200-NEXT: v_ldexp_f32 v3, v6, v3
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-NEXT: v_rndne_f32_e32 v4, v4
@@ -15986,31 +14895,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v1, v2, v1
; GFX1200-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s10
-; GFX1200-NEXT: .LBB12_18:
+; GFX1200-NEXT: .LBB12_16:
; GFX1200-NEXT: s_and_b32 s10, s9, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s11, s3, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cmp_ngt_f32 s10, s11
+; GFX1200-NEXT: s_cmp_gt_f32 s10, s11
; GFX1200-NEXT: s_cbranch_scc0 .LBB12_21
-; GFX1200-NEXT: ; %bb.19: ; %frem.else16
-; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s9
-; GFX1200-NEXT: s_cmp_eq_f32 s10, s11
-; GFX1200-NEXT: s_cselect_b32 s11, s12, s9
-; GFX1200-NEXT: s_mov_b32 s12, 0
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_22
-; GFX1200-NEXT: .LBB12_20:
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v2, s11
-; GFX1200-NEXT: s_branch .LBB12_27
-; GFX1200-NEXT: .LBB12_21:
-; GFX1200-NEXT: s_mov_b32 s12, -1
-; GFX1200-NEXT: ; implicit-def: $sgpr11
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_20
-; GFX1200-NEXT: .LBB12_22: ; %frem.compute15
+; GFX1200-NEXT: ; %bb.17: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f32_e64 v3, |s3|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v2, |s9|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
@@ -16045,13 +14936,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v5, v5, v8, v9
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v6
; GFX1200-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_26
-; GFX1200-NEXT: ; %bb.23: ; %frem.loop_body23.preheader
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_22
+; GFX1200-NEXT: ; %bb.18: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_24: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB12_19: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v7, v4
@@ -16071,14 +14961,23 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v4, v4, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_24
-; GFX1200-NEXT: ; %bb.25: ; %Flow117
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_19
+; GFX1200-NEXT: ; %bb.20:
; GFX1200-NEXT: v_mov_b32_e32 v6, s11
-; GFX1200-NEXT: v_mov_b32_e32 v4, v7
-; GFX1200-NEXT: .LBB12_26: ; %frem.loop_exit24
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v6, -11, v6
-; GFX1200-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1200-NEXT: s_branch .LBB12_23
+; GFX1200-NEXT: .LBB12_21: ; %frem.else16
+; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s9
+; GFX1200-NEXT: s_cmp_eq_f32 s10, s11
+; GFX1200-NEXT: s_cselect_b32 s9, s12, s9
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v2, s9
+; GFX1200-NEXT: s_branch .LBB12_24
+; GFX1200-NEXT: .LBB12_22:
+; GFX1200-NEXT: v_mov_b32_e32 v7, v4
+; GFX1200-NEXT: .LBB12_23: ; %frem.loop_exit24
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v4, -11, v6
+; GFX1200-NEXT: v_ldexp_f32 v4, v7, v4
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-NEXT: v_rndne_f32_e32 v5, v5
@@ -16093,31 +14992,13 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v2, v3, v2
; GFX1200-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s9
-; GFX1200-NEXT: .LBB12_27:
+; GFX1200-NEXT: .LBB12_24:
; GFX1200-NEXT: s_and_b32 s9, s7, 0x7fffffff
; GFX1200-NEXT: s_and_b32 s11, s2, 0x7fffffff
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cmp_ngt_f32 s9, s11
-; GFX1200-NEXT: s_cbranch_scc0 .LBB12_30
-; GFX1200-NEXT: ; %bb.28: ; %frem.else
-; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s7
-; GFX1200-NEXT: s_cmp_eq_f32 s9, s11
-; GFX1200-NEXT: s_cselect_b32 s11, s12, s7
-; GFX1200-NEXT: s_mov_b32 s12, 0
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_31
-; GFX1200-NEXT: .LBB12_29:
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_mov_b32_e32 v3, s11
-; GFX1200-NEXT: s_branch .LBB12_36
-; GFX1200-NEXT: .LBB12_30:
-; GFX1200-NEXT: s_mov_b32 s12, -1
-; GFX1200-NEXT: ; implicit-def: $sgpr11
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s12, s12, exec_lo
+; GFX1200-NEXT: s_cmp_gt_f32 s9, s11
; GFX1200-NEXT: s_cbranch_scc0 .LBB12_29
-; GFX1200-NEXT: .LBB12_31: ; %frem.compute
+; GFX1200-NEXT: ; %bb.25: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f32_e64 v4, |s2|
; GFX1200-NEXT: v_frexp_mant_f32_e64 v3, |s7|
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, s7
@@ -16152,13 +15033,12 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v7
; GFX1200-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB12_35
-; GFX1200-NEXT: ; %bb.32: ; %frem.loop_body.preheader
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_cbranch_vccnz .LBB12_30
+; GFX1200-NEXT: ; %bb.26: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s11, s11, s12
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s11, s11, 12
-; GFX1200-NEXT: .LBB12_33: ; %frem.loop_body
+; GFX1200-NEXT: .LBB12_27: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_mov_b32_e32 v8, v5
@@ -16178,14 +15058,23 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX1200-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1200-NEXT: s_cbranch_scc1 .LBB12_33
-; GFX1200-NEXT: ; %bb.34: ; %Flow
+; GFX1200-NEXT: s_cbranch_scc1 .LBB12_27
+; GFX1200-NEXT: ; %bb.28:
; GFX1200-NEXT: v_mov_b32_e32 v7, s11
-; GFX1200-NEXT: v_mov_b32_e32 v5, v8
-; GFX1200-NEXT: .LBB12_35: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_nc_u32_e32 v7, -11, v7
-; GFX1200-NEXT: v_ldexp_f32 v5, v5, v7
+; GFX1200-NEXT: s_branch .LBB12_31
+; GFX1200-NEXT: .LBB12_29: ; %frem.else
+; GFX1200-NEXT: s_and_b32 s12, 0x80000000, s7
+; GFX1200-NEXT: s_cmp_eq_f32 s9, s11
+; GFX1200-NEXT: s_cselect_b32 s7, s12, s7
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_mov_b32_e32 v3, s7
+; GFX1200-NEXT: s_branch .LBB12_32
+; GFX1200-NEXT: .LBB12_30:
+; GFX1200-NEXT: v_mov_b32_e32 v8, v5
+; GFX1200-NEXT: .LBB12_31: ; %frem.loop_exit
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_add_nc_u32_e32 v5, -11, v7
+; GFX1200-NEXT: v_ldexp_f32 v5, v8, v5
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1200-NEXT: v_rndne_f32_e32 v6, v6
@@ -16200,7 +15089,7 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_ldexp_f32 v3, v4, v3
; GFX1200-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, s7
-; GFX1200-NEXT: .LBB12_36: ; %Flow116
+; GFX1200-NEXT: .LBB12_32:
; GFX1200-NEXT: s_cmp_lg_f32 s6, 0
; GFX1200-NEXT: v_mov_b32_e32 v4, 0
; GFX1200-NEXT: s_cselect_b32 s6, -1, 0
@@ -16269,32 +15158,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_readfirstlane_b32 s10, v2
; SI-NEXT: v_mov_b32_e32 v0, s10
; SI-NEXT: v_mov_b32_e32 v1, s11
-; SI-NEXT: v_cmp_ngt_f64_e64 s[0:1], |s[6:7]|, |v[0:1]|
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[6:7]|, |v[0:1]|
; SI-NEXT: v_readfirstlane_b32 s4, v4
; SI-NEXT: v_readfirstlane_b32 s5, v5
-; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
-; SI-NEXT: s_cbranch_vccz .LBB13_3
-; SI-NEXT: ; %bb.1: ; %frem.else16
-; SI-NEXT: v_mov_b32_e32 v0, s10
-; SI-NEXT: v_mov_b32_e32 v1, s11
-; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[6:7]|, |v[0:1]|
-; SI-NEXT: s_and_b32 s12, s7, 0x80000000
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s1, s12, s7
-; SI-NEXT: s_cselect_b32 s0, 0, s6
-; SI-NEXT: s_mov_b64 s[12:13], 0
-; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
-; SI-NEXT: s_cbranch_scc1 .LBB13_4
-; SI-NEXT: .LBB13_2:
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: v_mov_b32_e32 v1, s1
-; SI-NEXT: s_branch .LBB13_9
-; SI-NEXT: .LBB13_3:
-; SI-NEXT: s_mov_b64 s[12:13], -1
-; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
-; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
-; SI-NEXT: s_cbranch_scc0 .LBB13_2
-; SI-NEXT: .LBB13_4: ; %frem.compute15
+; SI-NEXT: s_cbranch_vccz .LBB13_4
+; SI-NEXT: ; %bb.1: ; %frem.compute15
; SI-NEXT: s_and_b32 s0, s7, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[6:7]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -16306,7 +15174,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[6:7]
; SI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: s_cselect_b32 s13, s0, 0
+; SI-NEXT: s_cselect_b32 s15, s0, 0
; SI-NEXT: s_and_b32 s0, s11, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[10:11]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -16318,13 +15186,12 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[10:11]
; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1
; SI-NEXT: v_readfirstlane_b32 s0, v2
-; SI-NEXT: s_cselect_b32 s17, s0, 0
-; SI-NEXT: s_add_i32 s14, s17, -1
-; SI-NEXT: s_not_b32 s0, s14
-; SI-NEXT: s_add_i32 s16, s0, s13
+; SI-NEXT: s_cselect_b32 s16, s0, 0
+; SI-NEXT: s_add_i32 s13, s16, -1
+; SI-NEXT: s_not_b32 s0, s13
+; SI-NEXT: s_add_i32 s14, s0, s15
; SI-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], 1.0
-; SI-NEXT: s_brev_b32 s15, -2
-; SI-NEXT: s_mov_b32 s12, -1
+; SI-NEXT: s_brev_b32 s12, -2
; SI-NEXT: v_rcp_f64_e32 v[6:7], v[2:3]
; SI-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
; SI-NEXT: v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
@@ -16338,50 +15205,62 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], v[8:9]
; SI-NEXT: s_xor_b64 vcc, s[0:1], vcc
; SI-NEXT: v_div_fmas_f64 v[2:3], v[12:13], v[6:7], v[10:11]
-; SI-NEXT: s_cmp_lt_i32 s16, 27
+; SI-NEXT: s_cmp_lt_i32 s14, 27
; SI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0
-; SI-NEXT: s_cbranch_scc1 .LBB13_8
-; SI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
-; SI-NEXT: s_sub_i32 s0, s13, s17
-; SI-NEXT: s_add_i32 s16, s0, 26
-; SI-NEXT: s_mov_b32 s13, 0x432fffff
+; SI-NEXT: s_cbranch_scc1 .LBB13_5
+; SI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; SI-NEXT: s_sub_i32 s0, s15, s16
+; SI-NEXT: s_add_i32 s14, s0, 26
+; SI-NEXT: s_mov_b32 s0, -1
+; SI-NEXT: s_mov_b32 s1, 0x432fffff
; SI-NEXT: v_mov_b32_e32 v10, 0x43300000
-; SI-NEXT: v_mov_b32_e32 v6, 0
-; SI-NEXT: .LBB13_6: ; %frem.loop_body23
+; SI-NEXT: v_mov_b32_e32 v8, 0
+; SI-NEXT: .LBB13_3: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v9, v5
-; SI-NEXT: v_mov_b32_e32 v8, v4
-; SI-NEXT: v_mul_f64 v[4:5], v[8:9], v[2:3]
-; SI-NEXT: s_sub_i32 s16, s16, 26
-; SI-NEXT: v_bfi_b32 v7, s15, v10, v5
-; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[6:7]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[12:13]
-; SI-NEXT: v_add_f64 v[11:12], v[11:12], -v[6:7]
-; SI-NEXT: s_cmp_gt_i32 s16, 26
+; SI-NEXT: v_mov_b32_e32 v7, v5
+; SI-NEXT: v_mov_b32_e32 v6, v4
+; SI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3]
+; SI-NEXT: s_sub_i32 s14, s14, 26
+; SI-NEXT: v_bfi_b32 v9, s12, v10, v5
+; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[8:9]
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[0:1]
+; SI-NEXT: v_add_f64 v[11:12], v[11:12], -v[8:9]
+; SI-NEXT: s_cmp_gt_i32 s14, 26
; SI-NEXT: v_cndmask_b32_e32 v5, v12, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v11, v4, vcc
-; SI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[8:9]
+; SI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7]
; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; SI-NEXT: v_add_f64 v[11:12], v[4:5], v[0:1]
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc
; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; SI-NEXT: s_cbranch_scc1 .LBB13_6
-; SI-NEXT: ; %bb.7: ; %Flow51
-; SI-NEXT: v_mov_b32_e32 v4, v8
-; SI-NEXT: v_mov_b32_e32 v5, v9
-; SI-NEXT: .LBB13_8: ; %frem.loop_exit24
-; SI-NEXT: s_sub_i32 s0, s16, 25
-; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], s0
-; SI-NEXT: s_mov_b32 s0, -1
-; SI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
-; SI-NEXT: s_mov_b32 s1, 0x432fffff
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[0:1]
-; SI-NEXT: s_brev_b32 s0, -2
+; SI-NEXT: s_cbranch_scc1 .LBB13_3
+; SI-NEXT: s_branch .LBB13_6
+; SI-NEXT: .LBB13_4: ; %frem.else16
+; SI-NEXT: v_mov_b32_e32 v0, s10
+; SI-NEXT: v_mov_b32_e32 v1, s11
+; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[6:7]|, |v[0:1]|
+; SI-NEXT: s_and_b32 s12, s7, 0x80000000
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s1, s12, s7
+; SI-NEXT: s_cselect_b32 s0, 0, s6
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: s_branch .LBB13_7
+; SI-NEXT: .LBB13_5:
+; SI-NEXT: v_mov_b32_e32 v7, v5
+; SI-NEXT: v_mov_b32_e32 v6, v4
+; SI-NEXT: .LBB13_6: ; %frem.loop_exit24
+; SI-NEXT: s_sub_i32 s0, s14, 25
+; SI-NEXT: v_ldexp_f64 v[4:5], v[6:7], s0
; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
-; SI-NEXT: v_bfi_b32 v7, s0, v6, v3
+; SI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3]
+; SI-NEXT: s_mov_b32 s0, -1
+; SI-NEXT: v_bfi_b32 v7, s12, v6, v3
; SI-NEXT: v_mov_b32_e32 v6, 0
; SI-NEXT: v_add_f64 v[8:9], v[2:3], v[6:7]
+; SI-NEXT: s_mov_b32 s1, 0x432fffff
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[0:1]
; SI-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
; SI-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
@@ -16390,36 +15269,15 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
; SI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], s14
+; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], s13
; SI-NEXT: v_mov_b32_e32 v2, s7
-; SI-NEXT: v_bfi_b32 v1, s0, v1, v2
-; SI-NEXT: .LBB13_9:
-; SI-NEXT: v_mov_b32_e32 v2, s4
-; SI-NEXT: v_mov_b32_e32 v3, s5
-; SI-NEXT: v_cmp_ngt_f64_e64 s[0:1], |s[2:3]|, |v[2:3]|
-; SI-NEXT: s_and_b64 vcc, exec, s[0:1]
-; SI-NEXT: s_cbranch_vccz .LBB13_12
-; SI-NEXT: ; %bb.10: ; %frem.else
+; SI-NEXT: v_bfi_b32 v1, s12, v1, v2
+; SI-NEXT: .LBB13_7:
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_mov_b32_e32 v3, s5
-; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[2:3]|, |v[2:3]|
-; SI-NEXT: s_and_b32 s12, s3, 0x80000000
-; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; SI-NEXT: s_cselect_b32 s1, s12, s3
-; SI-NEXT: s_cselect_b32 s0, 0, s2
-; SI-NEXT: s_mov_b64 s[12:13], 0
-; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
-; SI-NEXT: s_cbranch_scc1 .LBB13_13
-; SI-NEXT: .LBB13_11:
-; SI-NEXT: v_mov_b32_e32 v3, s1
-; SI-NEXT: v_mov_b32_e32 v2, s0
-; SI-NEXT: s_branch .LBB13_18
-; SI-NEXT: .LBB13_12:
-; SI-NEXT: s_mov_b64 s[12:13], -1
-; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
-; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
-; SI-NEXT: s_cbranch_scc0 .LBB13_11
-; SI-NEXT: .LBB13_13: ; %frem.compute
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, |v[2:3]|
+; SI-NEXT: s_cbranch_vccz .LBB13_11
+; SI-NEXT: ; %bb.8: ; %frem.compute
; SI-NEXT: s_and_b32 s0, s3, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[2:3]|
; SI-NEXT: s_cmp_lt_i32 s0, 0x7ff00000
@@ -16444,11 +15302,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_ldexp_f64 v[2:3], v[2:3], 1
; SI-NEXT: v_readfirstlane_b32 s0, v4
; SI-NEXT: s_cselect_b32 s17, s0, 0
-; SI-NEXT: s_add_i32 s14, s17, -1
-; SI-NEXT: s_not_b32 s0, s14
+; SI-NEXT: s_add_i32 s15, s17, -1
+; SI-NEXT: s_not_b32 s0, s15
; SI-NEXT: s_add_i32 s16, s0, s13
; SI-NEXT: v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], 1.0
-; SI-NEXT: s_brev_b32 s15, -2
+; SI-NEXT: s_brev_b32 s14, -2
; SI-NEXT: s_mov_b32 s12, -1
; SI-NEXT: v_rcp_f64_e32 v[8:9], v[4:5]
; SI-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5
@@ -16465,48 +15323,58 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_div_fmas_f64 v[4:5], v[14:15], v[8:9], v[12:13]
; SI-NEXT: s_cmp_lt_i32 s16, 27
; SI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0
-; SI-NEXT: s_cbranch_scc1 .LBB13_17
-; SI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB13_12
+; SI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; SI-NEXT: s_sub_i32 s0, s13, s17
; SI-NEXT: s_add_i32 s16, s0, 26
; SI-NEXT: s_mov_b32 s13, 0x432fffff
; SI-NEXT: v_mov_b32_e32 v12, 0x43300000
-; SI-NEXT: v_mov_b32_e32 v8, 0
-; SI-NEXT: .LBB13_15: ; %frem.loop_body
+; SI-NEXT: v_mov_b32_e32 v10, 0
+; SI-NEXT: .LBB13_10: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v11, v7
-; SI-NEXT: v_mov_b32_e32 v10, v6
-; SI-NEXT: v_mul_f64 v[6:7], v[10:11], v[4:5]
+; SI-NEXT: v_mov_b32_e32 v9, v7
+; SI-NEXT: v_mov_b32_e32 v8, v6
+; SI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
; SI-NEXT: s_sub_i32 s16, s16, 26
-; SI-NEXT: v_bfi_b32 v9, s15, v12, v7
-; SI-NEXT: v_add_f64 v[13:14], v[6:7], v[8:9]
+; SI-NEXT: v_bfi_b32 v11, s14, v12, v7
+; SI-NEXT: v_add_f64 v[13:14], v[6:7], v[10:11]
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[6:7]|, s[12:13]
-; SI-NEXT: v_add_f64 v[13:14], v[13:14], -v[8:9]
+; SI-NEXT: v_add_f64 v[13:14], v[13:14], -v[10:11]
; SI-NEXT: s_cmp_gt_i32 s16, 26
; SI-NEXT: v_cndmask_b32_e32 v7, v14, v7, vcc
; SI-NEXT: v_cndmask_b32_e32 v6, v13, v6, vcc
-; SI-NEXT: v_fma_f64 v[6:7], -v[6:7], v[2:3], v[10:11]
+; SI-NEXT: v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; SI-NEXT: v_add_f64 v[13:14], v[6:7], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v7, v7, v14, vcc
; SI-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc
; SI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; SI-NEXT: s_cbranch_scc1 .LBB13_15
-; SI-NEXT: ; %bb.16: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v6, v10
-; SI-NEXT: v_mov_b32_e32 v7, v11
-; SI-NEXT: .LBB13_17: ; %frem.loop_exit
+; SI-NEXT: s_cbranch_scc1 .LBB13_10
+; SI-NEXT: s_branch .LBB13_13
+; SI-NEXT: .LBB13_11: ; %frem.else
+; SI-NEXT: v_mov_b32_e32 v2, s4
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: v_cmp_eq_f64_e64 s[0:1], |s[2:3]|, |v[2:3]|
+; SI-NEXT: s_and_b32 s12, s3, 0x80000000
+; SI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; SI-NEXT: s_cselect_b32 s1, s12, s3
+; SI-NEXT: s_cselect_b32 s0, 0, s2
+; SI-NEXT: v_mov_b32_e32 v3, s1
+; SI-NEXT: v_mov_b32_e32 v2, s0
+; SI-NEXT: s_branch .LBB13_14
+; SI-NEXT: .LBB13_12:
+; SI-NEXT: v_mov_b32_e32 v9, v7
+; SI-NEXT: v_mov_b32_e32 v8, v6
+; SI-NEXT: .LBB13_13: ; %frem.loop_exit
; SI-NEXT: s_sub_i32 s0, s16, 25
-; SI-NEXT: v_ldexp_f64 v[6:7], v[6:7], s0
-; SI-NEXT: s_mov_b32 s0, -1
-; SI-NEXT: v_mul_f64 v[4:5], v[6:7], v[4:5]
-; SI-NEXT: s_mov_b32 s1, 0x432fffff
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[0:1]
-; SI-NEXT: s_brev_b32 s0, -2
+; SI-NEXT: v_ldexp_f64 v[6:7], v[8:9], s0
; SI-NEXT: v_mov_b32_e32 v8, 0x43300000
-; SI-NEXT: v_bfi_b32 v9, s0, v8, v5
+; SI-NEXT: v_mul_f64 v[4:5], v[6:7], v[4:5]
+; SI-NEXT: s_mov_b32 s13, 0x432fffff
+; SI-NEXT: v_bfi_b32 v9, s14, v8, v5
; SI-NEXT: v_mov_b32_e32 v8, 0
; SI-NEXT: v_add_f64 v[10:11], v[4:5], v[8:9]
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[12:13]
; SI-NEXT: v_add_f64 v[8:9], v[10:11], -v[8:9]
; SI-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
@@ -16515,10 +15383,10 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NEXT: v_ldexp_f64 v[2:3], v[2:3], s14
+; SI-NEXT: v_ldexp_f64 v[2:3], v[2:3], s15
; SI-NEXT: v_mov_b32_e32 v4, s3
-; SI-NEXT: v_bfi_b32 v3, s0, v3, v4
-; SI-NEXT: .LBB13_18: ; %Flow50
+; SI-NEXT: v_bfi_b32 v3, s14, v3, v4
+; SI-NEXT: .LBB13_14:
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
; SI-NEXT: v_cmp_lg_f64_e64 s[0:1], s[10:11], 0
@@ -16551,24 +15419,9 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
; CI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:64
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB13_2
-; CI-NEXT: ; %bb.1: ; %frem.else16
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
-; CI-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
-; CI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB13_3
-; CI-NEXT: s_branch .LBB13_8
-; CI-NEXT: .LBB13_2:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr8_vgpr9
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB13_8
-; CI-NEXT: .LBB13_3: ; %frem.compute15
+; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; CI-NEXT: s_cbranch_vccz .LBB13_4
+; CI-NEXT: ; %bb.1: ; %frem.compute15
; CI-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v15, v[4:5]
; CI-NEXT: v_frexp_exp_i32_f64_e32 v14, v[0:1]
@@ -16591,11 +15444,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v17
; CI-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB13_7
-; CI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB13_6
+; CI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; CI-NEXT: v_sub_i32_e32 v14, vcc, v14, v15
; CI-NEXT: v_add_i32_e32 v17, vcc, 26, v14
-; CI-NEXT: .LBB13_5: ; %frem.loop_body23
+; CI-NEXT: .LBB13_3: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v15, v13
; CI-NEXT: v_mov_b32_e32 v14, v12
@@ -16609,13 +15462,27 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
; CI-NEXT: v_subrev_i32_e32 v17, vcc, 26, v17
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v17
-; CI-NEXT: s_cbranch_vccnz .LBB13_5
-; CI-NEXT: ; %bb.6: ; %Flow51
-; CI-NEXT: v_mov_b32_e32 v12, v14
-; CI-NEXT: v_mov_b32_e32 v13, v15
+; CI-NEXT: s_cbranch_vccnz .LBB13_3
+; CI-NEXT: s_branch .LBB13_7
+; CI-NEXT: .LBB13_4: ; %frem.else16
+; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; CI-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; CI-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
+; CI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
+; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; CI-NEXT: s_cbranch_vccnz .LBB13_8
+; CI-NEXT: .LBB13_5: ; %frem.else
+; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; CI-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; CI-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
+; CI-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
+; CI-NEXT: s_branch .LBB13_13
+; CI-NEXT: .LBB13_6:
+; CI-NEXT: v_mov_b32_e32 v15, v13
+; CI-NEXT: v_mov_b32_e32 v14, v12
; CI-NEXT: .LBB13_7: ; %frem.loop_exit24
-; CI-NEXT: v_subrev_i32_e32 v14, vcc, 25, v17
-; CI-NEXT: v_ldexp_f64 v[12:13], v[12:13], v14
+; CI-NEXT: v_subrev_i32_e32 v12, vcc, 25, v17
+; CI-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
; CI-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
@@ -16626,25 +15493,9 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
; CI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; CI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; CI-NEXT: .LBB13_8:
-; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB13_10
-; CI-NEXT: ; %bb.9: ; %frem.else
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; CI-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
-; CI-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB13_11
-; CI-NEXT: s_branch .LBB13_16
-; CI-NEXT: .LBB13_10:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr10_vgpr11
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB13_16
-; CI-NEXT: .LBB13_11: ; %frem.compute
+; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; CI-NEXT: s_cbranch_vccz .LBB13_5
+; CI-NEXT: .LBB13_8: ; %frem.compute
; CI-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; CI-NEXT: v_frexp_exp_i32_f64_e32 v17, v[6:7]
; CI-NEXT: v_frexp_exp_i32_f64_e32 v16, v[2:3]
@@ -16667,11 +15518,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v19
; CI-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; CI-NEXT: s_cbranch_vccnz .LBB13_15
-; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; CI-NEXT: s_cbranch_vccnz .LBB13_11
+; CI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; CI-NEXT: v_sub_i32_e32 v16, vcc, v16, v17
; CI-NEXT: v_add_i32_e32 v19, vcc, 26, v16
-; CI-NEXT: .LBB13_13: ; %frem.loop_body
+; CI-NEXT: .LBB13_10: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
; CI-NEXT: v_mov_b32_e32 v17, v15
; CI-NEXT: v_mov_b32_e32 v16, v14
@@ -16685,13 +15536,14 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
; CI-NEXT: v_subrev_i32_e32 v19, vcc, 26, v19
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v19
-; CI-NEXT: s_cbranch_vccnz .LBB13_13
-; CI-NEXT: ; %bb.14: ; %Flow
-; CI-NEXT: v_mov_b32_e32 v14, v16
-; CI-NEXT: v_mov_b32_e32 v15, v17
-; CI-NEXT: .LBB13_15: ; %frem.loop_exit
-; CI-NEXT: v_subrev_i32_e32 v16, vcc, 25, v19
-; CI-NEXT: v_ldexp_f64 v[14:15], v[14:15], v16
+; CI-NEXT: s_cbranch_vccnz .LBB13_10
+; CI-NEXT: s_branch .LBB13_12
+; CI-NEXT: .LBB13_11:
+; CI-NEXT: v_mov_b32_e32 v17, v15
+; CI-NEXT: v_mov_b32_e32 v16, v14
+; CI-NEXT: .LBB13_12: ; %frem.loop_exit
+; CI-NEXT: v_subrev_i32_e32 v14, vcc, 25, v19
+; CI-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
; CI-NEXT: s_brev_b32 s2, -2
; CI-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
; CI-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
@@ -16702,7 +15554,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; CI-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc
; CI-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; CI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; CI-NEXT: .LBB13_16: ; %Flow50
+; CI-NEXT: .LBB13_13:
; CI-NEXT: s_mov_b32 s4, 0
; CI-NEXT: s_mov_b32 s5, 0x7ff00000
; CI-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[4:5]
@@ -16735,24 +15587,9 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB13_2
-; VI-NEXT: ; %bb.1: ; %frem.else16
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
-; VI-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
-; VI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB13_3
-; VI-NEXT: s_branch .LBB13_8
-; VI-NEXT: .LBB13_2:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr8_vgpr9
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB13_8
-; VI-NEXT: .LBB13_3: ; %frem.compute15
+; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; VI-NEXT: s_cbranch_vccz .LBB13_4
+; VI-NEXT: ; %bb.1: ; %frem.compute15
; VI-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v15, v[4:5]
; VI-NEXT: v_frexp_exp_i32_f64_e32 v14, v[0:1]
@@ -16775,11 +15612,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v17
; VI-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB13_7
-; VI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB13_6
+; VI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; VI-NEXT: v_sub_u32_e32 v14, vcc, v14, v15
; VI-NEXT: v_add_u32_e32 v17, vcc, 26, v14
-; VI-NEXT: .LBB13_5: ; %frem.loop_body23
+; VI-NEXT: .LBB13_3: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v15, v13
; VI-NEXT: v_mov_b32_e32 v14, v12
@@ -16793,13 +15630,27 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
; VI-NEXT: v_subrev_u32_e32 v17, vcc, 26, v17
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v17
-; VI-NEXT: s_cbranch_vccnz .LBB13_5
-; VI-NEXT: ; %bb.6: ; %Flow51
-; VI-NEXT: v_mov_b32_e32 v12, v14
-; VI-NEXT: v_mov_b32_e32 v13, v15
+; VI-NEXT: s_cbranch_vccnz .LBB13_3
+; VI-NEXT: s_branch .LBB13_7
+; VI-NEXT: .LBB13_4: ; %frem.else16
+; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; VI-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; VI-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
+; VI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
+; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; VI-NEXT: s_cbranch_vccnz .LBB13_8
+; VI-NEXT: .LBB13_5: ; %frem.else
+; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; VI-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; VI-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
+; VI-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
+; VI-NEXT: s_branch .LBB13_13
+; VI-NEXT: .LBB13_6:
+; VI-NEXT: v_mov_b32_e32 v15, v13
+; VI-NEXT: v_mov_b32_e32 v14, v12
; VI-NEXT: .LBB13_7: ; %frem.loop_exit24
-; VI-NEXT: v_subrev_u32_e32 v14, vcc, 25, v17
-; VI-NEXT: v_ldexp_f64 v[12:13], v[12:13], v14
+; VI-NEXT: v_subrev_u32_e32 v12, vcc, 25, v17
+; VI-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
; VI-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
@@ -16810,25 +15661,9 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
; VI-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; VI-NEXT: v_bfi_b32 v9, s2, v9, v1
-; VI-NEXT: .LBB13_8:
-; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB13_10
-; VI-NEXT: ; %bb.9: ; %frem.else
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; VI-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
-; VI-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB13_11
-; VI-NEXT: s_branch .LBB13_16
-; VI-NEXT: .LBB13_10:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr10_vgpr11
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB13_16
-; VI-NEXT: .LBB13_11: ; %frem.compute
+; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; VI-NEXT: s_cbranch_vccz .LBB13_5
+; VI-NEXT: .LBB13_8: ; %frem.compute
; VI-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; VI-NEXT: v_frexp_exp_i32_f64_e32 v17, v[6:7]
; VI-NEXT: v_frexp_exp_i32_f64_e32 v16, v[2:3]
@@ -16851,11 +15686,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v19
; VI-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; VI-NEXT: s_cbranch_vccnz .LBB13_15
-; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; VI-NEXT: s_cbranch_vccnz .LBB13_11
+; VI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; VI-NEXT: v_sub_u32_e32 v16, vcc, v16, v17
; VI-NEXT: v_add_u32_e32 v19, vcc, 26, v16
-; VI-NEXT: .LBB13_13: ; %frem.loop_body
+; VI-NEXT: .LBB13_10: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v17, v15
; VI-NEXT: v_mov_b32_e32 v16, v14
@@ -16869,13 +15704,14 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
; VI-NEXT: v_subrev_u32_e32 v19, vcc, 26, v19
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v19
-; VI-NEXT: s_cbranch_vccnz .LBB13_13
-; VI-NEXT: ; %bb.14: ; %Flow
-; VI-NEXT: v_mov_b32_e32 v14, v16
-; VI-NEXT: v_mov_b32_e32 v15, v17
-; VI-NEXT: .LBB13_15: ; %frem.loop_exit
-; VI-NEXT: v_subrev_u32_e32 v16, vcc, 25, v19
-; VI-NEXT: v_ldexp_f64 v[14:15], v[14:15], v16
+; VI-NEXT: s_cbranch_vccnz .LBB13_10
+; VI-NEXT: s_branch .LBB13_12
+; VI-NEXT: .LBB13_11:
+; VI-NEXT: v_mov_b32_e32 v17, v15
+; VI-NEXT: v_mov_b32_e32 v16, v14
+; VI-NEXT: .LBB13_12: ; %frem.loop_exit
+; VI-NEXT: v_subrev_u32_e32 v14, vcc, 25, v19
+; VI-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
; VI-NEXT: s_brev_b32 s2, -2
; VI-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
; VI-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
@@ -16886,7 +15722,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc
; VI-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; VI-NEXT: v_bfi_b32 v11, s2, v11, v3
-; VI-NEXT: .LBB13_16: ; %Flow50
+; VI-NEXT: .LBB13_13:
; VI-NEXT: s_mov_b32 s2, 0
; VI-NEXT: s_mov_b32 s3, 0x7ff00000
; VI-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[4:5]
@@ -16914,24 +15750,9 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3]
; GFX9-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB13_2
-; GFX9-NEXT: ; %bb.1: ; %frem.else16
-; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
-; GFX9-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB13_3
-; GFX9-NEXT: s_branch .LBB13_8
-; GFX9-NEXT: .LBB13_2:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB13_8
-; GFX9-NEXT: .LBB13_3: ; %frem.compute15
+; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; GFX9-NEXT: s_cbranch_vccz .LBB13_4
+; GFX9-NEXT: ; %bb.1: ; %frem.compute15
; GFX9-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v15, v[4:5]
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v14, v[0:1]
@@ -16954,11 +15775,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[18:19], v[22:23]
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v17
; GFX9-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_7
-; GFX9-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_6
+; GFX9-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX9-NEXT: v_sub_u32_e32 v14, v14, v15
; GFX9-NEXT: v_add_u32_e32 v17, 26, v14
-; GFX9-NEXT: .LBB13_5: ; %frem.loop_body23
+; GFX9-NEXT: .LBB13_3: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v15, v13
; GFX9-NEXT: v_mov_b32_e32 v14, v12
@@ -16972,13 +15793,27 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v18, vcc
; GFX9-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v17
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_5
-; GFX9-NEXT: ; %bb.6: ; %Flow51
-; GFX9-NEXT: v_mov_b32_e32 v12, v14
-; GFX9-NEXT: v_mov_b32_e32 v13, v15
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_3
+; GFX9-NEXT: s_branch .LBB13_7
+; GFX9-NEXT: .LBB13_4: ; %frem.else16
+; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; GFX9-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
+; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_8
+; GFX9-NEXT: .LBB13_5: ; %frem.else
+; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
+; GFX9-NEXT: s_branch .LBB13_13
+; GFX9-NEXT: .LBB13_6:
+; GFX9-NEXT: v_mov_b32_e32 v15, v13
+; GFX9-NEXT: v_mov_b32_e32 v14, v12
; GFX9-NEXT: .LBB13_7: ; %frem.loop_exit24
-; GFX9-NEXT: v_subrev_u32_e32 v14, 25, v17
-; GFX9-NEXT: v_ldexp_f64 v[12:13], v[12:13], v14
+; GFX9-NEXT: v_subrev_u32_e32 v12, 25, v17
+; GFX9-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
; GFX9-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
@@ -16989,25 +15824,9 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
; GFX9-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX9-NEXT: v_bfi_b32 v9, s2, v9, v1
-; GFX9-NEXT: .LBB13_8:
-; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB13_10
-; GFX9-NEXT: ; %bb.9: ; %frem.else
-; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
-; GFX9-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB13_11
-; GFX9-NEXT: s_branch .LBB13_16
-; GFX9-NEXT: .LBB13_10:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr10_vgpr11
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB13_16
-; GFX9-NEXT: .LBB13_11: ; %frem.compute
+; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; GFX9-NEXT: s_cbranch_vccz .LBB13_5
+; GFX9-NEXT: .LBB13_8: ; %frem.compute
; GFX9-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v17, v[6:7]
; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v16, v[2:3]
@@ -17030,11 +15849,11 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[20:21], v[24:25]
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v19
; GFX9-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_15
-; GFX9-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_11
+; GFX9-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; GFX9-NEXT: v_sub_u32_e32 v16, v16, v17
; GFX9-NEXT: v_add_u32_e32 v19, 26, v16
-; GFX9-NEXT: .LBB13_13: ; %frem.loop_body
+; GFX9-NEXT: .LBB13_10: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v17, v15
; GFX9-NEXT: v_mov_b32_e32 v16, v14
@@ -17048,13 +15867,14 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v14, v14, v20, vcc
; GFX9-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v19
-; GFX9-NEXT: s_cbranch_vccnz .LBB13_13
-; GFX9-NEXT: ; %bb.14: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v14, v16
-; GFX9-NEXT: v_mov_b32_e32 v15, v17
-; GFX9-NEXT: .LBB13_15: ; %frem.loop_exit
-; GFX9-NEXT: v_subrev_u32_e32 v16, 25, v19
-; GFX9-NEXT: v_ldexp_f64 v[14:15], v[14:15], v16
+; GFX9-NEXT: s_cbranch_vccnz .LBB13_10
+; GFX9-NEXT: s_branch .LBB13_12
+; GFX9-NEXT: .LBB13_11:
+; GFX9-NEXT: v_mov_b32_e32 v17, v15
+; GFX9-NEXT: v_mov_b32_e32 v16, v14
+; GFX9-NEXT: .LBB13_12: ; %frem.loop_exit
+; GFX9-NEXT: v_subrev_u32_e32 v14, 25, v19
+; GFX9-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
; GFX9-NEXT: s_brev_b32 s2, -2
; GFX9-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
; GFX9-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
@@ -17065,7 +15885,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc
; GFX9-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX9-NEXT: v_bfi_b32 v11, s2, v11, v3
-; GFX9-NEXT: .LBB13_16: ; %Flow50
+; GFX9-NEXT: .LBB13_13:
; GFX9-NEXT: s_mov_b32 s2, 0
; GFX9-NEXT: s_mov_b32 s3, 0x7ff00000
; GFX9-NEXT: v_cmp_lg_f64_e32 vcc, 0, v[4:5]
@@ -17094,160 +15914,146 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX10-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3]
; GFX10-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB13_2
-; GFX10-NEXT: ; %bb.1: ; %frem.else16
-; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX10-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB13_3
-; GFX10-NEXT: s_branch .LBB13_8
-; GFX10-NEXT: .LBB13_2:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB13_8
-; GFX10-NEXT: .LBB13_3: ; %frem.compute15
+; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX10-NEXT: s_cbranch_vccz .LBB13_5
+; GFX10-NEXT: ; %bb.1: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
-; GFX10-NEXT: v_ldexp_f64 v[10:11], v[8:9], 26
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v11, v[4:5]
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
+; GFX10-NEXT: v_ldexp_f64 v[12:13], v[8:9], 26
; GFX10-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
-; GFX10-NEXT: v_add_nc_u32_e32 v16, -1, v13
-; GFX10-NEXT: v_readfirstlane_b32 s3, v13
-; GFX10-NEXT: v_readfirstlane_b32 s2, v12
-; GFX10-NEXT: v_not_b32_e32 v13, v16
-; GFX10-NEXT: v_add_nc_u32_e32 v17, v13, v12
+; GFX10-NEXT: v_add_nc_u32_e32 v16, -1, v11
+; GFX10-NEXT: v_readfirstlane_b32 s3, v11
+; GFX10-NEXT: v_readfirstlane_b32 s2, v10
+; GFX10-NEXT: v_not_b32_e32 v11, v16
+; GFX10-NEXT: v_add_nc_u32_e32 v17, v11, v10
; GFX10-NEXT: v_ldexp_f64 v[8:9], v[8:9], 1
-; GFX10-NEXT: v_div_scale_f64 v[12:13], s4, v[8:9], v[8:9], 1.0
-; GFX10-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
-; GFX10-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX10-NEXT: v_div_scale_f64 v[10:11], s4, v[8:9], v[8:9], 1.0
+; GFX10-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
+; GFX10-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX10-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX10-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX10-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX10-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX10-NEXT: v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
; GFX10-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15]
-; GFX10-NEXT: v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
-; GFX10-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
+; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX10-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
-; GFX10-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX10-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; GFX10-NEXT: s_cbranch_vccnz .LBB13_7
-; GFX10-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX10-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 26
-; GFX10-NEXT: .LBB13_5: ; %frem.loop_body23
+; GFX10-NEXT: .LBB13_3: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v15, v11
-; GFX10-NEXT: v_mov_b32_e32 v14, v10
+; GFX10-NEXT: v_mov_b32_e32 v15, v13
+; GFX10-NEXT: v_mov_b32_e32 v14, v12
; GFX10-NEXT: s_sub_i32 s2, s2, 26
; GFX10-NEXT: s_cmp_gt_i32 s2, 26
-; GFX10-NEXT: v_mul_f64 v[10:11], v[14:15], v[12:13]
-; GFX10-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
-; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
-; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
-; GFX10-NEXT: v_add_f64 v[17:18], v[10:11], v[8:9]
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc_lo
-; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB13_5
-; GFX10-NEXT: ; %bb.6: ; %Flow51
-; GFX10-NEXT: v_mov_b32_e32 v17, s2
-; GFX10-NEXT: v_mov_b32_e32 v10, v14
-; GFX10-NEXT: v_mov_b32_e32 v11, v15
-; GFX10-NEXT: .LBB13_7: ; %frem.loop_exit24
-; GFX10-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
-; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
-; GFX10-NEXT: v_mul_f64 v[12:13], v[10:11], v[12:13]
+; GFX10-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11]
; GFX10-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
-; GFX10-NEXT: v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; GFX10-NEXT: v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
+; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX10-NEXT: v_add_f64 v[17:18], v[12:13], v[8:9]
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v18, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v17, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX10-NEXT: s_cbranch_scc1 .LBB13_3
+; GFX10-NEXT: ; %bb.4:
+; GFX10-NEXT: v_mov_b32_e32 v17, s2
+; GFX10-NEXT: s_branch .LBB13_8
+; GFX10-NEXT: .LBB13_5: ; %frem.else16
+; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX10-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX10-NEXT: s_cbranch_vccnz .LBB13_9
+; GFX10-NEXT: .LBB13_6: ; %frem.else
+; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX10-NEXT: s_branch .LBB13_15
+; GFX10-NEXT: .LBB13_7:
+; GFX10-NEXT: v_mov_b32_e32 v15, v13
+; GFX10-NEXT: v_mov_b32_e32 v14, v12
+; GFX10-NEXT: .LBB13_8: ; %frem.loop_exit24
+; GFX10-NEXT: v_subrev_nc_u32_e32 v12, 25, v17
+; GFX10-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
+; GFX10-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
+; GFX10-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX10-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_add_f64 v[8:9], v[10:11], v[8:9]
; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX10-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX10-NEXT: .LBB13_8:
-; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB13_10
-; GFX10-NEXT: ; %bb.9: ; %frem.else
-; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX10-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB13_11
-; GFX10-NEXT: s_branch .LBB13_16
-; GFX10-NEXT: .LBB13_10:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr10_vgpr11
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB13_16
-; GFX10-NEXT: .LBB13_11: ; %frem.compute
+; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX10-NEXT: s_cbranch_vccz .LBB13_6
+; GFX10-NEXT: .LBB13_9: ; %frem.compute
; GFX10-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
-; GFX10-NEXT: v_ldexp_f64 v[12:13], v[10:11], 26
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v13, v[6:7]
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v12, v[2:3]
+; GFX10-NEXT: v_ldexp_f64 v[14:15], v[10:11], 26
; GFX10-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
-; GFX10-NEXT: v_add_nc_u32_e32 v18, -1, v15
-; GFX10-NEXT: v_readfirstlane_b32 s3, v15
-; GFX10-NEXT: v_readfirstlane_b32 s2, v14
-; GFX10-NEXT: v_not_b32_e32 v15, v18
-; GFX10-NEXT: v_add_nc_u32_e32 v19, v15, v14
+; GFX10-NEXT: v_add_nc_u32_e32 v18, -1, v13
+; GFX10-NEXT: v_readfirstlane_b32 s3, v13
+; GFX10-NEXT: v_readfirstlane_b32 s2, v12
+; GFX10-NEXT: v_not_b32_e32 v13, v18
+; GFX10-NEXT: v_add_nc_u32_e32 v19, v13, v12
; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], 1
-; GFX10-NEXT: v_div_scale_f64 v[14:15], s4, v[10:11], v[10:11], 1.0
-; GFX10-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
-; GFX10-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX10-NEXT: v_div_scale_f64 v[12:13], s4, v[10:11], v[10:11], 1.0
+; GFX10-NEXT: v_rcp_f64_e32 v[16:17], v[12:13]
+; GFX10-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
; GFX10-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
-; GFX10-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX10-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
; GFX10-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX10-NEXT: v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
; GFX10-NEXT: v_mul_f64 v[22:23], v[20:21], v[16:17]
-; GFX10-NEXT: v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
-; GFX10-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
+; GFX10-NEXT: v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
+; GFX10-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[22:23]
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
-; GFX10-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
-; GFX10-NEXT: s_cbranch_vccnz .LBB13_15
-; GFX10-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX10-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
+; GFX10-NEXT: s_cbranch_vccnz .LBB13_13
+; GFX10-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX10-NEXT: s_sub_i32 s2, s2, s3
; GFX10-NEXT: s_add_i32 s2, s2, 26
-; GFX10-NEXT: .LBB13_13: ; %frem.loop_body
+; GFX10-NEXT: .LBB13_11: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v17, v13
-; GFX10-NEXT: v_mov_b32_e32 v16, v12
+; GFX10-NEXT: v_mov_b32_e32 v17, v15
+; GFX10-NEXT: v_mov_b32_e32 v16, v14
; GFX10-NEXT: s_sub_i32 s2, s2, 26
; GFX10-NEXT: s_cmp_gt_i32 s2, 26
-; GFX10-NEXT: v_mul_f64 v[12:13], v[16:17], v[14:15]
-; GFX10-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
-; GFX10-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
-; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
-; GFX10-NEXT: v_add_f64 v[19:20], v[12:13], v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v20, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v19, vcc_lo
-; GFX10-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB13_13
-; GFX10-NEXT: ; %bb.14: ; %Flow
-; GFX10-NEXT: v_mov_b32_e32 v19, s2
-; GFX10-NEXT: v_mov_b32_e32 v12, v16
-; GFX10-NEXT: v_mov_b32_e32 v13, v17
-; GFX10-NEXT: .LBB13_15: ; %frem.loop_exit
-; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
-; GFX10-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
-; GFX10-NEXT: v_mul_f64 v[14:15], v[12:13], v[14:15]
+; GFX10-NEXT: v_mul_f64 v[14:15], v[16:17], v[12:13]
; GFX10-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
-; GFX10-NEXT: v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; GFX10-NEXT: v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
+; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
+; GFX10-NEXT: v_add_f64 v[19:20], v[14:15], v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v20, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v19, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
+; GFX10-NEXT: s_cbranch_scc1 .LBB13_11
+; GFX10-NEXT: ; %bb.12:
+; GFX10-NEXT: v_mov_b32_e32 v19, s2
+; GFX10-NEXT: s_branch .LBB13_14
+; GFX10-NEXT: .LBB13_13:
+; GFX10-NEXT: v_mov_b32_e32 v17, v15
+; GFX10-NEXT: v_mov_b32_e32 v16, v14
+; GFX10-NEXT: .LBB13_14: ; %frem.loop_exit
+; GFX10-NEXT: v_subrev_nc_u32_e32 v14, 25, v19
+; GFX10-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
+; GFX10-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
+; GFX10-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX10-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX10-NEXT: v_add_f64 v[10:11], v[12:13], v[10:11]
; GFX10-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX10-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX10-NEXT: .LBB13_16: ; %Flow50
+; GFX10-NEXT: .LBB13_15:
; GFX10-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX10-NEXT: v_mov_b32_e32 v4, 0
@@ -17273,92 +16079,92 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: global_load_b128 v[0:3], v4, s[2:3]
; GFX11-NEXT: global_load_b128 v[4:7], v4, s[4:5] offset:64
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB13_2
-; GFX11-NEXT: ; %bb.1: ; %frem.else16
-; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX11-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB13_3
-; GFX11-NEXT: s_branch .LBB13_8
-; GFX11-NEXT: .LBB13_2:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB13_8
-; GFX11-NEXT: .LBB13_3: ; %frem.compute15
+; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX11-NEXT: s_cbranch_vccz .LBB13_5
+; GFX11-NEXT: ; %bb.1: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v11, v[4:5]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_ldexp_f64 v[10:11], v[8:9], 26
+; GFX11-NEXT: v_ldexp_f64 v[12:13], v[8:9], 26
; GFX11-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
-; GFX11-NEXT: v_add_nc_u32_e32 v16, -1, v13
-; GFX11-NEXT: v_readfirstlane_b32 s3, v13
-; GFX11-NEXT: v_readfirstlane_b32 s2, v12
+; GFX11-NEXT: v_add_nc_u32_e32 v16, -1, v11
+; GFX11-NEXT: v_readfirstlane_b32 s3, v11
+; GFX11-NEXT: v_readfirstlane_b32 s2, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_not_b32_e32 v13, v16
-; GFX11-NEXT: v_add_nc_u32_e32 v17, v13, v12
+; GFX11-NEXT: v_not_b32_e32 v11, v16
+; GFX11-NEXT: v_add_nc_u32_e32 v17, v11, v10
; GFX11-NEXT: v_ldexp_f64 v[8:9], v[8:9], 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
-; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX11-NEXT: v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
+; GFX11-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX11-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX11-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX11-NEXT: v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
; GFX11-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
-; GFX11-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
+; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX11-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX11-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; GFX11-NEXT: s_cbranch_vccnz .LBB13_7
-; GFX11-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX11-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 26
; GFX11-NEXT: .p2align 6
-; GFX11-NEXT: .LBB13_5: ; %frem.loop_body23
+; GFX11-NEXT: .LBB13_3: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
+; GFX11-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
; GFX11-NEXT: s_sub_i32 s2, s2, 26
; GFX11-NEXT: s_cmp_gt_i32 s2, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[10:11], v[14:15], v[12:13]
-; GFX11-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX11-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11]
+; GFX11-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
-; GFX11-NEXT: v_add_f64 v[17:18], v[10:11], v[8:9]
+; GFX11-NEXT: v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
+; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX11-NEXT: v_add_f64 v[17:18], v[12:13], v[8:9]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
-; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB13_5
-; GFX11-NEXT: ; %bb.6: ; %Flow51
-; GFX11-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
-; GFX11-NEXT: v_mov_b32_e32 v11, v15
-; GFX11-NEXT: .LBB13_7: ; %frem.loop_exit24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
-; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
+; GFX11-NEXT: v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v17
+; GFX11-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX11-NEXT: s_cbranch_scc1 .LBB13_3
+; GFX11-NEXT: ; %bb.4:
+; GFX11-NEXT: v_mov_b32_e32 v17, s2
+; GFX11-NEXT: s_branch .LBB13_8
+; GFX11-NEXT: .LBB13_5: ; %frem.else16
+; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX11-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX11-NEXT: s_cbranch_vccnz .LBB13_9
+; GFX11-NEXT: .LBB13_6: ; %frem.else
+; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX11-NEXT: s_branch .LBB13_15
+; GFX11-NEXT: .LBB13_7:
+; GFX11-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
+; GFX11-NEXT: .LBB13_8: ; %frem.loop_exit24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[12:13], v[10:11], v[12:13]
-; GFX11-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX11-NEXT: v_subrev_nc_u32_e32 v12, 25, v17
+; GFX11-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; GFX11-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
+; GFX11-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX11-NEXT: v_add_f64 v[8:9], v[10:11], v[8:9]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17366,93 +16172,77 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX11-NEXT: .LBB13_8:
-; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB13_10
-; GFX11-NEXT: ; %bb.9: ; %frem.else
-; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX11-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB13_11
-; GFX11-NEXT: s_branch .LBB13_16
-; GFX11-NEXT: .LBB13_10:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr10_vgpr11
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB13_16
-; GFX11-NEXT: .LBB13_11: ; %frem.compute
+; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX11-NEXT: s_cbranch_vccz .LBB13_6
+; GFX11-NEXT: .LBB13_9: ; %frem.compute
; GFX11-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v13, v[6:7]
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v12, v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_ldexp_f64 v[12:13], v[10:11], 26
+; GFX11-NEXT: v_ldexp_f64 v[14:15], v[10:11], 26
; GFX11-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
-; GFX11-NEXT: v_add_nc_u32_e32 v18, -1, v15
-; GFX11-NEXT: v_readfirstlane_b32 s3, v15
-; GFX11-NEXT: v_readfirstlane_b32 s2, v14
+; GFX11-NEXT: v_add_nc_u32_e32 v18, -1, v13
+; GFX11-NEXT: v_readfirstlane_b32 s3, v13
+; GFX11-NEXT: v_readfirstlane_b32 s2, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_not_b32_e32 v15, v18
-; GFX11-NEXT: v_add_nc_u32_e32 v19, v15, v14
+; GFX11-NEXT: v_not_b32_e32 v13, v18
+; GFX11-NEXT: v_add_nc_u32_e32 v19, v13, v12
; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], 1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
-; GFX11-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
+; GFX11-NEXT: v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], 1.0
+; GFX11-NEXT: v_rcp_f64_e32 v[16:17], v[12:13]
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX11-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
-; GFX11-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX11-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX11-NEXT: v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
; GFX11-NEXT: v_mul_f64 v[22:23], v[20:21], v[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
-; GFX11-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
+; GFX11-NEXT: v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
+; GFX11-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[22:23]
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
-; GFX11-NEXT: s_cbranch_vccnz .LBB13_15
-; GFX11-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX11-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
+; GFX11-NEXT: s_cbranch_vccnz .LBB13_13
+; GFX11-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX11-NEXT: s_sub_i32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, 26
; GFX11-NEXT: .p2align 6
-; GFX11-NEXT: .LBB13_13: ; %frem.loop_body
+; GFX11-NEXT: .LBB13_11: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
+; GFX11-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
; GFX11-NEXT: s_sub_i32 s2, s2, 26
; GFX11-NEXT: s_cmp_gt_i32 s2, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[12:13], v[16:17], v[14:15]
-; GFX11-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX11-NEXT: v_mul_f64 v[14:15], v[16:17], v[12:13]
+; GFX11-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
-; GFX11-NEXT: v_add_f64 v[19:20], v[12:13], v[10:11]
+; GFX11-NEXT: v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
+; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
+; GFX11-NEXT: v_add_f64 v[19:20], v[14:15], v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
-; GFX11-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB13_13
-; GFX11-NEXT: ; %bb.14: ; %Flow
-; GFX11-NEXT: v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
-; GFX11-NEXT: v_mov_b32_e32 v13, v17
-; GFX11-NEXT: .LBB13_15: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
-; GFX11-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
+; GFX11-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_cndmask_b32 v14, v14, v19
+; GFX11-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
+; GFX11-NEXT: s_cbranch_scc1 .LBB13_11
+; GFX11-NEXT: ; %bb.12:
+; GFX11-NEXT: v_mov_b32_e32 v19, s2
+; GFX11-NEXT: s_branch .LBB13_14
+; GFX11-NEXT: .LBB13_13:
+; GFX11-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
+; GFX11-NEXT: .LBB13_14: ; %frem.loop_exit
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f64 v[14:15], v[12:13], v[14:15]
-; GFX11-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
+; GFX11-NEXT: v_subrev_nc_u32_e32 v14, 25, v19
+; GFX11-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
+; GFX11-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; GFX11-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX11-NEXT: v_add_f64 v[10:11], v[12:13], v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17460,7 +16250,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX11-NEXT: .LBB13_16: ; %Flow50
+; GFX11-NEXT: .LBB13_15:
; GFX11-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -17484,91 +16274,91 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: global_load_b128 v[0:3], v4, s[2:3]
; GFX1150-NEXT: global_load_b128 v[4:7], v4, s[4:5] offset:64
; GFX1150-NEXT: s_waitcnt vmcnt(0)
-; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
-; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1150-NEXT: s_cbranch_vccz .LBB13_2
-; GFX1150-NEXT: ; %bb.1: ; %frem.else16
-; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX1150-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; GFX1150-NEXT: s_mov_b32 s2, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB13_3
-; GFX1150-NEXT: s_branch .LBB13_8
-; GFX1150-NEXT: .LBB13_2:
-; GFX1150-NEXT: s_mov_b32 s2, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB13_8
-; GFX1150-NEXT: .LBB13_3: ; %frem.compute15
+; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX1150-NEXT: s_cbranch_vccz .LBB13_5
+; GFX1150-NEXT: ; %bb.1: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v11, v[4:5]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[8:9], 26
+; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[8:9], 26
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
-; GFX1150-NEXT: v_add_nc_u32_e32 v16, -1, v13
-; GFX1150-NEXT: v_readfirstlane_b32 s3, v13
-; GFX1150-NEXT: v_readfirstlane_b32 s2, v12
+; GFX1150-NEXT: v_add_nc_u32_e32 v16, -1, v11
+; GFX1150-NEXT: v_readfirstlane_b32 s3, v11
+; GFX1150-NEXT: v_readfirstlane_b32 s2, v10
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_not_b32_e32 v13, v16
-; GFX1150-NEXT: v_add_nc_u32_e32 v17, v13, v12
+; GFX1150-NEXT: v_not_b32_e32 v11, v16
+; GFX1150-NEXT: v_add_nc_u32_e32 v17, v11, v10
; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[8:9], 1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
-; GFX1150-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX1150-NEXT: v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
+; GFX1150-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX1150-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX1150-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX1150-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX1150-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX1150-NEXT: v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f64 v[20:21], v[18:19], v[14:15]
-; GFX1150-NEXT: v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
+; GFX1150-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
+; GFX1150-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
-; GFX1150-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX1150-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; GFX1150-NEXT: s_cbranch_vccnz .LBB13_7
-; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_sub_i32 s2, s2, s3
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s2, s2, 26
; GFX1150-NEXT: .p2align 6
-; GFX1150-NEXT: .LBB13_5: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB13_3: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-NEXT: v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
+; GFX1150-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
; GFX1150-NEXT: s_sub_i32 s2, s2, 26
; GFX1150-NEXT: s_cmp_gt_i32 s2, 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[10:11], v[14:15], v[12:13]
-; GFX1150-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX1150-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11]
+; GFX1150-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
-; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
-; GFX1150-NEXT: v_add_f64 v[17:18], v[10:11], v[8:9]
+; GFX1150-NEXT: v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
+; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX1150-NEXT: v_add_f64 v[17:18], v[12:13], v[8:9]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
-; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB13_5
-; GFX1150-NEXT: ; %bb.6: ; %Flow51
-; GFX1150-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
-; GFX1150-NEXT: v_mov_b32_e32 v11, v15
-; GFX1150-NEXT: .LBB13_7: ; %frem.loop_exit24
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
-; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
+; GFX1150-NEXT: v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v17
+; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX1150-NEXT: s_cbranch_scc1 .LBB13_3
+; GFX1150-NEXT: ; %bb.4:
+; GFX1150-NEXT: v_mov_b32_e32 v17, s2
+; GFX1150-NEXT: s_branch .LBB13_8
+; GFX1150-NEXT: .LBB13_5: ; %frem.else16
+; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX1150-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX1150-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX1150-NEXT: s_cbranch_vccnz .LBB13_9
+; GFX1150-NEXT: .LBB13_6: ; %frem.else
+; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX1150-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX1150-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB13_15
+; GFX1150-NEXT: .LBB13_7:
+; GFX1150-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
+; GFX1150-NEXT: .LBB13_8: ; %frem.loop_exit24
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[12:13], v[10:11], v[12:13]
-; GFX1150-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1150-NEXT: v_subrev_nc_u32_e32 v12, 25, v17
+; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; GFX1150-NEXT: v_mul_f64 v[10:11], v[12:13], v[10:11]
+; GFX1150-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX1150-NEXT: v_add_f64 v[8:9], v[10:11], v[8:9]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17576,92 +16366,76 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX1150-NEXT: .LBB13_8:
-; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
-; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1150-NEXT: s_cbranch_vccz .LBB13_10
-; GFX1150-NEXT: ; %bb.9: ; %frem.else
-; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX1150-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX1150-NEXT: s_mov_b32 s2, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB13_11
-; GFX1150-NEXT: s_branch .LBB13_16
-; GFX1150-NEXT: .LBB13_10:
-; GFX1150-NEXT: s_mov_b32 s2, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr10_vgpr11
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB13_16
-; GFX1150-NEXT: .LBB13_11: ; %frem.compute
+; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX1150-NEXT: s_cbranch_vccz .LBB13_6
+; GFX1150-NEXT: .LBB13_9: ; %frem.compute
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v13, v[6:7]
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v12, v[2:3]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[10:11], 26
+; GFX1150-NEXT: v_ldexp_f64 v[14:15], v[10:11], 26
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
-; GFX1150-NEXT: v_add_nc_u32_e32 v18, -1, v15
-; GFX1150-NEXT: v_readfirstlane_b32 s3, v15
-; GFX1150-NEXT: v_readfirstlane_b32 s2, v14
+; GFX1150-NEXT: v_add_nc_u32_e32 v18, -1, v13
+; GFX1150-NEXT: v_readfirstlane_b32 s3, v13
+; GFX1150-NEXT: v_readfirstlane_b32 s2, v12
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_not_b32_e32 v15, v18
-; GFX1150-NEXT: v_add_nc_u32_e32 v19, v15, v14
+; GFX1150-NEXT: v_not_b32_e32 v13, v18
+; GFX1150-NEXT: v_add_nc_u32_e32 v19, v13, v12
; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], 1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
-; GFX1150-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
+; GFX1150-NEXT: v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], 1.0
+; GFX1150-NEXT: v_rcp_f64_e32 v[16:17], v[12:13]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX1150-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
; GFX1150-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX1150-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
; GFX1150-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX1150-NEXT: v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_mul_f64 v[22:23], v[20:21], v[16:17]
-; GFX1150-NEXT: v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
+; GFX1150-NEXT: v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
+; GFX1150-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[22:23]
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
-; GFX1150-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
-; GFX1150-NEXT: s_cbranch_vccnz .LBB13_15
-; GFX1150-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX1150-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
+; GFX1150-NEXT: s_cbranch_vccnz .LBB13_13
+; GFX1150-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_sub_i32 s2, s2, s3
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-NEXT: s_add_i32 s2, s2, 26
; GFX1150-NEXT: .p2align 6
-; GFX1150-NEXT: .LBB13_13: ; %frem.loop_body
+; GFX1150-NEXT: .LBB13_11: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-NEXT: v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
+; GFX1150-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
; GFX1150-NEXT: s_sub_i32 s2, s2, 26
; GFX1150-NEXT: s_cmp_gt_i32 s2, 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[12:13], v[16:17], v[14:15]
-; GFX1150-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1150-NEXT: v_mul_f64 v[14:15], v[16:17], v[12:13]
+; GFX1150-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
-; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
-; GFX1150-NEXT: v_add_f64 v[19:20], v[12:13], v[10:11]
+; GFX1150-NEXT: v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
+; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
+; GFX1150-NEXT: v_add_f64 v[19:20], v[14:15], v[10:11]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
-; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB13_13
-; GFX1150-NEXT: ; %bb.14: ; %Flow
-; GFX1150-NEXT: v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
-; GFX1150-NEXT: v_mov_b32_e32 v13, v17
-; GFX1150-NEXT: .LBB13_15: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
-; GFX1150-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
+; GFX1150-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_cndmask_b32 v14, v14, v19
+; GFX1150-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
+; GFX1150-NEXT: s_cbranch_scc1 .LBB13_11
+; GFX1150-NEXT: ; %bb.12:
+; GFX1150-NEXT: v_mov_b32_e32 v19, s2
+; GFX1150-NEXT: s_branch .LBB13_14
+; GFX1150-NEXT: .LBB13_13:
+; GFX1150-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
+; GFX1150-NEXT: .LBB13_14: ; %frem.loop_exit
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_mul_f64 v[14:15], v[12:13], v[14:15]
-; GFX1150-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
+; GFX1150-NEXT: v_subrev_nc_u32_e32 v14, 25, v19
+; GFX1150-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_mul_f64 v[12:13], v[14:15], v[12:13]
+; GFX1150-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; GFX1150-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX1150-NEXT: v_add_f64 v[10:11], v[12:13], v[10:11]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -17669,7 +16443,7 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX1150-NEXT: .LBB13_16: ; %Flow50
+; GFX1150-NEXT: .LBB13_15:
; GFX1150-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
; GFX1150-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
@@ -17693,92 +16467,92 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: global_load_b128 v[0:3], v4, s[2:3]
; GFX1200-NEXT: global_load_b128 v[4:7], v4, s[4:5] offset:64
; GFX1200-NEXT: s_wait_loadcnt 0x0
-; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
-; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1200-NEXT: s_cbranch_vccz .LBB13_2
-; GFX1200-NEXT: ; %bb.1: ; %frem.else16
-; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
-; GFX1200-NEXT: v_and_b32_e32 v8, 0x80000000, v1
-; GFX1200-NEXT: s_mov_b32 s2, 0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
-; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB13_3
-; GFX1200-NEXT: s_branch .LBB13_8
-; GFX1200-NEXT: .LBB13_2:
-; GFX1200-NEXT: s_mov_b32 s2, -1
-; GFX1200-NEXT: ; implicit-def: $vgpr8_vgpr9
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB13_8
-; GFX1200-NEXT: .LBB13_3: ; %frem.compute15
+; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX1200-NEXT: s_cbranch_vccz .LBB13_5
+; GFX1200-NEXT: ; %bb.1: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v13, v[4:5]
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v12, v[0:1]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v11, v[4:5]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v10, v[0:1]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[8:9], 26
+; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[8:9], 26
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
-; GFX1200-NEXT: v_add_nc_u32_e32 v16, -1, v13
-; GFX1200-NEXT: v_readfirstlane_b32 s3, v13
-; GFX1200-NEXT: v_readfirstlane_b32 s2, v12
+; GFX1200-NEXT: v_add_nc_u32_e32 v16, -1, v11
+; GFX1200-NEXT: v_readfirstlane_b32 s3, v11
+; GFX1200-NEXT: v_readfirstlane_b32 s2, v10
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_not_b32_e32 v13, v16
-; GFX1200-NEXT: v_add_nc_u32_e32 v17, v13, v12
+; GFX1200-NEXT: v_not_b32_e32 v11, v16
+; GFX1200-NEXT: v_add_nc_u32_e32 v17, v11, v10
; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[8:9], 1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
-; GFX1200-NEXT: v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX1200-NEXT: v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
+; GFX1200-NEXT: v_rcp_f64_e32 v[14:15], v[10:11]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX1200-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX1200-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX1200-NEXT: v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
; GFX1200-NEXT: v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
; GFX1200-NEXT: v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f64_e32 v[20:21], v[18:19], v[14:15]
-; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
+; GFX1200-NEXT: v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v17
-; GFX1200-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX1200-NEXT: v_div_fixup_f64 v[10:11], v[10:11], v[8:9], 1.0
; GFX1200-NEXT: s_cbranch_vccnz .LBB13_7
-; GFX1200-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_sub_co_i32 s2, s2, s3
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 26
-; GFX1200-NEXT: .LBB13_5: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB13_3: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-NEXT: v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
+; GFX1200-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_mul_f64_e32 v[10:11], v[14:15], v[12:13]
-; GFX1200-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX1200-NEXT: v_mul_f64_e32 v[12:13], v[14:15], v[10:11]
+; GFX1200-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
-; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
-; GFX1200-NEXT: v_add_f64_e32 v[17:18], v[10:11], v[8:9]
+; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[8:9], v[14:15]
+; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX1200-NEXT: v_add_f64_e32 v[17:18], v[12:13], v[8:9]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
-; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB13_5
-; GFX1200-NEXT: ; %bb.6: ; %Flow51
-; GFX1200-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
-; GFX1200-NEXT: v_mov_b32_e32 v11, v15
-; GFX1200-NEXT: .LBB13_7: ; %frem.loop_exit24
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_subrev_nc_u32_e32 v14, 25, v17
-; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], v14
+; GFX1200-NEXT: v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v17
+; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX1200-NEXT: s_cbranch_scc1 .LBB13_3
+; GFX1200-NEXT: ; %bb.4:
+; GFX1200-NEXT: v_mov_b32_e32 v17, s2
+; GFX1200-NEXT: s_branch .LBB13_8
+; GFX1200-NEXT: .LBB13_5: ; %frem.else16
+; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX1200-NEXT: v_and_b32_e32 v8, 0x80000000, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX1200-NEXT: s_cbranch_vccnz .LBB13_9
+; GFX1200-NEXT: .LBB13_6: ; %frem.else
+; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX1200-NEXT: v_and_b32_e32 v10, 0x80000000, v3
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX1200-NEXT: s_branch .LBB13_15
+; GFX1200-NEXT: .LBB13_7:
+; GFX1200-NEXT: v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
+; GFX1200-NEXT: .LBB13_8: ; %frem.loop_exit24
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_mul_f64_e32 v[12:13], v[10:11], v[12:13]
-; GFX1200-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1200-NEXT: v_subrev_nc_u32_e32 v12, 25, v17
+; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[14:15], v12
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_mul_f64_e32 v[10:11], v[12:13], v[10:11]
+; GFX1200-NEXT: v_rndne_f64_e32 v[10:11], v[10:11]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; GFX1200-NEXT: v_fma_f64 v[10:11], -v[10:11], v[8:9], v[12:13]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
; GFX1200-NEXT: v_add_f64_e32 v[8:9], v[10:11], v[8:9]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -17787,99 +16561,79 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_ldexp_f64 v[8:9], v[8:9], v16
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v9, 0x7fffffff, v9, v1
-; GFX1200-NEXT: .LBB13_8:
-; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
-; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cbranch_vccz .LBB13_10
-; GFX1200-NEXT: ; %bb.9: ; %frem.else
-; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
-; GFX1200-NEXT: v_and_b32_e32 v10, 0x80000000, v3
-; GFX1200-NEXT: s_mov_b32 s2, 0
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_cndmask_b32_e32 v11, v3, v10, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, v2, 0, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB13_11
-; GFX1200-NEXT: s_branch .LBB13_16
-; GFX1200-NEXT: .LBB13_10:
-; GFX1200-NEXT: s_mov_b32 s2, -1
-; GFX1200-NEXT: ; implicit-def: $vgpr10_vgpr11
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB13_16
-; GFX1200-NEXT: .LBB13_11: ; %frem.compute
+; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX1200-NEXT: s_cbranch_vccz .LBB13_6
+; GFX1200-NEXT: .LBB13_9: ; %frem.compute
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v15, v[6:7]
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v14, v[2:3]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v13, v[6:7]
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v12, v[2:3]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[10:11], 26
+; GFX1200-NEXT: v_ldexp_f64 v[14:15], v[10:11], 26
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
-; GFX1200-NEXT: v_add_nc_u32_e32 v18, -1, v15
-; GFX1200-NEXT: v_readfirstlane_b32 s3, v15
-; GFX1200-NEXT: v_readfirstlane_b32 s2, v14
+; GFX1200-NEXT: v_add_nc_u32_e32 v18, -1, v13
+; GFX1200-NEXT: v_readfirstlane_b32 s3, v13
+; GFX1200-NEXT: v_readfirstlane_b32 s2, v12
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_not_b32_e32 v15, v18
-; GFX1200-NEXT: v_add_nc_u32_e32 v19, v15, v14
+; GFX1200-NEXT: v_not_b32_e32 v13, v18
+; GFX1200-NEXT: v_add_nc_u32_e32 v19, v13, v12
; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], 1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
-; GFX1200-NEXT: v_rcp_f64_e32 v[16:17], v[14:15]
+; GFX1200-NEXT: v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], 1.0
+; GFX1200-NEXT: v_rcp_f64_e32 v[16:17], v[12:13]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX1200-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
; GFX1200-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX1200-NEXT: v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
; GFX1200-NEXT: v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
; GFX1200-NEXT: v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_mul_f64_e32 v[22:23], v[20:21], v[16:17]
-; GFX1200-NEXT: v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
+; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
+; GFX1200-NEXT: v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[22:23]
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v19
-; GFX1200-NEXT: v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
-; GFX1200-NEXT: s_cbranch_vccnz .LBB13_15
-; GFX1200-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_div_fixup_f64 v[12:13], v[12:13], v[10:11], 1.0
+; GFX1200-NEXT: s_cbranch_vccnz .LBB13_13
+; GFX1200-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_sub_co_i32 s2, s2, s3
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_add_co_i32 s2, s2, 26
-; GFX1200-NEXT: .LBB13_13: ; %frem.loop_body
+; GFX1200-NEXT: .LBB13_11: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
+; GFX1200-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
-; GFX1200-NEXT: v_mul_f64_e32 v[12:13], v[16:17], v[14:15]
+; GFX1200-NEXT: v_mul_f64_e32 v[14:15], v[16:17], v[12:13]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
-; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; GFX1200-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
+; GFX1200-NEXT: v_fma_f64 v[14:15], -v[14:15], v[10:11], v[16:17]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
-; GFX1200-NEXT: v_add_f64_e32 v[19:20], v[12:13], v[10:11]
+; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[14:15]
+; GFX1200-NEXT: v_add_f64_e32 v[19:20], v[14:15], v[10:11]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
+; GFX1200-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_cndmask_b32 v14, v14, v19
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[12:13], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB13_13
-; GFX1200-NEXT: ; %bb.14: ; %Flow
-; GFX1200-NEXT: v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
-; GFX1200-NEXT: v_mov_b32_e32 v13, v17
-; GFX1200-NEXT: .LBB13_15: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_subrev_nc_u32_e32 v16, 25, v19
-; GFX1200-NEXT: v_ldexp_f64 v[12:13], v[12:13], v16
+; GFX1200-NEXT: v_ldexp_f64 v[14:15], v[14:15], 26
+; GFX1200-NEXT: s_cbranch_scc1 .LBB13_11
+; GFX1200-NEXT: ; %bb.12:
+; GFX1200-NEXT: v_mov_b32_e32 v19, s2
+; GFX1200-NEXT: s_branch .LBB13_14
+; GFX1200-NEXT: .LBB13_13:
+; GFX1200-NEXT: v_dual_mov_b32 v17, v15 :: v_dual_mov_b32 v16, v14
+; GFX1200-NEXT: .LBB13_14: ; %frem.loop_exit
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_mul_f64_e32 v[14:15], v[12:13], v[14:15]
-; GFX1200-NEXT: v_rndne_f64_e32 v[14:15], v[14:15]
+; GFX1200-NEXT: v_subrev_nc_u32_e32 v14, 25, v19
+; GFX1200-NEXT: v_ldexp_f64 v[14:15], v[16:17], v14
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_mul_f64_e32 v[12:13], v[14:15], v[12:13]
+; GFX1200-NEXT: v_rndne_f64_e32 v[12:13], v[12:13]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; GFX1200-NEXT: v_fma_f64 v[12:13], -v[12:13], v[10:11], v[14:15]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
; GFX1200-NEXT: v_add_f64_e32 v[10:11], v[12:13], v[10:11]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -17888,10 +16642,9 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-NEXT: v_ldexp_f64 v[10:11], v[10:11], v18
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, v3
-; GFX1200-NEXT: .LBB13_16: ; %Flow50
+; GFX1200-NEXT: .LBB13_15:
; GFX1200-NEXT: v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
; GFX1200-NEXT: v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[2:3]|
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -18104,30 +16857,11 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s3, v1
; SI-NEXT: v_readfirstlane_b32 s2, v0
-; SI-NEXT: v_cmp_ngt_f64_e64 s[6:7], |s[2:3]|, 1.0
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, 1.0
; SI-NEXT: v_readfirstlane_b32 s4, v2
; SI-NEXT: v_readfirstlane_b32 s5, v3
-; SI-NEXT: s_and_b64 vcc, exec, s[6:7]
-; SI-NEXT: s_cbranch_vccz .LBB15_3
-; SI-NEXT: ; %bb.1: ; %frem.else16
-; SI-NEXT: v_cmp_eq_f64_e64 s[6:7], |s[2:3]|, 1.0
-; SI-NEXT: s_and_b32 s8, s3, 0x80000000
-; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
-; SI-NEXT: s_cselect_b32 s7, s8, s3
-; SI-NEXT: s_cselect_b32 s6, 0, s2
-; SI-NEXT: s_mov_b64 s[8:9], 0
-; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
-; SI-NEXT: s_cbranch_scc1 .LBB15_4
-; SI-NEXT: .LBB15_2:
-; SI-NEXT: v_mov_b32_e32 v0, s6
-; SI-NEXT: v_mov_b32_e32 v1, s7
-; SI-NEXT: s_branch .LBB15_9
-; SI-NEXT: .LBB15_3:
-; SI-NEXT: s_mov_b64 s[8:9], -1
-; SI-NEXT: ; implicit-def: $sgpr6_sgpr7
-; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
-; SI-NEXT: s_cbranch_scc0 .LBB15_2
-; SI-NEXT: .LBB15_4: ; %frem.compute15
+; SI-NEXT: s_cbranch_vccz .LBB15_4
+; SI-NEXT: ; %bb.1: ; %frem.compute15
; SI-NEXT: s_and_b32 s6, s3, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
; SI-NEXT: s_cmp_lt_i32 s6, 0x7ff00000
@@ -18137,52 +16871,71 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_mov_b32_e32 v2, s2
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; SI-NEXT: v_frexp_exp_i32_f64_e32 v2, s[2:3]
-; SI-NEXT: s_brev_b32 s8, -2
+; SI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26
; SI-NEXT: v_readfirstlane_b32 s6, v2
-; SI-NEXT: s_cselect_b32 s7, s6, 0
-; SI-NEXT: s_add_i32 s9, s7, -1
-; SI-NEXT: v_ldexp_f64 v[1:2], v[0:1], 26
-; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_cselect_b32 s6, s6, 0
+; SI-NEXT: s_add_i32 s9, s6, -1
+; SI-NEXT: s_brev_b32 s8, -2
; SI-NEXT: s_cmp_lt_i32 s9, 27
-; SI-NEXT: s_cbranch_scc1 .LBB15_8
-; SI-NEXT: ; %bb.5: ; %frem.loop_body23.preheader
-; SI-NEXT: s_add_i32 s9, s7, 25
-; SI-NEXT: v_mov_b32_e32 v5, 0x43300000
+; SI-NEXT: s_cbranch_scc1 .LBB15_6
+; SI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; SI-NEXT: s_add_i32 s9, s6, 25
+; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
; SI-NEXT: v_mov_b32_e32 v0, 0
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: .LBB15_6: ; %frem.loop_body23
+; SI-NEXT: .LBB15_3: ; %frem.loop_body23
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v4, v2
-; SI-NEXT: v_mov_b32_e32 v3, v1
-; SI-NEXT: v_bfi_b32 v1, s8, v5, v4
-; SI-NEXT: v_add_f64 v[6:7], v[3:4], v[0:1]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[3:4]|, s[6:7]
-; SI-NEXT: v_add_f64 v[1:2], v[6:7], -v[0:1]
+; SI-NEXT: v_mov_b32_e32 v3, v5
+; SI-NEXT: v_mov_b32_e32 v2, v4
+; SI-NEXT: v_bfi_b32 v1, s8, v6, v3
+; SI-NEXT: v_add_f64 v[4:5], v[2:3], v[0:1]
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
+; SI-NEXT: v_add_f64 v[4:5], v[4:5], -v[0:1]
; SI-NEXT: s_sub_i32 s9, s9, 26
-; SI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; SI-NEXT: v_add_f64 v[1:2], v[3:4], -v[1:2]
+; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc
+; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
+; SI-NEXT: v_add_f64 v[4:5], v[2:3], -v[4:5]
; SI-NEXT: s_cmp_gt_i32 s9, 26
-; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[1:2]
-; SI-NEXT: v_add_f64 v[6:7], v[1:2], 1.0
-; SI-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
-; SI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
-; SI-NEXT: v_ldexp_f64 v[1:2], v[1:2], 26
-; SI-NEXT: s_cbranch_scc1 .LBB15_6
-; SI-NEXT: ; %bb.7: ; %Flow50
-; SI-NEXT: v_mov_b32_e32 v1, v3
+; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
+; SI-NEXT: v_add_f64 v[7:8], v[4:5], 1.0
+; SI-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; SI-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; SI-NEXT: s_cbranch_scc1 .LBB15_3
+; SI-NEXT: s_branch .LBB15_7
+; SI-NEXT: .LBB15_4: ; %frem.else16
+; SI-NEXT: v_cmp_eq_f64_e64 s[6:7], |s[2:3]|, 1.0
+; SI-NEXT: s_and_b32 s8, s3, 0x80000000
+; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; SI-NEXT: s_cselect_b32 s7, s8, s3
+; SI-NEXT: s_cselect_b32 s6, 0, s2
+; SI-NEXT: v_mov_b32_e32 v0, s6
+; SI-NEXT: v_mov_b32_e32 v1, s7
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[4:5]|, 1.0
+; SI-NEXT: s_cbranch_vccnz .LBB15_8
+; SI-NEXT: .LBB15_5: ; %frem.else
+; SI-NEXT: v_cmp_eq_f64_e64 s[6:7], |s[4:5]|, 1.0
+; SI-NEXT: s_and_b32 s8, s5, 0x80000000
+; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; SI-NEXT: s_cselect_b32 s7, s8, s5
+; SI-NEXT: s_cselect_b32 s6, 0, s4
+; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v3, s7
+; SI-NEXT: s_branch .LBB15_13
+; SI-NEXT: .LBB15_6:
; SI-NEXT: v_mov_b32_e32 v2, v4
-; SI-NEXT: .LBB15_8: ; %frem.loop_exit24
+; SI-NEXT: v_mov_b32_e32 v3, v5
+; SI-NEXT: .LBB15_7: ; %frem.loop_exit24
; SI-NEXT: s_sub_i32 s6, s9, 25
-; SI-NEXT: v_ldexp_f64 v[0:1], v[1:2], s6
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[6:7]
-; SI-NEXT: s_brev_b32 s6, -2
+; SI-NEXT: v_ldexp_f64 v[0:1], v[2:3], s6
; SI-NEXT: v_mov_b32_e32 v2, 0x43300000
-; SI-NEXT: v_bfi_b32 v3, s6, v2, v1
+; SI-NEXT: v_bfi_b32 v3, s8, v2, v1
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: v_add_f64 v[4:5], v[0:1], v[2:3]
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s7, 0x432fffff
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[6:7]
; SI-NEXT: v_add_f64 v[2:3], v[4:5], -v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
@@ -18192,30 +16945,10 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; SI-NEXT: v_mov_b32_e32 v2, s3
-; SI-NEXT: v_bfi_b32 v1, s6, v1, v2
-; SI-NEXT: .LBB15_9:
-; SI-NEXT: v_cmp_ngt_f64_e64 s[6:7], |s[4:5]|, 1.0
-; SI-NEXT: s_and_b64 vcc, exec, s[6:7]
-; SI-NEXT: s_cbranch_vccz .LBB15_12
-; SI-NEXT: ; %bb.10: ; %frem.else
-; SI-NEXT: v_cmp_eq_f64_e64 s[6:7], |s[4:5]|, 1.0
-; SI-NEXT: s_and_b32 s8, s5, 0x80000000
-; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
-; SI-NEXT: s_cselect_b32 s7, s8, s5
-; SI-NEXT: s_cselect_b32 s6, 0, s4
-; SI-NEXT: s_mov_b64 s[8:9], 0
-; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
-; SI-NEXT: s_cbranch_scc1 .LBB15_13
-; SI-NEXT: .LBB15_11:
-; SI-NEXT: v_mov_b32_e32 v2, s6
-; SI-NEXT: v_mov_b32_e32 v3, s7
-; SI-NEXT: s_branch .LBB15_18
-; SI-NEXT: .LBB15_12:
-; SI-NEXT: s_mov_b64 s[8:9], -1
-; SI-NEXT: ; implicit-def: $sgpr6_sgpr7
-; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
-; SI-NEXT: s_cbranch_scc0 .LBB15_11
-; SI-NEXT: .LBB15_13: ; %frem.compute
+; SI-NEXT: v_bfi_b32 v1, s8, v1, v2
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[4:5]|, 1.0
+; SI-NEXT: s_cbranch_vccz .LBB15_5
+; SI-NEXT: .LBB15_8: ; %frem.compute
; SI-NEXT: s_and_b32 s6, s5, 0x7fffffff
; SI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[4:5]|
; SI-NEXT: s_cmp_lt_i32 s6, 0x7ff00000
@@ -18225,52 +16958,51 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; SI-NEXT: v_frexp_exp_i32_f64_e32 v4, s[4:5]
-; SI-NEXT: s_brev_b32 s8, -2
+; SI-NEXT: v_ldexp_f64 v[6:7], v[2:3], 26
; SI-NEXT: v_readfirstlane_b32 s6, v4
; SI-NEXT: s_cselect_b32 s7, s6, 0
; SI-NEXT: s_add_i32 s9, s7, -1
-; SI-NEXT: v_ldexp_f64 v[3:4], v[2:3], 26
+; SI-NEXT: s_brev_b32 s8, -2
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_cmp_lt_i32 s9, 27
-; SI-NEXT: s_cbranch_scc1 .LBB15_17
-; SI-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; SI-NEXT: s_cbranch_scc1 .LBB15_11
+; SI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
; SI-NEXT: s_add_i32 s9, s7, 25
-; SI-NEXT: v_mov_b32_e32 v7, 0x43300000
+; SI-NEXT: v_mov_b32_e32 v8, 0x43300000
; SI-NEXT: v_mov_b32_e32 v2, 0
; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: .LBB15_15: ; %frem.loop_body
+; SI-NEXT: .LBB15_10: ; %frem.loop_body
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_mov_b32_e32 v6, v4
-; SI-NEXT: v_mov_b32_e32 v5, v3
-; SI-NEXT: v_bfi_b32 v3, s8, v7, v6
-; SI-NEXT: v_add_f64 v[8:9], v[5:6], v[2:3]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[5:6]|, s[6:7]
-; SI-NEXT: v_add_f64 v[3:4], v[8:9], -v[2:3]
+; SI-NEXT: v_mov_b32_e32 v5, v7
+; SI-NEXT: v_mov_b32_e32 v4, v6
+; SI-NEXT: v_bfi_b32 v3, s8, v8, v5
+; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[2:3]
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
+; SI-NEXT: v_add_f64 v[6:7], v[6:7], -v[2:3]
; SI-NEXT: s_sub_i32 s9, s9, 26
-; SI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; SI-NEXT: v_add_f64 v[3:4], v[5:6], -v[3:4]
+; SI-NEXT: v_cndmask_b32_e32 v7, v7, v5, vcc
+; SI-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc
+; SI-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
; SI-NEXT: s_cmp_gt_i32 s9, 26
-; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[3:4]
-; SI-NEXT: v_add_f64 v[8:9], v[3:4], 1.0
-; SI-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
-; SI-NEXT: v_ldexp_f64 v[3:4], v[3:4], 26
-; SI-NEXT: s_cbranch_scc1 .LBB15_15
-; SI-NEXT: ; %bb.16: ; %Flow
-; SI-NEXT: v_mov_b32_e32 v3, v5
+; SI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; SI-NEXT: v_add_f64 v[9:10], v[6:7], 1.0
+; SI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; SI-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; SI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; SI-NEXT: s_cbranch_scc1 .LBB15_10
+; SI-NEXT: s_branch .LBB15_12
+; SI-NEXT: .LBB15_11:
; SI-NEXT: v_mov_b32_e32 v4, v6
-; SI-NEXT: .LBB15_17: ; %frem.loop_exit
-; SI-NEXT: s_sub_i32 s6, s9, 25
-; SI-NEXT: v_ldexp_f64 v[2:3], v[3:4], s6
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
-; SI-NEXT: s_brev_b32 s6, -2
+; SI-NEXT: v_mov_b32_e32 v5, v7
+; SI-NEXT: .LBB15_12: ; %frem.loop_exit
+; SI-NEXT: s_sub_i32 s7, s9, 25
+; SI-NEXT: v_ldexp_f64 v[2:3], v[4:5], s7
; SI-NEXT: v_mov_b32_e32 v4, 0x43300000
-; SI-NEXT: v_bfi_b32 v5, s6, v4, v3
+; SI-NEXT: v_bfi_b32 v5, s8, v4, v3
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: v_add_f64 v[6:7], v[2:3], v[4:5]
+; SI-NEXT: s_mov_b32 s7, 0x432fffff
+; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
; SI-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
@@ -18280,8 +17012,8 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; SI-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; SI-NEXT: v_mov_b32_e32 v4, s5
-; SI-NEXT: v_bfi_b32 v3, s6, v3, v4
-; SI-NEXT: .LBB15_18: ; %Flow49
+; SI-NEXT: v_bfi_b32 v3, s8, v3, v4
+; SI-NEXT: .LBB15_13:
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
; SI-NEXT: v_cmp_nge_f64_e64 vcc, |s[2:3]|, v[4:5]
@@ -18306,47 +17038,46 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: s_mov_b32 s5, s3
; CI-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, 1.0
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB15_2
-; CI-NEXT: ; %bb.1: ; %frem.else16
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
-; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
-; CI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB15_3
-; CI-NEXT: s_branch .LBB15_8
-; CI-NEXT: .LBB15_2:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr4_vgpr5
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB15_8
-; CI-NEXT: .LBB15_3: ; %frem.compute15
-; CI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; CI-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v6
+; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, 1.0
+; CI-NEXT: s_cbranch_vccz .LBB15_4
+; CI-NEXT: ; %bb.1: ; %frem.compute15
+; CI-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[0:1]|
+; CI-NEXT: v_frexp_exp_i32_f64_e32 v4, v[0:1]
+; CI-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
+; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v4
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v8
-; CI-NEXT: s_cbranch_vccnz .LBB15_7
-; CI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
-; CI-NEXT: v_add_i32_e32 v8, vcc, 25, v6
-; CI-NEXT: .LBB15_5: ; %frem.loop_body23
+; CI-NEXT: s_cbranch_vccnz .LBB15_6
+; CI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; CI-NEXT: v_add_i32_e32 v8, vcc, 25, v4
+; CI-NEXT: .LBB15_3: ; %frem.loop_body23
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v7, v5
-; CI-NEXT: v_mov_b32_e32 v6, v4
-; CI-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
-; CI-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
-; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; CI-NEXT: v_add_f64 v[9:10], v[4:5], 1.0
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
-; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; CI-NEXT: v_mov_b32_e32 v4, v6
+; CI-NEXT: v_mov_b32_e32 v5, v7
+; CI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; CI-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; CI-NEXT: v_add_f64 v[9:10], v[6:7], 1.0
+; CI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; CI-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; CI-NEXT: v_subrev_i32_e32 v8, vcc, 26, v8
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v8
-; CI-NEXT: s_cbranch_vccnz .LBB15_5
-; CI-NEXT: ; %bb.6: ; %Flow50
+; CI-NEXT: s_cbranch_vccnz .LBB15_3
+; CI-NEXT: s_branch .LBB15_7
+; CI-NEXT: .LBB15_4: ; %frem.else16
+; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
+; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; CI-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc
+; CI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
+; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
+; CI-NEXT: s_cbranch_vccnz .LBB15_8
+; CI-NEXT: .LBB15_5: ; %frem.else
+; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
+; CI-NEXT: v_and_b32_e32 v4, 0x80000000, v3
+; CI-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc
+; CI-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc
+; CI-NEXT: s_branch .LBB15_13
+; CI-NEXT: .LBB15_6:
; CI-NEXT: v_mov_b32_e32 v4, v6
; CI-NEXT: v_mov_b32_e32 v5, v7
; CI-NEXT: .LBB15_7: ; %frem.loop_exit24
@@ -18357,42 +17088,26 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; CI-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; CI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; CI-NEXT: .LBB15_8:
-; CI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, 1.0
-; CI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; CI-NEXT: s_cbranch_vccz .LBB15_10
-; CI-NEXT: ; %bb.9: ; %frem.else
-; CI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
-; CI-NEXT: v_and_b32_e32 v6, 0x80000000, v3
-; CI-NEXT: s_mov_b64 s[2:3], 0
-; CI-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc
-; CI-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc1 .LBB15_11
-; CI-NEXT: s_branch .LBB15_16
-; CI-NEXT: .LBB15_10:
-; CI-NEXT: s_mov_b64 s[2:3], -1
-; CI-NEXT: ; implicit-def: $vgpr6_vgpr7
-; CI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; CI-NEXT: s_cbranch_scc0 .LBB15_16
-; CI-NEXT: .LBB15_11: ; %frem.compute
-; CI-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
-; CI-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
-; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; CI-NEXT: v_add_i32_e32 v10, vcc, -1, v8
+; CI-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc
+; CI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
+; CI-NEXT: v_bfi_b32 v9, s2, v4, v1
+; CI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
+; CI-NEXT: s_cbranch_vccz .LBB15_5
+; CI-NEXT: .LBB15_8: ; %frem.compute
+; CI-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[2:3]|
+; CI-NEXT: v_frexp_exp_i32_f64_e32 v4, v[2:3]
+; CI-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
+; CI-NEXT: v_add_i32_e32 v10, vcc, -1, v4
; CI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v10
-; CI-NEXT: s_cbranch_vccnz .LBB15_15
-; CI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; CI-NEXT: v_add_i32_e32 v10, vcc, 25, v8
-; CI-NEXT: .LBB15_13: ; %frem.loop_body
+; CI-NEXT: s_cbranch_vccnz .LBB15_11
+; CI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; CI-NEXT: v_add_i32_e32 v10, vcc, 25, v4
+; CI-NEXT: .LBB15_10: ; %frem.loop_body
; CI-NEXT: ; =>This Inner Loop Header: Depth=1
-; CI-NEXT: v_mov_b32_e32 v9, v7
-; CI-NEXT: v_mov_b32_e32 v8, v6
-; CI-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
-; CI-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
+; CI-NEXT: v_mov_b32_e32 v4, v6
+; CI-NEXT: v_mov_b32_e32 v5, v7
+; CI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; CI-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; CI-NEXT: v_add_f64 v[11:12], v[6:7], 1.0
; CI-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
@@ -18400,33 +17115,34 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; CI-NEXT: v_subrev_i32_e32 v10, vcc, 26, v10
; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v10
-; CI-NEXT: s_cbranch_vccnz .LBB15_13
-; CI-NEXT: ; %bb.14: ; %Flow
-; CI-NEXT: v_mov_b32_e32 v6, v8
-; CI-NEXT: v_mov_b32_e32 v7, v9
-; CI-NEXT: .LBB15_15: ; %frem.loop_exit
-; CI-NEXT: v_subrev_i32_e32 v8, vcc, 25, v10
-; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; CI-NEXT: s_cbranch_vccnz .LBB15_10
+; CI-NEXT: s_branch .LBB15_12
+; CI-NEXT: .LBB15_11:
+; CI-NEXT: v_mov_b32_e32 v4, v6
+; CI-NEXT: v_mov_b32_e32 v5, v7
+; CI-NEXT: .LBB15_12: ; %frem.loop_exit
+; CI-NEXT: v_subrev_i32_e32 v6, vcc, 25, v10
+; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; CI-NEXT: s_brev_b32 s2, -2
-; CI-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
-; CI-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
-; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
-; CI-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
-; CI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; CI-NEXT: v_bfi_b32 v7, s2, v7, v3
-; CI-NEXT: .LBB15_16: ; %Flow49
+; CI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; CI-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
+; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
+; CI-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
+; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; CI-NEXT: v_bfi_b32 v5, s2, v5, v3
+; CI-NEXT: .LBB15_13:
; CI-NEXT: s_mov_b32 s4, 0
; CI-NEXT: s_mov_b32 s5, 0x7ff00000
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[4:5]
-; CI-NEXT: v_mov_b32_e32 v8, 0x7ff80000
+; CI-NEXT: v_mov_b32_e32 v6, 0x7ff80000
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, -1
-; CI-NEXT: v_cndmask_b32_e32 v1, v8, v5, vcc
-; CI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; CI-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc
+; CI-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[4:5]
-; CI-NEXT: v_cndmask_b32_e32 v3, v8, v7, vcc
-; CI-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
+; CI-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc
+; CI-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; CI-NEXT: s_endpgm
;
@@ -18438,47 +17154,46 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, 1.0
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB15_2
-; VI-NEXT: ; %bb.1: ; %frem.else16
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
-; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
-; VI-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB15_3
-; VI-NEXT: s_branch .LBB15_8
-; VI-NEXT: .LBB15_2:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr4_vgpr5
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB15_8
-; VI-NEXT: .LBB15_3: ; %frem.compute15
-; VI-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; VI-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v6
+; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, 1.0
+; VI-NEXT: s_cbranch_vccz .LBB15_4
+; VI-NEXT: ; %bb.1: ; %frem.compute15
+; VI-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[0:1]|
+; VI-NEXT: v_frexp_exp_i32_f64_e32 v4, v[0:1]
+; VI-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
+; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v4
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v8
-; VI-NEXT: s_cbranch_vccnz .LBB15_7
-; VI-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
-; VI-NEXT: v_add_u32_e32 v8, vcc, 25, v6
-; VI-NEXT: .LBB15_5: ; %frem.loop_body23
+; VI-NEXT: s_cbranch_vccnz .LBB15_6
+; VI-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; VI-NEXT: v_add_u32_e32 v8, vcc, 25, v4
+; VI-NEXT: .LBB15_3: ; %frem.loop_body23
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v7, v5
-; VI-NEXT: v_mov_b32_e32 v6, v4
-; VI-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
-; VI-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
-; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; VI-NEXT: v_add_f64 v[9:10], v[4:5], 1.0
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
-; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; VI-NEXT: v_mov_b32_e32 v4, v6
+; VI-NEXT: v_mov_b32_e32 v5, v7
+; VI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; VI-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; VI-NEXT: v_add_f64 v[9:10], v[6:7], 1.0
+; VI-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; VI-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; VI-NEXT: v_subrev_u32_e32 v8, vcc, 26, v8
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v8
-; VI-NEXT: s_cbranch_vccnz .LBB15_5
-; VI-NEXT: ; %bb.6: ; %Flow50
+; VI-NEXT: s_cbranch_vccnz .LBB15_3
+; VI-NEXT: s_branch .LBB15_7
+; VI-NEXT: .LBB15_4: ; %frem.else16
+; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
+; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; VI-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc
+; VI-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
+; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
+; VI-NEXT: s_cbranch_vccnz .LBB15_8
+; VI-NEXT: .LBB15_5: ; %frem.else
+; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
+; VI-NEXT: v_and_b32_e32 v4, 0x80000000, v3
+; VI-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc
+; VI-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc
+; VI-NEXT: s_branch .LBB15_13
+; VI-NEXT: .LBB15_6:
; VI-NEXT: v_mov_b32_e32 v4, v6
; VI-NEXT: v_mov_b32_e32 v5, v7
; VI-NEXT: .LBB15_7: ; %frem.loop_exit24
@@ -18489,42 +17204,26 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; VI-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; VI-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; VI-NEXT: v_bfi_b32 v5, s2, v5, v1
-; VI-NEXT: .LBB15_8:
-; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, 1.0
-; VI-NEXT: s_and_b64 vcc, exec, s[2:3]
-; VI-NEXT: s_cbranch_vccz .LBB15_10
-; VI-NEXT: ; %bb.9: ; %frem.else
-; VI-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
-; VI-NEXT: v_and_b32_e32 v6, 0x80000000, v3
-; VI-NEXT: s_mov_b64 s[2:3], 0
-; VI-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc
-; VI-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc1 .LBB15_11
-; VI-NEXT: s_branch .LBB15_16
-; VI-NEXT: .LBB15_10:
-; VI-NEXT: s_mov_b64 s[2:3], -1
-; VI-NEXT: ; implicit-def: $vgpr6_vgpr7
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; VI-NEXT: s_cbranch_scc0 .LBB15_16
-; VI-NEXT: .LBB15_11: ; %frem.compute
-; VI-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
-; VI-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
-; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; VI-NEXT: v_add_u32_e32 v10, vcc, -1, v8
+; VI-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc
+; VI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
+; VI-NEXT: v_bfi_b32 v9, s2, v4, v1
+; VI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
+; VI-NEXT: s_cbranch_vccz .LBB15_5
+; VI-NEXT: .LBB15_8: ; %frem.compute
+; VI-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[2:3]|
+; VI-NEXT: v_frexp_exp_i32_f64_e32 v4, v[2:3]
+; VI-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
+; VI-NEXT: v_add_u32_e32 v10, vcc, -1, v4
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 27, v10
-; VI-NEXT: s_cbranch_vccnz .LBB15_15
-; VI-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; VI-NEXT: v_add_u32_e32 v10, vcc, 25, v8
-; VI-NEXT: .LBB15_13: ; %frem.loop_body
+; VI-NEXT: s_cbranch_vccnz .LBB15_11
+; VI-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; VI-NEXT: v_add_u32_e32 v10, vcc, 25, v4
+; VI-NEXT: .LBB15_10: ; %frem.loop_body
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_mov_b32_e32 v9, v7
-; VI-NEXT: v_mov_b32_e32 v8, v6
-; VI-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
-; VI-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
+; VI-NEXT: v_mov_b32_e32 v4, v6
+; VI-NEXT: v_mov_b32_e32 v5, v7
+; VI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; VI-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; VI-NEXT: v_add_f64 v[11:12], v[6:7], 1.0
; VI-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
@@ -18532,34 +17231,35 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; VI-NEXT: v_subrev_u32_e32 v10, vcc, 26, v10
; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v10
-; VI-NEXT: s_cbranch_vccnz .LBB15_13
-; VI-NEXT: ; %bb.14: ; %Flow
-; VI-NEXT: v_mov_b32_e32 v6, v8
-; VI-NEXT: v_mov_b32_e32 v7, v9
-; VI-NEXT: .LBB15_15: ; %frem.loop_exit
-; VI-NEXT: v_subrev_u32_e32 v8, vcc, 25, v10
-; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; VI-NEXT: s_cbranch_vccnz .LBB15_10
+; VI-NEXT: s_branch .LBB15_12
+; VI-NEXT: .LBB15_11:
+; VI-NEXT: v_mov_b32_e32 v4, v6
+; VI-NEXT: v_mov_b32_e32 v5, v7
+; VI-NEXT: .LBB15_12: ; %frem.loop_exit
+; VI-NEXT: v_subrev_u32_e32 v6, vcc, 25, v10
+; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; VI-NEXT: s_brev_b32 s2, -2
-; VI-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
-; VI-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
-; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
-; VI-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
-; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; VI-NEXT: v_bfi_b32 v7, s2, v7, v3
-; VI-NEXT: .LBB15_16: ; %Flow49
+; VI-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; VI-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
+; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
+; VI-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
+; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; VI-NEXT: v_bfi_b32 v5, s2, v5, v3
+; VI-NEXT: .LBB15_13:
; VI-NEXT: s_mov_b32 s2, 0
; VI-NEXT: s_mov_b32 s3, 0x7ff00000
; VI-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[2:3]
-; VI-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; VI-NEXT: v_cndmask_b32_e32 v1, v8, v5, vcc
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; VI-NEXT: v_mov_b32_e32 v10, 0x7ff80000
+; VI-NEXT: v_mov_b32_e32 v6, s0
+; VI-NEXT: v_mov_b32_e32 v7, s1
+; VI-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; VI-NEXT: v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[2:3]
-; VI-NEXT: v_mov_b32_e32 v4, s0
-; VI-NEXT: v_mov_b32_e32 v5, s1
-; VI-NEXT: v_cndmask_b32_e32 v3, v8, v7, vcc
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
-; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; VI-NEXT: v_cndmask_b32_e32 v3, v10, v5, vcc
+; VI-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; VI-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: frem_v2f64_const_one_denum:
@@ -18569,47 +17269,46 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, 1.0
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB15_2
-; GFX9-NEXT: ; %bb.1: ; %frem.else16
-; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
-; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB15_3
-; GFX9-NEXT: s_branch .LBB15_8
-; GFX9-NEXT: .LBB15_2:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB15_8
-; GFX9-NEXT: .LBB15_3: ; %frem.compute15
-; GFX9-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
-; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX9-NEXT: v_add_u32_e32 v8, -1, v6
+; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, 1.0
+; GFX9-NEXT: s_cbranch_vccz .LBB15_4
+; GFX9-NEXT: ; %bb.1: ; %frem.compute15
+; GFX9-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[0:1]|
+; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v4, v[0:1]
+; GFX9-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
+; GFX9-NEXT: v_add_u32_e32 v8, -1, v4
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v8
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_7
-; GFX9-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
-; GFX9-NEXT: v_add_u32_e32 v8, 25, v6
-; GFX9-NEXT: .LBB15_5: ; %frem.loop_body23
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_6
+; GFX9-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
+; GFX9-NEXT: v_add_u32_e32 v8, 25, v4
+; GFX9-NEXT: .LBB15_3: ; %frem.loop_body23
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v7, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, v4
-; GFX9-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
+; GFX9-NEXT: v_mov_b32_e32 v4, v6
+; GFX9-NEXT: v_mov_b32_e32 v5, v7
+; GFX9-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
; GFX9-NEXT: v_subrev_u32_e32 v8, 26, v8
-; GFX9-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
-; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
-; GFX9-NEXT: v_add_f64 v[9:10], v[4:5], 1.0
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
-; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
+; GFX9-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; GFX9-NEXT: v_add_f64 v[9:10], v[6:7], 1.0
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
+; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v8
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_5
-; GFX9-NEXT: ; %bb.6: ; %Flow50
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_3
+; GFX9-NEXT: s_branch .LBB15_7
+; GFX9-NEXT: .LBB15_4: ; %frem.else16
+; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[0:1]|, 1.0
+; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc
+; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_8
+; GFX9-NEXT: .LBB15_5: ; %frem.else
+; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
+; GFX9-NEXT: v_and_b32_e32 v4, 0x80000000, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc
+; GFX9-NEXT: s_branch .LBB15_13
+; GFX9-NEXT: .LBB15_6:
; GFX9-NEXT: v_mov_b32_e32 v4, v6
; GFX9-NEXT: v_mov_b32_e32 v5, v7
; GFX9-NEXT: .LBB15_7: ; %frem.loop_exit24
@@ -18620,76 +17319,61 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
; GFX9-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v1
-; GFX9-NEXT: .LBB15_8:
-; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, 1.0
-; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3]
-; GFX9-NEXT: s_cbranch_vccz .LBB15_10
-; GFX9-NEXT: ; %bb.9: ; %frem.else
-; GFX9-NEXT: v_cmp_eq_f64_e64 vcc, |v[2:3]|, 1.0
-; GFX9-NEXT: v_and_b32_e32 v6, 0x80000000, v3
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc1 .LBB15_11
-; GFX9-NEXT: s_branch .LBB15_16
-; GFX9-NEXT: .LBB15_10:
-; GFX9-NEXT: s_mov_b64 s[2:3], -1
-; GFX9-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX9-NEXT: s_cbranch_scc0 .LBB15_16
-; GFX9-NEXT: .LBB15_11: ; %frem.compute
-; GFX9-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
-; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
-; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX9-NEXT: v_add_u32_e32 v10, -1, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
+; GFX9-NEXT: v_bfi_b32 v9, s2, v4, v1
+; GFX9-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, 1.0
+; GFX9-NEXT: s_cbranch_vccz .LBB15_5
+; GFX9-NEXT: .LBB15_8: ; %frem.compute
+; GFX9-NEXT: v_frexp_mant_f64_e64 v[5:6], |v[2:3]|
+; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v4, v[2:3]
+; GFX9-NEXT: v_ldexp_f64 v[6:7], v[5:6], 26
+; GFX9-NEXT: v_add_u32_e32 v10, -1, v4
; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 27, v10
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_15
-; GFX9-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; GFX9-NEXT: v_add_u32_e32 v10, 25, v8
-; GFX9-NEXT: .LBB15_13: ; %frem.loop_body
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_11
+; GFX9-NEXT: ; %bb.9: ; %frem.loop_body.preheader
+; GFX9-NEXT: v_add_u32_e32 v10, 25, v4
+; GFX9-NEXT: .LBB15_10: ; %frem.loop_body
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_mov_b32_e32 v9, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, v6
-; GFX9-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
+; GFX9-NEXT: v_mov_b32_e32 v4, v6
+; GFX9-NEXT: v_mov_b32_e32 v5, v7
+; GFX9-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
; GFX9-NEXT: v_subrev_u32_e32 v10, 26, v10
-; GFX9-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
+; GFX9-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
; GFX9-NEXT: v_add_f64 v[11:12], v[6:7], 1.0
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc
; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 26, v10
-; GFX9-NEXT: s_cbranch_vccnz .LBB15_13
-; GFX9-NEXT: ; %bb.14: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v6, v8
-; GFX9-NEXT: v_mov_b32_e32 v7, v9
-; GFX9-NEXT: .LBB15_15: ; %frem.loop_exit
-; GFX9-NEXT: v_subrev_u32_e32 v8, 25, v10
-; GFX9-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; GFX9-NEXT: s_cbranch_vccnz .LBB15_10
+; GFX9-NEXT: s_branch .LBB15_12
+; GFX9-NEXT: .LBB15_11:
+; GFX9-NEXT: v_mov_b32_e32 v4, v6
+; GFX9-NEXT: v_mov_b32_e32 v5, v7
+; GFX9-NEXT: .LBB15_12: ; %frem.loop_exit
+; GFX9-NEXT: v_subrev_u32_e32 v6, 25, v10
+; GFX9-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX9-NEXT: s_brev_b32 s2, -2
-; GFX9-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
-; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
-; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7]
-; GFX9-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
-; GFX9-NEXT: v_bfi_b32 v7, s2, v7, v3
-; GFX9-NEXT: .LBB15_16: ; %Flow49
+; GFX9-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
+; GFX9-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v3
+; GFX9-NEXT: .LBB15_13:
; GFX9-NEXT: s_mov_b32 s2, 0
; GFX9-NEXT: s_mov_b32 s3, 0x7ff00000
; GFX9-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v5, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x7ff80000
+; GFX9-NEXT: v_mov_b32_e32 v7, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc
; GFX9-NEXT: v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v7, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc
-; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX9-NEXT: global_store_dwordx4 v7, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: frem_v2f64_const_one_denum:
@@ -18699,126 +17383,112 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, 1.0
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB15_2
-; GFX10-NEXT: ; %bb.1: ; %frem.else16
-; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB15_3
-; GFX10-NEXT: s_branch .LBB15_8
-; GFX10-NEXT: .LBB15_2:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB15_8
-; GFX10-NEXT: .LBB15_3: ; %frem.compute15
+; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX10-NEXT: s_cbranch_vccz .LBB15_5
+; GFX10-NEXT: ; %bb.1: ; %frem.compute15
; GFX10-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX10-NEXT: v_add_nc_u32_e32 v8, -1, v6
; GFX10-NEXT: v_readfirstlane_b32 s2, v6
+; GFX10-NEXT: v_add_nc_u32_e32 v8, -1, v6
+; GFX10-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
; GFX10-NEXT: s_cbranch_vccnz .LBB15_7
-; GFX10-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX10-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX10-NEXT: s_add_i32 s2, s2, 25
-; GFX10-NEXT: .LBB15_5: ; %frem.loop_body23
+; GFX10-NEXT: .LBB15_3: ; %frem.loop_body23
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v7, v5
-; GFX10-NEXT: v_mov_b32_e32 v6, v4
+; GFX10-NEXT: v_mov_b32_e32 v4, v6
+; GFX10-NEXT: v_mov_b32_e32 v5, v7
; GFX10-NEXT: s_sub_i32 s2, s2, 26
; GFX10-NEXT: s_cmp_gt_i32 s2, 26
-; GFX10-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
-; GFX10-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
-; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
-; GFX10-NEXT: v_add_f64 v[8:9], v[4:5], 1.0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
-; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB15_5
-; GFX10-NEXT: ; %bb.6: ; %Flow50
+; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX10-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
+; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX10-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX10-NEXT: s_cbranch_scc1 .LBB15_3
+; GFX10-NEXT: ; %bb.4:
; GFX10-NEXT: v_mov_b32_e32 v8, s2
+; GFX10-NEXT: s_branch .LBB15_8
+; GFX10-NEXT: .LBB15_5: ; %frem.else16
+; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX10-NEXT: s_cbranch_vccnz .LBB15_9
+; GFX10-NEXT: .LBB15_6: ; %frem.else
+; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX10-NEXT: v_and_b32_e32 v4, 0x80000000, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc_lo
+; GFX10-NEXT: s_branch .LBB15_15
+; GFX10-NEXT: .LBB15_7:
; GFX10-NEXT: v_mov_b32_e32 v4, v6
; GFX10-NEXT: v_mov_b32_e32 v5, v7
-; GFX10-NEXT: .LBB15_7: ; %frem.loop_exit24
+; GFX10-NEXT: .LBB15_8: ; %frem.loop_exit24
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
; GFX10-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX10-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX10-NEXT: .LBB15_8:
-; GFX10-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
-; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX10-NEXT: s_cbranch_vccz .LBB15_10
-; GFX10-NEXT: ; %bb.9: ; %frem.else
-; GFX10-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX10-NEXT: v_and_b32_e32 v6, 0x80000000, v3
-; GFX10-NEXT: s_mov_b32 s2, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc1 .LBB15_11
-; GFX10-NEXT: s_branch .LBB15_16
-; GFX10-NEXT: .LBB15_10:
-; GFX10-NEXT: s_mov_b32 s2, -1
-; GFX10-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cbranch_scc0 .LBB15_16
-; GFX10-NEXT: .LBB15_11: ; %frem.compute
-; GFX10-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
-; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
-; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX10-NEXT: v_add_nc_u32_e32 v10, -1, v8
-; GFX10-NEXT: v_readfirstlane_b32 s2, v8
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v9, 0x7fffffff, v4, v1
+; GFX10-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX10-NEXT: s_cbranch_vccz .LBB15_6
+; GFX10-NEXT: .LBB15_9: ; %frem.compute
+; GFX10-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v6, v[2:3]
+; GFX10-NEXT: v_readfirstlane_b32 s2, v6
+; GFX10-NEXT: v_add_nc_u32_e32 v10, -1, v6
+; GFX10-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX10-NEXT: s_cbranch_vccnz .LBB15_15
-; GFX10-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX10-NEXT: s_cbranch_vccnz .LBB15_13
+; GFX10-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX10-NEXT: s_add_i32 s2, s2, 25
-; GFX10-NEXT: .LBB15_13: ; %frem.loop_body
+; GFX10-NEXT: .LBB15_11: ; %frem.loop_body
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: v_mov_b32_e32 v9, v7
-; GFX10-NEXT: v_mov_b32_e32 v8, v6
+; GFX10-NEXT: v_mov_b32_e32 v4, v6
+; GFX10-NEXT: v_mov_b32_e32 v5, v7
; GFX10-NEXT: s_sub_i32 s2, s2, 26
; GFX10-NEXT: s_cmp_gt_i32 s2, 26
-; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
-; GFX10-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
+; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX10-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX10-NEXT: v_add_f64 v[10:11], v[6:7], 1.0
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX10-NEXT: s_cbranch_scc1 .LBB15_13
-; GFX10-NEXT: ; %bb.14: ; %Flow
+; GFX10-NEXT: s_cbranch_scc1 .LBB15_11
+; GFX10-NEXT: ; %bb.12:
; GFX10-NEXT: v_mov_b32_e32 v10, s2
-; GFX10-NEXT: v_mov_b32_e32 v6, v8
-; GFX10-NEXT: v_mov_b32_e32 v7, v9
-; GFX10-NEXT: .LBB15_15: ; %frem.loop_exit
-; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
-; GFX10-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
-; GFX10-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
-; GFX10-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
-; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX10-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
-; GFX10-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
-; GFX10-NEXT: .LBB15_16: ; %Flow49
+; GFX10-NEXT: s_branch .LBB15_14
+; GFX10-NEXT: .LBB15_13:
+; GFX10-NEXT: v_mov_b32_e32 v4, v6
+; GFX10-NEXT: v_mov_b32_e32 v5, v7
+; GFX10-NEXT: .LBB15_14: ; %frem.loop_exit
+; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 25, v10
+; GFX10-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; GFX10-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX10-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
+; GFX10-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
+; GFX10-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX10-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v3
+; GFX10-NEXT: .LBB15_15:
; GFX10-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v6, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v8, vcc_lo
; GFX10-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
-; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7ff80000, v7, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc_lo
-; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX10-NEXT: v_cndmask_b32_e32 v3, 0x7ff80000, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
+; GFX10-NEXT: global_store_dwordx4 v6, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: frem_v2f64_const_one_denum:
@@ -18828,58 +17498,59 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, 1.0
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB15_2
-; GFX11-NEXT: ; %bb.1: ; %frem.else16
-; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB15_3
-; GFX11-NEXT: s_branch .LBB15_8
-; GFX11-NEXT: .LBB15_2:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB15_8
-; GFX11-NEXT: .LBB15_3: ; %frem.compute15
+; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX11-NEXT: s_cbranch_vccz .LBB15_5
+; GFX11-NEXT: ; %bb.1: ; %frem.compute15
; GFX11-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX11-NEXT: v_add_nc_u32_e32 v8, -1, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_readfirstlane_b32 s2, v6
+; GFX11-NEXT: v_add_nc_u32_e32 v8, -1, v6
+; GFX11-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
; GFX11-NEXT: s_cbranch_vccnz .LBB15_7
-; GFX11-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX11-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX11-NEXT: s_add_i32 s2, s2, 25
-; GFX11-NEXT: .LBB15_5: ; %frem.loop_body23
+; GFX11-NEXT: .LBB15_3: ; %frem.loop_body23
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX11-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
; GFX11-NEXT: s_sub_i32 s2, s2, 26
; GFX11-NEXT: s_cmp_gt_i32 s2, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
-; GFX11-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
+; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX11-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
-; GFX11-NEXT: v_add_f64 v[8:9], v[4:5], 1.0
-; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
+; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX11-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB15_5
-; GFX11-NEXT: ; %bb.6: ; %Flow50
-; GFX11-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
-; GFX11-NEXT: v_mov_b32_e32 v4, v6
-; GFX11-NEXT: .LBB15_7: ; %frem.loop_exit24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX11-NEXT: s_cbranch_scc1 .LBB15_3
+; GFX11-NEXT: ; %bb.4:
+; GFX11-NEXT: v_mov_b32_e32 v8, s2
+; GFX11-NEXT: s_branch .LBB15_8
+; GFX11-NEXT: .LBB15_5: ; %frem.else16
+; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX11-NEXT: s_cbranch_vccnz .LBB15_9
+; GFX11-NEXT: .LBB15_6: ; %frem.else
+; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX11-NEXT: v_and_b32_e32 v4, 0x80000000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc_lo
+; GFX11-NEXT: s_branch .LBB15_15
+; GFX11-NEXT: .LBB15_7:
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX11-NEXT: .LBB15_8: ; %frem.loop_exit24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -18888,81 +17559,67 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX11-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX11-NEXT: .LBB15_8:
-; GFX11-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX11-NEXT: s_cbranch_vccz .LBB15_10
-; GFX11-NEXT: ; %bb.9: ; %frem.else
-; GFX11-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX11-NEXT: v_and_b32_e32 v6, 0x80000000, v3
-; GFX11-NEXT: s_mov_b32 s2, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc1 .LBB15_11
-; GFX11-NEXT: s_branch .LBB15_16
-; GFX11-NEXT: .LBB15_10:
-; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-NEXT: s_cbranch_scc0 .LBB15_16
-; GFX11-NEXT: .LBB15_11: ; %frem.compute
-; GFX11-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
-; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX11-NEXT: v_add_nc_u32_e32 v10, -1, v8
-; GFX11-NEXT: v_readfirstlane_b32 s2, v8
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
+; GFX11-NEXT: v_bfi_b32 v9, 0x7fffffff, v4, v1
+; GFX11-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX11-NEXT: s_cbranch_vccz .LBB15_6
+; GFX11-NEXT: .LBB15_9: ; %frem.compute
+; GFX11-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v6, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_readfirstlane_b32 s2, v6
+; GFX11-NEXT: v_add_nc_u32_e32 v10, -1, v6
+; GFX11-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX11-NEXT: s_cbranch_vccnz .LBB15_15
-; GFX11-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX11-NEXT: s_cbranch_vccnz .LBB15_13
+; GFX11-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX11-NEXT: s_add_i32 s2, s2, 25
-; GFX11-NEXT: .LBB15_13: ; %frem.loop_body
+; GFX11-NEXT: .LBB15_11: ; %frem.loop_body
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
+; GFX11-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
; GFX11-NEXT: s_sub_i32 s2, s2, 26
; GFX11-NEXT: s_cmp_gt_i32 s2, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
-; GFX11-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
+; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX11-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX11-NEXT: v_add_f64 v[10:11], v[6:7], 1.0
; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX11-NEXT: s_cbranch_scc1 .LBB15_13
-; GFX11-NEXT: ; %bb.14: ; %Flow
-; GFX11-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
-; GFX11-NEXT: v_mov_b32_e32 v6, v8
-; GFX11-NEXT: .LBB15_15: ; %frem.loop_exit
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
-; GFX11-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; GFX11-NEXT: s_cbranch_scc1 .LBB15_11
+; GFX11-NEXT: ; %bb.12:
+; GFX11-NEXT: v_mov_b32_e32 v10, s2
+; GFX11-NEXT: s_branch .LBB15_14
+; GFX11-NEXT: .LBB15_13:
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX11-NEXT: .LBB15_14: ; %frem.loop_exit
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_nc_u32_e32 v6, 25, v10
+; GFX11-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
-; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
+; GFX11-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX11-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
-; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
-; GFX11-NEXT: .LBB15_16: ; %Flow49
+; GFX11-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v3
+; GFX11-NEXT: .LBB15_15:
; GFX11-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
-; GFX11-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v5 :: v_dual_cndmask_b32 v0, 0, v4
+; GFX11-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v9 :: v_dual_cndmask_b32 v0, 0, v8
; GFX11-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v7
-; GFX11-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc_lo
-; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX11-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
+; GFX11-NEXT: global_store_b128 v6, v[0:3], s[0:1]
; GFX11-NEXT: s_endpgm
;
; GFX1150-LABEL: frem_v2f64_const_one_denum:
@@ -18972,58 +17629,59 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: s_waitcnt lgkmcnt(0)
; GFX1150-NEXT: global_load_b128 v[0:3], v0, s[2:3]
; GFX1150-NEXT: s_waitcnt vmcnt(0)
-; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, 1.0
-; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1150-NEXT: s_cbranch_vccz .LBB15_2
-; GFX1150-NEXT: ; %bb.1: ; %frem.else16
-; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX1150-NEXT: s_mov_b32 s2, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB15_3
-; GFX1150-NEXT: s_branch .LBB15_8
-; GFX1150-NEXT: .LBB15_2:
-; GFX1150-NEXT: s_mov_b32 s2, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB15_8
-; GFX1150-NEXT: .LBB15_3: ; %frem.compute15
+; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX1150-NEXT: s_cbranch_vccz .LBB15_5
+; GFX1150-NEXT: ; %bb.1: ; %frem.compute15
; GFX1150-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX1150-NEXT: v_add_nc_u32_e32 v8, -1, v6
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1150-NEXT: v_readfirstlane_b32 s2, v6
+; GFX1150-NEXT: v_add_nc_u32_e32 v8, -1, v6
+; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
; GFX1150-NEXT: s_cbranch_vccnz .LBB15_7
-; GFX1150-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX1150-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX1150-NEXT: s_add_i32 s2, s2, 25
-; GFX1150-NEXT: .LBB15_5: ; %frem.loop_body23
+; GFX1150-NEXT: .LBB15_3: ; %frem.loop_body23
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX1150-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
; GFX1150-NEXT: s_sub_i32 s2, s2, 26
; GFX1150-NEXT: s_cmp_gt_i32 s2, 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
-; GFX1150-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
+; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX1150-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
-; GFX1150-NEXT: v_add_f64 v[8:9], v[4:5], 1.0
-; GFX1150-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
+; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1150-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
+; GFX1150-NEXT: v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB15_5
-; GFX1150-NEXT: ; %bb.6: ; %Flow50
-; GFX1150-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
-; GFX1150-NEXT: v_mov_b32_e32 v4, v6
-; GFX1150-NEXT: .LBB15_7: ; %frem.loop_exit24
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX1150-NEXT: s_cbranch_scc1 .LBB15_3
+; GFX1150-NEXT: ; %bb.4:
+; GFX1150-NEXT: v_mov_b32_e32 v8, s2
+; GFX1150-NEXT: s_branch .LBB15_8
+; GFX1150-NEXT: .LBB15_5: ; %frem.else16
+; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc_lo
+; GFX1150-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX1150-NEXT: s_cbranch_vccnz .LBB15_9
+; GFX1150-NEXT: .LBB15_6: ; %frem.else
+; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX1150-NEXT: v_and_b32_e32 v4, 0x80000000, v3
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc_lo
+; GFX1150-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc_lo
+; GFX1150-NEXT: s_branch .LBB15_15
+; GFX1150-NEXT: .LBB15_7:
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX1150-NEXT: .LBB15_8: ; %frem.loop_exit24
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -19032,81 +17690,67 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1150-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
-; GFX1150-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX1150-NEXT: .LBB15_8:
-; GFX1150-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
-; GFX1150-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1150-NEXT: s_cbranch_vccz .LBB15_10
-; GFX1150-NEXT: ; %bb.9: ; %frem.else
-; GFX1150-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX1150-NEXT: v_and_b32_e32 v6, 0x80000000, v3
-; GFX1150-NEXT: s_mov_b32 s2, 0
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
-; GFX1150-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
-; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cbranch_scc1 .LBB15_11
-; GFX1150-NEXT: s_branch .LBB15_16
-; GFX1150-NEXT: .LBB15_10:
-; GFX1150-NEXT: s_mov_b32 s2, -1
-; GFX1150-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-NEXT: s_cbranch_scc0 .LBB15_16
-; GFX1150-NEXT: .LBB15_11: ; %frem.compute
-; GFX1150-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
-; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1150-NEXT: v_add_nc_u32_e32 v10, -1, v8
-; GFX1150-NEXT: v_readfirstlane_b32 s2, v8
+; GFX1150-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc_lo
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
+; GFX1150-NEXT: v_bfi_b32 v9, 0x7fffffff, v4, v1
+; GFX1150-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX1150-NEXT: s_cbranch_vccz .LBB15_6
+; GFX1150-NEXT: .LBB15_9: ; %frem.compute
+; GFX1150-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; GFX1150-NEXT: v_frexp_exp_i32_f64_e32 v6, v[2:3]
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1150-NEXT: v_readfirstlane_b32 s2, v6
+; GFX1150-NEXT: v_add_nc_u32_e32 v10, -1, v6
+; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1150-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX1150-NEXT: s_cbranch_vccnz .LBB15_15
-; GFX1150-NEXT: ; %bb.12: ; %frem.loop_body.preheader
+; GFX1150-NEXT: s_cbranch_vccnz .LBB15_13
+; GFX1150-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX1150-NEXT: s_add_i32 s2, s2, 25
-; GFX1150-NEXT: .LBB15_13: ; %frem.loop_body
+; GFX1150-NEXT: .LBB15_11: ; %frem.loop_body
; GFX1150-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
+; GFX1150-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
; GFX1150-NEXT: s_sub_i32 s2, s2, 26
; GFX1150-NEXT: s_cmp_gt_i32 s2, 26
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
-; GFX1150-NEXT: v_add_f64 v[6:7], v[8:9], -v[6:7]
+; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX1150-NEXT: v_add_f64 v[6:7], v[4:5], -v[6:7]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1150-NEXT: v_add_f64 v[10:11], v[6:7], 1.0
; GFX1150-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1150-NEXT: s_cbranch_scc1 .LBB15_13
-; GFX1150-NEXT: ; %bb.14: ; %Flow
-; GFX1150-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
-; GFX1150-NEXT: v_mov_b32_e32 v6, v8
-; GFX1150-NEXT: .LBB15_15: ; %frem.loop_exit
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
-; GFX1150-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; GFX1150-NEXT: s_cbranch_scc1 .LBB15_11
+; GFX1150-NEXT: ; %bb.12:
+; GFX1150-NEXT: v_mov_b32_e32 v10, s2
+; GFX1150-NEXT: s_branch .LBB15_14
+; GFX1150-NEXT: .LBB15_13:
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX1150-NEXT: .LBB15_14: ; %frem.loop_exit
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
-; GFX1150-NEXT: v_add_f64 v[6:7], v[6:7], -v[8:9]
+; GFX1150-NEXT: v_subrev_nc_u32_e32 v6, 25, v10
+; GFX1150-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX1150-NEXT: v_add_f64 v[4:5], v[4:5], -v[6:7]
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX1150-NEXT: v_add_f64 v[8:9], v[6:7], 1.0
-; GFX1150-NEXT: v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX1150-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
+; GFX1150-NEXT: v_add_f64 v[6:7], v[4:5], 1.0
+; GFX1150-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
-; GFX1150-NEXT: .LBB15_16: ; %Flow49
+; GFX1150-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v3
+; GFX1150-NEXT: .LBB15_15:
; GFX1150-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
-; GFX1150-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v5 :: v_dual_cndmask_b32 v0, 0, v4
+; GFX1150-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v9 :: v_dual_cndmask_b32 v0, 0, v8
; GFX1150-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1150-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v7
-; GFX1150-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc_lo
-; GFX1150-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1150-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v5
+; GFX1150-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
+; GFX1150-NEXT: global_store_b128 v6, v[0:3], s[0:1]
; GFX1150-NEXT: s_endpgm
;
; GFX1200-LABEL: frem_v2f64_const_one_denum:
@@ -19116,59 +17760,61 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: global_load_b128 v[0:3], v0, s[2:3]
; GFX1200-NEXT: s_wait_loadcnt 0x0
-; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[0:1]|, 1.0
-; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1200-NEXT: s_cbranch_vccz .LBB15_2
-; GFX1200-NEXT: ; %bb.1: ; %frem.else16
-; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
-; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v1
-; GFX1200-NEXT: s_mov_b32 s2, 0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_cndmask_b32_e32 v5, v1, v4, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v4, v0, 0, vcc_lo
-; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB15_3
-; GFX1200-NEXT: s_branch .LBB15_8
-; GFX1200-NEXT: .LBB15_2:
-; GFX1200-NEXT: s_mov_b32 s2, -1
-; GFX1200-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB15_8
-; GFX1200-NEXT: .LBB15_3: ; %frem.compute15
+; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX1200-NEXT: s_cbranch_vccz .LBB15_5
+; GFX1200-NEXT: ; %bb.1: ; %frem.compute15
; GFX1200-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v6, v[0:1]
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX1200-NEXT: v_add_nc_u32_e32 v8, -1, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_readfirstlane_b32 s2, v6
+; GFX1200-NEXT: v_add_nc_u32_e32 v8, -1, v6
+; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v8
; GFX1200-NEXT: s_cbranch_vccnz .LBB15_7
-; GFX1200-NEXT: ; %bb.4: ; %frem.loop_body23.preheader
+; GFX1200-NEXT: ; %bb.2: ; %frem.loop_body23.preheader
; GFX1200-NEXT: s_add_co_i32 s2, s2, 25
-; GFX1200-NEXT: .LBB15_5: ; %frem.loop_body23
+; GFX1200-NEXT: .LBB15_3: ; %frem.loop_body23
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
+; GFX1200-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_rndne_f64_e32 v[4:5], v[6:7]
-; GFX1200-NEXT: v_add_f64_e64 v[4:5], v[6:7], -v[4:5]
+; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX1200-NEXT: v_add_f64_e64 v[6:7], v[4:5], -v[6:7]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
-; GFX1200-NEXT: v_add_f64_e32 v[8:9], 1.0, v[4:5]
+; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1200-NEXT: v_add_f64_e32 v[8:9], 1.0, v[6:7]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_cndmask_b32 v4, v4, v8
+; GFX1200-NEXT: v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB15_5
-; GFX1200-NEXT: ; %bb.6: ; %Flow50
-; GFX1200-NEXT: v_dual_mov_b32 v8, s2 :: v_dual_mov_b32 v5, v7
-; GFX1200-NEXT: v_mov_b32_e32 v4, v6
-; GFX1200-NEXT: .LBB15_7: ; %frem.loop_exit24
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX1200-NEXT: s_cbranch_scc1 .LBB15_3
+; GFX1200-NEXT: ; %bb.4:
+; GFX1200-NEXT: v_mov_b32_e32 v8, s2
+; GFX1200-NEXT: s_branch .LBB15_8
+; GFX1200-NEXT: .LBB15_5: ; %frem.else16
+; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, 1.0
+; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b32_e32 v9, v1, v4, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX1200-NEXT: s_cbranch_vccnz .LBB15_9
+; GFX1200-NEXT: .LBB15_6: ; %frem.else
+; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX1200-NEXT: v_and_b32_e32 v4, 0x80000000, v3
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b32_e32 v5, v3, v4, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v4, v2, 0, vcc_lo
+; GFX1200-NEXT: s_branch .LBB15_15
+; GFX1200-NEXT: .LBB15_7:
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX1200-NEXT: .LBB15_8: ; %frem.loop_exit24
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_subrev_nc_u32_e32 v6, 25, v8
; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -19178,89 +17824,71 @@ define amdgpu_kernel void @frem_v2f64_const_one_denum(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
; GFX1200-NEXT: v_add_f64_e32 v[6:7], 1.0, v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v1
-; GFX1200-NEXT: .LBB15_8:
-; GFX1200-NEXT: v_cmp_ngt_f64_e64 s2, |v[2:3]|, 1.0
-; GFX1200-NEXT: s_and_b32 vcc_lo, exec_lo, s2
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_cbranch_vccz .LBB15_10
-; GFX1200-NEXT: ; %bb.9: ; %frem.else
-; GFX1200-NEXT: v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, 1.0
-; GFX1200-NEXT: v_and_b32_e32 v6, 0x80000000, v3
-; GFX1200-NEXT: s_mov_b32 s2, 0
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_cndmask_b32_e32 v7, v3, v6, vcc_lo
-; GFX1200-NEXT: v_cndmask_b32_e64 v6, v2, 0, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cbranch_scc1 .LBB15_11
-; GFX1200-NEXT: s_branch .LBB15_16
-; GFX1200-NEXT: .LBB15_10:
-; GFX1200-NEXT: s_mov_b32 s2, -1
-; GFX1200-NEXT: ; implicit-def: $vgpr6_vgpr7
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-NEXT: s_cbranch_scc0 .LBB15_16
-; GFX1200-NEXT: .LBB15_11: ; %frem.compute
-; GFX1200-NEXT: v_frexp_mant_f64_e64 v[6:7], |v[2:3]|
-; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v8, v[2:3]
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1200-NEXT: v_add_nc_u32_e32 v10, -1, v8
-; GFX1200-NEXT: v_readfirstlane_b32 s2, v8
+; GFX1200-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
+; GFX1200-NEXT: v_bfi_b32 v9, 0x7fffffff, v4, v1
+; GFX1200-NEXT: v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, 1.0
+; GFX1200-NEXT: s_cbranch_vccz .LBB15_6
+; GFX1200-NEXT: .LBB15_9: ; %frem.compute
+; GFX1200-NEXT: v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; GFX1200-NEXT: v_frexp_exp_i32_f64_e32 v6, v[2:3]
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_readfirstlane_b32 s2, v6
+; GFX1200-NEXT: v_add_nc_u32_e32 v10, -1, v6
+; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[4:5], 26
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 27, v10
-; GFX1200-NEXT: s_cbranch_vccnz .LBB15_15
-; GFX1200-NEXT: ; %bb.12: ; %frem.loop_body.preheader
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_cbranch_vccnz .LBB15_13
+; GFX1200-NEXT: ; %bb.10: ; %frem.loop_body.preheader
; GFX1200-NEXT: s_add_co_i32 s2, s2, 25
-; GFX1200-NEXT: .LBB15_13: ; %frem.loop_body
+; GFX1200-NEXT: .LBB15_11: ; %frem.loop_body
; GFX1200-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
+; GFX1200-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_sub_co_i32 s2, s2, 26
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_cmp_gt_i32 s2, 26
-; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[8:9]
+; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_add_f64_e64 v[6:7], v[8:9], -v[6:7]
+; GFX1200-NEXT: v_add_f64_e64 v[6:7], v[4:5], -v[6:7]
; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
; GFX1200-NEXT: v_add_f64_e32 v[10:11], 1.0, v[6:7]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_cndmask_b32 v6, v6, v10
; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26
-; GFX1200-NEXT: s_cbranch_scc1 .LBB15_13
-; GFX1200-NEXT: ; %bb.14: ; %Flow
-; GFX1200-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v7, v9
-; GFX1200-NEXT: v_mov_b32_e32 v6, v8
-; GFX1200-NEXT: .LBB15_15: ; %frem.loop_exit
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_subrev_nc_u32_e32 v8, 25, v10
-; GFX1200-NEXT: v_ldexp_f64 v[6:7], v[6:7], v8
+; GFX1200-NEXT: s_cbranch_scc1 .LBB15_11
+; GFX1200-NEXT: ; %bb.12:
+; GFX1200-NEXT: v_mov_b32_e32 v10, s2
+; GFX1200-NEXT: s_branch .LBB15_14
+; GFX1200-NEXT: .LBB15_13:
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7
+; GFX1200-NEXT: .LBB15_14: ; %frem.loop_exit
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_rndne_f64_e32 v[8:9], v[6:7]
-; GFX1200-NEXT: v_add_f64_e64 v[6:7], v[6:7], -v[8:9]
+; GFX1200-NEXT: v_subrev_nc_u32_e32 v6, 25, v10
+; GFX1200-NEXT: v_ldexp_f64 v[4:5], v[4:5], v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_rndne_f64_e32 v[6:7], v[4:5]
+; GFX1200-NEXT: v_add_f64_e64 v[4:5], v[4:5], -v[6:7]
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
-; GFX1200-NEXT: v_add_f64_e32 v[8:9], 1.0, v[6:7]
+; GFX1200-NEXT: v_cmp_gt_f64_e32 vcc_lo, 0, v[4:5]
+; GFX1200-NEXT: v_add_f64_e32 v[6:7], 1.0, v[4:5]
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v7, v7, v9
+; GFX1200-NEXT: v_dual_cndmask_b32 v4, v4, v6 :: v_dual_cndmask_b32 v5, v5, v7
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v3
-; GFX1200-NEXT: .LBB15_16: ; %Flow49
+; GFX1200-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v3
+; GFX1200-NEXT: .LBB15_15:
; GFX1200-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v5 :: v_dual_cndmask_b32 v0, 0, v4
+; GFX1200-NEXT: v_dual_cndmask_b32 v1, 0x7ff80000, v9 :: v_dual_cndmask_b32 v0, 0, v8
; GFX1200-NEXT: v_cmp_nle_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v7
-; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc_lo
-; GFX1200-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1200-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v3, 0x7ff80000, v5
+; GFX1200-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
+; GFX1200-NEXT: global_store_b128 v6, v[0:3], s[0:1]
; GFX1200-NEXT: s_endpgm
%r0 = load <2 x double>, ptr addrspace(1) %in, align 16
%r1 = frem <2 x double> %r0, <double 1.0, double 1.0>
diff --git a/llvm/test/CodeGen/AMDGPU/itofp-odd-width-load.ll b/llvm/test/CodeGen/AMDGPU/itofp-odd-width-load.ll
index 75dd8d6748264b..da1b22f5b5690b 100644
--- a/llvm/test/CodeGen/AMDGPU/itofp-odd-width-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/itofp-odd-width-load.ll
@@ -310,12 +310,14 @@ define amdgpu_kernel void @sitofp_i48_constant_align2(ptr addrspace(4) %in, ptr
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: global_load_b32 v0, v2, s[0:1] nv
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: s_load_i16 s0, s[0:1], 0x4 nv
+; GFX1250-NEXT: s_load_u16 s0, s[0:1], 0x4 nv
; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100000
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: v_mov_b32_e32 v1, s0
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1250-NEXT: s_xor_b32 s1, s1, s0
+; GFX1250-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1250-NEXT: s_xor_b32 s1, s4, s0
; GFX1250-NEXT: s_cls_i32 s0, s0
; GFX1250-NEXT: s_ashr_i32 s1, s1, 31
; GFX1250-NEXT: s_add_co_i32 s0, s0, -1
@@ -437,23 +439,25 @@ define amdgpu_kernel void @sitofp_i48_global_align8(ptr addrspace(1) %in, ptr ad
; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b32 s4, s[0:1], 0x0
-; GFX1250-NEXT: s_load_i16 s5, s[0:1], 0x4
+; GFX1250-NEXT: s_load_u16 s4, s[0:1], 0x4
+; GFX1250-NEXT: s_load_b32 s6, s[0:1], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_xor_b32 s0, s4, s5
-; GFX1250-NEXT: s_cls_i32 s1, s5
-; GFX1250-NEXT: s_ashr_i32 s0, s0, 31
-; GFX1250-NEXT: s_add_co_i32 s1, s1, -1
-; GFX1250-NEXT: s_add_co_i32 s0, s0, 32
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_min_u32 s6, s1, s0
-; GFX1250-NEXT: s_lshl_b64 s[0:1], s[4:5], s6
+; GFX1250-NEXT: s_bfe_i64 s[0:1], s[4:5], 0x100000
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_xor_b32 s1, s6, s0
+; GFX1250-NEXT: s_cls_i32 s4, s0
+; GFX1250-NEXT: s_ashr_i32 s1, s1, 31
+; GFX1250-NEXT: s_add_co_i32 s4, s4, -1
+; GFX1250-NEXT: s_add_co_i32 s1, s1, 32
+; GFX1250-NEXT: s_mov_b32 s7, s0
+; GFX1250-NEXT: s_min_u32 s4, s4, s1
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_lshl_b64 s[0:1], s[6:7], s4
; GFX1250-NEXT: s_min_u32 s0, s0, 1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_3)
; GFX1250-NEXT: s_or_b32 s0, s1, s0
-; GFX1250-NEXT: s_sub_co_i32 s1, 32, s6
+; GFX1250-NEXT: s_sub_co_i32 s1, 32, s4
; GFX1250-NEXT: s_cvt_f32_i32 s0, s0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-NEXT: v_ldexp_f32 v1, s0, s1
; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT: s_endpgm
More information about the llvm-commits
mailing list