[llvm] [AMDGPU] Legalize uniform 16-bit loads to match subword load instructions (PR #225097)

[Matt Arsenault via llvm-commits]

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@@ -17972,7 +17884,8 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
 
   // fold (truncate (load x)) -> (smaller load x)
   // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
-  if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
+  if (!LegalTypes ||
+      TLI.isTypeDesirableForOp(N0.getOpcode(), VT, N0.getNode())) {
     if (SDValue Reduced = reduceLoadWidth(N))
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arsenm wrote:

We need to complete the migration to getLoadAction (and introduce the appropriate store mirror, which annoyingly only almost exists in the form of getTruncStoreAction)

https://github.com/llvm/llvm-project/pull/225097