[llvm] [RISCV][P-ext] Remove unnecessary check from (p)m(racc) handling in LowerIntrinsic_WO_CHAIN. NFC (PR #228172)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

This was rejecting MVT::i32 on RV64, but this check was mutually exclusive with every other case handled in this block. We can let it go to the final return SDValue().

I'm not sure we can even get to this case anyway since ReplaceNodeResults should be called for an illegal MVT::i32 on RV64.

---
Full diff: https://github.com/llvm/llvm-project/pull/228172.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (-4) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5c2cb79379dfa..21b570a75ad28 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13071,10 +13071,6 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     SDValue Rs2 = Op.getOperand(3);
     MVT XLenVT = Subtarget.getXLenVT();
 
-    bool IsScalarHalfword = VT == MVT::i32;
-    if (Subtarget.is64Bit() && IsScalarHalfword)
-      return SDValue();
-
     if (VT == MVT::v2i32 && Rs1.getSimpleValueType() == MVT::v4i16) {
       if (Subtarget.is64Bit()) {
         unsigned Opc = getRVPQFormatAccOpcode(IntNo);

``````````

</details>


https://github.com/llvm/llvm-project/pull/228172