[llvm] [SelectionDAG] Avoid redundant comparisons in bit-test switch lowering (PR #222626)
Shreeyash Pandey via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 21:58:37 PDT 2026
https://github.com/bojle updated https://github.com/llvm/llvm-project/pull/222626
>From e951b2a512c5c3af7999cb4576de590ab68c4b8a Mon Sep 17 00:00:00 2001
From: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: Tue, 15 Sep 2026 17:49:05 +0530
Subject: [PATCH 1/7] [SelectionDAG] Avoid redundant comparisons in bit-test
switch lowering
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Fixes https://github.com/llvm/llvm-project/issues/155953
Previously, SelectionDAG switch lowering used the same BitTestBlock::Default/fallthrough destination for
both bit-test misses and failures of the bit-test’s numeric range check. This could produce redundant
comparisons, such as testing x == 4 after x > 12 had already been established. The patch creates stable
MBB entries for all clusters and records a separate RangeCheckDefault, allowing a range-check failure to
jump directly to the first safe upper out-of-range cluster, or to the switch default, while bit-test misses
retain the normal fallthrough chain. This is enabled only for zero-based bit-test ranges whose remaining
clusters form an in-range prefix followed by an upper out-of-range suffix. In the reproducer, cases 7–12
form a bit-test with First = 0, so its numeric range is [0,12] (values 0–6 are holes), [4,4] is still in
range, and a later cluster such as [1897,1897] is above the range and can be targeted directly.
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
---
.../AArch64/switch-bittest-range-check.ll | 167 ++++++++++++++++++
1 file changed, 167 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll
diff --git a/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll b/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll
new file mode 100644
index 00000000000000..6c4041a6233be3
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll
@@ -0,0 +1,167 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -O2 -verify-machineinstrs < %s | FileCheck %s
+
+declare void @foo1(i32)
+declare void @foo2(i32)
+declare void @foo3(i32)
+declare void @foo4(i32)
+declare void @foo5(i32)
+
+define i32 @switch1(i32 %x) "no-jump-tables"="true" {
+; CHECK-LABEL: switch1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w19, -8
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: mov w19, w0
+; CHECK-NEXT: cmp w0, #12
+; CHECK-NEXT: b.hi .LBB0_6
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: mov w8, #1152 // =0x480
+; CHECK-NEXT: lsr w8, w8, w19
+; CHECK-NEXT: tbnz w8, #0, .LBB0_8
+; CHECK-NEXT: // %bb.2: // %entry
+; CHECK-NEXT: mov w8, #2304 // =0x900
+; CHECK-NEXT: lsr w8, w8, w19
+; CHECK-NEXT: tbnz w8, #0, .LBB0_5
+; CHECK-NEXT: // %bb.3: // %entry
+; CHECK-NEXT: mov w8, #4608 // =0x1200
+; CHECK-NEXT: lsr w8, w8, w19
+; CHECK-NEXT: tbz w8, #0, .LBB0_6
+; CHECK-NEXT: // %bb.4: // %case9
+; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: bl foo3
+; CHECK-NEXT: b .LBB0_10
+; CHECK-NEXT: .LBB0_5: // %case8
+; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: bl foo2
+; CHECK-NEXT: b .LBB0_10
+; CHECK-NEXT: .LBB0_6: // %entry
+; CHECK-NEXT: cmp w19, #4
+; CHECK-NEXT: b.ne .LBB0_9
+; CHECK-NEXT: // %bb.7: // %case4
+; CHECK-NEXT: mov w0, #4 // =0x4
+; CHECK-NEXT: bl foo4
+; CHECK-NEXT: b .LBB0_10
+; CHECK-NEXT: .LBB0_8: // %case7
+; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: bl foo1
+; CHECK-NEXT: b .LBB0_10
+; CHECK-NEXT: .LBB0_9:
+; CHECK-NEXT: mov w19, wzr
+; CHECK-NEXT: .LBB0_10: // %return
+; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+entry:
+ switch i32 %x, label %return [
+ i32 7, label %case7
+ i32 10, label %case7
+ i32 8, label %case8
+ i32 11, label %case8
+ i32 9, label %case9
+ i32 12, label %case9
+ i32 4, label %case4
+ ]
+case7:
+ tail call void @foo1(i32 %x)
+ br label %return
+case8:
+ tail call void @foo2(i32 %x)
+ br label %return
+case9:
+ tail call void @foo3(i32 %x)
+ br label %return
+case4:
+ tail call void @foo4(i32 4)
+ br label %return
+return:
+ %result = phi i32 [ 0, %entry ], [ 4, %case4 ], [ %x, %case9 ], [ %x, %case8 ], [ %x, %case7 ]
+ ret i32 %result
+}
+
+define i32 @switch2(i32 %x) "no-jump-tables"="true" {
+; CHECK-LABEL: switch2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w19, -8
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: mov w19, w0
+; CHECK-NEXT: cmp w0, #12
+; CHECK-NEXT: b.hi .LBB1_5
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: mov w8, #1152 // =0x480
+; CHECK-NEXT: lsr w8, w8, w19
+; CHECK-NEXT: tbnz w8, #0, .LBB1_9
+; CHECK-NEXT: // %bb.2: // %entry
+; CHECK-NEXT: mov w8, #2304 // =0x900
+; CHECK-NEXT: lsr w8, w8, w19
+; CHECK-NEXT: tbnz w8, #0, .LBB1_8
+; CHECK-NEXT: // %bb.3: // %entry
+; CHECK-NEXT: mov w8, #4608 // =0x1200
+; CHECK-NEXT: lsr w8, w8, w19
+; CHECK-NEXT: tbz w8, #0, .LBB1_5
+; CHECK-NEXT: // %bb.4: // %case9
+; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: bl foo3
+; CHECK-NEXT: b .LBB1_12
+; CHECK-NEXT: .LBB1_5: // %entry
+; CHECK-NEXT: cmp w19, #4
+; CHECK-NEXT: b.eq .LBB1_10
+; CHECK-NEXT: // %bb.6: // %entry
+; CHECK-NEXT: cmp w19, #1897
+; CHECK-NEXT: b.ne .LBB1_11
+; CHECK-NEXT: // %bb.7: // %case1897
+; CHECK-NEXT: mov w0, #4 // =0x4
+; CHECK-NEXT: bl foo5
+; CHECK-NEXT: b .LBB1_12
+; CHECK-NEXT: .LBB1_8: // %case8
+; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: bl foo2
+; CHECK-NEXT: b .LBB1_12
+; CHECK-NEXT: .LBB1_9: // %case7
+; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: bl foo1
+; CHECK-NEXT: b .LBB1_12
+; CHECK-NEXT: .LBB1_10: // %case4
+; CHECK-NEXT: mov w0, #4 // =0x4
+; CHECK-NEXT: bl foo4
+; CHECK-NEXT: b .LBB1_12
+; CHECK-NEXT: .LBB1_11:
+; CHECK-NEXT: mov w19, wzr
+; CHECK-NEXT: .LBB1_12: // %return
+; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+entry:
+ switch i32 %x, label %return [
+ i32 7, label %case7
+ i32 10, label %case7
+ i32 8, label %case8
+ i32 11, label %case8
+ i32 9, label %case9
+ i32 12, label %case9
+ i32 4, label %case4
+ i32 1897, label %case1897
+ ]
+case7:
+ tail call void @foo1(i32 %x)
+ br label %return
+case8:
+ tail call void @foo2(i32 %x)
+ br label %return
+case9:
+ tail call void @foo3(i32 %x)
+ br label %return
+case4:
+ tail call void @foo4(i32 4)
+ br label %return
+case1897:
+ tail call void @foo5(i32 4)
+ br label %return
+return:
+ %result = phi i32 [ 0, %entry ], [ 4, %case4 ], [ 1897, %case1897 ], [ %x, %case9 ], [ %x, %case8 ], [ %x, %case7 ]
+ ret i32 %result
+}
>From 37e39cce9b409d89cee7fdcf001de80a22889178 Mon Sep 17 00:00:00 2001
From: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: Tue, 15 Sep 2026 17:51:12 +0530
Subject: [PATCH 2/7] add code
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
---
.../llvm/CodeGen/SwitchLoweringUtils.h | 3 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 91 +++++++++++---
.../AArch64/switch-bittest-range-check.ll | 116 +++++++++---------
3 files changed, 138 insertions(+), 72 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h b/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
index 33fa71ae109ea8..89f05f71d8adf8 100644
--- a/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
+++ b/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
@@ -224,6 +224,7 @@ struct BitTestBlock {
bool ContiguousRange;
MachineBasicBlock *Parent;
MachineBasicBlock *Default;
+ MachineBasicBlock *RangeCheckDefault; // When outside [First, First + Range]
BitTestInfo Cases;
BranchProbability Prob;
BranchProbability DefaultProb;
@@ -234,7 +235,7 @@ struct BitTestBlock {
BitTestInfo C, BranchProbability Pr)
: First(std::move(F)), Range(std::move(R)), SValue(SV), Reg(Rg),
RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
- Cases(std::move(C)), Prob(Pr) {}
+ RangeCheckDefault(nullptr), Cases(std::move(C)), Prob(Pr) {}
};
/// Return the range of values within a range.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index eea69e41b26ebc..fd906de81bb164 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -3352,10 +3352,12 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
B.Reg = FuncInfo.CreateReg(B.RegVT);
SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
- MachineBasicBlock* MBB = B.Cases[0].ThisBB;
+ MachineBasicBlock *MBB = B.Cases[0].ThisBB;
+ MachineBasicBlock *RangeCheckDefault =
+ B.RangeCheckDefault ? B.RangeCheckDefault : B.Default;
if (!B.FallthroughUnreachable)
- addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
+ addSuccessorWithProb(SwitchBB, RangeCheckDefault, B.DefaultProb);
addSuccessorWithProb(SwitchBB, MBB, B.Prob);
SwitchBB->normalizeSuccProbs();
@@ -3369,7 +3371,7 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
ISD::SETUGT);
Root = DAG.getNode(ISD::BRCOND, dl, MVT::Other, Root, RangeCmp,
- DAG.getBasicBlock(B.Default));
+ DAG.getBasicBlock(RangeCheckDefault));
}
// Avoid emitting unnecessary branches to the next block.
@@ -12578,20 +12580,45 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
UnhandledProbs += I->Prob;
- MachineBasicBlock *CurMBB = W.MBB;
- for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
+ // Insert bit-test blocks before the linear work-item continuation blocks so
+ // that pre-creating the latter preserves the existing layout.
+ for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
+ if (I->Kind != CC_BitTests)
+ continue;
+ BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex];
+ for (BitTestCase &BTC : BTB->Cases)
+ CurMF->insert(BBI, BTC.ThisBB);
+ }
+
+ // Give every cluster a stable entry block. Besides making the normal
+ // fallthrough chain explicit, this lets a bit-test range failure jump over
+ // preceding clusters that cannot contain an out-of-range value.
+ SmallVector<MachineBasicBlock *, 8> ClusterMBBs;
+ ClusterMBBs.reserve(Size);
+ ClusterMBBs.push_back(W.MBB);
+ for (unsigned Index = 1; Index < Size; ++Index) {
+ MachineBasicBlock *EntryMBB =
+ CurMF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
+ CurMF->insert(BBI, EntryMBB);
+ ClusterMBBs.push_back(EntryMBB);
+ }
+ if (Size > 1)
+ ExportFromCurrentBlock(Cond);
+
+ MachineBasicBlock *CurMBB = nullptr;
+ for (unsigned ClusterIndex = 0; ClusterIndex < Size; ++ClusterIndex) {
+ CaseClusterIt I = W.FirstCluster + ClusterIndex;
+ CurMBB = ClusterMBBs[ClusterIndex];
+
bool FallthroughUnreachable = false;
MachineBasicBlock *Fallthrough;
- if (I == W.LastCluster) {
+ if (ClusterIndex + 1 == Size) {
// For the last cluster, fall through to the default destination.
Fallthrough = DefaultMBB;
FallthroughUnreachable = isa<UnreachableInst>(
DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg());
} else {
- Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
- CurMF->insert(BBI, Fallthrough);
- // Put Cond in a virtual register to make it available from the new blocks.
- ExportFromCurrentBlock(Cond);
+ Fallthrough = ClusterMBBs[ClusterIndex + 1];
}
UnhandledProbs -= I->Prob;
@@ -12661,13 +12688,48 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
// FIXME: Optimize away range check based on pivot comparisons.
BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex];
- // The bit test blocks haven't been inserted yet; insert them here.
- for (BitTestCase &BTC : BTB->Cases)
- CurMF->insert(BBI, BTC.ThisBB);
+ // The bit-test blocks were inserted before the work-item entry
+ // blocks were created.
// Fill in fields of the BitTestBlock.
BTB->Parent = CurMBB;
BTB->Default = Fallthrough;
+ BTB->RangeCheckDefault = nullptr;
+
+ // In the zero-based form, a range failure is either below First or
+ // above First + Range. If the remaining clusters are laid out as an
+ // in-range prefix followed by an out-of-range suffix, the suffix has
+ // a stable entry block that can be used as the range-failure target.
+ // Otherwise retain the old combined continuation for now.
+ if (BTB->First.isZero()) {
+ APInt RangeEnd = BTB->First + BTB->Range;
+ unsigned FirstUpperOutOfRange = Size;
+ bool HasLowerOutOfRange = false;
+ bool HasInRangeAfterUpper = false;
+
+ for (unsigned JIndex = ClusterIndex + 1; JIndex < Size; ++JIndex) {
+ CaseClusterIt J = W.FirstCluster + JIndex;
+ bool IsBelowRange = J->High->getValue().slt(BTB->First);
+ bool IsAboveRange = J->Low->getValue().sgt(RangeEnd);
+ if (IsBelowRange) {
+ HasLowerOutOfRange = true;
+ break;
+ }
+ if (IsAboveRange) {
+ if (FirstUpperOutOfRange == Size)
+ FirstUpperOutOfRange = JIndex;
+ } else if (FirstUpperOutOfRange != Size) {
+ HasInRangeAfterUpper = true;
+ break;
+ }
+ }
+
+ if (!HasLowerOutOfRange && !HasInRangeAfterUpper) {
+ BTB->RangeCheckDefault = FirstUpperOutOfRange == Size
+ ? DefaultMBB
+ : ClusterMBBs[FirstUpperOutOfRange];
+ }
+ }
BTB->DefaultProb = UnhandledProbs;
// If the cases in bit test don't form a contiguous range, we evenly
@@ -12720,8 +12782,7 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
break;
}
- }
- CurMBB = Fallthrough;
+ }
}
}
diff --git a/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll b/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll
index 6c4041a6233be3..0911fcadcde6e0 100644
--- a/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll
+++ b/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll
@@ -16,42 +16,43 @@ define i32 @switch1(i32 %x) "no-jump-tables"="true" {
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: cmp w0, #12
-; CHECK-NEXT: b.hi .LBB0_6
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: b.hi .LBB0_8
; CHECK-NEXT: // %bb.1: // %entry
-; CHECK-NEXT: mov w8, #1152 // =0x480
-; CHECK-NEXT: lsr w8, w8, w19
-; CHECK-NEXT: tbnz w8, #0, .LBB0_8
+; CHECK-NEXT: mov w9, #1152 // =0x480
+; CHECK-NEXT: lsr w9, w9, w19
+; CHECK-NEXT: tbnz w9, #0, .LBB0_6
; CHECK-NEXT: // %bb.2: // %entry
-; CHECK-NEXT: mov w8, #2304 // =0x900
-; CHECK-NEXT: lsr w8, w8, w19
-; CHECK-NEXT: tbnz w8, #0, .LBB0_5
+; CHECK-NEXT: mov w9, #2304 // =0x900
+; CHECK-NEXT: lsr w9, w9, w19
+; CHECK-NEXT: tbnz w9, #0, .LBB0_5
; CHECK-NEXT: // %bb.3: // %entry
-; CHECK-NEXT: mov w8, #4608 // =0x1200
-; CHECK-NEXT: lsr w8, w8, w19
-; CHECK-NEXT: tbz w8, #0, .LBB0_6
+; CHECK-NEXT: mov w9, #4608 // =0x1200
+; CHECK-NEXT: lsr w9, w9, w19
+; CHECK-NEXT: tbz w9, #0, .LBB0_9
; CHECK-NEXT: // %bb.4: // %case9
; CHECK-NEXT: mov w0, w19
; CHECK-NEXT: bl foo3
-; CHECK-NEXT: b .LBB0_10
+; CHECK-NEXT: b .LBB0_7
; CHECK-NEXT: .LBB0_5: // %case8
; CHECK-NEXT: mov w0, w19
; CHECK-NEXT: bl foo2
-; CHECK-NEXT: b .LBB0_10
-; CHECK-NEXT: .LBB0_6: // %entry
-; CHECK-NEXT: cmp w19, #4
-; CHECK-NEXT: b.ne .LBB0_9
-; CHECK-NEXT: // %bb.7: // %case4
-; CHECK-NEXT: mov w0, #4 // =0x4
-; CHECK-NEXT: bl foo4
-; CHECK-NEXT: b .LBB0_10
-; CHECK-NEXT: .LBB0_8: // %case7
+; CHECK-NEXT: b .LBB0_7
+; CHECK-NEXT: .LBB0_6: // %case7
; CHECK-NEXT: mov w0, w19
; CHECK-NEXT: bl foo1
-; CHECK-NEXT: b .LBB0_10
-; CHECK-NEXT: .LBB0_9:
-; CHECK-NEXT: mov w19, wzr
-; CHECK-NEXT: .LBB0_10: // %return
+; CHECK-NEXT: .LBB0_7: // %return
; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: .LBB0_8: // %return
+; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB0_9: // %entry
+; CHECK-NEXT: cmp w19, #4
+; CHECK-NEXT: b.ne .LBB0_8
+; CHECK-NEXT: // %bb.10: // %case4
+; CHECK-NEXT: mov w0, #4 // =0x4
+; CHECK-NEXT: bl foo4
+; CHECK-NEXT: mov w0, #4 // =0x4
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
@@ -88,51 +89,54 @@ define i32 @switch2(i32 %x) "no-jump-tables"="true" {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16
-; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: cmp w0, #12
-; CHECK-NEXT: b.hi .LBB1_5
+; CHECK-NEXT: b.hi .LBB1_9
; CHECK-NEXT: // %bb.1: // %entry
; CHECK-NEXT: mov w8, #1152 // =0x480
-; CHECK-NEXT: lsr w8, w8, w19
-; CHECK-NEXT: tbnz w8, #0, .LBB1_9
+; CHECK-NEXT: lsr w8, w8, w0
+; CHECK-NEXT: tbnz w8, #0, .LBB1_6
; CHECK-NEXT: // %bb.2: // %entry
; CHECK-NEXT: mov w8, #2304 // =0x900
-; CHECK-NEXT: lsr w8, w8, w19
-; CHECK-NEXT: tbnz w8, #0, .LBB1_8
+; CHECK-NEXT: lsr w8, w8, w0
+; CHECK-NEXT: tbnz w8, #0, .LBB1_5
; CHECK-NEXT: // %bb.3: // %entry
; CHECK-NEXT: mov w8, #4608 // =0x1200
-; CHECK-NEXT: lsr w8, w8, w19
-; CHECK-NEXT: tbz w8, #0, .LBB1_5
+; CHECK-NEXT: lsr w8, w8, w0
+; CHECK-NEXT: tbz w8, #0, .LBB1_8
; CHECK-NEXT: // %bb.4: // %case9
-; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl foo3
-; CHECK-NEXT: b .LBB1_12
-; CHECK-NEXT: .LBB1_5: // %entry
-; CHECK-NEXT: cmp w19, #4
-; CHECK-NEXT: b.eq .LBB1_10
-; CHECK-NEXT: // %bb.6: // %entry
-; CHECK-NEXT: cmp w19, #1897
-; CHECK-NEXT: b.ne .LBB1_11
-; CHECK-NEXT: // %bb.7: // %case1897
-; CHECK-NEXT: mov w0, #4 // =0x4
-; CHECK-NEXT: bl foo5
-; CHECK-NEXT: b .LBB1_12
-; CHECK-NEXT: .LBB1_8: // %case8
-; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: b .LBB1_7
+; CHECK-NEXT: .LBB1_5: // %case8
+; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl foo2
-; CHECK-NEXT: b .LBB1_12
-; CHECK-NEXT: .LBB1_9: // %case7
-; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: b .LBB1_7
+; CHECK-NEXT: .LBB1_6: // %case7
+; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: bl foo1
-; CHECK-NEXT: b .LBB1_12
-; CHECK-NEXT: .LBB1_10: // %case4
+; CHECK-NEXT: .LBB1_7: // %case7
+; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB1_8: // %entry
+; CHECK-NEXT: cmp w0, #4
+; CHECK-NEXT: b.eq .LBB1_12
+; CHECK-NEXT: .LBB1_9: // %entry
+; CHECK-NEXT: cmp w0, #1897
+; CHECK-NEXT: b.ne .LBB1_11
+; CHECK-NEXT: // %bb.10: // %case1897
; CHECK-NEXT: mov w0, #4 // =0x4
-; CHECK-NEXT: bl foo4
-; CHECK-NEXT: b .LBB1_12
+; CHECK-NEXT: bl foo5
+; CHECK-NEXT: mov w0, #1897 // =0x769
+; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_11:
-; CHECK-NEXT: mov w19, wzr
-; CHECK-NEXT: .LBB1_12: // %return
-; CHECK-NEXT: mov w0, w19
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB1_12: // %case4
+; CHECK-NEXT: bl foo4
+; CHECK-NEXT: mov w0, #4 // =0x4
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
>From fb46ec3748d1bfed75a97243494d5a457b74aed7 Mon Sep 17 00:00:00 2001
From: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: Fri, 11 Sep 2026 18:18:27 +0530
Subject: [PATCH 3/7] fix test churn in x86 and powerpc
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
---
llvm/test/CodeGen/PowerPC/bittest.ll | 51 ++++-----
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 106 +++++++++---------
llvm/test/CodeGen/X86/switch.ll | 36 +++---
llvm/test/CodeGen/X86/x86-shrink-wrapping.ll | 40 +++----
4 files changed, 117 insertions(+), 116 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/bittest.ll b/llvm/test/CodeGen/PowerPC/bittest.ll
index cba56e3d5798f5..22d56054e7e3dc 100644
--- a/llvm/test/CodeGen/PowerPC/bittest.ll
+++ b/llvm/test/CodeGen/PowerPC/bittest.ll
@@ -108,50 +108,51 @@ define i32 @goo(i32 noundef signext %x) {
; CHECK-NEXT: cmplwi r3, 12
; CHECK-NEXT: stw r31, 60(r1) # 4-byte Folded Spill
; CHECK-NEXT: mr r31, r3
-; CHECK-NEXT: bgt cr0, L..BB1_7
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: bgt cr0, L..BB1_6
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: li r3, 1
-; CHECK-NEXT: slw r3, r3, r31
-; CHECK-NEXT: andi. r4, r3, 5632
+; CHECK-NEXT: li r4, 1
+; CHECK-NEXT: slw r4, r4, r31
+; CHECK-NEXT: andi. r5, r4, 5632
; CHECK-NEXT: bne cr0, L..BB1_4
; CHECK-NEXT: # %bb.2: # %entry
-; CHECK-NEXT: andi. r3, r3, 2304
-; CHECK-NEXT: beq cr0, L..BB1_5
+; CHECK-NEXT: andi. r4, r4, 2304
+; CHECK-NEXT: beq cr0, L..BB1_7
; CHECK-NEXT: # %bb.3: # %sw.bb1
; CHECK-NEXT: mr r3, r31
; CHECK-NEXT: bl .foo2[PR]
; CHECK-NEXT: nop
-; CHECK-NEXT: b L..BB1_9
+; CHECK-NEXT: b L..BB1_5
; CHECK-NEXT: L..BB1_4: # %sw.bb2
; CHECK-NEXT: mr r3, r31
; CHECK-NEXT: bl .foo3[PR]
; CHECK-NEXT: nop
-; CHECK-NEXT: b L..BB1_9
-; CHECK-NEXT: L..BB1_5: # %entry
+; CHECK-NEXT: L..BB1_5: # %return
+; CHECK-NEXT: mr r3, r31
+; CHECK-NEXT: L..BB1_6: # %return
+; CHECK-NEXT: lwz r31, 60(r1) # 4-byte Folded Reload
+; CHECK-NEXT: addi r1, r1, 64
+; CHECK-NEXT: lwz r0, 8(r1)
+; CHECK-NEXT: mtlr r0
+; CHECK-NEXT: blr
+; CHECK-NEXT: L..BB1_7: # %entry
; CHECK-NEXT: cmplwi r31, 7
-; CHECK-NEXT: bne cr0, L..BB1_7
-; CHECK-NEXT: # %bb.6: # %sw.bb
+; CHECK-NEXT: bne cr0, L..BB1_9
+; CHECK-NEXT: # %bb.8: # %sw.bb
; CHECK-NEXT: li r3, 7
-; CHECK-NEXT: li r31, 7
; CHECK-NEXT: bl .foo1[PR]
; CHECK-NEXT: nop
-; CHECK-NEXT: b L..BB1_9
-; CHECK-NEXT: L..BB1_7: # %entry
+; CHECK-NEXT: li r3, 7
+; CHECK-NEXT: b L..BB1_6
+; CHECK-NEXT: L..BB1_9: # %entry
; CHECK-NEXT: cmplwi r31, 4
-; CHECK-NEXT: li r31, 0
-; CHECK-NEXT: bne cr0, L..BB1_9
-; CHECK-NEXT: # %bb.8: # %sw.bb3
+; CHECK-NEXT: bne cr0, L..BB1_6
+; CHECK-NEXT: # %bb.10: # %sw.bb3
; CHECK-NEXT: li r3, 4
-; CHECK-NEXT: li r31, 4
; CHECK-NEXT: bl .foo4[PR]
; CHECK-NEXT: nop
-; CHECK-NEXT: L..BB1_9: # %return
-; CHECK-NEXT: mr r3, r31
-; CHECK-NEXT: lwz r31, 60(r1) # 4-byte Folded Reload
-; CHECK-NEXT: addi r1, r1, 64
-; CHECK-NEXT: lwz r0, 8(r1)
-; CHECK-NEXT: mtlr r0
-; CHECK-NEXT: blr
+; CHECK-NEXT: li r3, 4
+; CHECK-NEXT: b L..BB1_6
entry:
switch i32 %x, label %return [
i32 7, label %sw.bb
diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
index 60ebb4bd41ebb6..2715f4f1d23a6b 100644
--- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
+++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
@@ -45,10 +45,10 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: jne LBB0_5
; CHECK-NEXT: ## %bb.2: ## %if.then4
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: je LBB0_54
+; CHECK-NEXT: je LBB0_55
; CHECK-NEXT: ## %bb.3: ## %SyTime.exit
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: je LBB0_54
+; CHECK-NEXT: je LBB0_55
; CHECK-NEXT: LBB0_4: ## %cleanup
; CHECK-NEXT: addq $552, %rsp ## imm = 0x228
; CHECK-NEXT: popq %rbx
@@ -60,7 +60,7 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: retq
; CHECK-NEXT: LBB0_5: ## %if.end25
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: je LBB0_54
+; CHECK-NEXT: je LBB0_55
; CHECK-NEXT: ## %bb.6: ## %SyTime.exit2720
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx
@@ -102,10 +102,10 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
; CHECK-NEXT: xorl %r13d, %r13d
; CHECK-NEXT: jmp LBB0_13
-; CHECK-NEXT: LBB0_43: ## %while.cond1037.preheader
+; CHECK-NEXT: LBB0_44: ## %while.cond1037.preheader
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: testb %r12b, %r12b
-; CHECK-NEXT: je LBB0_54
+; CHECK-NEXT: je LBB0_55
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: LBB0_20: ## %while.cond197.backedge
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
@@ -116,11 +116,11 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: LBB0_13: ## %while.body200
; CHECK-NEXT: ## =>This Loop Header: Depth=1
; CHECK-NEXT: ## Child Loop BB0_28 Depth 2
-; CHECK-NEXT: ## Child Loop BB0_37 Depth 2
-; CHECK-NEXT: leal -268(%rbx), %eax
+; CHECK-NEXT: ## Child Loop BB0_38 Depth 2
+; CHECK-NEXT: leal -268(%rbp), %eax
; CHECK-NEXT: cmpl $105, %eax
; CHECK-NEXT: ja LBB0_14
-; CHECK-NEXT: ## %bb.55: ## %while.body200
+; CHECK-NEXT: ## %bb.56: ## %while.body200
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: movslq (%r14,%rax,4), %rax
; CHECK-NEXT: addq %r14, %rax
@@ -149,7 +149,7 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
; CHECK-NEXT: testb %sil, %sil
-; CHECK-NEXT: jne LBB0_54
+; CHECK-NEXT: jne LBB0_55
; CHECK-NEXT: ## %bb.29: ## %cond.true.i.i2780
; CHECK-NEXT: ## in Loop: Header=BB0_28 Depth=2
; CHECK-NEXT: movq %rax, %r15
@@ -179,17 +179,17 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: movl $1, %ebx
; CHECK-NEXT: jmp LBB0_20
-; CHECK-NEXT: LBB0_44: ## %sw.bb1134
+; CHECK-NEXT: LBB0_45: ## %sw.bb1134
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx
; CHECK-NEXT: cmpq %rax, %rcx
-; CHECK-NEXT: jb LBB0_54
-; CHECK-NEXT: ## %bb.45: ## in Loop: Header=BB0_13 Depth=1
+; CHECK-NEXT: jb LBB0_55
+; CHECK-NEXT: ## %bb.46: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
; CHECK-NEXT: movl $268, %ebx ## imm = 0x10C
; CHECK-NEXT: jmp LBB0_20
-; CHECK-NEXT: LBB0_39: ## %sw.bb566
+; CHECK-NEXT: LBB0_40: ## %sw.bb566
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: movl $20, %ebx
; CHECK-NEXT: jmp LBB0_20
@@ -204,44 +204,44 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: leal -324(%r13), %eax
; CHECK-NEXT: cmpl $59, %eax
-; CHECK-NEXT: ja LBB0_34
-; CHECK-NEXT: ## %bb.56: ## %if.end517
+; CHECK-NEXT: ja LBB0_35
+; CHECK-NEXT: ## %bb.34: ## %if.end517
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: movabsq $576460756598390785, %rcx ## imm = 0x800000100000001
; CHECK-NEXT: btq %rax, %rcx
-; CHECK-NEXT: jb LBB0_37
-; CHECK-NEXT: LBB0_34: ## %if.end517
+; CHECK-NEXT: jb LBB0_38
+; CHECK-NEXT: LBB0_35: ## %if.end517
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: cmpl $11, %r13d
-; CHECK-NEXT: je LBB0_37
-; CHECK-NEXT: ## %bb.35: ## %if.end517
+; CHECK-NEXT: cmpl $11, %r15d
+; CHECK-NEXT: je LBB0_38
+; CHECK-NEXT: ## %bb.36: ## %if.end517
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: cmpl $24, %r13d
-; CHECK-NEXT: je LBB0_37
-; CHECK-NEXT: ## %bb.36: ## %if.then532
+; CHECK-NEXT: cmpl $24, %r15d
+; CHECK-NEXT: je LBB0_38
+; CHECK-NEXT: ## %bb.37: ## %if.then532
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: movq _SyFgets.yank at GOTPCREL(%rip), %rax
; CHECK-NEXT: movb $0, (%rax)
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: LBB0_37: ## %for.cond534
+; CHECK-NEXT: LBB0_38: ## %for.cond534
; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
; CHECK-NEXT: testb %r12b, %r12b
-; CHECK-NEXT: jne LBB0_37
-; CHECK-NEXT: ## %bb.38: ## %for.cond542.preheader
+; CHECK-NEXT: jne LBB0_38
+; CHECK-NEXT: ## %bb.39: ## %for.cond542.preheader
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: movb $0, (%r15)
; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx
; CHECK-NEXT: jmp LBB0_20
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: LBB0_41: ## %while.cond864
+; CHECK-NEXT: LBB0_42: ## %while.cond864
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: jmp LBB0_41
+; CHECK-NEXT: jmp LBB0_42
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: LBB0_42: ## %while.cond962
+; CHECK-NEXT: LBB0_43: ## %while.cond962
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: jmp LBB0_42
+; CHECK-NEXT: jmp LBB0_43
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: LBB0_24: ## %for.cond357
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
@@ -249,17 +249,17 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: LBB0_11:
; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
; CHECK-NEXT: LBB0_21: ## %while.end1465
-; CHECK-NEXT: incl %ebx
-; CHECK-NEXT: cmpl $16, %ebx
-; CHECK-NEXT: ja LBB0_49
+; CHECK-NEXT: incl %ebp
+; CHECK-NEXT: cmpl $16, %ebp
+; CHECK-NEXT: ja LBB0_50
; CHECK-NEXT: ## %bb.22: ## %while.end1465
; CHECK-NEXT: movl $83969, %eax ## imm = 0x14801
-; CHECK-NEXT: btl %ebx, %eax
-; CHECK-NEXT: jae LBB0_49
+; CHECK-NEXT: btl %ebp, %eax
+; CHECK-NEXT: jae LBB0_50
; CHECK-NEXT: ## %bb.23:
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 ## 8-byte Reload
-; CHECK-NEXT: LBB0_47: ## %if.then1477
+; CHECK-NEXT: LBB0_48: ## %if.then1477
; CHECK-NEXT: ## implicit-def: $edi
; CHECK-NEXT: ## implicit-def: $rsi
; CHECK-NEXT: movl $1, %edx
@@ -268,49 +268,49 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: movq _syHistory at GOTPCREL(%rip), %rax
; CHECK-NEXT: leaq 8189(%r14,%rax), %rax
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: LBB0_48: ## %for.body1723
+; CHECK-NEXT: LBB0_49: ## %for.body1723
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: decq %rax
-; CHECK-NEXT: jmp LBB0_48
-; CHECK-NEXT: LBB0_46: ## %if.then1477.loopexit
+; CHECK-NEXT: jmp LBB0_49
+; CHECK-NEXT: LBB0_47: ## %if.then1477.loopexit
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 ## 8-byte Reload
; CHECK-NEXT: movq %r14, %rbx
-; CHECK-NEXT: jmp LBB0_47
+; CHECK-NEXT: jmp LBB0_48
; CHECK-NEXT: LBB0_16: ## %while.cond635.preheader
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: je LBB0_40
+; CHECK-NEXT: je LBB0_41
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: LBB0_17: ## %for.body643.us
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: jmp LBB0_17
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: LBB0_40: ## %while.cond661
+; CHECK-NEXT: LBB0_41: ## %while.cond661
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: jmp LBB0_40
-; CHECK-NEXT: LBB0_49: ## %for.cond1480.preheader
+; CHECK-NEXT: jmp LBB0_41
+; CHECK-NEXT: LBB0_50: ## %for.cond1480.preheader
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: je LBB0_54
-; CHECK-NEXT: ## %bb.50: ## %for.body1664.lr.ph
+; CHECK-NEXT: je LBB0_55
+; CHECK-NEXT: ## %bb.51: ## %for.body1664.lr.ph
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx ## 8-byte Reload
; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp ## 4-byte Reload
-; CHECK-NEXT: jne LBB0_53
-; CHECK-NEXT: ## %bb.51: ## %while.body1679.preheader
+; CHECK-NEXT: jne LBB0_54
+; CHECK-NEXT: ## %bb.52: ## %while.body1679.preheader
; CHECK-NEXT: incl %ebp
; CHECK-NEXT: xorl %r14d, %r14d
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: LBB0_52: ## %while.body1679
+; CHECK-NEXT: LBB0_53: ## %while.body1679
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq (%rbx), %rdi
; CHECK-NEXT: callq _fileno
; CHECK-NEXT: incl %ebp
-; CHECK-NEXT: testb %r14b, %r14b
-; CHECK-NEXT: jne LBB0_52
-; CHECK-NEXT: LBB0_53: ## %while.cond1683.preheader
+; CHECK-NEXT: testb %bl, %bl
+; CHECK-NEXT: jne LBB0_53
+; CHECK-NEXT: LBB0_54: ## %while.cond1683.preheader
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: LBB0_54: ## %if.then.i
+; CHECK-NEXT: LBB0_55: ## %if.then.i
; CHECK-NEXT: ud2
entry:
%sub.ptr.rhs.cast646 = ptrtoint ptr %line to i64
diff --git a/llvm/test/CodeGen/X86/switch.ll b/llvm/test/CodeGen/X86/switch.ll
index c75819c2fd2c59..2e1eda77d70e03 100644
--- a/llvm/test/CodeGen/X86/switch.ll
+++ b/llvm/test/CodeGen/X86/switch.ll
@@ -1064,33 +1064,33 @@ define void @optimal_jump_table2(i32 %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $9, %edi
; CHECK-NEXT: ja .LBB11_1
-; CHECK-NEXT: # %bb.10: # %entry
+; CHECK-NEXT: # %bb.4: # %entry
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: jmpq *.LJTI11_0(,%rax,8)
-; CHECK-NEXT: .LBB11_4: # %bb0
+; CHECK-NEXT: .LBB11_5: # %bb0
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
; CHECK-NEXT: .LBB11_1: # %entry
; CHECK-NEXT: cmpl $14, %edi
-; CHECK-NEXT: je .LBB11_8
+; CHECK-NEXT: je .LBB11_9
; CHECK-NEXT: # %bb.2: # %entry
; CHECK-NEXT: cmpl $15, %edi
-; CHECK-NEXT: jne .LBB11_9
+; CHECK-NEXT: jne .LBB11_10
; CHECK-NEXT: # %bb.3: # %bb5
; CHECK-NEXT: movl $5, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
-; CHECK-NEXT: .LBB11_9: # %return
+; CHECK-NEXT: .LBB11_10: # %return
; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB11_7: # %bb3
+; CHECK-NEXT: .LBB11_8: # %bb3
; CHECK-NEXT: movl $3, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
-; CHECK-NEXT: .LBB11_5: # %bb1
+; CHECK-NEXT: .LBB11_6: # %bb1
; CHECK-NEXT: movl $1, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
-; CHECK-NEXT: .LBB11_6: # %bb2
+; CHECK-NEXT: .LBB11_7: # %bb2
; CHECK-NEXT: movl $2, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
-; CHECK-NEXT: .LBB11_8: # %bb4
+; CHECK-NEXT: .LBB11_9: # %bb4
; CHECK-NEXT: movl $4, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
;
@@ -2652,32 +2652,32 @@ define void @switch_i8(i32 %a) {
; CHECK-NEXT: leal -1(%rdi), %eax
; CHECK-NEXT: cmpl $8, %eax
; CHECK-NEXT: ja .LBB26_1
-; CHECK-NEXT: # %bb.10:
+; CHECK-NEXT: # %bb.4:
; CHECK-NEXT: jmpq *.LJTI26_0(,%rax,8)
-; CHECK-NEXT: .LBB26_4: # %bb0
+; CHECK-NEXT: .LBB26_5: # %bb0
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
; CHECK-NEXT: .LBB26_1:
; CHECK-NEXT: cmpl $13, %edi
-; CHECK-NEXT: je .LBB26_8
+; CHECK-NEXT: je .LBB26_9
; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: cmpl $42, %edi
-; CHECK-NEXT: jne .LBB26_9
+; CHECK-NEXT: jne .LBB26_10
; CHECK-NEXT: # %bb.3: # %bb5
; CHECK-NEXT: movl $5, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
-; CHECK-NEXT: .LBB26_9: # %return
+; CHECK-NEXT: .LBB26_10: # %return
; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB26_7: # %bb3
+; CHECK-NEXT: .LBB26_8: # %bb3
; CHECK-NEXT: movl $3, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
-; CHECK-NEXT: .LBB26_5: # %bb1
+; CHECK-NEXT: .LBB26_6: # %bb1
; CHECK-NEXT: movl $1, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
-; CHECK-NEXT: .LBB26_6: # %bb2
+; CHECK-NEXT: .LBB26_7: # %bb2
; CHECK-NEXT: movl $2, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
-; CHECK-NEXT: .LBB26_8: # %bb4
+; CHECK-NEXT: .LBB26_9: # %bb4
; CHECK-NEXT: movl $4, %edi
; CHECK-NEXT: jmp g at PLT # TAILCALL
;
diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
index bd760f62817a06..0347359a65e69c 100644
--- a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
+++ b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
@@ -651,26 +651,26 @@ define void @useLEA(ptr readonly %x) {
; ENABLE-NEXT: movzwl (%rdi), %eax
; ENABLE-NEXT: leal -54(%rax), %ecx
; ENABLE-NEXT: cmpl $14, %ecx
-; ENABLE-NEXT: ja LBB8_3
-; ENABLE-NEXT: ## %bb.7: ## %lor.lhs.false
+; ENABLE-NEXT: ja LBB8_4
+; ENABLE-NEXT: ## %bb.3: ## %lor.lhs.false
; ENABLE-NEXT: movl $24599, %edx ## imm = 0x6017
; ENABLE-NEXT: btl %ecx, %edx
-; ENABLE-NEXT: jae LBB8_3
+; ENABLE-NEXT: jae LBB8_4
; ENABLE-NEXT: LBB8_8:
; ENABLE-NEXT: addq $8, %rsp
; ENABLE-NEXT: LBB8_9: ## %cleanup
; ENABLE-NEXT: retq
-; ENABLE-NEXT: LBB8_3: ## %lor.lhs.false
+; ENABLE-NEXT: LBB8_4: ## %lor.lhs.false
; ENABLE-NEXT: cmpl $134, %eax
; ENABLE-NEXT: je LBB8_8
-; ENABLE-NEXT: ## %bb.4: ## %lor.lhs.false
+; ENABLE-NEXT: ## %bb.5: ## %lor.lhs.false
; ENABLE-NEXT: cmpl $140, %eax
; ENABLE-NEXT: je LBB8_8
-; ENABLE-NEXT: ## %bb.5: ## %if.end.55
+; ENABLE-NEXT: ## %bb.6: ## %if.end.55
; ENABLE-NEXT: callq _find_temp_slot_from_address
; ENABLE-NEXT: testq %rax, %rax
; ENABLE-NEXT: je LBB8_8
-; ENABLE-NEXT: ## %bb.6: ## %if.then.60
+; ENABLE-NEXT: ## %bb.7: ## %if.then.60
; ENABLE-NEXT: movb $1, 57(%rax)
; ENABLE-NEXT: jmp LBB8_8
;
@@ -679,34 +679,34 @@ define void @useLEA(ptr readonly %x) {
; DISABLE-NEXT: pushq %rax
; DISABLE-NEXT: .cfi_def_cfa_offset 16
; DISABLE-NEXT: testq %rdi, %rdi
-; DISABLE-NEXT: je LBB8_7
+; DISABLE-NEXT: je LBB8_8
; DISABLE-NEXT: ## %bb.1: ## %if.end
; DISABLE-NEXT: cmpw $66, (%rdi)
-; DISABLE-NEXT: jne LBB8_7
+; DISABLE-NEXT: jne LBB8_8
; DISABLE-NEXT: ## %bb.2: ## %lor.lhs.false
; DISABLE-NEXT: movq 8(%rdi), %rdi
; DISABLE-NEXT: movzwl (%rdi), %eax
; DISABLE-NEXT: leal -54(%rax), %ecx
; DISABLE-NEXT: cmpl $14, %ecx
-; DISABLE-NEXT: ja LBB8_3
-; DISABLE-NEXT: ## %bb.8: ## %lor.lhs.false
+; DISABLE-NEXT: ja LBB8_4
+; DISABLE-NEXT: ## %bb.3: ## %lor.lhs.false
; DISABLE-NEXT: movl $24599, %edx ## imm = 0x6017
; DISABLE-NEXT: btl %ecx, %edx
-; DISABLE-NEXT: jae LBB8_3
-; DISABLE-NEXT: LBB8_7: ## %cleanup
+; DISABLE-NEXT: jae LBB8_4
+; DISABLE-NEXT: LBB8_8: ## %cleanup
; DISABLE-NEXT: popq %rax
; DISABLE-NEXT: retq
-; DISABLE-NEXT: LBB8_3: ## %lor.lhs.false
+; DISABLE-NEXT: LBB8_4: ## %lor.lhs.false
; DISABLE-NEXT: cmpl $134, %eax
-; DISABLE-NEXT: je LBB8_7
-; DISABLE-NEXT: ## %bb.4: ## %lor.lhs.false
+; DISABLE-NEXT: je LBB8_8
+; DISABLE-NEXT: ## %bb.5: ## %lor.lhs.false
; DISABLE-NEXT: cmpl $140, %eax
-; DISABLE-NEXT: je LBB8_7
-; DISABLE-NEXT: ## %bb.5: ## %if.end.55
+; DISABLE-NEXT: je LBB8_8
+; DISABLE-NEXT: ## %bb.6: ## %if.end.55
; DISABLE-NEXT: callq _find_temp_slot_from_address
; DISABLE-NEXT: testq %rax, %rax
-; DISABLE-NEXT: je LBB8_7
-; DISABLE-NEXT: ## %bb.6: ## %if.then.60
+; DISABLE-NEXT: je LBB8_8
+; DISABLE-NEXT: ## %bb.7: ## %if.then.60
; DISABLE-NEXT: movb $1, 57(%rax)
; DISABLE-NEXT: popq %rax
; DISABLE-NEXT: retq
>From fee66349cd2ca50a6ed468e3acc5a6b6c0276ea8 Mon Sep 17 00:00:00 2001
From: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: Fri, 11 Sep 2026 18:23:47 +0530
Subject: [PATCH 4/7] Update switch-edge-weight
this is expected from the patch
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
---
llvm/test/CodeGen/X86/switch-edge-weight.ll | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/test/CodeGen/X86/switch-edge-weight.ll b/llvm/test/CodeGen/X86/switch-edge-weight.ll
index 27db6d7b704944..64149f97db0a5d 100644
--- a/llvm/test/CodeGen/X86/switch-edge-weight.ll
+++ b/llvm/test/CodeGen/X86/switch-edge-weight.ll
@@ -214,13 +214,13 @@ sw.epilog:
; statement.
;
; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
-; %bb.0 to %bb.6: [0, 110] + [116, UINT32_MAX] (20)
-; %bb.0 to %bb.7: [111, 115] (bit test) (50)
-; CHECK: successors: %bb.6(0x24924925), %bb.7(0x5b6db6db)
+; %bb.0 to %bb.8: [0, 110] + [116, UINT32_MAX] (20)
+; %bb.0 to %bb.6: [111, 115] (bit test) (50)
+; CHECK: successors: %bb.8(0x24924925), %bb.6(0x5b6db6db)
;
-; CHECK: bb.7{{[0-9a-zA-Z.]*}}:
-; %bb.7 to %bb.2: {111, 114, 115} (30)
-; %bb.7 to %bb.3: {112, 113} (20)
+; CHECK: bb.6{{[0-9a-zA-Z.]*}}:
+; %bb.6 to %bb.2: {111, 114, 115} (30)
+; %bb.6 to %bb.3: {112, 113} (20)
; CHECK: successors: %bb.2(0x4ccccccd), %bb.3(0x33333333)
}
>From 4b8bb429a2029b84e659b19b97f269b9a03cf68d Mon Sep 17 00:00:00 2001
From: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: Fri, 11 Sep 2026 18:29:29 +0530
Subject: [PATCH 5/7] use reference not pointers
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index fd906de81bb164..8af7ad06c72dbe 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -12585,8 +12585,8 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
if (I->Kind != CC_BitTests)
continue;
- BitTestBlock *BTB = &SL->BitTestCases[I->BTCasesIndex];
- for (BitTestCase &BTC : BTB->Cases)
+ BitTestBlock &BTB = SL->BitTestCases[I->BTCasesIndex];
+ for (BitTestCase &BTC : BTB.Cases)
CurMF->insert(BBI, BTC.ThisBB);
}
>From 9efea8636611b3430795ad310d7b9d20cbb53b85 Mon Sep 17 00:00:00 2001
From: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: Tue, 15 Sep 2026 17:53:59 +0530
Subject: [PATCH 6/7] add unwind; remove -O2 from test
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
---
.../CodeGen/AArch64/switch-bittest-range-check.ll | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll b/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll
index 0911fcadcde6e0..ffe255bd8812d3 100644
--- a/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll
+++ b/llvm/test/CodeGen/AArch64/switch-bittest-range-check.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=aarch64 -O2 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
declare void @foo1(i32)
declare void @foo2(i32)
@@ -7,13 +7,10 @@ declare void @foo3(i32)
declare void @foo4(i32)
declare void @foo5(i32)
-define i32 @switch1(i32 %x) "no-jump-tables"="true" {
+define i32 @switch1(i32 %x) nounwind "no-jump-tables"="true" {
; CHECK-LABEL: switch1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: cmp w0, #12
; CHECK-NEXT: mov w0, wzr
@@ -82,13 +79,10 @@ return:
ret i32 %result
}
-define i32 @switch2(i32 %x) "no-jump-tables"="true" {
+define i32 @switch2(i32 %x) nounwind "no-jump-tables"="true" {
; CHECK-LABEL: switch2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: cmp w0, #12
; CHECK-NEXT: b.hi .LBB1_9
; CHECK-NEXT: // %bb.1: // %entry
>From 6b0cc92a7e2766e5119f73ad203e131c870c6f71 Mon Sep 17 00:00:00 2001
From: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: Thu, 1 Oct 2026 10:26:57 +0530
Subject: [PATCH 7/7] churn
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
---
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
index 2715f4f1d23a6b..56bc0114e1b45f 100644
--- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
+++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
@@ -117,7 +117,7 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: ## =>This Loop Header: Depth=1
; CHECK-NEXT: ## Child Loop BB0_28 Depth 2
; CHECK-NEXT: ## Child Loop BB0_38 Depth 2
-; CHECK-NEXT: leal -268(%rbp), %eax
+; CHECK-NEXT: leal -268(%rbx), %eax
; CHECK-NEXT: cmpl $105, %eax
; CHECK-NEXT: ja LBB0_14
; CHECK-NEXT: ## %bb.56: ## %while.body200
@@ -212,11 +212,11 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: jb LBB0_38
; CHECK-NEXT: LBB0_35: ## %if.end517
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: cmpl $11, %r15d
+; CHECK-NEXT: cmpl $11, %r13d
; CHECK-NEXT: je LBB0_38
; CHECK-NEXT: ## %bb.36: ## %if.end517
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT: cmpl $24, %r15d
+; CHECK-NEXT: cmpl $24, %r13d
; CHECK-NEXT: je LBB0_38
; CHECK-NEXT: ## %bb.37: ## %if.then532
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1
@@ -249,12 +249,12 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: LBB0_11:
; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
; CHECK-NEXT: LBB0_21: ## %while.end1465
-; CHECK-NEXT: incl %ebp
-; CHECK-NEXT: cmpl $16, %ebp
+; CHECK-NEXT: incl %ebx
+; CHECK-NEXT: cmpl $16, %ebx
; CHECK-NEXT: ja LBB0_50
; CHECK-NEXT: ## %bb.22: ## %while.end1465
; CHECK-NEXT: movl $83969, %eax ## imm = 0x14801
-; CHECK-NEXT: btl %ebp, %eax
+; CHECK-NEXT: btl %ebx, %eax
; CHECK-NEXT: jae LBB0_50
; CHECK-NEXT: ## %bb.23:
; CHECK-NEXT: xorl %ebx, %ebx
@@ -306,7 +306,7 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: movq (%rbx), %rdi
; CHECK-NEXT: callq _fileno
; CHECK-NEXT: incl %ebp
-; CHECK-NEXT: testb %bl, %bl
+; CHECK-NEXT: testb %r14b, %r14b
; CHECK-NEXT: jne LBB0_53
; CHECK-NEXT: LBB0_54: ## %while.cond1683.preheader
; CHECK-NEXT: testb %al, %al
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