[llvm] [Hexagon] Do not co-packetize scalar FP/mpy def with a consuming transfer of control (PR #227178)

[Brian Cain via llvm-commits]

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@@ -474,6 +474,15 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
   short getEquivalentHWInstr(const MachineInstr &MI) const;
   unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
                                       const MachineInstr &MI) const;
+  /// Return true if \p DefMI defines \p Reg (or a super-register of it) with
+  /// a scheduling class whose per-operand write latency prevents packetizing
+  /// the def with a consumer that reads \p Reg in the same packet (currently
+  /// scalar floating-point TC4x classes, whose writes commit after the point
+  /// at which a co-packetized call transfers control). \p UseMI is retained
----------------
androm3da wrote:

> currently scalar floating-point TC4x classes, whose writes commit after the point at which a co-packetized call transfers control

does this comment agree with the implementation?

```c++
  return is_TC3x(SchedClass) || is_TC4x(SchedClass);
```

https://github.com/llvm/llvm-project/pull/227178