[llvm] [Hexagon] Do not co-packetize scalar FP/mpy def with a consuming transfer of control (PR #227178)

[Brian Cain via llvm-commits]

https://github.com/androm3da commented:

This was always a constraint of the scalar ISA and we just haven't encountered it until now?  Not like we're talking about an erratum or something?

>  HexagonInstrInfo::hasMultiCycleDefLatency() which, for a given def MI, use MI and physical register, decides whether the pair may share a packet. 

Stupid question maybe - why does hasMultiCycleDefLatency() need both producer and consumer instructions?  Does the producer alone not tell us enough about the latency for the given output?  Also - perhaps related - I don't think `UseMI` is considered by `hasMultiCycleDefLatency`.



https://github.com/llvm/llvm-project/pull/227178