[llvm] 74c86a7 - [AMDGPU] Use S_CMP to lower a copy of a lane mask to SCC (#221445)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 29 02:59:31 PDT 2026
Author: Jay Foad
Date: 2026-09-29T09:59:22Z
New Revision: 74c86a79968b3f23eb3b292d318429364709f6b2
URL: https://github.com/llvm/llvm-project/commit/74c86a79968b3f23eb3b292d318429364709f6b2
DIFF: https://github.com/llvm/llvm-project/commit/74c86a79968b3f23eb3b292d318429364709f6b2.diff
LOG: [AMDGPU] Use S_CMP to lower a copy of a lane mask to SCC (#221445)
SIFixSGPRCopies lowers a copy of a lane mask to SCC as an AND with EXEC,
whose destination register is created by the pass and is always dead.
The AND with EXEC is only needed because SCC has to be "any active lane
is set". When the lane mask already has 0 in the bits of all inactive
lanes, that is just "the mask is non-zero", which S_CMP computes without
needing a destination register. In some cases the S_CMP can be optimized
away later by SIInstrInfo::optimizeCompareInstr.
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Added:
llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp-wave32.mir
llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp.mir
Modified:
llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
llvm/test/CodeGen/AMDGPU/anyext.ll
llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
llvm/test/CodeGen/AMDGPU/fp-classify.ll
llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
llvm/test/CodeGen/AMDGPU/fpow.ll
llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
llvm/test/CodeGen/AMDGPU/frem.ll
llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
llvm/test/CodeGen/AMDGPU/literal64.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
llvm/test/CodeGen/AMDGPU/llvm.log.ll
llvm/test/CodeGen/AMDGPU/llvm.log10.ll
llvm/test/CodeGen/AMDGPU/llvm.log2.ll
llvm/test/CodeGen/AMDGPU/max.ll
llvm/test/CodeGen/AMDGPU/min.ll
llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
llvm/test/CodeGen/AMDGPU/or.ll
llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
llvm/test/CodeGen/AMDGPU/rsq.f64.ll
llvm/test/CodeGen/AMDGPU/saddo.ll
llvm/test/CodeGen/AMDGPU/scmp.ll
llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
llvm/test/CodeGen/AMDGPU/ssubo.ll
llvm/test/CodeGen/AMDGPU/ucmp.ll
llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
llvm/test/CodeGen/AMDGPU/wave32.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h b/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
index af14066c1bd46..9bd8acd945c7e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
@@ -32,6 +32,7 @@ class LaneMaskConstants {
const unsigned AndSaveExecTermOpc;
const unsigned BfmOpc;
const unsigned CMovOpc;
+ const unsigned CmpLgOpc; // GFX8+ only in wave64
const unsigned CSelectOpc;
const unsigned MovOpc;
const unsigned MovTermOpc;
@@ -61,6 +62,7 @@ class LaneMaskConstants {
: AMDGPU::S_AND_SAVEEXEC_B64_term),
BfmOpc(IsWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64),
CMovOpc(IsWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
+ CmpLgOpc(IsWave32 ? AMDGPU::S_CMP_LG_U32 : AMDGPU::S_CMP_LG_U64),
CSelectOpc(IsWave32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64),
MovOpc(IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64),
MovTermOpc(IsWave32 ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term),
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index 964ddde0fbb01..605e84bafdb7d 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -1183,8 +1183,11 @@ void SIFixSGPRCopies::lowerVGPR2SGPRCopies(MachineFunction &MF) {
}
void SIFixSGPRCopies::fixSCCCopies(MachineFunction &MF) {
- const AMDGPU::LaneMaskConstants &LMC =
- AMDGPU::LaneMaskConstants::get(MF.getSubtarget<GCNSubtarget>());
+ const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+ const AMDGPU::LaneMaskConstants &LMC = AMDGPU::LaneMaskConstants::get(ST);
+ // S_CMP_LG_U64 is only available on GFX8+. S_CMP_LG_U32 always is, and
+ // wave32 implies GFX10+ anyway.
+ bool HasCmp = ST.isWave32() || ST.hasScalarCompareEq64();
for (MachineBasicBlock &MBB : MF) {
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
++I) {
@@ -1192,7 +1195,8 @@ void SIFixSGPRCopies::fixSCCCopies(MachineFunction &MF) {
// May already have been lowered.
if (!MI.isCopy())
continue;
- Register SrcReg = MI.getOperand(1).getReg();
+ const MachineOperand &Src = MI.getOperand(1);
+ Register SrcReg = Src.getReg();
Register DstReg = MI.getOperand(0).getReg();
if (SrcReg == AMDGPU::SCC) {
Register SCCCopy =
@@ -1208,12 +1212,25 @@ void SIFixSGPRCopies::fixSCCCopies(MachineFunction &MF) {
continue;
}
if (DstReg == AMDGPU::SCC) {
- Register Tmp = MRI->createVirtualRegister(TRI->getBoolRC());
- I = BuildMI(*MI.getParent(), std::next(MachineBasicBlock::iterator(MI)),
- MI.getDebugLoc(), TII->get(LMC.AndOpc))
- .addReg(Tmp, getDefRegState(true))
- .addReg(SrcReg)
- .addReg(LMC.ExecReg);
+ MachineBasicBlock::iterator InsPt =
+ std::next(MachineBasicBlock::iterator(MI));
+ if (HasCmp && !Src.getSubReg() &&
+ TII->isMaskedByExec(SrcReg, MI, *MRI)) {
+ // The source already has 0 in the bits of all inactive lanes, so
+ // SCC is just "source is non-zero". S_CMP computes that without
+ // needing a destination register.
+ I = BuildMI(*MI.getParent(), InsPt, MI.getDebugLoc(),
+ TII->get(LMC.CmpLgOpc))
+ .add(Src)
+ .addImm(0);
+ } else {
+ Register Tmp = MRI->createVirtualRegister(TRI->getBoolRC());
+ I = BuildMI(*MI.getParent(), InsPt, MI.getDebugLoc(),
+ TII->get(LMC.AndOpc))
+ .addReg(Tmp, getDefRegState(true))
+ .add(Src)
+ .addReg(LMC.ExecReg);
+ }
MI.eraseFromParent();
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 0346ebc254361..6ffcc71ba3d0f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5134,6 +5134,67 @@ bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
return pseudoToMCOpcode(Op32) != -1;
}
+/// Return true if \p MI is a VALU comparison, i.e. an instruction that writes
+/// a lane mask with one bit per lane, and zeroes the bits of lanes that were
+/// inactive when it executed.
+///
+/// TODO: Also handle the sdst result of V_ADD_CO_U32 and V_SUB_CO_U32 and
+/// V_DIV_SCALE_F32.
+static bool isVCmp(const SIInstrInfo &TII, const MachineInstr &MI) {
+ if (TII.isVOPC(MI))
+ return true;
+ int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
+ return Op32 != -1 && TII.isVOPC(Op32);
+}
+
+bool SIInstrInfo::isMaskedByExec(Register Reg, const MachineInstr &Use,
+ const MachineRegisterInfo &MRI,
+ unsigned Depth) const {
+ assert(MRI.isSSA() && "isMaskedByExec requires SSA form");
+ const AMDGPU::LaneMaskConstants &LMC = AMDGPU::LaneMaskConstants::get(ST);
+ const MachineBasicBlock *MBB = Use.getParent();
+
+ // EXEC itself is trivially masked by EXEC.
+ if (Reg == LMC.ExecReg)
+ return true;
+
+ // Maximum depth of the def-use walk.
+ constexpr unsigned MaxDepth = 6;
+ if (Depth >= MaxDepth || !Reg.isVirtual())
+ return false;
+
+ // Only look at definitions that can execute under the same EXEC mask as the
+ // use.
+ const MachineInstr *Def = MRI.getVRegDef(Reg);
+ if (!Def || Def->getParent() != MBB)
+ return false;
+
+ if (isVCmp(*this, *Def))
+ return true;
+
+ // Recurse into an operand, which must be a whole register to say anything
+ // about the whole lane mask.
+ auto Recurse = [&](unsigned OpIdx) {
+ const MachineOperand &MO = Def->getOperand(OpIdx);
+ return MO.isReg() && !MO.getSubReg() &&
+ isMaskedByExec(MO.getReg(), Use, MRI, Depth + 1);
+ };
+
+ unsigned Opc = Def->getOpcode();
+ if (Opc == AMDGPU::COPY && Recurse(1))
+ return true;
+ if (Opc == LMC.AndOpc && (Recurse(1) || Recurse(2)))
+ return true;
+ if (Opc == LMC.AndN2Opc && Recurse(1))
+ return true;
+ if ((Opc == LMC.OrOpc || Opc == LMC.XorOpc) && Recurse(1) && Recurse(2))
+ return true;
+ // TODO: Sometimes we encounter "reg = S_CSELECT -1, 0". If Reg has no other
+ // uses this could be optimized to "reg = S_CSELECT $exec, 0".
+
+ return false;
+}
+
bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
// The src0_modifier operand is present on all instructions
// that have modifiers.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 48eba6b2a567d..c0dc46e2a89c6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1393,6 +1393,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// This function will return false if you pass it a 32-bit instruction.
bool hasVALU32BitEncoding(unsigned Opcode) const;
+ /// Return true if \p Reg is a lane mask that already has 0 in every bit
+ /// corresponding to a lane that is inactive in EXEC where \p Use executes,
+ /// so that ANDing it with EXEC there would be a no-op. Requires SSA form.
+ bool isMaskedByExec(Register Reg, const MachineInstr &Use,
+ const MachineRegisterInfo &MRI, unsigned Depth = 0) const;
+
bool physRegUsesConstantBus(const MachineOperand &Reg) const;
bool regUsesConstantBus(const MachineOperand &Reg,
const MachineRegisterInfo &MRI) const;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 738e928e1f58d..f1870654d71d3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -18979,7 +18979,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
@@ -19913,7 +19913,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
@@ -20849,11 +20849,11 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
@@ -20890,9 +20890,9 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB15_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
@@ -20956,19 +20956,19 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v167, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v162, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v177, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
@@ -21141,7 +21141,8 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v177
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
@@ -21181,8 +21182,8 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v167, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
@@ -21428,9 +21429,9 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:12
@@ -21469,9 +21470,9 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB15_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
@@ -21535,7 +21536,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -21547,7 +21548,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v176, v166, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
@@ -21720,7 +21721,8 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v176
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
@@ -21761,7 +21763,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
@@ -55117,7 +55119,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
@@ -56051,7 +56053,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
@@ -56987,11 +56989,11 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
@@ -57028,9 +57030,9 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB39_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
@@ -57094,19 +57096,19 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v167, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v162, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v177, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
@@ -57279,7 +57281,8 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v177
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
@@ -57319,8 +57322,8 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v167, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
@@ -57566,9 +57569,9 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:12
@@ -57607,9 +57610,9 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB39_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
@@ -57673,7 +57676,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -57685,7 +57688,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v176, v166, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
@@ -57858,7 +57861,8 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v176
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
@@ -57899,7 +57903,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
@@ -89468,7 +89472,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
@@ -90402,7 +90406,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
@@ -91338,11 +91342,11 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
@@ -91379,9 +91383,9 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB59_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
@@ -91445,19 +91449,19 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v167, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v162, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v177, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
@@ -91630,7 +91634,8 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v177
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
@@ -91670,8 +91675,8 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v167, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
@@ -91917,9 +91922,9 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:12
@@ -91958,9 +91963,9 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB59_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
@@ -92024,7 +92029,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -92036,7 +92041,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v176, v166, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
@@ -92209,7 +92214,8 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v176
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
@@ -92250,7 +92256,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
@@ -122705,7 +122711,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
@@ -123639,7 +123645,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
@@ -124575,11 +124581,11 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
@@ -124616,9 +124622,9 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB75_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
@@ -124682,19 +124688,19 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v167, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v162, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v177, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
@@ -124867,7 +124873,8 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v177
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
@@ -124907,8 +124914,8 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v167, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
@@ -125154,9 +125161,9 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:12
@@ -125195,9 +125202,9 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB75_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
@@ -125261,7 +125268,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -125273,7 +125280,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v176, v166, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
@@ -125446,7 +125453,8 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v176
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
@@ -125487,7 +125495,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
@@ -148348,7 +148356,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:268
; VI-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:264
; VI-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:260
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:256
@@ -149310,7 +149318,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:20
; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:16
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:12
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_waitcnt vmcnt(27)
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:276
@@ -150212,56 +150220,56 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v27
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v28
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v27
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v25
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v25
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v24
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v22
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v22
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v19
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v20
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v19
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v17
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v17
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v13
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v7
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB89_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0x6050400
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v178, v181, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v177, v180, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v148, v162, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v160, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v11
@@ -150272,44 +150280,44 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s5, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s13, s8, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s4, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s12, s6, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s12, s7, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s5, s56, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s6, s56, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s72, s45, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s42, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s13, s46, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s44, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s14, s46, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s57, s63, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s57, s62, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s43, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v12.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s41, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s47, s62, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s40, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s47, s61, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v13.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v176, v177, 0x6050400
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v167, v176, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s41, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v179, s74, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v178, s74, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v150, v132, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v13.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v181, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v144, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v165, v167, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v165, v182, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v134, v118, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v166, v163, 0xc0c0004
@@ -150471,81 +150479,82 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v160
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v167
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v162
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v165, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v182
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v181
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v180
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v176
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v178, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v167, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s42, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s47, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s41, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s47, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s44, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s43, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s72, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s43, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s42, s11, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s6, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s7, v1
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s10, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s13, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s40, s10, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s14, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v71, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s15, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s45, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s72, s45, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s63, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s57, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s7, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v80, s40, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v80, s13, s8, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v83, s26, s27, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v84, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
@@ -150664,34 +150673,34 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:116
; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:112
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:108
-; GFX11-FAKE16-NEXT: scratch_load_u16 v54, off, s32 offset:104
+; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:88
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:80
; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v54, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:64
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:60
; GFX11-FAKE16-NEXT: s_clause 0xf
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:56
; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:44
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
+; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
-; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:16
+; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:12
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v30
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v29
@@ -150706,7 +150715,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v20
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v19
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v18
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v17
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v17
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v16
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v15
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v14
@@ -150715,19 +150724,19 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v11
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v10
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v9
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v8
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v7
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v6
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB89_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0xc0c0004
@@ -150735,7 +150744,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v32, v48, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v36, v49, 0x6050400
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v54, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v9
@@ -150751,7 +150760,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s11, s8, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s13, s8, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s42, s15, v9
@@ -150759,7 +150768,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s6, s4, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s12, s9, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s11, s9, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s41, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v5
@@ -150770,7 +150779,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s57, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s13, s40, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s40, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v16, s45, s56, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
@@ -150781,8 +150790,8 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s73, s72, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v16, 16, v14
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v53, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v66, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v68, 0x6050400
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v15, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s61, s63, v11
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -150790,18 +150799,18 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v38, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v39, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v17, 16, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v65, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v65, v39, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v82, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v64, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v82, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v34, v50, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v69, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v96, v85, 0xc0c0004
@@ -150809,7 +150818,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v98, v83, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v20, 16, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v71, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v71, v53, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v21
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v81, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
@@ -150962,36 +150971,36 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v82
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v83, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v68
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v67
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v69
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v80
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v65
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v64
; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v65, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v67
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v53
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v68
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v49
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v52, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v50
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v37, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v38
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v34, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc0c0004
@@ -151006,19 +151015,19 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s62, s59, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
; GFX11-FAKE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s73, s72, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s40, s13, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s40, s12, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s63, s61, v2
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s12, s9, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s11, s9, v2
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v3
@@ -151029,7 +151038,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s46, s43, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s58, s47, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s11, s8, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s13, s8, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v50, s24, s25, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v65, s0, s1, v2
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
@@ -151044,7 +151053,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s44, s41, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s14, s10, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s42, s15, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v50
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s26, s27, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v67, s2, s3, v2
@@ -151071,7 +151080,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s20, s21, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v66, s18, s19, v2
@@ -151087,7 +151096,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v35, 16, v33
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v32, 16, v36
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v34, 16, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v54
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v71
; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v17
@@ -151098,9 +151107,9 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v64
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff, v51
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v55, 16, v32
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v52, 16, v33
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v52
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v54, 16, v32
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v51, 16, v33
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v20, 16, v34
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v21, 16, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v99
@@ -151111,9 +151120,9 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v66, 16, v64
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v68
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v53, 16, v51
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v55, 16, v52
; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v48
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v24
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v100, 16, v32
@@ -151129,7 +151138,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v65
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v49, 16, v48
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v10, 16, v50
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v51
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v52
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v37
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v16, 16, v38
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v70, 16, v19
@@ -174942,7 +174951,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:268
; VI-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:264
; VI-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:260
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:256
@@ -175904,7 +175913,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:20
; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:16
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:12
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_waitcnt vmcnt(27)
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:276
@@ -176806,56 +176815,56 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v27
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v28
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v27
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v25
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v25
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v24
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v22
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v22
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v19
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v20
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v19
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v17
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v17
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v13
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v7
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB93_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0x6050400
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v178, v181, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v177, v180, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v148, v162, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v160, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v11
@@ -176866,44 +176875,44 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s5, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s13, s8, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s4, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s12, s6, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s12, s7, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s5, s56, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s6, s56, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s72, s45, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s42, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s13, s46, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s44, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s14, s46, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s57, s63, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s57, s62, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s43, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v12.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s41, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s47, s62, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s40, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s47, s61, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v13.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v176, v177, 0x6050400
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v167, v176, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s41, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v179, s74, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v178, s74, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v150, v132, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v13.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v181, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v144, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v165, v167, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v165, v182, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v134, v118, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v166, v163, 0xc0c0004
@@ -177065,81 +177074,82 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v160
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v167
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v162
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v165, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v182
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v181
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v180
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v176
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v178, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v167, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s42, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s47, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s41, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s47, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s44, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s43, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s72, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s43, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s42, s11, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s6, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s7, v1
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s10, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s13, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s40, s10, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s14, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v71, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s15, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s45, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s72, s45, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s63, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s57, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s7, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v80, s40, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v80, s13, s8, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v83, s26, s27, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v84, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
@@ -177258,34 +177268,34 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:116
; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:112
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:108
-; GFX11-FAKE16-NEXT: scratch_load_u16 v54, off, s32 offset:104
+; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:88
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:80
; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v54, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:64
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:60
; GFX11-FAKE16-NEXT: s_clause 0xf
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:56
; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:44
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
+; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
-; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:16
+; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:12
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v30
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v29
@@ -177300,7 +177310,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v20
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v19
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v18
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v17
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v17
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v16
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v15
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v14
@@ -177309,19 +177319,19 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v11
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v10
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v9
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v8
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v7
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v6
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB93_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0xc0c0004
@@ -177329,7 +177339,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v32, v48, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v36, v49, 0x6050400
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v54, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v9
@@ -177345,7 +177355,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s11, s8, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s13, s8, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s42, s15, v9
@@ -177353,7 +177363,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s6, s4, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s12, s9, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s11, s9, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s41, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v5
@@ -177364,7 +177374,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s57, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s13, s40, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s40, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v16, s45, s56, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
@@ -177375,8 +177385,8 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s73, s72, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v16, 16, v14
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v53, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v66, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v68, 0x6050400
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v15, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s61, s63, v11
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -177384,18 +177394,18 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v38, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v39, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v17, 16, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v65, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v65, v39, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v82, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v64, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v82, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v34, v50, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v69, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v96, v85, 0xc0c0004
@@ -177403,7 +177413,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v98, v83, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v20, 16, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v71, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v71, v53, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v21
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v81, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
@@ -177556,36 +177566,36 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v82
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v83, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v68
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v67
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v69
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v80
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v65
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v64
; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v65, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v67
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v53
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v68
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v49
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v52, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v50
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v37, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v38
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v34, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc0c0004
@@ -177600,19 +177610,19 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s62, s59, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
; GFX11-FAKE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s73, s72, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s40, s13, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s40, s12, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s63, s61, v2
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s12, s9, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s11, s9, v2
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v3
@@ -177623,7 +177633,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s46, s43, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s58, s47, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s11, s8, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s13, s8, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v50, s24, s25, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v65, s0, s1, v2
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
@@ -177638,7 +177648,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s44, s41, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s14, s10, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s42, s15, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v50
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s26, s27, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v67, s2, s3, v2
@@ -177665,7 +177675,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s20, s21, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v66, s18, s19, v2
@@ -177681,7 +177691,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v35, 16, v33
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v32, 16, v36
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v34, 16, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v54
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v71
; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v17
@@ -177692,9 +177702,9 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v64
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff, v51
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v55, 16, v32
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v52, 16, v33
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v52
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v54, 16, v32
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v51, 16, v33
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v20, 16, v34
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v21, 16, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v99
@@ -177705,9 +177715,9 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v66, 16, v64
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v68
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v53, 16, v51
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v55, 16, v52
; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v48
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v24
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v100, 16, v32
@@ -177723,7 +177733,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v65
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v49, 16, v48
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v10, 16, v50
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v51
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v52
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v37
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v16, 16, v38
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v70, 16, v19
@@ -195611,7 +195621,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:268
; VI-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:264
; VI-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:260
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:256
@@ -196573,7 +196583,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:20
; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:16
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:12
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_waitcnt vmcnt(27)
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:276
@@ -197475,56 +197485,56 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v27
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v28
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v27
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v25
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v25
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v24
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v22
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v22
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v19
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v20
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v19
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v17
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v17
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v16
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v13
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v7
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB97_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0x6050400
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v178, v181, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v177, v180, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v148, v162, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v160, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v11
@@ -197535,44 +197545,44 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s5, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s13, s8, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s4, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s12, s6, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s12, s7, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s5, s56, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s6, s56, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s72, s45, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s42, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s13, s46, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s44, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s14, s46, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s57, s63, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s57, s62, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s43, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v12.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s41, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s47, s62, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s40, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s47, s61, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v13.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v176, v177, 0x6050400
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v167, v176, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s41, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v179, s74, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v178, s74, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v150, v132, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v13.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v181, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v144, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v165, v167, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v165, v182, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v134, v118, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v166, v163, 0xc0c0004
@@ -197734,81 +197744,82 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v160
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v167
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v162
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v165, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v182
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v181
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v180
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v176
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v178, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v167, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s42, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s47, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s41, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s47, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s44, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s43, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s72, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s43, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s42, s11, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s6, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s7, v1
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s10, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s13, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s40, s10, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s14, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v71, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s15, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s45, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s72, s45, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s63, s57, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s57, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s7, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v80, s40, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v80, s13, s8, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v83, s26, s27, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v84, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
@@ -197927,34 +197938,34 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:116
; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:112
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:108
-; GFX11-FAKE16-NEXT: scratch_load_u16 v54, off, s32 offset:104
+; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:88
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:80
; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v54, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:64
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:60
; GFX11-FAKE16-NEXT: s_clause 0xf
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:56
; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:44
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
+; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
-; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:16
+; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:12
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:8
-; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v30
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v29
@@ -197969,7 +197980,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v20
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v19
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v18
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v17
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v17
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v16
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v15
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v14
@@ -197978,19 +197989,19 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v11
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v10
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v9
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v8
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v7
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v6
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v3
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB97_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0xc0c0004
@@ -197998,7 +198009,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v32, v48, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v36, v49, 0x6050400
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v68, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v54, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v9
@@ -198014,7 +198025,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s11, s8, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s13, s8, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s42, s15, v9
@@ -198022,7 +198033,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s6, s4, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s12, s9, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s11, s9, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s41, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v5
@@ -198033,7 +198044,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s57, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s13, s40, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s40, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v16, s45, s56, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
@@ -198044,8 +198055,8 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s73, s72, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v16, 16, v14
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v53, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v66, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v68, 0x6050400
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v15, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s61, s63, v11
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -198053,18 +198064,18 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v38, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v39, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v17, 16, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v65, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v65, v39, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v82, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v64, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v82, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v34, v50, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v69, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v96, v85, 0xc0c0004
@@ -198072,7 +198083,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v98, v83, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v20, 16, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v71, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v71, v53, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v21
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v86, v81, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
@@ -198225,36 +198236,36 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v82
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v83, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v68
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v67
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v69
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v80
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v65
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v64
; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v65, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v67
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v53
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v68
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v49
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v52, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v50
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v37, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v38
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v34, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc0c0004
@@ -198269,19 +198280,19 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s62, s59, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
; GFX11-FAKE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s73, s72, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s40, s13, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s40, s12, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s63, s61, v2
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s12, s9, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s11, s9, v2
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s11, s11, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v3
@@ -198292,7 +198303,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s46, s43, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s58, s47, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s11, s8, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s13, s8, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v50, s24, s25, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v65, s0, s1, v2
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
@@ -198307,7 +198318,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s44, s41, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s14, s10, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s42, s15, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v50
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s26, s27, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v67, s2, s3, v2
@@ -198334,7 +198345,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s20, s21, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v66, s18, s19, v2
@@ -198350,7 +198361,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v35, 16, v33
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v32, 16, v36
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v34, 16, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v54
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v71
; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v17
@@ -198361,9 +198372,9 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v64
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff, v51
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v55, 16, v32
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v52, 16, v33
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v52
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v54, 16, v32
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v51, 16, v33
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v20, 16, v34
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v21, 16, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v99
@@ -198374,9 +198385,9 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v66, 16, v64
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v68
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v53, 16, v51
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v55, 16, v52
; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v48
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v24
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v100, 16, v32
@@ -198392,7 +198403,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v65
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v49, 16, v48
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v10, 16, v50
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v51
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v52
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v37
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v16, 16, v38
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v70, 16, v19
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index f4274c5a2e29e..cd262717b336c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -14334,7 +14334,7 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s76, v0
; VI-NEXT: s_waitcnt vmcnt(14)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cbranch_scc0 .LBB27_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -14651,7 +14651,7 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s76, v0
; GFX9-NEXT: s_waitcnt vmcnt(19)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -14912,9 +14912,9 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
@@ -14953,9 +14953,9 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB27_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -14963,7 +14963,7 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v39, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
@@ -15015,7 +15015,7 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -15143,7 +15143,7 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
@@ -15156,7 +15156,7 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
@@ -15201,8 +15201,8 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
@@ -15242,9 +15242,9 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB27_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -29548,7 +29548,7 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s76, v0
; VI-NEXT: s_waitcnt vmcnt(14)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cbranch_scc0 .LBB51_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -29865,7 +29865,7 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s76, v0
; GFX9-NEXT: s_waitcnt vmcnt(19)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB51_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -30126,9 +30126,9 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
@@ -30167,9 +30167,9 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB51_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -30177,7 +30177,7 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v39, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
@@ -30229,7 +30229,7 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -30357,7 +30357,7 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
@@ -30370,7 +30370,7 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
@@ -30415,8 +30415,8 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
@@ -30456,9 +30456,9 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB51_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -43665,7 +43665,7 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s76, v0
; VI-NEXT: s_waitcnt vmcnt(14)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cbranch_scc0 .LBB71_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -43982,7 +43982,7 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s76, v0
; GFX9-NEXT: s_waitcnt vmcnt(19)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB71_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -44243,9 +44243,9 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
@@ -44284,9 +44284,9 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB71_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -44294,7 +44294,7 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v39, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
@@ -44346,7 +44346,7 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -44474,7 +44474,7 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
@@ -44487,7 +44487,7 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
@@ -44532,8 +44532,8 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
@@ -44573,9 +44573,9 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB71_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -57172,7 +57172,7 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s76, v0
; VI-NEXT: s_waitcnt vmcnt(14)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cbranch_scc0 .LBB87_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -57489,7 +57489,7 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s76, v0
; GFX9-NEXT: s_waitcnt vmcnt(19)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB87_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -57750,9 +57750,9 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
@@ -57791,9 +57791,9 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB87_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -57801,7 +57801,7 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v39, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
@@ -57853,7 +57853,7 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -57981,7 +57981,7 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
@@ -57994,7 +57994,7 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v38, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
@@ -58039,8 +58039,8 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
@@ -58080,9 +58080,9 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB87_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -71301,7 +71301,7 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s57, v0
; VI-NEXT: s_waitcnt vmcnt(14)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cbranch_scc0 .LBB99_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -71624,7 +71624,7 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_waitcnt vmcnt(19)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB99_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -71888,56 +71888,56 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v29
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v28
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v27
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v26
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v25
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v24
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v20
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v19
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v17
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v14
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v12
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v7
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB99_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0x6050400
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v49, v52, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v48, v51, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v32, v36, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v31, v34, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v11
@@ -71948,42 +71948,42 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s5, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s15, s7, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s4, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s13, s5, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s14, s6, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s9, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s42, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s14, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s72, s46, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s13, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s12, s56, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s44, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s11, s45, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s58, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s62, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s43, s60, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s40, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v12.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s46, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s9, s47, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s73, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v13.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v39, v48, 0x6050400
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v38, v39, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s63, s56, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v50, s74, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v49, s74, 0x6050400
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v13.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v52, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v38, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v53, 0x6050400
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v37, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
@@ -72000,83 +72000,83 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v34
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v36
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v53
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v51
; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s63, s56, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s13, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s42, s12, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s40, v1
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s47, s9, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s45, s11, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s62, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s72, s46, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s14, s6, v1
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s60, s43, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, s41, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, s15, s7, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v27, s26, s27, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
@@ -72123,18 +72123,18 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0xf
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:52
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:44
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:20
-; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
+; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:12
; GFX11-FAKE16-NEXT: scratch_load_u16 v31, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32
@@ -72170,16 +72170,16 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB99_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0x6050400
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v52, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v51, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v38, v51, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v38, v50, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v39, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v9
@@ -72228,15 +72228,15 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v16, 16, v14
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v34, s74, 0x6050400
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v35, v50, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v52, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v35, v53, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s59, s61, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v31, v37, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v49, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v48, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v12
@@ -72254,19 +72254,19 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s75, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB99_5
; GFX11-FAKE16-NEXT: ; %bb.4: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v52
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v51
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v50
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v52
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v53
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v48
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v51
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v50
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v39
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v48, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
@@ -83919,7 +83919,7 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s57, v0
; VI-NEXT: s_waitcnt vmcnt(14)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cbranch_scc0 .LBB107_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -84242,7 +84242,7 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_waitcnt vmcnt(19)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB107_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -84506,56 +84506,56 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v29
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v28
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v27
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v26
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v25
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v24
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v20
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v19
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v17
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v14
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v12
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v7
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB107_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0x6050400
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v49, v52, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v48, v51, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v32, v36, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v31, v34, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v11
@@ -84566,42 +84566,42 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s5, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s15, s7, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s4, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s13, s5, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s14, s6, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s9, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s42, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s14, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s72, s46, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s13, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s12, s56, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s44, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s11, s45, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s58, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s62, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s43, s60, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s40, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v12.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s46, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s9, s47, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s73, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v13.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v39, v48, 0x6050400
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v38, v39, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s63, s56, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v50, s74, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v49, s74, 0x6050400
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v13.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v52, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v38, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v53, 0x6050400
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v37, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
@@ -84618,83 +84618,83 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v34
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v36
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v53
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v51
; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s63, s56, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s13, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s42, s12, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s40, v1
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s47, s9, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s45, s11, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s62, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s72, s46, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s14, s6, v1
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s60, s43, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, s41, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, s15, s7, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v27, s26, s27, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
@@ -84741,18 +84741,18 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0xf
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:52
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:44
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:20
-; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
+; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:12
; GFX11-FAKE16-NEXT: scratch_load_u16 v31, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32
@@ -84788,16 +84788,16 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB107_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0x6050400
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v52, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v51, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v38, v51, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v38, v50, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v39, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v9
@@ -84846,15 +84846,15 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v16, 16, v14
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v34, s74, 0x6050400
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v35, v50, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v52, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v35, v53, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s59, s61, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v31, v37, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v49, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v48, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v12
@@ -84872,19 +84872,19 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s75, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB107_5
; GFX11-FAKE16-NEXT: ; %bb.4: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v52
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v51
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v50
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v52
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v53
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v48
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v51
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v50
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v39
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v48, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
@@ -94490,7 +94490,7 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; VI-NEXT: v_readfirstlane_b32 s57, v0
; VI-NEXT: s_waitcnt vmcnt(14)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cbranch_scc0 .LBB111_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -94813,7 +94813,7 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_waitcnt vmcnt(19)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB111_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
@@ -95077,56 +95077,56 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v29
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v28
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v27
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v26
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v25
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v24
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v20
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v19
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v17
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v14
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v12
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v7
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v3
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB111_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0x6050400
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v49, v52, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v48, v51, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v32, v36, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v31, v34, 0x6050400
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v11
@@ -95137,42 +95137,42 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s5, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s15, s7, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s4, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s13, s5, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s14, s6, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s9, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s42, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s14, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s72, s46, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s13, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s12, s56, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s44, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s11, s45, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s58, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s62, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s43, s60, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s40, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v12.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s11, s46, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s9, s47, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s57, s73, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v13.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v39, v48, 0x6050400
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v38, v39, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s63, s56, v11
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v50, s74, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v49, s74, 0x6050400
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v13.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v52, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v38, 0x6050400
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v53, 0x6050400
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v37, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
@@ -95189,83 +95189,83 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v34
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v52
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v36
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v53
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v51
; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s63, s56, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s13, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s42, s12, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s47, s47, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s45, s45, 3
; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s40, v1
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s47, s9, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s45, s11, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s62, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s72, s46, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s14, s6, v1
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s60, s43, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s5, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, s41, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, s15, s7, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v27, s26, s27, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
@@ -95312,18 +95312,18 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0xf
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:52
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:44
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:40
; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
-; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:20
-; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:20
+; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
+; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:12
; GFX11-FAKE16-NEXT: scratch_load_u16 v31, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32
@@ -95359,16 +95359,16 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
-; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB111_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0x6050400
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v52, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v51, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v38, v51, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v38, v50, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v33, v39, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v9
@@ -95417,15 +95417,15 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v16, 16, v14
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v34, s74, 0x6050400
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v35, v50, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v52, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v35, v53, 0x6050400
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s59, s61, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v31, v37, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v49, 0x6050400
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v48, 0x6050400
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v12
@@ -95443,19 +95443,19 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s75, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB111_5
; GFX11-FAKE16-NEXT: ; %bb.4: ; %cmp.true
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v52
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v51
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v50
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v52
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v53
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v48
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v51
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v50
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v39
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v48, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
diff --git a/llvm/test/CodeGen/AMDGPU/anyext.ll b/llvm/test/CodeGen/AMDGPU/anyext.ll
index 8e409fef60a8e..7b63efe8e19cf 100644
--- a/llvm/test/CodeGen/AMDGPU/anyext.ll
+++ b/llvm/test/CodeGen/AMDGPU/anyext.ll
@@ -163,7 +163,7 @@ define amdgpu_kernel void @anyext_v2i16_to_v2i32() #0 {
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_and_b32_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
-; GFX8-NEXT: s_and_b64 s[0:1], vcc, exec
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: buffer_store_byte v0, off, s[0:3], 0
@@ -179,7 +179,7 @@ define amdgpu_kernel void @anyext_v2i16_to_v2i32() #0 {
; GFX9-NEXT: v_and_b32_e32 v0, 0x80018001, v0
; GFX9-NEXT: v_bfi_b32 v0, v1, 0, v0
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
-; GFX9-NEXT: s_and_b64 s[0:1], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], 0
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index 4b16a4a371c18..3988eab1a5d71 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -13692,19 +13692,19 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX8_ITERATIVE-NEXT: .LBB23_1: ; %ComputeLoop
; GFX8_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8_ITERATIVE-NEXT: s_ff1_i32_b64 s8, s[2:3]
-; GFX8_ITERATIVE-NEXT: v_readlane_b32 s9, v3, s8
-; GFX8_ITERATIVE-NEXT: v_readlane_b32 s10, v0, s8
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s10
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v5, s9
+; GFX8_ITERATIVE-NEXT: s_ff1_i32_b64 s6, s[2:3]
+; GFX8_ITERATIVE-NEXT: v_readlane_b32 s7, v3, s6
+; GFX8_ITERATIVE-NEXT: v_readlane_b32 s8, v0, s6
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s8
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v5, s7
; GFX8_ITERATIVE-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[4:5]
-; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, s8
-; GFX8_ITERATIVE-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, s6
+; GFX8_ITERATIVE-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8_ITERATIVE-NEXT: v_writelane_b32 v2, s1, m0
; GFX8_ITERATIVE-NEXT: v_writelane_b32 v1, s0, m0
-; GFX8_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s9
-; GFX8_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s10
-; GFX8_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s8
+; GFX8_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
+; GFX8_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s8
+; GFX8_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s6
; GFX8_ITERATIVE-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX8_ITERATIVE-NEXT: s_cbranch_scc1 .LBB23_1
; GFX8_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -13747,19 +13747,19 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX9_ITERATIVE-NEXT: .LBB23_1: ; %ComputeLoop
; GFX9_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9_ITERATIVE-NEXT: s_ff1_i32_b64 s8, s[2:3]
-; GFX9_ITERATIVE-NEXT: v_readlane_b32 s9, v3, s8
-; GFX9_ITERATIVE-NEXT: v_readlane_b32 s10, v0, s8
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s10
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v5, s9
+; GFX9_ITERATIVE-NEXT: s_ff1_i32_b64 s6, s[2:3]
+; GFX9_ITERATIVE-NEXT: v_readlane_b32 s7, v3, s6
+; GFX9_ITERATIVE-NEXT: v_readlane_b32 s8, v0, s6
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s8
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v5, s7
; GFX9_ITERATIVE-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[4:5]
-; GFX9_ITERATIVE-NEXT: s_mov_b32 m0, s8
-; GFX9_ITERATIVE-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX9_ITERATIVE-NEXT: s_mov_b32 m0, s6
+; GFX9_ITERATIVE-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9_ITERATIVE-NEXT: v_writelane_b32 v2, s1, m0
; GFX9_ITERATIVE-NEXT: v_writelane_b32 v1, s0, m0
-; GFX9_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s9
-; GFX9_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s10
-; GFX9_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s8
+; GFX9_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
+; GFX9_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s8
+; GFX9_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s6
; GFX9_ITERATIVE-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX9_ITERATIVE-NEXT: s_cbranch_scc1 .LBB23_1
; GFX9_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -13807,7 +13807,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: v_writelane_b32 v2, s1, s10
; GFX1064_ITERATIVE-NEXT: v_writelane_b32 v1, s0, s10
; GFX1064_ITERATIVE-NEXT: v_cmp_gt_i64_e64 s[8:9], s[0:1], s[6:7]
-; GFX1064_ITERATIVE-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX1064_ITERATIVE-NEXT: s_cmp_lg_u64 s[8:9], 0
; GFX1064_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1064_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1064_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s10
@@ -13858,7 +13858,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: v_writelane_b32 v2, s1, s3
; GFX1032_ITERATIVE-NEXT: v_writelane_b32 v1, s0, s3
; GFX1032_ITERATIVE-NEXT: v_cmp_gt_i64_e64 s8, s[0:1], s[6:7]
-; GFX1032_ITERATIVE-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1032_ITERATIVE-NEXT: s_cmp_lg_u32 s8, 0
; GFX1032_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1032_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1032_ITERATIVE-NEXT: s_lshl_b32 s3, 1, s3
@@ -13911,7 +13911,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: v_writelane_b32 v1, s1, s10
; GFX1164_ITERATIVE-NEXT: v_writelane_b32 v0, s0, s10
; GFX1164_ITERATIVE-NEXT: v_cmp_gt_i64_e64 s[8:9], s[0:1], s[6:7]
-; GFX1164_ITERATIVE-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX1164_ITERATIVE-NEXT: s_cmp_lg_u64 s[8:9], 0
; GFX1164_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1164_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1164_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s10
@@ -13966,7 +13966,7 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1132_ITERATIVE-NEXT: v_writelane_b32 v1, s1, s3
; GFX1132_ITERATIVE-NEXT: v_writelane_b32 v0, s0, s3
; GFX1132_ITERATIVE-NEXT: v_cmp_gt_i64_e64 s8, s[0:1], s[6:7]
-; GFX1132_ITERATIVE-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1132_ITERATIVE-NEXT: s_cmp_lg_u32 s8, 0
; GFX1132_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1132_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1132_ITERATIVE-NEXT: s_lshl_b32 s3, 1, s3
@@ -15897,19 +15897,19 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX8_ITERATIVE-NEXT: .LBB26_1: ; %ComputeLoop
; GFX8_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8_ITERATIVE-NEXT: s_ff1_i32_b64 s8, s[2:3]
-; GFX8_ITERATIVE-NEXT: v_readlane_b32 s9, v3, s8
-; GFX8_ITERATIVE-NEXT: v_readlane_b32 s10, v0, s8
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s10
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v5, s9
+; GFX8_ITERATIVE-NEXT: s_ff1_i32_b64 s6, s[2:3]
+; GFX8_ITERATIVE-NEXT: v_readlane_b32 s7, v3, s6
+; GFX8_ITERATIVE-NEXT: v_readlane_b32 s8, v0, s6
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s8
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v5, s7
; GFX8_ITERATIVE-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[4:5]
-; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, s8
-; GFX8_ITERATIVE-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, s6
+; GFX8_ITERATIVE-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8_ITERATIVE-NEXT: v_writelane_b32 v2, s1, m0
; GFX8_ITERATIVE-NEXT: v_writelane_b32 v1, s0, m0
-; GFX8_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s9
-; GFX8_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s10
-; GFX8_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s8
+; GFX8_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
+; GFX8_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s8
+; GFX8_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s6
; GFX8_ITERATIVE-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX8_ITERATIVE-NEXT: s_cbranch_scc1 .LBB26_1
; GFX8_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -15952,19 +15952,19 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX9_ITERATIVE-NEXT: .LBB26_1: ; %ComputeLoop
; GFX9_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9_ITERATIVE-NEXT: s_ff1_i32_b64 s8, s[2:3]
-; GFX9_ITERATIVE-NEXT: v_readlane_b32 s9, v3, s8
-; GFX9_ITERATIVE-NEXT: v_readlane_b32 s10, v0, s8
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s10
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v5, s9
+; GFX9_ITERATIVE-NEXT: s_ff1_i32_b64 s6, s[2:3]
+; GFX9_ITERATIVE-NEXT: v_readlane_b32 s7, v3, s6
+; GFX9_ITERATIVE-NEXT: v_readlane_b32 s8, v0, s6
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s8
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v5, s7
; GFX9_ITERATIVE-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[4:5]
-; GFX9_ITERATIVE-NEXT: s_mov_b32 m0, s8
-; GFX9_ITERATIVE-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX9_ITERATIVE-NEXT: s_mov_b32 m0, s6
+; GFX9_ITERATIVE-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9_ITERATIVE-NEXT: v_writelane_b32 v2, s1, m0
; GFX9_ITERATIVE-NEXT: v_writelane_b32 v1, s0, m0
-; GFX9_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s9
-; GFX9_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s10
-; GFX9_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s8
+; GFX9_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
+; GFX9_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s8
+; GFX9_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s6
; GFX9_ITERATIVE-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX9_ITERATIVE-NEXT: s_cbranch_scc1 .LBB26_1
; GFX9_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -16012,7 +16012,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: v_writelane_b32 v2, s1, s10
; GFX1064_ITERATIVE-NEXT: v_writelane_b32 v1, s0, s10
; GFX1064_ITERATIVE-NEXT: v_cmp_lt_i64_e64 s[8:9], s[0:1], s[6:7]
-; GFX1064_ITERATIVE-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX1064_ITERATIVE-NEXT: s_cmp_lg_u64 s[8:9], 0
; GFX1064_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1064_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1064_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s10
@@ -16063,7 +16063,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: v_writelane_b32 v2, s1, s3
; GFX1032_ITERATIVE-NEXT: v_writelane_b32 v1, s0, s3
; GFX1032_ITERATIVE-NEXT: v_cmp_lt_i64_e64 s8, s[0:1], s[6:7]
-; GFX1032_ITERATIVE-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1032_ITERATIVE-NEXT: s_cmp_lg_u32 s8, 0
; GFX1032_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1032_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1032_ITERATIVE-NEXT: s_lshl_b32 s3, 1, s3
@@ -16116,7 +16116,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: v_writelane_b32 v1, s1, s10
; GFX1164_ITERATIVE-NEXT: v_writelane_b32 v0, s0, s10
; GFX1164_ITERATIVE-NEXT: v_cmp_lt_i64_e64 s[8:9], s[0:1], s[6:7]
-; GFX1164_ITERATIVE-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX1164_ITERATIVE-NEXT: s_cmp_lg_u64 s[8:9], 0
; GFX1164_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1164_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1164_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s10
@@ -16171,7 +16171,7 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1132_ITERATIVE-NEXT: v_writelane_b32 v1, s1, s3
; GFX1132_ITERATIVE-NEXT: v_writelane_b32 v0, s0, s3
; GFX1132_ITERATIVE-NEXT: v_cmp_lt_i64_e64 s8, s[0:1], s[6:7]
-; GFX1132_ITERATIVE-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1132_ITERATIVE-NEXT: s_cmp_lg_u32 s8, 0
; GFX1132_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1132_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1132_ITERATIVE-NEXT: s_lshl_b32 s3, 1, s3
@@ -18095,19 +18095,19 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX8_ITERATIVE-NEXT: .LBB29_1: ; %ComputeLoop
; GFX8_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8_ITERATIVE-NEXT: s_ff1_i32_b64 s8, s[2:3]
-; GFX8_ITERATIVE-NEXT: v_readlane_b32 s9, v3, s8
-; GFX8_ITERATIVE-NEXT: v_readlane_b32 s10, v0, s8
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s10
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v5, s9
+; GFX8_ITERATIVE-NEXT: s_ff1_i32_b64 s6, s[2:3]
+; GFX8_ITERATIVE-NEXT: v_readlane_b32 s7, v3, s6
+; GFX8_ITERATIVE-NEXT: v_readlane_b32 s8, v0, s6
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s8
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v5, s7
; GFX8_ITERATIVE-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
-; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, s8
-; GFX8_ITERATIVE-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, s6
+; GFX8_ITERATIVE-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8_ITERATIVE-NEXT: v_writelane_b32 v2, s1, m0
; GFX8_ITERATIVE-NEXT: v_writelane_b32 v1, s0, m0
-; GFX8_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s9
-; GFX8_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s10
-; GFX8_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s8
+; GFX8_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
+; GFX8_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s8
+; GFX8_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s6
; GFX8_ITERATIVE-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX8_ITERATIVE-NEXT: s_cbranch_scc1 .LBB29_1
; GFX8_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -18149,19 +18149,19 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX9_ITERATIVE-NEXT: .LBB29_1: ; %ComputeLoop
; GFX9_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9_ITERATIVE-NEXT: s_ff1_i32_b64 s8, s[2:3]
-; GFX9_ITERATIVE-NEXT: v_readlane_b32 s9, v3, s8
-; GFX9_ITERATIVE-NEXT: v_readlane_b32 s10, v0, s8
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s10
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v5, s9
+; GFX9_ITERATIVE-NEXT: s_ff1_i32_b64 s6, s[2:3]
+; GFX9_ITERATIVE-NEXT: v_readlane_b32 s7, v3, s6
+; GFX9_ITERATIVE-NEXT: v_readlane_b32 s8, v0, s6
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s8
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v5, s7
; GFX9_ITERATIVE-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
-; GFX9_ITERATIVE-NEXT: s_mov_b32 m0, s8
-; GFX9_ITERATIVE-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX9_ITERATIVE-NEXT: s_mov_b32 m0, s6
+; GFX9_ITERATIVE-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9_ITERATIVE-NEXT: v_writelane_b32 v2, s1, m0
; GFX9_ITERATIVE-NEXT: v_writelane_b32 v1, s0, m0
-; GFX9_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s9
-; GFX9_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s10
-; GFX9_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s8
+; GFX9_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
+; GFX9_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s8
+; GFX9_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s6
; GFX9_ITERATIVE-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX9_ITERATIVE-NEXT: s_cbranch_scc1 .LBB29_1
; GFX9_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -18208,7 +18208,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: v_writelane_b32 v2, s1, s10
; GFX1064_ITERATIVE-NEXT: v_writelane_b32 v1, s0, s10
; GFX1064_ITERATIVE-NEXT: v_cmp_gt_u64_e64 s[8:9], s[0:1], s[6:7]
-; GFX1064_ITERATIVE-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX1064_ITERATIVE-NEXT: s_cmp_lg_u64 s[8:9], 0
; GFX1064_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1064_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1064_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s10
@@ -18258,7 +18258,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: v_writelane_b32 v2, s1, s3
; GFX1032_ITERATIVE-NEXT: v_writelane_b32 v1, s0, s3
; GFX1032_ITERATIVE-NEXT: v_cmp_gt_u64_e64 s8, s[0:1], s[6:7]
-; GFX1032_ITERATIVE-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1032_ITERATIVE-NEXT: s_cmp_lg_u32 s8, 0
; GFX1032_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1032_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1032_ITERATIVE-NEXT: s_lshl_b32 s3, 1, s3
@@ -18311,7 +18311,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: v_writelane_b32 v0, s0, s10
; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164_ITERATIVE-NEXT: v_cmp_gt_u64_e64 s[8:9], s[0:1], s[6:7]
-; GFX1164_ITERATIVE-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX1164_ITERATIVE-NEXT: s_cmp_lg_u64 s[8:9], 0
; GFX1164_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1164_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1164_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s10
@@ -18365,7 +18365,7 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1132_ITERATIVE-NEXT: v_writelane_b32 v0, s0, s3
; GFX1132_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132_ITERATIVE-NEXT: v_cmp_gt_u64_e64 s8, s[0:1], s[6:7]
-; GFX1132_ITERATIVE-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1132_ITERATIVE-NEXT: s_cmp_lg_u32 s8, 0
; GFX1132_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1132_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1132_ITERATIVE-NEXT: s_lshl_b32 s3, 1, s3
@@ -20283,19 +20283,19 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX8_ITERATIVE-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX8_ITERATIVE-NEXT: .LBB32_1: ; %ComputeLoop
; GFX8_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8_ITERATIVE-NEXT: s_ff1_i32_b64 s8, s[2:3]
-; GFX8_ITERATIVE-NEXT: v_readlane_b32 s9, v3, s8
-; GFX8_ITERATIVE-NEXT: v_readlane_b32 s10, v0, s8
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s10
-; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v5, s9
+; GFX8_ITERATIVE-NEXT: s_ff1_i32_b64 s6, s[2:3]
+; GFX8_ITERATIVE-NEXT: v_readlane_b32 s7, v3, s6
+; GFX8_ITERATIVE-NEXT: v_readlane_b32 s8, v0, s6
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v4, s8
+; GFX8_ITERATIVE-NEXT: v_mov_b32_e32 v5, s7
; GFX8_ITERATIVE-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[4:5]
-; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, s8
-; GFX8_ITERATIVE-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX8_ITERATIVE-NEXT: s_mov_b32 m0, s6
+; GFX8_ITERATIVE-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8_ITERATIVE-NEXT: v_writelane_b32 v2, s1, m0
; GFX8_ITERATIVE-NEXT: v_writelane_b32 v1, s0, m0
-; GFX8_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s9
-; GFX8_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s10
-; GFX8_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s8
+; GFX8_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
+; GFX8_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s8
+; GFX8_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s6
; GFX8_ITERATIVE-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX8_ITERATIVE-NEXT: s_cbranch_scc1 .LBB32_1
; GFX8_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -20337,19 +20337,19 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX9_ITERATIVE-NEXT: ; implicit-def: $vgpr1_vgpr2
; GFX9_ITERATIVE-NEXT: .LBB32_1: ; %ComputeLoop
; GFX9_ITERATIVE-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9_ITERATIVE-NEXT: s_ff1_i32_b64 s8, s[2:3]
-; GFX9_ITERATIVE-NEXT: v_readlane_b32 s9, v3, s8
-; GFX9_ITERATIVE-NEXT: v_readlane_b32 s10, v0, s8
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s10
-; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v5, s9
+; GFX9_ITERATIVE-NEXT: s_ff1_i32_b64 s6, s[2:3]
+; GFX9_ITERATIVE-NEXT: v_readlane_b32 s7, v3, s6
+; GFX9_ITERATIVE-NEXT: v_readlane_b32 s8, v0, s6
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v4, s8
+; GFX9_ITERATIVE-NEXT: v_mov_b32_e32 v5, s7
; GFX9_ITERATIVE-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[4:5]
-; GFX9_ITERATIVE-NEXT: s_mov_b32 m0, s8
-; GFX9_ITERATIVE-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX9_ITERATIVE-NEXT: s_mov_b32 m0, s6
+; GFX9_ITERATIVE-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9_ITERATIVE-NEXT: v_writelane_b32 v2, s1, m0
; GFX9_ITERATIVE-NEXT: v_writelane_b32 v1, s0, m0
-; GFX9_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s9
-; GFX9_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s10
-; GFX9_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s8
+; GFX9_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
+; GFX9_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s8
+; GFX9_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s6
; GFX9_ITERATIVE-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX9_ITERATIVE-NEXT: s_cbranch_scc1 .LBB32_1
; GFX9_ITERATIVE-NEXT: ; %bb.2: ; %ComputeEnd
@@ -20396,7 +20396,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1064_ITERATIVE-NEXT: v_writelane_b32 v2, s1, s10
; GFX1064_ITERATIVE-NEXT: v_writelane_b32 v1, s0, s10
; GFX1064_ITERATIVE-NEXT: v_cmp_lt_u64_e64 s[8:9], s[0:1], s[6:7]
-; GFX1064_ITERATIVE-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX1064_ITERATIVE-NEXT: s_cmp_lg_u64 s[8:9], 0
; GFX1064_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1064_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1064_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s10
@@ -20446,7 +20446,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1032_ITERATIVE-NEXT: v_writelane_b32 v2, s1, s3
; GFX1032_ITERATIVE-NEXT: v_writelane_b32 v1, s0, s3
; GFX1032_ITERATIVE-NEXT: v_cmp_lt_u64_e64 s8, s[0:1], s[6:7]
-; GFX1032_ITERATIVE-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1032_ITERATIVE-NEXT: s_cmp_lg_u32 s8, 0
; GFX1032_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1032_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1032_ITERATIVE-NEXT: s_lshl_b32 s3, 1, s3
@@ -20499,7 +20499,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1164_ITERATIVE-NEXT: v_writelane_b32 v0, s0, s10
; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164_ITERATIVE-NEXT: v_cmp_lt_u64_e64 s[8:9], s[0:1], s[6:7]
-; GFX1164_ITERATIVE-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX1164_ITERATIVE-NEXT: s_cmp_lg_u64 s[8:9], 0
; GFX1164_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1164_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1164_ITERATIVE-NEXT: s_lshl_b64 s[6:7], 1, s10
@@ -20553,7 +20553,7 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1132_ITERATIVE-NEXT: v_writelane_b32 v0, s0, s3
; GFX1132_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132_ITERATIVE-NEXT: v_cmp_lt_u64_e64 s8, s[0:1], s[6:7]
-; GFX1132_ITERATIVE-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1132_ITERATIVE-NEXT: s_cmp_lg_u32 s8, 0
; GFX1132_ITERATIVE-NEXT: s_cselect_b32 s1, s1, s7
; GFX1132_ITERATIVE-NEXT: s_cselect_b32 s0, s0, s6
; GFX1132_ITERATIVE-NEXT: s_lshl_b32 s3, 1, s3
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
index 43100e1839426..0450b6cf7401a 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
@@ -91,7 +91,7 @@ define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_s(<2 x float> inreg %src) {
; GFX-942-NEXT: s_or_b32 s4, s1, 0x400000
; GFX-942-NEXT: s_add_i32 s5, s2, 0x7fff
; GFX-942-NEXT: v_cmp_u_f32_e64 s[2:3], s1, s1
-; GFX-942-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX-942-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX-942-NEXT: s_cselect_b32 s1, s4, s5
; GFX-942-NEXT: s_lshr_b32 s2, s1, 16
; GFX-942-NEXT: s_bfe_u32 s1, s0, 0x10010
@@ -99,7 +99,7 @@ define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_s(<2 x float> inreg %src) {
; GFX-942-NEXT: s_or_b32 s3, s0, 0x400000
; GFX-942-NEXT: s_add_i32 s4, s1, 0x7fff
; GFX-942-NEXT: v_cmp_u_f32_e64 s[0:1], s0, s0
-; GFX-942-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX-942-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX-942-NEXT: s_cselect_b32 s0, s3, s4
; GFX-942-NEXT: s_lshr_b32 s0, s0, 16
; GFX-942-NEXT: s_pack_ll_b32_b16 s0, s0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll b/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
index 122c0f7068f4f..b8408f3a686dd 100644
--- a/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
+++ b/llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
@@ -15,13 +15,13 @@ define protected amdgpu_kernel void @sccClobber(ptr addrspace(1) %a, ptr addrspa
; RRLIST-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x44
; RRLIST-NEXT: s_load_dword s17, s[14:15], 0x0
; RRLIST-NEXT: s_waitcnt lgkmcnt(0)
-; RRLIST-NEXT: s_min_i32 s8, s16, 0
+; RRLIST-NEXT: s_min_i32 s4, s16, 0
; RRLIST-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; RRLIST-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
-; RRLIST-NEXT: s_and_b64 s[4:5], vcc, exec
-; RRLIST-NEXT: s_cselect_b32 s4, s16, s17
+; RRLIST-NEXT: s_cmp_lg_u64 vcc, 0
+; RRLIST-NEXT: s_cselect_b32 s5, s16, s17
; RRLIST-NEXT: s_cmp_eq_u64 s[2:3], s[0:1]
-; RRLIST-NEXT: s_cselect_b32 s0, s8, s4
+; RRLIST-NEXT: s_cselect_b32 s0, s4, s5
; RRLIST-NEXT: v_mov_b32_e32 v0, s0
; RRLIST-NEXT: global_store_dword v2, v0, s[6:7]
; RRLIST-NEXT: s_endpgm
@@ -37,13 +37,13 @@ define protected amdgpu_kernel void @sccClobber(ptr addrspace(1) %a, ptr addrspa
; FAST-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x44
; FAST-NEXT: s_load_dword s17, s[14:15], 0x0
; FAST-NEXT: s_waitcnt lgkmcnt(0)
-; FAST-NEXT: s_min_i32 s8, s16, 0
+; FAST-NEXT: s_min_i32 s4, s16, 0
; FAST-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
; FAST-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
-; FAST-NEXT: s_and_b64 s[4:5], vcc, exec
-; FAST-NEXT: s_cselect_b32 s4, s16, s17
+; FAST-NEXT: s_cmp_lg_u64 vcc, 0
+; FAST-NEXT: s_cselect_b32 s5, s16, s17
; FAST-NEXT: s_cmp_eq_u64 s[2:3], s[0:1]
-; FAST-NEXT: s_cselect_b32 s0, s8, s4
+; FAST-NEXT: s_cselect_b32 s0, s4, s5
; FAST-NEXT: v_mov_b32_e32 v0, s0
; FAST-NEXT: global_store_dword v2, v0, s[6:7]
; FAST-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
index b62ef69266c9b..7b764aef5b299 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
@@ -1660,7 +1660,7 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
-; GFX9-NEXT: s_and_b64 s[34:35], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB7_2
; GFX9-NEXT: ; %bb.1: ; %F
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[2:3], off offset:16 glc
@@ -1721,7 +1721,7 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB7_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %F
; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
@@ -1772,7 +1772,7 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB7_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %F
; GFX11-FAKE16-NEXT: global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
@@ -2000,7 +2000,7 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
-; GFX9-NEXT: s_and_b64 s[34:35], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB8_2
; GFX9-NEXT: ; %bb.1: ; %F
; GFX9-NEXT: global_load_dwordx4 v[4:7], v[2:3], off offset:16 glc
@@ -2059,7 +2059,7 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB8_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %F
; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
@@ -2110,7 +2110,7 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB8_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %F
; GFX11-FAKE16-NEXT: global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
index 01874a584c968..1720f242fcc96 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
@@ -55,7 +55,7 @@ define amdgpu_kernel void @fcmp_f16_lt(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -82,7 +82,7 @@ define amdgpu_kernel void @fcmp_f16_lt(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -110,7 +110,7 @@ define amdgpu_kernel void @fcmp_f16_lt(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -227,7 +227,7 @@ define amdgpu_kernel void @fcmp_f16_lt_abs(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_lt_f16_e64 s[0:1], |v0|, |v1|
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -254,7 +254,7 @@ define amdgpu_kernel void @fcmp_f16_lt_abs(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e64 s2, |v0.l|, |v0.h|
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -282,7 +282,7 @@ define amdgpu_kernel void @fcmp_f16_lt_abs(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_lt_f16_e64 s2, |v0|, |v1|
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -407,7 +407,7 @@ define amdgpu_kernel void @fcmp_f16_eq(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_eq_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -434,7 +434,7 @@ define amdgpu_kernel void @fcmp_f16_eq(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -462,7 +462,7 @@ define amdgpu_kernel void @fcmp_f16_eq(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -579,7 +579,7 @@ define amdgpu_kernel void @fcmp_f16_le(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_le_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -606,7 +606,7 @@ define amdgpu_kernel void @fcmp_f16_le(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -634,7 +634,7 @@ define amdgpu_kernel void @fcmp_f16_le(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -751,7 +751,7 @@ define amdgpu_kernel void @fcmp_f16_gt(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_gt_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -778,7 +778,7 @@ define amdgpu_kernel void @fcmp_f16_gt(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -806,7 +806,7 @@ define amdgpu_kernel void @fcmp_f16_gt(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -923,7 +923,7 @@ define amdgpu_kernel void @fcmp_f16_lg(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_lg_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -950,7 +950,7 @@ define amdgpu_kernel void @fcmp_f16_lg(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -978,7 +978,7 @@ define amdgpu_kernel void @fcmp_f16_lg(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1095,7 +1095,7 @@ define amdgpu_kernel void @fcmp_f16_ge(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_ge_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -1122,7 +1122,7 @@ define amdgpu_kernel void @fcmp_f16_ge(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1150,7 +1150,7 @@ define amdgpu_kernel void @fcmp_f16_ge(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1267,7 +1267,7 @@ define amdgpu_kernel void @fcmp_f16_o(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_o_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -1294,7 +1294,7 @@ define amdgpu_kernel void @fcmp_f16_o(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1322,7 +1322,7 @@ define amdgpu_kernel void @fcmp_f16_o(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1439,7 +1439,7 @@ define amdgpu_kernel void @fcmp_f16_u(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_u_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -1466,7 +1466,7 @@ define amdgpu_kernel void @fcmp_f16_u(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1494,7 +1494,7 @@ define amdgpu_kernel void @fcmp_f16_u(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1611,7 +1611,7 @@ define amdgpu_kernel void @fcmp_f16_nge(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_nge_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -1638,7 +1638,7 @@ define amdgpu_kernel void @fcmp_f16_nge(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1666,7 +1666,7 @@ define amdgpu_kernel void @fcmp_f16_nge(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1783,7 +1783,7 @@ define amdgpu_kernel void @fcmp_f16_nlg(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_nlg_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -1810,7 +1810,7 @@ define amdgpu_kernel void @fcmp_f16_nlg(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1838,7 +1838,7 @@ define amdgpu_kernel void @fcmp_f16_nlg(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -1955,7 +1955,7 @@ define amdgpu_kernel void @fcmp_f16_ngt(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -1982,7 +1982,7 @@ define amdgpu_kernel void @fcmp_f16_ngt(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -2010,7 +2010,7 @@ define amdgpu_kernel void @fcmp_f16_ngt(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -2127,7 +2127,7 @@ define amdgpu_kernel void @fcmp_f16_nle(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_nle_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -2154,7 +2154,7 @@ define amdgpu_kernel void @fcmp_f16_nle(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -2182,7 +2182,7 @@ define amdgpu_kernel void @fcmp_f16_nle(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -2299,7 +2299,7 @@ define amdgpu_kernel void @fcmp_f16_neq(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_neq_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -2326,7 +2326,7 @@ define amdgpu_kernel void @fcmp_f16_neq(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -2354,7 +2354,7 @@ define amdgpu_kernel void @fcmp_f16_neq(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -2471,7 +2471,7 @@ define amdgpu_kernel void @fcmp_f16_nlt(
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -2498,7 +2498,7 @@ define amdgpu_kernel void @fcmp_f16_nlt(
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1
; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -2526,7 +2526,7 @@ define amdgpu_kernel void @fcmp_f16_nlt(
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s1
; GFX11-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX11-FAKE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
@@ -2654,9 +2654,9 @@ define amdgpu_kernel void @fcmp_v2f16_lt(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_lt_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -2686,9 +2686,9 @@ define amdgpu_kernel void @fcmp_v2f16_lt(
; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -2719,9 +2719,9 @@ define amdgpu_kernel void @fcmp_v2f16_lt(
; GFX11-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_lt_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -2863,9 +2863,9 @@ define amdgpu_kernel void @fcmp_v2f16_eq(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_eq_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_eq_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -2895,9 +2895,9 @@ define amdgpu_kernel void @fcmp_v2f16_eq(
; GFX11-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_eq_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -2928,9 +2928,9 @@ define amdgpu_kernel void @fcmp_v2f16_eq(
; GFX11-FAKE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_eq_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -3071,9 +3071,9 @@ define amdgpu_kernel void @fcmp_v2f16_le(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_le_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_le_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -3103,9 +3103,9 @@ define amdgpu_kernel void @fcmp_v2f16_le(
; GFX11-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_le_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -3136,9 +3136,9 @@ define amdgpu_kernel void @fcmp_v2f16_le(
; GFX11-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_le_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -3279,9 +3279,9 @@ define amdgpu_kernel void @fcmp_v2f16_gt(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_gt_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_gt_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -3311,9 +3311,9 @@ define amdgpu_kernel void @fcmp_v2f16_gt(
; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -3344,9 +3344,9 @@ define amdgpu_kernel void @fcmp_v2f16_gt(
; GFX11-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_gt_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -3488,9 +3488,9 @@ define amdgpu_kernel void @fcmp_v2f16_lg(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_lg_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_lg_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -3520,9 +3520,9 @@ define amdgpu_kernel void @fcmp_v2f16_lg(
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -3553,9 +3553,9 @@ define amdgpu_kernel void @fcmp_v2f16_lg(
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_lg_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -3697,9 +3697,9 @@ define amdgpu_kernel void @fcmp_v2f16_ge(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_ge_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_ge_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -3729,9 +3729,9 @@ define amdgpu_kernel void @fcmp_v2f16_ge(
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -3762,9 +3762,9 @@ define amdgpu_kernel void @fcmp_v2f16_ge(
; GFX11-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_ge_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -3906,9 +3906,9 @@ define amdgpu_kernel void @fcmp_v2f16_o(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_o_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_o_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -3938,9 +3938,9 @@ define amdgpu_kernel void @fcmp_v2f16_o(
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -3971,9 +3971,9 @@ define amdgpu_kernel void @fcmp_v2f16_o(
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_o_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -4115,9 +4115,9 @@ define amdgpu_kernel void @fcmp_v2f16_u(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_u_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_u_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -4147,9 +4147,9 @@ define amdgpu_kernel void @fcmp_v2f16_u(
; GFX11-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_u_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -4180,9 +4180,9 @@ define amdgpu_kernel void @fcmp_v2f16_u(
; GFX11-FAKE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_u_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -4323,9 +4323,9 @@ define amdgpu_kernel void @fcmp_v2f16_nge(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_nge_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -4355,9 +4355,9 @@ define amdgpu_kernel void @fcmp_v2f16_nge(
; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -4388,9 +4388,9 @@ define amdgpu_kernel void @fcmp_v2f16_nge(
; GFX11-FAKE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_nge_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -4531,9 +4531,9 @@ define amdgpu_kernel void @fcmp_v2f16_nlg(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_nlg_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_nlg_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -4563,9 +4563,9 @@ define amdgpu_kernel void @fcmp_v2f16_nlg(
; GFX11-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_nlg_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -4596,9 +4596,9 @@ define amdgpu_kernel void @fcmp_v2f16_nlg(
; GFX11-FAKE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_nlg_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -4740,9 +4740,9 @@ define amdgpu_kernel void @fcmp_v2f16_ngt(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_ngt_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -4772,9 +4772,9 @@ define amdgpu_kernel void @fcmp_v2f16_ngt(
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -4805,9 +4805,9 @@ define amdgpu_kernel void @fcmp_v2f16_ngt(
; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -4948,9 +4948,9 @@ define amdgpu_kernel void @fcmp_v2f16_nle(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_nle_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_nle_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -4980,9 +4980,9 @@ define amdgpu_kernel void @fcmp_v2f16_nle(
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -5013,9 +5013,9 @@ define amdgpu_kernel void @fcmp_v2f16_nle(
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -5156,9 +5156,9 @@ define amdgpu_kernel void @fcmp_v2f16_neq(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_neq_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_neq_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -5188,9 +5188,9 @@ define amdgpu_kernel void @fcmp_v2f16_neq(
; GFX11-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_neq_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -5221,9 +5221,9 @@ define amdgpu_kernel void @fcmp_v2f16_neq(
; GFX11-FAKE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_neq_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
@@ -5364,9 +5364,9 @@ define amdgpu_kernel void @fcmp_v2f16_nlt(
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v1, v0
; VI-NEXT: v_cmp_nlt_f16_e64 s[0:1], v3, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, -1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, -1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s0
@@ -5396,9 +5396,9 @@ define amdgpu_kernel void @fcmp_v2f16_nlt(
; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
@@ -5429,9 +5429,9 @@ define amdgpu_kernel void @fcmp_v2f16_nlt(
; GFX11-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_nlt_f16_e64 s0, v3, v2
-; GFX11-FAKE16-NEXT: s_and_b32 s1, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, s8
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 31b868993156d..2ee29afdba76f 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -3091,7 +3091,7 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_f32_sign_bf16(float inreg %mag, bf
; GFX8-NEXT: s_or_b32 s4, s0, 0x400000
; GFX8-NEXT: s_add_i32 s6, s2, 0x7fff
; GFX8-NEXT: v_cmp_u_f32_e64 s[2:3], s0, s0
-; GFX8-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: s_cselect_b32 s0, s4, s6
; GFX8-NEXT: s_lshr_b32 s0, s0, 16
; GFX8-NEXT: s_movk_i32 s5, 0x7fff
@@ -3108,7 +3108,7 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_f32_sign_bf16(float inreg %mag, bf
; GFX9-NEXT: s_or_b32 s4, s0, 0x400000
; GFX9-NEXT: s_add_i32 s6, s2, 0x7fff
; GFX9-NEXT: v_cmp_u_f32_e64 s[2:3], s0, s0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9-NEXT: s_cselect_b32 s0, s4, s6
; GFX9-NEXT: s_lshr_b32 s0, s0, 16
; GFX9-NEXT: s_movk_i32 s5, 0x7fff
@@ -3126,7 +3126,7 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_f32_sign_bf16(float inreg %mag, bf
; GFX10-NEXT: s_bitset1_b32 s0, 22
; GFX10-NEXT: s_addk_i32 s2, 0x7fff
; GFX10-NEXT: v_mov_b32_e32 v0, s1
-; GFX10-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s3, 0
; GFX10-NEXT: s_cselect_b32 s0, s0, s2
; GFX10-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-NEXT: v_bfi_b32 v0, 0x7fff, s0, v0
@@ -3141,7 +3141,7 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_f32_sign_bf16(float inreg %mag, bf
; GFX11TRUE16-NEXT: s_bitset1_b32 s0, 22
; GFX11TRUE16-NEXT: s_addk_i32 s2, 0x7fff
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
-; GFX11TRUE16-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX11TRUE16-NEXT: s_cmp_lg_u32 s3, 0
; GFX11TRUE16-NEXT: s_cselect_b32 s0, s0, s2
; GFX11TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11TRUE16-NEXT: s_lshr_b32 s0, s0, 16
@@ -3159,7 +3159,7 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_f32_sign_bf16(float inreg %mag, bf
; GFX11FAKE16-NEXT: s_bitset1_b32 s0, 22
; GFX11FAKE16-NEXT: s_addk_i32 s2, 0x7fff
; GFX11FAKE16-NEXT: v_mov_b32_e32 v0, s1
-; GFX11FAKE16-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX11FAKE16-NEXT: s_cmp_lg_u32 s3, 0
; GFX11FAKE16-NEXT: s_cselect_b32 s0, s0, s2
; GFX11FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11FAKE16-NEXT: s_lshr_b32 s0, s0, 16
@@ -4309,14 +4309,14 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f32_sign_v2bf16(<2 x float> in
; GFX8-NEXT: s_or_b32 s3, s0, 0x400000
; GFX8-NEXT: s_add_i32 s6, s4, 0x7fff
; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], s0, s0
-; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX8-NEXT: s_cselect_b32 s0, s3, s6
; GFX8-NEXT: s_bfe_u32 s4, s1, 0x10010
; GFX8-NEXT: s_add_i32 s4, s4, s1
; GFX8-NEXT: s_or_b32 s3, s1, 0x400000
; GFX8-NEXT: s_add_i32 s6, s4, 0x7fff
; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], s1, s1
-; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX8-NEXT: s_cselect_b32 s1, s3, s6
; GFX8-NEXT: s_lshr_b32 s1, s1, 16
; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
@@ -4334,7 +4334,7 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f32_sign_v2bf16(<2 x float> in
; GFX9-NEXT: s_or_b32 s3, s1, 0x400000
; GFX9-NEXT: s_add_i32 s6, s4, 0x7fff
; GFX9-NEXT: v_cmp_u_f32_e64 s[4:5], s1, s1
-; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX9-NEXT: s_cselect_b32 s1, s3, s6
; GFX9-NEXT: s_lshr_b32 s3, s1, 16
; GFX9-NEXT: s_bfe_u32 s1, s0, 0x10010
@@ -4342,7 +4342,7 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f32_sign_v2bf16(<2 x float> in
; GFX9-NEXT: s_or_b32 s4, s0, 0x400000
; GFX9-NEXT: s_add_i32 s5, s1, 0x7fff
; GFX9-NEXT: v_cmp_u_f32_e64 s[0:1], s0, s0
-; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, s4, s5
; GFX9-NEXT: s_lshr_b32 s0, s0, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3
@@ -4361,15 +4361,15 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f32_sign_v2bf16(<2 x float> in
; GFX10-NEXT: s_bitset1_b32 s1, 22
; GFX10-NEXT: s_addk_i32 s3, 0x7fff
; GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GFX10-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, s0, s0
; GFX10-NEXT: s_cselect_b32 s1, s1, s3
; GFX10-NEXT: s_bfe_u32 s3, s0, 0x10010
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, s0, s0
-; GFX10-NEXT: s_add_i32 s3, s3, s0
; GFX10-NEXT: s_lshr_b32 s1, s1, 16
+; GFX10-NEXT: s_add_i32 s3, s3, s0
; GFX10-NEXT: s_bitset1_b32 s0, 22
; GFX10-NEXT: s_addk_i32 s3, 0x7fff
-; GFX10-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
; GFX10-NEXT: s_cselect_b32 s0, s0, s3
; GFX10-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
@@ -4385,15 +4385,15 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f32_sign_v2bf16(<2 x float> in
; GFX11-NEXT: s_bitset1_b32 s1, 22
; GFX11-NEXT: s_addk_i32 s3, 0x7fff
; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s4, 0
+; GFX11-NEXT: v_cmp_u_f32_e64 s4, s0, s0
; GFX11-NEXT: s_cselect_b32 s1, s1, s3
; GFX11-NEXT: s_bfe_u32 s3, s0, 0x10010
-; GFX11-NEXT: v_cmp_u_f32_e64 s4, s0, s0
-; GFX11-NEXT: s_add_i32 s3, s3, s0
; GFX11-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-NEXT: s_add_i32 s3, s3, s0
; GFX11-NEXT: s_bitset1_b32 s0, 22
; GFX11-NEXT: s_addk_i32 s3, 0x7fff
-; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s4, 0
; GFX11-NEXT: s_cselect_b32 s0, s0, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s0, s0, 16
@@ -4456,7 +4456,7 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX8-NEXT: v_cmp_nlg_f64_e64 s[0:1], s[2:3], v[0:1]
; GFX8-NEXT: v_cmp_gt_f64_e64 s[12:13], |s[2:3]|, |v[0:1]|
; GFX8-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
-; GFX8-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[8:9], 0
; GFX8-NEXT: s_cselect_b32 s8, 1, -1
; GFX8-NEXT: s_add_i32 s14, s5, s8
; GFX8-NEXT: s_and_b64 s[8:9], s[10:11], exec
@@ -4465,13 +4465,13 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX8-NEXT: s_add_i32 s8, s8, s5
; GFX8-NEXT: s_addk_i32 s8, 0x7fff
; GFX8-NEXT: s_bitset1_b32 s5, 22
-; GFX8-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX8-NEXT: s_cselect_b32 s6, s5, s8
; GFX8-NEXT: v_readfirstlane_b32 s5, v3
; GFX8-NEXT: s_bitcmp1_b32 s5, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], -1, 0
; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
-; GFX8-NEXT: s_and_b64 s[8:9], s[12:13], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[12:13], 0
; GFX8-NEXT: v_cmp_u_f64_e64 s[2:3], s[2:3], s[2:3]
; GFX8-NEXT: s_cselect_b32 s7, 1, -1
; GFX8-NEXT: s_add_i32 s7, s5, s7
@@ -4479,10 +4479,10 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX8-NEXT: s_cselect_b32 s0, s5, s7
; GFX8-NEXT: s_bfe_u32 s1, s0, 0x10010
; GFX8-NEXT: s_add_i32 s1, s1, s0
-; GFX8-NEXT: s_add_i32 s5, s1, 0x7fff
-; GFX8-NEXT: s_or_b32 s7, s0, 0x400000
-; GFX8-NEXT: s_and_b64 s[0:1], s[2:3], exec
-; GFX8-NEXT: s_cselect_b32 s0, s7, s5
+; GFX8-NEXT: s_addk_i32 s1, 0x7fff
+; GFX8-NEXT: s_bitset1_b32 s0, 22
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX8-NEXT: s_cselect_b32 s0, s0, s1
; GFX8-NEXT: s_lshr_b32 s7, s0, 16
; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], 16
; GFX8-NEXT: s_mov_b32 s1, 0x7fff7fff
@@ -4506,7 +4506,7 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX9-NEXT: v_cvt_f64_f32_e32 v[0:1], v3
; GFX9-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[0:1], v[0:1]
; GFX9-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
-; GFX9-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX9-NEXT: s_cselect_b32 s6, 1, -1
; GFX9-NEXT: s_add_i32 s12, s5, s6
; GFX9-NEXT: s_and_b64 s[6:7], s[10:11], exec
@@ -4516,14 +4516,14 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX9-NEXT: s_add_i32 s5, s6, s5
; GFX9-NEXT: v_cmp_gt_f64_e64 s[6:7], |s[0:1]|, |v[0:1]|
; GFX9-NEXT: s_addk_i32 s5, 0x7fff
-; GFX9-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0
; GFX9-NEXT: s_cselect_b32 s5, s10, s5
; GFX9-NEXT: s_lshr_b32 s5, s5, 16
; GFX9-NEXT: v_readfirstlane_b32 s10, v3
; GFX9-NEXT: s_bitcmp1_b32 s10, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], -1, 0
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
-; GFX9-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX9-NEXT: v_cmp_u_f64_e64 s[0:1], s[0:1], s[0:1]
; GFX9-NEXT: s_cselect_b32 s6, 1, -1
; GFX9-NEXT: s_add_i32 s6, s10, s6
@@ -4533,7 +4533,7 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX9-NEXT: s_add_i32 s3, s3, s2
; GFX9-NEXT: s_addk_i32 s3, 0x7fff
; GFX9-NEXT: s_bitset1_b32 s2, 22
-; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, s2, s3
; GFX9-NEXT: s_lshr_b32 s0, s0, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s5
@@ -4557,36 +4557,36 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX10-NEXT: v_cmp_gt_f64_e64 s5, |s[2:3]|, |v[0:1]|
; GFX10-NEXT: v_cmp_u_f64_e64 s3, s[2:3], s[2:3]
; GFX10-NEXT: v_cmp_nlg_f64_e64 s2, s[0:1], v[2:3]
-; GFX10-NEXT: v_cmp_gt_f64_e64 s8, |s[0:1]|, |v[2:3]|
-; GFX10-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: s_or_b32 s7, vcc_lo, s7
-; GFX10-NEXT: s_and_b32 s5, s5, exec_lo
-; GFX10-NEXT: s_cselect_b32 s5, 1, -1
-; GFX10-NEXT: s_add_i32 s5, s6, s5
+; GFX10-NEXT: s_cmp_lg_u32 s5, 0
+; GFX10-NEXT: v_cmp_gt_f64_e64 s5, |s[0:1]|, |v[2:3]|
+; GFX10-NEXT: s_cselect_b32 s8, 1, -1
+; GFX10-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
+; GFX10-NEXT: s_add_i32 s8, s6, s8
; GFX10-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX10-NEXT: s_cselect_b32 s5, s6, s5
-; GFX10-NEXT: v_readfirstlane_b32 s6, v5
-; GFX10-NEXT: s_bfe_u32 s1, s5, 0x10010
-; GFX10-NEXT: s_add_i32 s1, s1, s5
-; GFX10-NEXT: s_bitset1_b32 s5, 22
-; GFX10-NEXT: s_addk_i32 s1, 0x7fff
-; GFX10-NEXT: s_and_b32 s3, s3, exec_lo
-; GFX10-NEXT: s_cselect_b32 s1, s5, s1
+; GFX10-NEXT: s_cselect_b32 s6, s6, s8
+; GFX10-NEXT: v_readfirstlane_b32 s8, v5
+; GFX10-NEXT: s_bfe_u32 s7, s6, 0x10010
+; GFX10-NEXT: s_add_i32 s7, s7, s6
+; GFX10-NEXT: s_bitset1_b32 s6, 22
+; GFX10-NEXT: s_addk_i32 s7, 0x7fff
+; GFX10-NEXT: s_cmp_lg_u32 s3, 0
+; GFX10-NEXT: s_cselect_b32 s1, s6, s7
; GFX10-NEXT: s_lshr_b32 s1, s1, 16
-; GFX10-NEXT: s_bitcmp1_b32 s6, 0
+; GFX10-NEXT: s_bitcmp1_b32 s8, 0
; GFX10-NEXT: s_cselect_b32 s3, -1, 0
; GFX10-NEXT: s_or_b32 s2, s2, s3
-; GFX10-NEXT: s_and_b32 s3, s8, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s5, 0
; GFX10-NEXT: s_cselect_b32 s3, 1, -1
-; GFX10-NEXT: s_add_i32 s3, s6, s3
+; GFX10-NEXT: s_add_i32 s3, s8, s3
; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX10-NEXT: s_cselect_b32 s2, s6, s3
+; GFX10-NEXT: s_cselect_b32 s2, s8, s3
; GFX10-NEXT: s_bfe_u32 s3, s2, 0x10010
; GFX10-NEXT: s_add_i32 s3, s3, s2
; GFX10-NEXT: s_bitset1_b32 s2, 22
; GFX10-NEXT: s_addk_i32 s3, 0x7fff
-; GFX10-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-NEXT: s_cselect_b32 s0, s2, s3
; GFX10-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
@@ -4603,16 +4603,16 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX11-NEXT: v_cvt_f64_f32_e32 v[2:3], v5
; GFX11-NEXT: v_readfirstlane_b32 s7, v4
; GFX11-NEXT: s_bitcmp1_b32 s7, 0
+; GFX11-NEXT: s_cselect_b32 s8, -1, 0
; GFX11-NEXT: v_cmp_nlg_f64_e32 vcc_lo, s[2:3], v[0:1]
; GFX11-NEXT: v_cmp_gt_f64_e64 s5, |s[2:3]|, |v[0:1]|
; GFX11-NEXT: v_cmp_u_f64_e64 s3, s[2:3], s[2:3]
; GFX11-NEXT: v_cmp_nlg_f64_e64 s2, s[0:1], v[2:3]
; GFX11-NEXT: v_cmp_gt_f64_e64 s6, |s[0:1]|, |v[2:3]|
; GFX11-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
-; GFX11-NEXT: s_cselect_b32 s1, -1, 0
; GFX11-NEXT: v_mov_b32_e32 v0, s4
-; GFX11-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX11-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX11-NEXT: s_or_b32 s1, vcc_lo, s8
+; GFX11-NEXT: s_cmp_lg_u32 s5, 0
; GFX11-NEXT: s_cselect_b32 s5, 1, -1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s5, s7, s5
@@ -4623,14 +4623,14 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX11-NEXT: s_add_i32 s5, s5, s1
; GFX11-NEXT: s_bitset1_b32 s1, 22
; GFX11-NEXT: s_addk_i32 s5, 0x7fff
-; GFX11-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
; GFX11-NEXT: s_cselect_b32 s1, s1, s5
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s1, s1, 16
; GFX11-NEXT: s_bitcmp1_b32 s7, 0
; GFX11-NEXT: s_cselect_b32 s3, -1, 0
; GFX11-NEXT: s_or_b32 s2, s2, s3
-; GFX11-NEXT: s_and_b32 s3, s6, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s6, 0
; GFX11-NEXT: s_cselect_b32 s3, 1, -1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s3, s7, s3
@@ -4641,7 +4641,7 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> i
; GFX11-NEXT: s_add_i32 s3, s3, s2
; GFX11-NEXT: s_bitset1_b32 s2, 22
; GFX11-NEXT: s_addk_i32 s3, 0x7fff
-; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_cselect_b32 s0, s2, s3
; GFX11-NEXT: s_lshr_b32 s0, s0, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -4697,13 +4697,13 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2bf16_sign_v2f32(<2 x bfloat> i
; GFX8-NEXT: s_add_i32 s3, s3, s1
; GFX8-NEXT: s_addk_i32 s3, 0x7fff
; GFX8-NEXT: v_cmp_u_f32_e64 s[4:5], s1, s1
-; GFX8-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[4:5], 0
; GFX8-NEXT: s_cselect_b32 s4, s1, s3
; GFX8-NEXT: s_bfe_u32 s1, s2, 0x10010
; GFX8-NEXT: s_add_i32 s1, s1, s2
; GFX8-NEXT: s_addk_i32 s1, 0x7fff
; GFX8-NEXT: v_cmp_u_f32_e64 s[6:7], s2, s2
-; GFX8-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX8-NEXT: s_cselect_b32 s1, s2, s1
; GFX8-NEXT: s_lshr_b32 s5, s1, 16
; GFX8-NEXT: s_lshr_b64 s[2:3], s[4:5], 16
@@ -4721,7 +4721,7 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2bf16_sign_v2f32(<2 x bfloat> i
; GFX9-NEXT: s_or_b32 s4, s2, 0x400000
; GFX9-NEXT: s_add_i32 s5, s3, 0x7fff
; GFX9-NEXT: v_cmp_u_f32_e64 s[2:3], s2, s2
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9-NEXT: s_cselect_b32 s2, s4, s5
; GFX9-NEXT: s_lshr_b32 s4, s2, 16
; GFX9-NEXT: s_bfe_u32 s2, s1, 0x10010
@@ -4729,7 +4729,7 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2bf16_sign_v2f32(<2 x bfloat> i
; GFX9-NEXT: s_or_b32 s5, s1, 0x400000
; GFX9-NEXT: s_add_i32 s6, s2, 0x7fff
; GFX9-NEXT: v_cmp_u_f32_e64 s[2:3], s1, s1
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9-NEXT: s_cselect_b32 s1, s5, s6
; GFX9-NEXT: s_lshr_b32 s1, s1, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4
@@ -4747,15 +4747,15 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2bf16_sign_v2f32(<2 x bfloat> i
; GFX10-NEXT: s_add_i32 s3, s3, s2
; GFX10-NEXT: s_bitset1_b32 s2, 22
; GFX10-NEXT: s_addk_i32 s3, 0x7fff
-; GFX10-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: v_cmp_u_f32_e64 s4, s1, s1
; GFX10-NEXT: s_cselect_b32 s2, s2, s3
; GFX10-NEXT: s_bfe_u32 s3, s1, 0x10010
-; GFX10-NEXT: v_cmp_u_f32_e64 s4, s1, s1
-; GFX10-NEXT: s_add_i32 s3, s3, s1
; GFX10-NEXT: s_lshr_b32 s2, s2, 16
+; GFX10-NEXT: s_add_i32 s3, s3, s1
; GFX10-NEXT: s_bitset1_b32 s1, 22
; GFX10-NEXT: s_addk_i32 s3, 0x7fff
-; GFX10-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
; GFX10-NEXT: s_cselect_b32 s1, s1, s3
; GFX10-NEXT: s_lshr_b32 s1, s1, 16
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s2
@@ -4771,15 +4771,15 @@ define amdgpu_ps i32 @s_copysign_out_v2bf16_mag_v2bf16_sign_v2f32(<2 x bfloat> i
; GFX11-NEXT: s_add_i32 s3, s3, s2
; GFX11-NEXT: s_bitset1_b32 s2, 22
; GFX11-NEXT: s_addk_i32 s3, 0x7fff
-; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s4, 0
+; GFX11-NEXT: v_cmp_u_f32_e64 s4, s1, s1
; GFX11-NEXT: s_cselect_b32 s2, s2, s3
; GFX11-NEXT: s_bfe_u32 s3, s1, 0x10010
-; GFX11-NEXT: v_cmp_u_f32_e64 s4, s1, s1
-; GFX11-NEXT: s_add_i32 s3, s3, s1
; GFX11-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-NEXT: s_add_i32 s3, s3, s1
; GFX11-NEXT: s_bitset1_b32 s1, 22
; GFX11-NEXT: s_addk_i32 s3, 0x7fff
-; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s4, 0
; GFX11-NEXT: s_cselect_b32 s1, s1, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s1, s1, 16
@@ -7337,7 +7337,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f32(float inreg %sign) {
; GFX8-NEXT: s_add_i32 s1, s1, s0
; GFX8-NEXT: s_addk_i32 s1, 0x7fff
; GFX8-NEXT: v_cmp_u_f32_e64 s[2:3], s0, s0
-; GFX8-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: s_cselect_b32 s0, s0, s1
; GFX8-NEXT: s_lshr_b32 s0, s0, 16
; GFX8-NEXT: s_and_b32 s0, s0, 0x8000
@@ -7349,7 +7349,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f32(float inreg %sign) {
; GFX9-NEXT: s_add_i32 s1, s1, s0
; GFX9-NEXT: s_addk_i32 s1, 0x7fff
; GFX9-NEXT: v_cmp_u_f32_e64 s[2:3], s0, s0
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9-NEXT: s_cselect_b32 s0, s0, s1
; GFX9-NEXT: s_lshr_b32 s0, s0, 16
; GFX9-NEXT: s_and_b32 s0, s0, 0x8000
@@ -7361,7 +7361,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f32(float inreg %sign) {
; GFX10-NEXT: v_cmp_u_f32_e64 s2, s0, s0
; GFX10-NEXT: s_add_i32 s1, s1, s0
; GFX10-NEXT: s_addk_i32 s1, 0x7fff
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s2, 0
; GFX10-NEXT: s_cselect_b32 s0, s0, s1
; GFX10-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-NEXT: s_and_b32 s0, s0, 0x8000
@@ -7374,7 +7374,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f32(float inreg %sign) {
; GFX11-NEXT: s_add_i32 s1, s1, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_addk_i32 s1, 0x7fff
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s0, s0, s1
; GFX11-NEXT: s_lshr_b32 s0, s0, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -7471,7 +7471,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f64(double inreg %sign) {
; GFX8-NEXT: v_cmp_gt_f64_e64 s[2:3], |s[0:1]|, |v[0:1]|
; GFX8-NEXT: v_cmp_u_f64_e64 s[0:1], s[0:1], s[0:1]
; GFX8-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX8-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: s_cselect_b32 s2, 1, -1
; GFX8-NEXT: s_add_i32 s7, s6, s2
; GFX8-NEXT: s_and_b64 s[2:3], s[4:5], exec
@@ -7479,7 +7479,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f64(double inreg %sign) {
; GFX8-NEXT: s_bfe_u32 s3, s2, 0x10010
; GFX8-NEXT: s_add_i32 s3, s3, s2
; GFX8-NEXT: s_addk_i32 s3, 0x7fff
-; GFX8-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX8-NEXT: s_cselect_b32 s0, s2, s3
; GFX8-NEXT: s_lshr_b32 s0, s0, 16
; GFX8-NEXT: s_and_b32 s0, s0, 0x8000
@@ -7496,7 +7496,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f64(double inreg %sign) {
; GFX9-NEXT: v_cmp_gt_f64_e64 s[2:3], |s[0:1]|, |v[0:1]|
; GFX9-NEXT: v_cmp_u_f64_e64 s[0:1], s[0:1], s[0:1]
; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9-NEXT: s_cselect_b32 s2, 1, -1
; GFX9-NEXT: s_add_i32 s7, s6, s2
; GFX9-NEXT: s_and_b64 s[2:3], s[4:5], exec
@@ -7504,7 +7504,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f64(double inreg %sign) {
; GFX9-NEXT: s_bfe_u32 s3, s2, 0x10010
; GFX9-NEXT: s_add_i32 s3, s3, s2
; GFX9-NEXT: s_addk_i32 s3, 0x7fff
-; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, s2, s3
; GFX9-NEXT: s_lshr_b32 s0, s0, 16
; GFX9-NEXT: s_and_b32 s0, s0, 0x8000
@@ -7521,7 +7521,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f64(double inreg %sign) {
; GFX10-NEXT: v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
; GFX10-NEXT: s_cselect_b32 s1, -1, 0
; GFX10-NEXT: s_or_b32 s1, vcc_lo, s1
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s2, 0
; GFX10-NEXT: s_cselect_b32 s2, 1, -1
; GFX10-NEXT: s_add_i32 s2, s3, s2
; GFX10-NEXT: s_and_b32 s1, s1, exec_lo
@@ -7529,7 +7529,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f64(double inreg %sign) {
; GFX10-NEXT: s_bfe_u32 s2, s1, 0x10010
; GFX10-NEXT: s_add_i32 s2, s2, s1
; GFX10-NEXT: s_addk_i32 s2, 0x7fff
-; GFX10-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-NEXT: s_cselect_b32 s0, s1, s2
; GFX10-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-NEXT: s_and_b32 s0, s0, 0x8000
@@ -7548,7 +7548,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f64(double inreg %sign) {
; GFX11-NEXT: s_cselect_b32 s3, -1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s3, vcc_lo, s3
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, -1
; GFX11-NEXT: s_add_i32 s2, s1, s2
; GFX11-NEXT: s_and_b32 s3, s3, exec_lo
@@ -7558,7 +7558,7 @@ define amdgpu_ps i32 @s_copysign_bf16_0_f64(double inreg %sign) {
; GFX11-NEXT: s_add_i32 s2, s2, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_addk_i32 s2, 0x7fff
-; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_cselect_b32 s0, s1, s2
; GFX11-NEXT: s_lshr_b32 s0, s0, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -7733,13 +7733,13 @@ define amdgpu_ps i32 @s_copysign_v2bf16_0_v2f32(<2 x float> inreg %sign) {
; GFX8-NEXT: s_add_i32 s2, s2, s0
; GFX8-NEXT: s_add_i32 s4, s2, 0x7fff
; GFX8-NEXT: v_cmp_u_f32_e64 s[2:3], s0, s0
-; GFX8-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: s_cselect_b32 s0, s0, s4
; GFX8-NEXT: s_bfe_u32 s2, s1, 0x10010
; GFX8-NEXT: s_add_i32 s2, s2, s1
; GFX8-NEXT: s_add_i32 s4, s2, 0x7fff
; GFX8-NEXT: v_cmp_u_f32_e64 s[2:3], s1, s1
-; GFX8-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: s_cselect_b32 s1, s1, s4
; GFX8-NEXT: s_lshr_b32 s1, s1, 16
; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 16
@@ -7756,7 +7756,7 @@ define amdgpu_ps i32 @s_copysign_v2bf16_0_v2f32(<2 x float> inreg %sign) {
; GFX9-NEXT: s_or_b32 s4, s1, 0x400000
; GFX9-NEXT: s_add_i32 s5, s2, 0x7fff
; GFX9-NEXT: v_cmp_u_f32_e64 s[2:3], s1, s1
-; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9-NEXT: s_cselect_b32 s1, s4, s5
; GFX9-NEXT: s_lshr_b32 s2, s1, 16
; GFX9-NEXT: s_bfe_u32 s1, s0, 0x10010
@@ -7764,7 +7764,7 @@ define amdgpu_ps i32 @s_copysign_v2bf16_0_v2f32(<2 x float> inreg %sign) {
; GFX9-NEXT: s_or_b32 s3, s0, 0x400000
; GFX9-NEXT: s_add_i32 s4, s1, 0x7fff
; GFX9-NEXT: v_cmp_u_f32_e64 s[0:1], s0, s0
-; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
; GFX9-NEXT: s_cselect_b32 s0, s3, s4
; GFX9-NEXT: s_lshr_b32 s0, s0, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
@@ -7778,15 +7778,15 @@ define amdgpu_ps i32 @s_copysign_v2bf16_0_v2f32(<2 x float> inreg %sign) {
; GFX10-NEXT: s_add_i32 s2, s2, s1
; GFX10-NEXT: s_bitset1_b32 s1, 22
; GFX10-NEXT: s_addk_i32 s2, 0x7fff
-; GFX10-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s3, 0
+; GFX10-NEXT: v_cmp_u_f32_e64 s3, s0, s0
; GFX10-NEXT: s_cselect_b32 s1, s1, s2
; GFX10-NEXT: s_bfe_u32 s2, s0, 0x10010
-; GFX10-NEXT: v_cmp_u_f32_e64 s3, s0, s0
-; GFX10-NEXT: s_add_i32 s2, s2, s0
; GFX10-NEXT: s_lshr_b32 s1, s1, 16
+; GFX10-NEXT: s_add_i32 s2, s2, s0
; GFX10-NEXT: s_bitset1_b32 s0, 22
; GFX10-NEXT: s_addk_i32 s2, 0x7fff
-; GFX10-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s3, 0
; GFX10-NEXT: s_cselect_b32 s0, s0, s2
; GFX10-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
@@ -7800,15 +7800,15 @@ define amdgpu_ps i32 @s_copysign_v2bf16_0_v2f32(<2 x float> inreg %sign) {
; GFX11-NEXT: s_add_i32 s2, s2, s1
; GFX11-NEXT: s_bitset1_b32 s1, 22
; GFX11-NEXT: s_addk_i32 s2, 0x7fff
-; GFX11-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
+; GFX11-NEXT: v_cmp_u_f32_e64 s3, s0, s0
; GFX11-NEXT: s_cselect_b32 s1, s1, s2
; GFX11-NEXT: s_bfe_u32 s2, s0, 0x10010
-; GFX11-NEXT: v_cmp_u_f32_e64 s3, s0, s0
-; GFX11-NEXT: s_add_i32 s2, s2, s0
; GFX11-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-NEXT: s_add_i32 s2, s2, s0
; GFX11-NEXT: s_bitset1_b32 s0, 22
; GFX11-NEXT: s_addk_i32 s2, 0x7fff
-; GFX11-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s3, 0
; GFX11-NEXT: s_cselect_b32 s0, s0, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s0, s0, 16
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp-wave32.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp-wave32.mir
new file mode 100644
index 0000000000000..cda951d74d8f9
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp-wave32.mir
@@ -0,0 +1,47 @@
+# RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize32 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s
+
+# Wave32 version of fix-sgpr-copies-scc-cmp.mir, which uses S_CMP_LG_U32.
+
+---
+name: vcmp_to_scc
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: vcmp_to_scc
+ ; CHECK: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ ; CHECK-NEXT: S_CMP_LG_U32 [[CMP]], 0, implicit-def $scc
+ %0:sreg_32_xm0_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ $scc = COPY %0
+ %1:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %1
+...
+
+---
+name: exec_to_scc
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: exec_to_scc
+ ; CHECK: S_CMP_LG_U32 $exec_lo, 0, implicit-def $scc
+ $scc = COPY $exec_lo
+ %0:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %0
+...
+
+# Negative test: nothing is known about the lane mask, so it must be masked
+# with EXEC.
+---
+name: unknown_mask_to_scc
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; CHECK-LABEL: name: unknown_mask_to_scc
+ ; CHECK: [[MASK:%[0-9]+]]:sreg_32_xm0_xexec = COPY $sgpr0
+ ; CHECK-NEXT: {{%[0-9]+}}:sreg_32 = S_AND_B32 [[MASK]], $exec_lo, implicit-def $scc
+ %0:sreg_32_xm0_xexec = COPY $sgpr0
+ $scc = COPY %0
+ %1:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %1
+...
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp.mir
new file mode 100644
index 0000000000000..a00e5ac59daa6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp.mir
@@ -0,0 +1,224 @@
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck -check-prefixes=CHECK,GFX9 %s
+# RUN: llc -mtriple=amdgpu7.00 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck -check-prefixes=CHECK,GFX7 %s
+
+# A copy of a lane mask to SCC is lowered to an AND with EXEC, whose only
+# purpose is to define SCC. When the lane mask already has 0 in the bits of
+# all inactive lanes, S_CMP computes the same SCC without needing a
+# destination register.
+
+---
+name: vcmp_to_scc
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: vcmp_to_scc
+ ; CHECK: [[CMP:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ ; GFX9-NEXT: S_CMP_LG_U64 [[CMP]], 0, implicit-def $scc
+ ; GFX7-NEXT: {{%[0-9]+}}:sreg_64 = S_AND_B64 [[CMP]], $exec, implicit-def $scc
+ %0:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ $scc = COPY %0
+ %1:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %1
+...
+
+# Negative test: nothing is known about the lane mask, so it must be masked
+# with EXEC.
+---
+name: unknown_mask_to_scc
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; CHECK-LABEL: name: unknown_mask_to_scc
+ ; CHECK: [[MASK:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: {{%[0-9]+}}:sreg_64 = S_AND_B64 [[MASK]], $exec, implicit-def $scc
+ %0:sreg_64_xexec = COPY $sgpr0_sgpr1
+ $scc = COPY %0
+ %1:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %1
+...
+
+# Negative test: a register that is only ever read as undef has no defining
+# instruction at all, so nothing is known about the lane mask.
+---
+name: undef_mask_to_scc
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: undef_mask_to_scc
+ ; CHECK: {{%[0-9]+}}:sreg_64 = S_AND_B64 undef %{{[0-9]+}}:sreg_64_xexec, $exec, implicit-def $scc
+ $scc = COPY undef %0:sreg_64_xexec
+ %1:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %1
+...
+
+# An undef operand of an AND is not masked by EXEC, but the other operand is,
+# which is enough.
+---
+name: undef_and_operand
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: undef_and_operand
+ ; CHECK: [[CMP:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:sreg_64_xexec = S_AND_B64 undef %{{[0-9]+}}:sreg_64_xexec, [[CMP]], implicit-def dead $scc
+ ; GFX9-NEXT: S_CMP_LG_U64 [[AND]], 0, implicit-def $scc
+ ; GFX7-NEXT: {{%[0-9]+}}:sreg_64 = S_AND_B64 [[AND]], $exec, implicit-def $scc
+ %0:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ %2:sreg_64_xexec = S_AND_B64 undef %1:sreg_64_xexec, %0, implicit-def dead $scc
+ $scc = COPY %2
+ %3:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %3
+...
+
+# EXEC itself is trivially masked by EXEC.
+---
+name: exec_to_scc
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: exec_to_scc
+ ; GFX9: S_CMP_LG_U64 $exec, 0, implicit-def $scc
+ ; GFX7: {{%[0-9]+}}:sreg_64 = S_AND_B64 $exec, $exec, implicit-def $scc
+ $scc = COPY $exec
+ %0:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %0
+...
+
+# Negative test: the V_CMP is in a
diff erent block from the copy to SCC, so it
+# may have executed under a
diff erent EXEC mask.
+---
+name: vcmp_other_block
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: vcmp_other_block
+ ; CHECK: [[CMP:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ ; CHECK: bb.1:
+ ; CHECK-NEXT: {{%[0-9]+}}:sreg_64 = S_AND_B64 [[CMP]], $exec, implicit-def $scc
+ bb.0:
+ successors: %bb.1
+ liveins: $vgpr0, $vgpr1
+ %0:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ $scc = COPY %0
+ %1:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %1
+...
+
+# The walk looks through a chain of COPYs.
+---
+name: copy_chain
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: copy_chain
+ ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY %4
+ ; GFX9-NEXT: S_CMP_LG_U64 [[COPY]], 0, implicit-def $scc
+ ; GFX7-NEXT: {{%[0-9]+}}:sreg_64 = S_AND_B64 [[COPY]], $exec, implicit-def $scc
+ %0:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ %1:sreg_64 = COPY %0
+ %2:sreg_64 = COPY %1
+ %3:sreg_64 = COPY %2
+ %4:sreg_64 = COPY %3
+ %5:sreg_64 = COPY %4
+ $scc = COPY %5
+ %6:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %6
+...
+
+# OR needs both operands to be masked.
+---
+name: or_both_masked
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: or_both_masked
+ ; CHECK: [[OR:%[0-9]+]]:sreg_64 = S_OR_B64 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def dead $scc
+ ; GFX9-NEXT: S_CMP_LG_U64 [[OR]], 0, implicit-def $scc
+ ; GFX7-NEXT: {{%[0-9]+}}:sreg_64 = S_AND_B64 [[OR]], $exec, implicit-def $scc
+ %0:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ %1:sreg_64_xexec = V_CMP_EQ_U32_e64 $vgpr0, $vgpr1, implicit $exec
+ %2:sreg_64 = S_OR_B64 %0, %1, implicit-def dead $scc
+ $scc = COPY %2
+ %3:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %3
+...
+
+# Negative test: OR with only one masked operand.
+---
+name: or_one_masked
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
+ ; CHECK-LABEL: name: or_one_masked
+ ; CHECK: [[OR:%[0-9]+]]:sreg_64 = S_OR_B64 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def dead $scc
+ ; CHECK-NEXT: {{%[0-9]+}}:sreg_64 = S_AND_B64 [[OR]], $exec, implicit-def $scc
+ %0:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ %1:sreg_64 = COPY $sgpr0_sgpr1
+ %2:sreg_64 = S_OR_B64 %0, %1, implicit-def dead $scc
+ $scc = COPY %2
+ %3:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %3
+...
+
+# Negative test: XOR with only one masked operand.
+---
+name: xor_one_masked
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
+ ; CHECK-LABEL: name: xor_one_masked
+ ; CHECK: [[XOR:%[0-9]+]]:sreg_64 = S_XOR_B64 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def dead $scc
+ ; CHECK-NEXT: {{%[0-9]+}}:sreg_64 = S_AND_B64 [[XOR]], $exec, implicit-def $scc
+ %0:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ %1:sreg_64 = COPY $sgpr0_sgpr1
+ %2:sreg_64 = S_XOR_B64 %1, %0, implicit-def dead $scc
+ $scc = COPY %2
+ %3:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %3
+...
+
+# ANDN2 only needs its first operand to be masked.
+---
+name: andn2_first_masked
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
+ ; CHECK-LABEL: name: andn2_first_masked
+ ; CHECK: [[ANDN2:%[0-9]+]]:sreg_64 = S_ANDN2_B64 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def dead $scc
+ ; GFX9-NEXT: S_CMP_LG_U64 [[ANDN2]], 0, implicit-def $scc
+ ; GFX7-NEXT: {{%[0-9]+}}:sreg_64 = S_AND_B64 [[ANDN2]], $exec, implicit-def $scc
+ %0:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ %1:sreg_64 = COPY $sgpr0_sgpr1
+ %2:sreg_64 = S_ANDN2_B64 %0, %1, implicit-def dead $scc
+ $scc = COPY %2
+ %3:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %3
+...
+
+# Negative test: ANDN2 with only its second operand masked.
+---
+name: andn2_second_masked
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
+ ; CHECK-LABEL: name: andn2_second_masked
+ ; CHECK: [[ANDN2:%[0-9]+]]:sreg_64 = S_ANDN2_B64 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def dead $scc
+ ; CHECK-NEXT: {{%[0-9]+}}:sreg_64 = S_AND_B64 [[ANDN2]], $exec, implicit-def $scc
+ %0:sreg_64_xexec = V_CMP_LT_I32_e64 $vgpr0, $vgpr1, implicit $exec
+ %1:sreg_64 = COPY $sgpr0_sgpr1
+ %2:sreg_64 = S_ANDN2_B64 %1, %0, implicit-def dead $scc
+ $scc = COPY %2
+ %3:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+ S_ENDPGM 0, implicit %3
+...
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index 384b0a5ff90a6..7ba8c78714eb0 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -624,12 +624,12 @@ define amdgpu_ps double @fneg_fadd_0_f64(double inreg %tmp2, double inreg %tmp6,
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 0
; VI-NEXT: v_cmp_ngt_f64_e32 vcc, s[0:1], v[0:1]
; VI-NEXT: v_xor_b32_e32 v3, 0x80000000, v1
+; VI-NEXT: s_mov_b32 s0, 0
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; VI-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
-; VI-NEXT: s_mov_b32 s0, 0
; VI-NEXT: ; return to shader part epilog
.entry:
%tmp7 = fdiv double 1.000000e+00, %tmp6
@@ -691,12 +691,12 @@ define amdgpu_ps double @fneg_fadd_0_f64_nsz(double inreg %tmp2, double inreg %t
; VI-NEXT: s_brev_b32 s3, 1
; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[2:3]
; VI-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
+; VI-NEXT: s_mov_b32 s0, 0
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; VI-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
-; VI-NEXT: s_mov_b32 s0, 0
; VI-NEXT: ; return to shader part epilog
.entry:
%tmp7 = fdiv double 1.000000e+00, %tmp6
@@ -749,12 +749,12 @@ define amdgpu_ps double @fneg_fadd_0_nsz_f64(double inreg %tmp2, double inreg %t
; VI-NEXT: v_mov_b32_e32 v3, s0
; VI-NEXT: v_mul_f64 v[0:1], v[0:1], s[2:3]
; VI-NEXT: v_cmp_nlt_f64_e64 vcc, -v[0:1], s[0:1]
+; VI-NEXT: s_mov_b32 s0, 0
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; VI-NEXT: v_cmp_nlt_f64_e32 vcc, 0, v[0:1]
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s1, 0, 0x7ff80000
-; VI-NEXT: s_mov_b32 s0, 0
; VI-NEXT: ; return to shader part epilog
.entry:
%tmp7 = fdiv afn double 1.000000e+00, %tmp6
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
index 861a50a110c59..3dc817eb1c884 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
@@ -1674,32 +1674,49 @@ define amdgpu_kernel void @multiple_uses_fneg_select_f64(double %x, double %y, i
}
define amdgpu_kernel void @fnge_select_f32_multi_use_regression(float %.i2369) {
-; GCN-LABEL: fnge_select_f32_multi_use_regression:
-; GCN: ; %bb.0: ; %.entry
-; GCN-NEXT: s_load_dword s0, s[8:9], 0x0
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_cmp_nlt_f32_e64 s[0:1], s0, 0
-; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GCN-NEXT: s_cselect_b32 s2, 1, 0
-; GCN-NEXT: v_cmp_gt_f32_e64 s[0:1], s2, 0
-; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GCN-NEXT: s_cselect_b32 s0, s2, 0
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mul_f32_e64 v0, -s2, v0
-; GCN-NEXT: v_cmp_le_f32_e32 vcc, 0, v0
-; GCN-NEXT: s_and_b64 vcc, exec, vcc
-; GCN-NEXT: s_endpgm
+;
+; GFX7-LABEL: fnge_select_f32_multi_use_regression:
+; GFX7: ; %bb.0: ; %.entry
+; GFX7-NEXT: s_load_dword s0, s[8:9], 0x0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_cmp_nlt_f32_e64 s[0:1], s0, 0
+; GFX7-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX7-NEXT: s_cselect_b32 s2, 1, 0
+; GFX7-NEXT: v_cmp_gt_f32_e64 s[0:1], s2, 0
+; GFX7-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; GFX7-NEXT: s_cselect_b32 s0, s2, 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-NEXT: v_mul_f32_e64 v0, -s2, v0
+; GFX7-NEXT: v_cmp_le_f32_e32 vcc, 0, v0
+; GFX7-NEXT: s_and_b64 vcc, exec, vcc
+; GFX7-NEXT: s_endpgm
+;
+; GFX9-LABEL: fnge_select_f32_multi_use_regression:
+; GFX9: ; %bb.0: ; %.entry
+; GFX9-NEXT: s_load_dword s0, s[8:9], 0x0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_cmp_nlt_f32_e64 s[0:1], s0, 0
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: v_cmp_gt_f32_e64 s[0:1], s2, 0
+; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT: s_cselect_b32 s0, s2, 0
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-NEXT: v_mul_f32_e64 v0, -s2, v0
+; GFX9-NEXT: v_cmp_le_f32_e32 vcc, 0, v0
+; GFX9-NEXT: s_and_b64 vcc, exec, vcc
+; GFX9-NEXT: s_endpgm
;
; GFX11-LABEL: fnge_select_f32_multi_use_regression:
; GFX11: ; %bb.0: ; %.entry
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, s0, 0
-; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cmp_gt_f32_e64 s1, s0, 0
-; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
; GFX11-NEXT: s_cselect_b32 s1, s0, 0
; GFX11-NEXT: v_mul_f32_e64 v0, -s0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/fp-classify.ll b/llvm/test/CodeGen/AMDGPU/fp-classify.ll
index 6811f71f14b25..a357142925b87 100644
--- a/llvm/test/CodeGen/AMDGPU/fp-classify.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp-classify.ll
@@ -30,7 +30,7 @@ define amdgpu_kernel void @test_isinf_pattern(ptr addrspace(1) nocapture %out, f
; VI-NEXT: v_mov_b32_e32 v0, 0x204
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_class_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -45,7 +45,7 @@ define amdgpu_kernel void @test_isinf_pattern(ptr addrspace(1) nocapture %out, f
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x204
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -81,7 +81,7 @@ define amdgpu_kernel void @test_not_isinf_pattern_0(ptr addrspace(1) nocapture %
; VI-NEXT: v_mov_b32_e32 v0, 0x7f800000
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_nlg_f32_e64 s[2:3], |s2|, v0
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -96,7 +96,7 @@ define amdgpu_kernel void @test_not_isinf_pattern_0(ptr addrspace(1) nocapture %
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_nlg_f32_e64 s2, 0x7f800000, |s2|
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -167,7 +167,7 @@ define amdgpu_kernel void @test_isfinite_pattern_0(ptr addrspace(1) nocapture %o
; VI-NEXT: v_mov_b32_e32 v0, 0x1f8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_class_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -182,7 +182,7 @@ define amdgpu_kernel void @test_isfinite_pattern_0(ptr addrspace(1) nocapture %o
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x1f8
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -220,7 +220,7 @@ define amdgpu_kernel void @test_isfinite_pattern_1(ptr addrspace(1) nocapture %o
; VI-NEXT: v_mov_b32_e32 v0, 0x1f8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_class_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -235,7 +235,7 @@ define amdgpu_kernel void @test_isfinite_pattern_1(ptr addrspace(1) nocapture %o
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x1f8
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -270,7 +270,7 @@ define amdgpu_kernel void @test_isfinite_not_pattern_0(ptr addrspace(1) nocaptur
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_o_f32_e64 s[2:3], s2, s2
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -285,7 +285,7 @@ define amdgpu_kernel void @test_isfinite_not_pattern_0(ptr addrspace(1) nocaptur
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_o_f32_e64 s2, s2, s2
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -328,7 +328,6 @@ define amdgpu_kernel void @test_isfinite_not_pattern_1(ptr addrspace(1) nocaptur
; VI-NEXT: v_cmp_o_f32_e64 s[2:3], s6, s6
; VI-NEXT: v_cmp_neq_f32_e32 vcc, s6, v0
; VI-NEXT: s_and_b64 s[2:3], s[2:3], vcc
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -345,9 +344,8 @@ define amdgpu_kernel void @test_isfinite_not_pattern_1(ptr addrspace(1) nocaptur
; GFX11-NEXT: v_cmp_o_f32_e64 s3, s2, s2
; GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x7f800000, s2
; GFX11-NEXT: s_and_b32 s2, s3, s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
@@ -387,7 +385,6 @@ define amdgpu_kernel void @test_isfinite_not_pattern_2(ptr addrspace(1) nocaptur
; VI-NEXT: v_cmp_o_f32_e64 s[4:5], s2, s2
; VI-NEXT: v_cmp_neq_f32_e64 s[2:3], |s3|, v0
; VI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -402,9 +399,8 @@ define amdgpu_kernel void @test_isfinite_not_pattern_2(ptr addrspace(1) nocaptur
; GFX11-NEXT: v_cmp_o_f32_e64 s2, s2, s2
; GFX11-NEXT: v_cmp_neq_f32_e64 s3, 0x7f800000, |s3|
; GFX11-NEXT: s_and_b32 s2, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
@@ -445,7 +441,6 @@ define amdgpu_kernel void @test_isfinite_not_pattern_3(ptr addrspace(1) nocaptur
; VI-NEXT: v_cmp_u_f32_e64 s[2:3], s6, s6
; VI-NEXT: v_cmp_neq_f32_e64 s[4:5], |s6|, v0
; VI-NEXT: s_and_b64 s[2:3], s[2:3], s[4:5]
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -462,9 +457,8 @@ define amdgpu_kernel void @test_isfinite_not_pattern_3(ptr addrspace(1) nocaptur
; GFX11-NEXT: v_cmp_u_f32_e64 s3, s2, s2
; GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x7f800000, |s2|
; GFX11-NEXT: s_and_b32 s2, s3, s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
@@ -500,7 +494,7 @@ define amdgpu_kernel void @test_isfinite_pattern_4(ptr addrspace(1) nocapture %o
; VI-NEXT: v_mov_b32_e32 v0, 0x1f8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_class_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -515,7 +509,7 @@ define amdgpu_kernel void @test_isfinite_pattern_4(ptr addrspace(1) nocapture %o
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x1f8
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -553,7 +547,7 @@ define amdgpu_kernel void @test_isfinite_pattern_4_commute_and(ptr addrspace(1)
; VI-NEXT: v_mov_b32_e32 v0, 0x1f8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_class_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -568,7 +562,7 @@ define amdgpu_kernel void @test_isfinite_pattern_4_commute_and(ptr addrspace(1)
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x1f8
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -614,7 +608,6 @@ define amdgpu_kernel void @test_not_isfinite_pattern_4_wrong_ord_test(ptr addrsp
; VI-NEXT: v_cmp_class_f32_e32 vcc, s1, v0
; VI-NEXT: v_cmp_o_f32_e64 s[0:1], s1, v1
; VI-NEXT: s_and_b64 s[0:1], s[0:1], vcc
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; VI-NEXT: s_cselect_b32 s0, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
@@ -632,9 +625,8 @@ define amdgpu_kernel void @test_not_isfinite_pattern_4_wrong_ord_test(ptr addrsp
; GFX11-NEXT: v_cmp_o_f32_e64 s3, s2, s3
; GFX11-NEXT: v_cmp_class_f32_e64 s2, s2, 0x1f8
; GFX11-NEXT: s_and_b32 s2, s3, s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
@@ -671,7 +663,7 @@ define amdgpu_kernel void @test_isinf_pattern_f16(ptr addrspace(1) nocapture %ou
; VI-NEXT: v_mov_b32_e32 v0, 0x204
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_class_f16_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -686,7 +678,7 @@ define amdgpu_kernel void @test_isinf_pattern_f16(ptr addrspace(1) nocapture %ou
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_class_f16_e64 s2, s2, 0x204
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -726,7 +718,7 @@ define amdgpu_kernel void @test_isfinite_pattern_0_f16(ptr addrspace(1) nocaptur
; VI-NEXT: v_mov_b32_e32 v0, 0x1f8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_class_f16_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -741,7 +733,7 @@ define amdgpu_kernel void @test_isfinite_pattern_0_f16(ptr addrspace(1) nocaptur
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_class_f16_e64 s2, s2, 0x1f8
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -780,7 +772,7 @@ define amdgpu_kernel void @test_isfinite_pattern_4_f16(ptr addrspace(1) nocaptur
; VI-NEXT: v_mov_b32_e32 v0, 0x1f8
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_class_f16_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s2, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
@@ -795,7 +787,7 @@ define amdgpu_kernel void @test_isfinite_pattern_4_f16(ptr addrspace(1) nocaptur
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_class_f16_e64 s2, s2, 0x1f8
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
diff --git a/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll b/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
index 2618c670b8c23..d2eaf783f9584 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
@@ -1110,7 +1110,7 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i1(ptr addrspace(1) %out, float %in
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, s6
-; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
@@ -1123,7 +1123,7 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i1(ptr addrspace(1) %out, float %in
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_eq_f32_e64 s2, -1.0, s2
-; GFX11-SDAG-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-SDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-SDAG-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -1193,7 +1193,7 @@ define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(ptr addrspace(1) %out, floa
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], -1.0, |s6|
-; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
@@ -1206,7 +1206,7 @@ define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(ptr addrspace(1) %out, floa
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_eq_f32_e64 s2, -1.0, |s2|
-; GFX11-SDAG-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-SDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-SDAG-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
diff --git a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
index 1c198e33697f1..908a991e7fdc6 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
@@ -882,7 +882,7 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i1(ptr addrspace(1) %out, float %in
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, s6
-; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
@@ -895,7 +895,7 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i1(ptr addrspace(1) %out, float %in
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_eq_f32_e64 s2, 1.0, s2
-; GFX11-SDAG-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-SDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-SDAG-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -965,7 +965,7 @@ define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(ptr addrspace(1) %out, floa
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, |s6|
-; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
@@ -978,7 +978,7 @@ define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(ptr addrspace(1) %out, floa
; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: v_cmp_eq_f32_e64 s2, 1.0, |s2|
-; GFX11-SDAG-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-SDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-SDAG-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
diff --git a/llvm/test/CodeGen/AMDGPU/fpow.ll b/llvm/test/CodeGen/AMDGPU/fpow.ll
index 59976252bdc74..26600bda484ec 100644
--- a/llvm/test/CodeGen/AMDGPU/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/fpow.ll
@@ -3542,7 +3542,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v1
-; GFX8-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
; GFX8-NEXT: s_cselect_b32 s1, 32, 0
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
@@ -3581,7 +3581,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v1
-; GFX9-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
; GFX9-NEXT: s_cselect_b32 s1, 32, 0
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
@@ -3620,7 +3620,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v1
-; GFX90A-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX90A-NEXT: s_cmp_lg_u64 vcc, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42000000
; GFX90A-NEXT: s_cselect_b32 s1, 32, 0
; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
@@ -3660,8 +3660,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0|
; GFX10-NEXT: v_trunc_f32_e32 v5, v0
; GFX10-NEXT: v_cmp_class_f32_e64 s2, s0, 24
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1
-; GFX10-NEXT: s_and_b32 s1, s1, exec_lo
; GFX10-NEXT: s_cselect_b32 s1, 32, 0
; GFX10-NEXT: v_ldexp_f32 v2, |s0|, s1
; GFX10-NEXT: v_cmp_eq_f32_e64 s1, v5, v0
@@ -3690,34 +3690,33 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, |s0|
; GFX11-NEXT: v_trunc_f32_e32 v5, v0
; GFX11-NEXT: v_cmp_class_f32_e64 s2, s0, 24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s1
-; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
; GFX11-NEXT: s_cselect_b32 s1, 32, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_ldexp_f32 v2, |s0|, s1
; GFX11-NEXT: v_cmp_eq_f32_e64 s1, v5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v2, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v1, v2, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
; GFX11-NEXT: v_mul_f32_e32 v2, 0.5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v2
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
; GFX11-NEXT: s_and_b32 vcc_lo, s1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v1, s0
; GFX11-NEXT: v_cmp_neq_f32_e64 s0, v5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-NEXT: s_and_b32 s0, s2, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
@@ -3986,7 +3985,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0
-; GFX8-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000
; GFX8-NEXT: s_cselect_b32 s2, 32, 0
; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
@@ -4003,7 +4002,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
-; GFX8-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: v_ldexp_f32 v0, v0, s2
@@ -4025,7 +4024,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0
-; GFX9-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000
; GFX9-NEXT: s_cselect_b32 s2, 32, 0
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
@@ -4042,7 +4041,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
-; GFX9-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_ldexp_f32 v0, v0, s2
@@ -4064,7 +4063,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX90A-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0
-; GFX90A-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX90A-NEXT: s_cmp_lg_u64 vcc, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, 0x42000000
; GFX90A-NEXT: s_cselect_b32 s2, 32, 0
; GFX90A-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
@@ -4081,7 +4080,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX90A-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX90A-NEXT: v_add_f32_e32 v0, v0, v1
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
-; GFX90A-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX90A-NEXT: s_cmp_lg_u64 vcc, 0
; GFX90A-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX90A-NEXT: v_mov_b32_e32 v1, s0
; GFX90A-NEXT: v_ldexp_f32 v0, v0, s2
@@ -4104,8 +4103,8 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0|
; GFX10-NEXT: v_trunc_f32_e32 v3, s1
; GFX10-NEXT: v_cmp_class_f32_e64 s3, s0, 24
+; GFX10-NEXT: s_cmp_lg_u32 s2, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s2
-; GFX10-NEXT: s_and_b32 s2, s2, exec_lo
; GFX10-NEXT: s_cselect_b32 s2, 32, 0
; GFX10-NEXT: v_ldexp_f32 v1, |s0|, s2
; GFX10-NEXT: v_log_f32_e32 v1, v1
@@ -4113,7 +4112,7 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX10-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_f32_e64 v1, s1, 0.5
@@ -4135,31 +4134,31 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, |s0|
; GFX11-NEXT: v_trunc_f32_e32 v3, s1
; GFX11-NEXT: v_cmp_class_f32_e64 s3, s0, 24
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s2
-; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-NEXT: s_cselect_b32 s2, 32, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_ldexp_f32 v1, |s0|, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11-NEXT: v_mul_f32_e64 v1, s1, 0.5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_trunc_f32_e32 v2, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_lg_f32_e32 vcc_lo, v2, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
; GFX11-NEXT: v_cmp_eq_f32_e64 s2, s1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v0, s0
; GFX11-NEXT: v_cmp_neq_f32_e64 s0, s1, v3
; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
index 66b2ba892182a..c25be90e04d38 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
@@ -709,26 +709,26 @@ define i64 @test_s_signed_i64_f32(float inreg %f) nounwind {
; GFX9-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-NEXT: s_mov_b32 s7, s6
; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
-; GFX9-NEXT: s_sub_u32 s7, s4, s6
+; GFX9-NEXT: s_sub_u32 s4, s4, s6
; GFX9-NEXT: v_mov_b32_e32 v0, 0xdf000000
-; GFX9-NEXT: s_subb_u32 s10, s5, s6
+; GFX9-NEXT: s_subb_u32 s8, s5, s6
; GFX9-NEXT: v_cmp_nge_f32_e32 vcc, s16, v0
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_mov_b32_e32 v0, 0x5effffff
+; GFX9-NEXT: s_cselect_b32 s6, 0, s4
; GFX9-NEXT: v_cmp_gt_f32_e64 s[4:5], s16, v0
-; GFX9-NEXT: s_cselect_b32 s8, 0, s7
-; GFX9-NEXT: s_and_b64 s[6:7], s[4:5], exec
+; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9-NEXT: s_cselect_b32 s9, -1, s6
; GFX9-NEXT: v_cmp_u_f32_e64 s[6:7], s16, s16
-; GFX9-NEXT: s_cselect_b32 s11, -1, s8
-; GFX9-NEXT: s_and_b64 s[8:9], s[6:7], exec
-; GFX9-NEXT: s_cselect_b32 s11, 0, s11
-; GFX9-NEXT: s_and_b64 s[8:9], vcc, exec
-; GFX9-NEXT: s_cselect_b32 s8, 0x80000000, s10
-; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
-; GFX9-NEXT: s_cselect_b32 s8, 0x7fffffff, s8
-; GFX9-NEXT: s_and_b64 s[4:5], s[6:7], exec
-; GFX9-NEXT: s_cselect_b32 s4, 0, s8
-; GFX9-NEXT: v_mov_b32_e32 v0, s11
+; GFX9-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9-NEXT: s_cselect_b32 s9, 0, s9
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_cselect_b32 s8, 0x80000000, s8
+; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9-NEXT: s_cselect_b32 s4, 0x7fffffff, s8
+; GFX9-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9-NEXT: s_cselect_b32 s4, 0, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s9
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -736,33 +736,33 @@ define i64 @test_s_signed_i64_f32(float inreg %f) nounwind {
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_trunc_f32_e32 v0, s0
-; GFX11-NEXT: v_cmp_lt_f32_e64 s6, 0x5effffff, s0
; GFX11-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|
; GFX11-NEXT: v_readfirstlane_b32 s1, v0
; GFX11-NEXT: v_floor_f32_e32 v1, v1
; GFX11-NEXT: s_ashr_i32 s4, s1, 31
; GFX11-NEXT: v_cmp_nle_f32_e64 s1, 0xdf000000, s0
; GFX11-NEXT: s_mov_b32 s5, s4
-; GFX11-NEXT: v_cmp_u_f32_e64 s0, s0, s0
; GFX11-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0|
; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
+; GFX11-NEXT: v_cmp_lt_f32_e64 s5, 0x5effffff, s0
; GFX11-NEXT: s_sub_u32 s2, s2, s4
; GFX11-NEXT: s_subb_u32 s3, s3, s4
-; GFX11-NEXT: s_and_b32 s4, s1, exec_lo
+; GFX11-NEXT: v_cmp_u_f32_e64 s0, s0, s0
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
; GFX11-NEXT: s_cselect_b32 s2, 0, s2
-; GFX11-NEXT: s_and_b32 s4, s6, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s5, 0
; GFX11-NEXT: s_cselect_b32 s2, -1, s2
-; GFX11-NEXT: s_and_b32 s4, s0, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_cselect_b32 s2, 0, s2
-; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
; GFX11-NEXT: s_cselect_b32 s1, 0x80000000, s3
-; GFX11-NEXT: s_and_b32 s3, s6, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s5, 0
; GFX11-NEXT: s_cselect_b32 s1, 0x7fffffff, s1
-; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_cselect_b32 s0, 0, s1
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi.f16.ll b/llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
index 5faac8df0e028..9860b4c64560c 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
@@ -605,7 +605,7 @@ define amdgpu_kernel void @fptosi_f16_to_i1(ptr addrspace(1) %out, half %in) {
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_eq_f16_e64 s[4:5], -1.0, s6
-; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
@@ -619,7 +619,7 @@ define amdgpu_kernel void @fptosi_f16_to_i1(ptr addrspace(1) %out, half %in) {
; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_f16_e64 s2, -1.0, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -635,7 +635,7 @@ define amdgpu_kernel void @fptosi_f16_to_i1(ptr addrspace(1) %out, half %in) {
; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_eq_f16_e64 s2, -1.0, s2
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui.f16.ll b/llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
index 097d89b9e0ce1..60c09cfb8dff9 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
@@ -602,7 +602,7 @@ define amdgpu_kernel void @fptoui_f16_to_i1(ptr addrspace(1) %out, half %in) {
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_cmp_eq_f16_e64 s[4:5], 1.0, s6
-; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
@@ -616,7 +616,7 @@ define amdgpu_kernel void @fptoui_f16_to_i1(ptr addrspace(1) %out, half %in) {
; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_f16_e64 s2, 1.0, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
@@ -632,7 +632,7 @@ define amdgpu_kernel void @fptoui_f16_to_i1(ptr addrspace(1) %out, half %in) {
; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_eq_f16_e64 s2, 1.0, s2
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index e54926f38c731..f202227662c40 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -18166,12 +18166,12 @@ define amdgpu_kernel void @frem_v2f64_const_zero_num(ptr addrspace(1) %out, ptr
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cmp_nlg_f64_e32 vcc, 0, v[0:1]
; VI-NEXT: v_mov_b32_e32 v0, 0
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: v_cmp_nlg_f64_e32 vcc, 0, v[2:3]
; VI-NEXT: s_cselect_b32 s2, 0x7ff80000, 0
; VI-NEXT: v_mov_b32_e32 v1, s2
; VI-NEXT: v_mov_b32_e32 v2, v0
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, 0x7ff80000, 0
; VI-NEXT: v_mov_b32_e32 v3, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -18186,13 +18186,13 @@ define amdgpu_kernel void @frem_v2f64_const_zero_num(ptr addrspace(1) %out, ptr
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, 0, v[1:2]
; GFX9-NEXT: v_mov_b32_e32 v2, v0
-; GFX9-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_cmp_nlg_f64_e32 vcc, 0, v[3:4]
-; GFX9-NEXT: s_cselect_b32 s4, 0x7ff80000, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, s4
-; GFX9-NEXT: s_and_b64 s[2:3], vcc, exec
; GFX9-NEXT: s_cselect_b32 s2, 0x7ff80000, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_cselect_b32 s3, 0x7ff80000, 0
+; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: global_store_dwordx4 v0, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
;
@@ -18205,11 +18205,11 @@ define amdgpu_kernel void @frem_v2f64_const_zero_num(ptr addrspace(1) %out, ptr
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cmp_nlg_f64_e32 vcc_lo, 0, v[1:2]
; GFX10-NEXT: v_mov_b32_e32 v2, v0
-; GFX10-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX10-NEXT: v_cmp_nlg_f64_e32 vcc_lo, 0, v[3:4]
; GFX10-NEXT: s_cselect_b32 s2, 0x7ff80000, 0
; GFX10-NEXT: v_mov_b32_e32 v1, s2
-; GFX10-NEXT: s_and_b32 s3, vcc_lo, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX10-NEXT: s_cselect_b32 s3, 0x7ff80000, 0
; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: global_store_dwordx4 v0, v[0:3], s[0:1]
@@ -18224,12 +18224,12 @@ define amdgpu_kernel void @frem_v2f64_const_zero_num(ptr addrspace(1) %out, ptr
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_cmp_nlg_f64_e32 vcc_lo, 0, v[1:2]
; GFX11-NEXT: v_mov_b32_e32 v2, v0
-; GFX11-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-NEXT: v_cmp_nlg_f64_e32 vcc_lo, 0, v[3:4]
; GFX11-NEXT: s_cselect_b32 s2, 0x7ff80000, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v1, s2
-; GFX11-NEXT: s_and_b32 s3, vcc_lo, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11-NEXT: s_cselect_b32 s3, 0x7ff80000, 0
; GFX11-NEXT: v_mov_b32_e32 v3, s3
; GFX11-NEXT: global_store_b128 v0, v[0:3], s[0:1]
@@ -18244,12 +18244,12 @@ define amdgpu_kernel void @frem_v2f64_const_zero_num(ptr addrspace(1) %out, ptr
; GFX1150-NEXT: s_waitcnt vmcnt(0)
; GFX1150-NEXT: v_cmp_nlg_f64_e32 vcc_lo, 0, v[1:2]
; GFX1150-NEXT: v_mov_b32_e32 v2, v0
-; GFX1150-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX1150-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX1150-NEXT: v_cmp_nlg_f64_e32 vcc_lo, 0, v[3:4]
; GFX1150-NEXT: s_cselect_b32 s2, 0x7ff80000, 0
; GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1150-NEXT: v_mov_b32_e32 v1, s2
-; GFX1150-NEXT: s_and_b32 s3, vcc_lo, exec_lo
+; GFX1150-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX1150-NEXT: s_cselect_b32 s3, 0x7ff80000, 0
; GFX1150-NEXT: v_mov_b32_e32 v3, s3
; GFX1150-NEXT: global_store_b128 v0, v[0:3], s[0:1]
@@ -18264,12 +18264,12 @@ define amdgpu_kernel void @frem_v2f64_const_zero_num(ptr addrspace(1) %out, ptr
; GFX1200-NEXT: s_wait_loadcnt 0x0
; GFX1200-NEXT: v_cmp_nlg_f64_e32 vcc_lo, 0, v[1:2]
; GFX1200-NEXT: v_mov_b32_e32 v2, v0
-; GFX1200-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX1200-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX1200-NEXT: v_cmp_nlg_f64_e32 vcc_lo, 0, v[3:4]
; GFX1200-NEXT: s_cselect_b32 s2, 0x7ff80000, 0
; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT: v_mov_b32_e32 v1, s2
-; GFX1200-NEXT: s_and_b32 s3, vcc_lo, exec_lo
+; GFX1200-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX1200-NEXT: s_cselect_b32 s3, 0x7ff80000, 0
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: v_mov_b32_e32 v3, s3
diff --git a/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll b/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
index 5cd9738a8fa90..20a3c5f4d2067 100644
--- a/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
@@ -848,7 +848,7 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64(double inreg %x) {
; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX8-SDAG-NEXT: v_bfrev_b32_e32 v1, 8
; GFX8-SDAG-NEXT: v_cmp_lt_f64_e32 vcc, s[0:1], v[0:1]
-; GFX8-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX8-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-SDAG-NEXT: s_cselect_b32 s2, 0x100, 0
; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX8-SDAG-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
@@ -984,7 +984,7 @@ define amdgpu_ps <2 x i32> @s_sqrt_f64_ninf(double inreg %x) {
; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX8-SDAG-NEXT: v_bfrev_b32_e32 v1, 8
; GFX8-SDAG-NEXT: v_cmp_lt_f64_e32 vcc, s[0:1], v[0:1]
-; GFX8-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX8-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-SDAG-NEXT: s_cselect_b32 s2, 0x100, 0
; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, s2
; GFX8-SDAG-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
diff --git a/llvm/test/CodeGen/AMDGPU/literal64.ll b/llvm/test/CodeGen/AMDGPU/literal64.ll
index 2415fdd2c7682..b430171152213 100644
--- a/llvm/test/CodeGen/AMDGPU/literal64.ll
+++ b/llvm/test/CodeGen/AMDGPU/literal64.ll
@@ -219,7 +219,7 @@ define i1 @class_f64() noinline optnone {
; GFX1250-SDAG-NEXT: s_mov_b32 s2, 1
; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0x4063233333333333
; GFX1250-SDAG-NEXT: v_cmp_class_f64_e64 s0, s[0:1], s2
-; GFX1250-SDAG-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1250-SDAG-NEXT: s_cmp_lg_u32 s0, 0
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, 1, 0
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
@@ -248,7 +248,7 @@ define i1 @class_f64() noinline optnone {
; GFX13-SDAG-NEXT: s_mov_b32 s2, 1
; GFX13-SDAG-NEXT: s_mov_b64 s[0:1], 0x4063233333333333
; GFX13-SDAG-NEXT: v_cmp_class_f64_e64 s0, s[0:1], s2
-; GFX13-SDAG-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX13-SDAG-NEXT: s_cmp_lg_u32 s0, 0
; GFX13-SDAG-NEXT: s_cselect_b32 s0, 1, 0
; GFX13-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX13-SDAG-NEXT: s_set_pc_i64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
index b95212b16e5ac..90dab67613d01 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
@@ -25,7 +25,7 @@ define amdgpu_kernel void @class_f16(
; VI-SDAG-NEXT: s_mov_b32 s5, s1
; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
; VI-SDAG-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
-; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s0, -1, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
; VI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -75,7 +75,7 @@ define amdgpu_kernel void @class_f16_fabs(
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT: v_cmp_class_f16_e64 s[4:5], |s5|, v0
-; VI-SDAG-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-SDAG-NEXT: s_cselect_b32 s4, -1, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
@@ -120,7 +120,7 @@ define amdgpu_kernel void @class_f16_fneg(
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT: v_cmp_class_f16_e64 s[4:5], -s5, v0
-; VI-SDAG-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-SDAG-NEXT: s_cselect_b32 s4, -1, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
@@ -165,7 +165,7 @@ define amdgpu_kernel void @class_f16_fabs_fneg(
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT: v_cmp_class_f16_e64 s[4:5], -|s5|, v0
-; VI-SDAG-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-SDAG-NEXT: s_cselect_b32 s4, -1, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
@@ -209,7 +209,7 @@ define amdgpu_kernel void @class_f16_1(
; VI-SDAG-NEXT: s_mov_b32 s2, -1
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_class_f16_e64 s[4:5], s4, 1
-; VI-SDAG-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-SDAG-NEXT: s_cselect_b32 s4, -1, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
@@ -246,7 +246,7 @@ define amdgpu_kernel void @class_f16_64(
; VI-SDAG-NEXT: s_mov_b32 s2, -1
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_class_f16_e64 s[4:5], s4, 64
-; VI-SDAG-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0
; VI-SDAG-NEXT: s_cselect_b32 s4, -1, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
@@ -284,7 +284,7 @@ define amdgpu_kernel void @class_f16_full_mask(
; VI-SDAG-NEXT: s_mov_b32 s2, -1
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_class_f16_e32 vcc, s4, v0
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s4, -1, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
@@ -323,7 +323,7 @@ define amdgpu_kernel void @class_f16_nine_bit_mask(
; VI-SDAG-NEXT: s_mov_b32 s2, -1
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_class_f16_e32 vcc, s4, v0
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s4, -1, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
index 37d2498dce449..1e8553edc0c85 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
@@ -60,7 +60,7 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; VI-SDAG-NEXT: v_add_f32_e32 v0, s2, v0
; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
; VI-SDAG-NEXT: v_ldexp_f32 v2, v0, s2
@@ -98,7 +98,7 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: v_add_f32_e32 v0, s2, v0
; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, s2
@@ -232,17 +232,17 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-SDAG-NEXT: v_add_f32_e32 v2, s3, v2
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: v_exp_f32_e32 v2, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_add_f32_e32 v2, s3, v2
; VI-SDAG-NEXT: v_add_f32_e32 v0, s2, v0
+; VI-SDAG-NEXT: v_exp_f32_e32 v2, v2
; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: s_cselect_b32 s3, 0xffffffc0, 0
-; VI-SDAG-NEXT: v_ldexp_f32 v1, v2, s3
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, v2, s3
; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, s2
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
@@ -284,7 +284,7 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: v_add_f32_e32 v3, s3, v3
@@ -292,7 +292,7 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-SDAG-NEXT: v_exp_f32_e32 v3, v3
; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
; GFX900-SDAG-NEXT: s_cselect_b32 s4, 0xffffffc0, 0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v3, s4
; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, s2
@@ -466,23 +466,23 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
; VI-SDAG-NEXT: v_add_f32_e32 v2, s2, v2
-; VI-SDAG-NEXT: v_exp_f32_e32 v2, v2
; VI-SDAG-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-SDAG-NEXT: s_cselect_b32 s4, 0xffffffc0, 0
-; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; VI-SDAG-NEXT: v_ldexp_f32 v2, v2, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: v_exp_f32_e32 v2, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; VI-SDAG-NEXT: v_add_f32_e32 v3, s1, v3
; VI-SDAG-NEXT: v_add_f32_e32 v0, s0, v0
; VI-SDAG-NEXT: v_exp_f32_e32 v3, v3
; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v2, v2, s4
; VI-SDAG-NEXT: s_cselect_b32 s4, 0xffffffc0, 0
-; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
; VI-SDAG-NEXT: v_ldexp_f32 v1, v3, s4
; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, s0
@@ -537,22 +537,22 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
; GFX900-SDAG-NEXT: v_add_f32_e32 v2, s2, v2
-; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
; GFX900-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, s2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: v_add_f32_e32 v4, s1, v4
; GFX900-SDAG-NEXT: v_add_f32_e32 v0, s0, v0
; GFX900-SDAG-NEXT: v_exp_f32_e32 v4, v4
; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v2, s2
; GFX900-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
-; GFX900-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v4, s2
; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, s0
@@ -772,7 +772,7 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
; VI-SDAG-NEXT: v_add_f32_e32 v2, s3, v2
@@ -780,13 +780,13 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: v_exp_f32_e32 v2, v2
; VI-SDAG-NEXT: v_exp_f32_e32 v4, v3
; VI-SDAG-NEXT: s_cselect_b32 s6, 0xffffffc0, 0
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
; VI-SDAG-NEXT: v_ldexp_f32 v3, v2, s6
; VI-SDAG-NEXT: v_ldexp_f32 v2, v4, s2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; VI-SDAG-NEXT: v_add_f32_e32 v4, s1, v4
@@ -794,7 +794,7 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: v_exp_f32_e32 v4, v4
; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
-; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
; VI-SDAG-NEXT: v_ldexp_f32 v1, v4, s2
; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, s0
@@ -856,7 +856,7 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
; GFX900-SDAG-NEXT: v_add_f32_e32 v2, s3, v2
@@ -864,13 +864,13 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2
; GFX900-SDAG-NEXT: v_exp_f32_e32 v5, v3
; GFX900-SDAG-NEXT: s_cselect_b32 s4, 0xffffffc0, 0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
; GFX900-SDAG-NEXT: v_ldexp_f32 v3, v2, s4
; GFX900-SDAG-NEXT: v_ldexp_f32 v2, v5, s2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: v_add_f32_e32 v5, s1, v5
@@ -878,7 +878,7 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-SDAG-NEXT: v_exp_f32_e32 v5, v5
; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
; GFX900-SDAG-NEXT: s_cselect_b32 s2, 0xffffffc0, 0
-; GFX900-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v5, s2
; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, s0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
index 9d1169f5b2ade..1cd4cf24c1ee4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
@@ -50,7 +50,7 @@ define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
; GFX8SELDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8SELDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX8SELDAG-NEXT: v_cmp_class_f16_e64 s[2:3], s2, 3
-; GFX8SELDAG-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX8SELDAG-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8SELDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX8SELDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX8SELDAG-NEXT: v_mov_b32_e32 v1, s1
@@ -79,7 +79,7 @@ define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
; GFX9SELDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX9SELDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX9SELDAG-NEXT: v_cmp_class_f16_e64 s[2:3], s2, 3
-; GFX9SELDAG-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9SELDAG-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9SELDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX9SELDAG-NEXT: global_store_dword v0, v1, s[0:1]
@@ -106,7 +106,7 @@ define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
; GFX10SELDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX10SELDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX10SELDAG-NEXT: v_cmp_class_f16_e64 s2, s2, 3
-; GFX10SELDAG-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10SELDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX10SELDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX10SELDAG-NEXT: global_store_dword v0, v1, s[0:1]
@@ -135,7 +135,7 @@ define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
; GFX11SELDAG-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11SELDAG-TRUE16-NEXT: v_cmp_class_f16_e32 vcc_lo, s2, v0.l
; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX11SELDAG-TRUE16-NEXT: s_and_b32 s2, vcc_lo, exec_lo
+; GFX11SELDAG-TRUE16-NEXT: s_cmp_lg_u32 vcc_lo, 0
; GFX11SELDAG-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, s2
; GFX11SELDAG-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
@@ -148,7 +148,7 @@ define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
; GFX11SELDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11SELDAG-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11SELDAG-FAKE16-NEXT: v_cmp_class_f16_e64 s2, s2, 3
-; GFX11SELDAG-FAKE16-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11SELDAG-FAKE16-NEXT: s_cmp_lg_u32 s2, 0
; GFX11SELDAG-FAKE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11SELDAG-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11SELDAG-FAKE16-NEXT: global_store_b32 v0, v1, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
index 17f7a401e96c8..5deda210ede1d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
@@ -48,7 +48,7 @@ define amdgpu_kernel void @sgpr_isnan_f32(ptr addrspace(1) %out, float %x) {
; GFX8SELDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8SELDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX8SELDAG-NEXT: v_cmp_class_f32_e64 s[2:3], s2, 3
-; GFX8SELDAG-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX8SELDAG-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8SELDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX8SELDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX8SELDAG-NEXT: v_mov_b32_e32 v1, s1
@@ -77,7 +77,7 @@ define amdgpu_kernel void @sgpr_isnan_f32(ptr addrspace(1) %out, float %x) {
; GFX9SELDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX9SELDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX9SELDAG-NEXT: v_cmp_class_f32_e64 s[2:3], s2, 3
-; GFX9SELDAG-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9SELDAG-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9SELDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX9SELDAG-NEXT: global_store_dword v0, v1, s[0:1]
@@ -104,7 +104,7 @@ define amdgpu_kernel void @sgpr_isnan_f32(ptr addrspace(1) %out, float %x) {
; GFX10SELDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX10SELDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX10SELDAG-NEXT: v_cmp_class_f32_e64 s2, s2, 3
-; GFX10SELDAG-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10SELDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX10SELDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX10SELDAG-NEXT: global_store_dword v0, v1, s[0:1]
@@ -131,7 +131,7 @@ define amdgpu_kernel void @sgpr_isnan_f32(ptr addrspace(1) %out, float %x) {
; GFX11SELDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11SELDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11SELDAG-NEXT: v_cmp_class_f32_e64 s2, s2, 3
-; GFX11SELDAG-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11SELDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX11SELDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX11SELDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11SELDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
@@ -192,7 +192,7 @@ define amdgpu_kernel void @sgpr_isnan_f64(ptr addrspace(1) %out, double %x) {
; GFX8SELDAG-NEXT: v_cmp_class_f64_e64 s[2:3], s[2:3], 3
; GFX8SELDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX8SELDAG-NEXT: v_mov_b32_e32 v1, s1
-; GFX8SELDAG-NEXT: s_and_b64 s[0:1], s[2:3], exec
+; GFX8SELDAG-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8SELDAG-NEXT: s_cselect_b32 s0, -1, 0
; GFX8SELDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX8SELDAG-NEXT: flat_store_dword v[0:1], v2
@@ -217,7 +217,7 @@ define amdgpu_kernel void @sgpr_isnan_f64(ptr addrspace(1) %out, double %x) {
; GFX9SELDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX9SELDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX9SELDAG-NEXT: v_cmp_class_f64_e64 s[2:3], s[2:3], 3
-; GFX9SELDAG-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX9SELDAG-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9SELDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX9SELDAG-NEXT: global_store_dword v0, v1, s[0:1]
@@ -241,7 +241,7 @@ define amdgpu_kernel void @sgpr_isnan_f64(ptr addrspace(1) %out, double %x) {
; GFX10SELDAG-NEXT: v_mov_b32_e32 v0, 0
; GFX10SELDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX10SELDAG-NEXT: v_cmp_class_f64_e64 s2, s[2:3], 3
-; GFX10SELDAG-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX10SELDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX10SELDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX10SELDAG-NEXT: global_store_dword v0, v1, s[0:1]
@@ -264,7 +264,7 @@ define amdgpu_kernel void @sgpr_isnan_f64(ptr addrspace(1) %out, double %x) {
; GFX11SELDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11SELDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11SELDAG-NEXT: v_cmp_class_f64_e64 s2, s[2:3], 3
-; GFX11SELDAG-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX11SELDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX11SELDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX11SELDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11SELDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index 0602af5c21384..a015314a35958 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -80,19 +80,19 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
;
; VI-SDAG-LABEL: s_log_f32:
; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-SDAG-NEXT: s_load_dword s0, s[4:5], 0x2c
; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-SDAG-NEXT: s_cselect_b32 s0, 32, 0
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s0
-; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_log_f32_e32 v1, v1
; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
; VI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
@@ -154,18 +154,18 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
;
; GFX900-SDAG-LABEL: s_log_f32:
; GFX900-SDAG: ; %bb.0:
-; GFX900-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX900-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s2
-; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x3f317217
; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3377d1cf
@@ -219,23 +219,23 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s1, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s1
-; GFX1100-SDAG-NEXT: s_and_b32 s1, s1, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s0, s1
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v3, 0x3f317217, v1, -v2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v3, v1, 0x3377d1cf, v3
-; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
@@ -413,19 +413,19 @@ define amdgpu_kernel void @s_log_contract_f32(ptr addrspace(1) %out, float %in)
;
; VI-SDAG-LABEL: s_log_contract_f32:
; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-SDAG-NEXT: s_load_dword s0, s[4:5], 0x2c
; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-SDAG-NEXT: s_cselect_b32 s0, 32, 0
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s0
-; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_log_f32_e32 v1, v1
; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
; VI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
@@ -487,18 +487,18 @@ define amdgpu_kernel void @s_log_contract_f32(ptr addrspace(1) %out, float %in)
;
; GFX900-SDAG-LABEL: s_log_contract_f32:
; GFX900-SDAG: ; %bb.0:
-; GFX900-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX900-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s2
-; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x3f317217
; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3377d1cf
@@ -552,23 +552,23 @@ define amdgpu_kernel void @s_log_contract_f32(ptr addrspace(1) %out, float %in)
; GFX1100-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s1, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s1
-; GFX1100-SDAG-NEXT: s_and_b32 s1, s1, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s0, s1
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v3, 0x3f317217, v1, -v2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v3, v1, 0x3377d1cf, v3
-; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
@@ -787,14 +787,14 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
@@ -900,38 +900,38 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-SDAG-NEXT: s_mov_b32 s6, 0x3377d1cf
-; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x7f800000
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x7f800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, s4
; GFX900-SDAG-NEXT: v_ldexp_f32 v4, s3, v4
; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v4
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3f317217
; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v4
-; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX900-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
; GFX900-SDAG-NEXT: v_fma_f32 v6, v4, s3, -v5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s4
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v4, s6, v6
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s6
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v4, s4, v6
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v1
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s7
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317217, v6
; GFX900-SDAG-NEXT: v_fma_f32 v4, v6, s3, -v3
-; GFX900-SDAG-NEXT: v_fma_f32 v4, v6, s6, v4
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v6, s4, v4
; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
; GFX900-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX900-SDAG-NEXT: s_endpgm
@@ -996,37 +996,35 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s4, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s4
-; GFX1100-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s4, 32, 0
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, s5
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s5, 0
; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s3, s4
-; GFX1100-SDAG-NEXT: s_and_b32 s5, s5, exec_lo
-; GFX1100-SDAG-NEXT: s_cselect_b32 s5, 32, 0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s5
+; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, s5
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s3
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317217, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v6, 0x3f317217, v1, -v4
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v6, 0x3377d1cf, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v5, 0x3f317217, v3 :: v_dual_add_f32 v4, v4, v6
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_fma_f32 v7, 0x3f317217, v3, -v5
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v7, 0x3377d1cf, v3 :: v_dual_mov_b32 v4, 0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v1, v1, v0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_add_f32_e32 v5, v5, v7
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v3, v2
; GFX1100-SDAG-NEXT: global_store_b64 v4, v[0:1], s[0:1]
; GFX1100-SDAG-NEXT: s_endpgm
@@ -1340,37 +1338,37 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; VI-SDAG-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3f317000, v5
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
-; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; VI-SDAG-NEXT: s_cselect_b32 s5, 32, 0
; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, s5
; VI-SDAG-NEXT: v_ldexp_f32 v6, s1, v6
; VI-SDAG-NEXT: v_log_f32_e32 v6, v6
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-SDAG-NEXT: s_mov_b32 s6, 0x7f800000
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s6
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
; VI-SDAG-NEXT: v_and_b32_e32 v3, 0xfffff000, v6
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; VI-SDAG-NEXT: v_sub_f32_e32 v4, v6, v3
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3f317000, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v3
@@ -1383,7 +1381,7 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
; VI-SDAG-NEXT: v_log_f32_e32 v4, v1
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s6
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v5
; VI-SDAG-NEXT: v_and_b32_e32 v3, 0xfffff000, v4
@@ -1395,7 +1393,7 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s6
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
@@ -1503,50 +1501,50 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-SDAG-NEXT: s_mov_b32 s8, 0x7f800000
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s3
; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-SDAG-NEXT: s_cselect_b32 s5, 32, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x3f317217
; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v3
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s2
-; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3377d1cf
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s4, -v5
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s5
+; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s2, -v5
; GFX900-SDAG-NEXT: v_ldexp_f32 v7, s1, v7
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s5, v6
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s3, v6
; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v7
; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317217, v7
; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
-; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s4, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s2, -v3
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s5, v5
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s3, v5
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
; GFX900-SDAG-NEXT: v_log_f32_e32 v5, v1
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc
; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v6
; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317217, v5
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s4, -v3
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s5, v6
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s2, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s3, v6
; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v6
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s8
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
@@ -1636,23 +1634,22 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s3
-; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_cselect_b32 s7, 32, 0
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s6, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s6
-; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x41b17218, s7
; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s3
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s7
; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; GFX1100-SDAG-NEXT: v_ldexp_f32 v4, s1, s6
; GFX1100-SDAG-NEXT: v_ldexp_f32 v5, s0, s2
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x41b17218, s3
; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
@@ -2092,33 +2089,33 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-SDAG-NEXT: s_mov_b32 s8, 0x7f800000
; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s6
; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3f317000, v5
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
-; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; VI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-SDAG-NEXT: v_mov_b32_e32 v6, s3
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, s6
; VI-SDAG-NEXT: v_ldexp_f32 v6, s2, v6
; VI-SDAG-NEXT: v_log_f32_e32 v6, v6
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: s_mov_b32 s3, 0x7f800000
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v6
@@ -2127,7 +2124,7 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3f317000, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v2
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_add_f32_e32 v4, v8, v4
; VI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; VI-SDAG-NEXT: v_add_f32_e32 v4, v7, v4
@@ -2137,13 +2134,13 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v5
; VI-SDAG-NEXT: v_and_b32_e32 v5, 0xfffff000, v7
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; VI-SDAG-NEXT: v_sub_f32_e32 v6, v7, v5
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3f317000, v6
; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v6
; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v5
@@ -2156,7 +2153,7 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
; VI-SDAG-NEXT: v_log_f32_e32 v6, v1
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v4
; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v6
@@ -2168,7 +2165,7 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
@@ -2301,64 +2298,64 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-SDAG-NEXT: s_mov_b32 s8, 0x3f317217
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x7f800000
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s4
; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3f317217
; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v3
-; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
-; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3377d1cf
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s8, -v5
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s3
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s9, v6
-; GFX900-SDAG-NEXT: s_mov_b32 s10, 0x7f800000
+; GFX900-SDAG-NEXT: s_cselect_b32 s8, 32, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s3, -v5
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s8
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s4, v6
; GFX900-SDAG-NEXT: v_ldexp_f32 v7, s2, v7
; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v7
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s10
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v7
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s2
-; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s8, -v2
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s3, -v2
; GFX900-SDAG-NEXT: v_ldexp_f32 v8, s1, v8
-; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s9, v5
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s4, v5
; GFX900-SDAG-NEXT: v_log_f32_e32 v8, v8
; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v6
; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, 0x3f317217, v8
; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
-; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s8, -v6
+; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s3, -v6
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s9, v7
+; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s4, v7
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v6, v6, v7
; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v1
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s10
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v5
; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v7
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s8, -v5
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s9, v6
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s3, -v5
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s4, v6
; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v5, v0
@@ -2470,59 +2467,65 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s6, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s6
-; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s7
-; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s3, s6
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s8
-; GFX1100-SDAG-NEXT: s_cselect_b32 s7, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s9, 32, 0
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s3, s9
; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s6, s9, exec_lo
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s7
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s8, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s3
; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v6, s1, s3
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v7, s0, s2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v6, s1, s2
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s7
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s8
; GFX1100-SDAG-NEXT: v_log_f32_e32 v6, v6
-; GFX1100-SDAG-NEXT: v_log_f32_e32 v7, v7
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 0x41b17218, s9
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-SDAG-NEXT: v_dual_mul_f32 v8, 0x3f317217, v2 :: v_dual_mul_f32 v9, 0x3f317217, v3
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 0x41b17218, s6
+; GFX1100-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v8, 0x3f317217, v2
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v7, s0, s1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-NEXT: v_dual_mul_f32 v10, 0x3f317217, v6 :: v_dual_mul_f32 v11, 0x3f317217, v7
-; GFX1100-SDAG-NEXT: v_fma_f32 v12, 0x3f317217, v2, -v8
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v9, 0x3f317217, v3
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: v_fma_f32 v11, 0x3f317217, v2, -v8
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v7, v7
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_fma_f32 v13, 0x3f317217, v3, -v9
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v11, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v13, 0x3377d1cf, v3
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v10, 0x3f317217, v6
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v8, v8, v11
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v9, v9, v13
; GFX1100-SDAG-NEXT: v_fma_f32 v14, 0x3f317217, v6, -v10
-; GFX1100-SDAG-NEXT: v_fma_f32 v15, 0x3f317217, v7, -v11
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v12, 0x3377d1cf, v2 :: v_dual_fmac_f32 v13, 0x3377d1cf, v3
-; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v14, 0x3377d1cf, v6 :: v_dual_fmac_f32 v15, 0x3377d1cf, v7
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT: v_dual_add_f32 v8, v8, v12 :: v_dual_add_f32 v9, v9, v13
-; GFX1100-SDAG-NEXT: v_dual_add_f32 v10, v10, v14 :: v_dual_add_f32 v11, v11, v15
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
-; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v8, v3, v9 :: v_dual_mov_b32 v9, 0
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v14, 0x3377d1cf, v6 :: v_dual_cndmask_b32 v9, v3, v9
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v3, v2, v0
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v10, v10, v14
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v9, v1
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v7|
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
-; GFX1100-SDAG-NEXT: v_sub_f32_e32 v3, v2, v0
-; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v8, v1
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v12, 0x3f317217, v7
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v15, 0x3f317217, v7, -v12
+; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v15, 0x3377d1cf, v7
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v8, v12, v15
+; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v7, v7, v8 :: v_dual_mov_b32 v8, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-SDAG-NEXT: global_store_b128 v9, v[0:3], s[0:1]
+; GFX1100-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1]
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log_v4f32:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 809501d0e5db5..c8abc78a1ba85 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -80,19 +80,19 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
;
; VI-SDAG-LABEL: s_log10_f32:
; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-SDAG-NEXT: s_load_dword s0, s[4:5], 0x2c
; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-SDAG-NEXT: s_cselect_b32 s0, 32, 0
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s0
-; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_log_f32_e32 v1, v1
; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
; VI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
@@ -154,18 +154,18 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
;
; GFX900-SDAG-LABEL: s_log10_f32:
; GFX900-SDAG: ; %bb.0:
-; GFX900-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX900-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s2
-; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x3e9a209a
; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3284fbcf
@@ -219,23 +219,23 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s1, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s1
-; GFX1100-SDAG-NEXT: s_and_b32 s1, s1, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s0, s1
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v3, 0x3e9a209a, v1, -v2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v3, v1, 0x3284fbcf, v3
-; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
@@ -413,19 +413,19 @@ define amdgpu_kernel void @s_log10_contract_f32(ptr addrspace(1) %out, float %in
;
; VI-SDAG-LABEL: s_log10_contract_f32:
; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-SDAG-NEXT: s_load_dword s0, s[4:5], 0x2c
; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-SDAG-NEXT: s_cselect_b32 s0, 32, 0
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s0
-; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_log_f32_e32 v1, v1
; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
; VI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
@@ -487,18 +487,18 @@ define amdgpu_kernel void @s_log10_contract_f32(ptr addrspace(1) %out, float %in
;
; GFX900-SDAG-LABEL: s_log10_contract_f32:
; GFX900-SDAG: ; %bb.0:
-; GFX900-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX900-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s2
-; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x3e9a209a
; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3284fbcf
@@ -552,23 +552,23 @@ define amdgpu_kernel void @s_log10_contract_f32(ptr addrspace(1) %out, float %in
; GFX1100-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s1, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s1
-; GFX1100-SDAG-NEXT: s_and_b32 s1, s1, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s0, s1
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v3, 0x3e9a209a, v1, -v2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fmamk_f32 v3, v1, 0x3284fbcf, v3
-; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
@@ -787,14 +787,14 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
@@ -900,38 +900,38 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-SDAG-NEXT: s_mov_b32 s6, 0x3284fbcf
-; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x7f800000
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x7f800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, s4
; GFX900-SDAG-NEXT: v_ldexp_f32 v4, s3, v4
; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v4
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3e9a209a
; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v4
-; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX900-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
; GFX900-SDAG-NEXT: v_fma_f32 v6, v4, s3, -v5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s4
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v4, s6, v6
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s6
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v4, s4, v6
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v1
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s7
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v6
; GFX900-SDAG-NEXT: v_fma_f32 v4, v6, s3, -v3
-; GFX900-SDAG-NEXT: v_fma_f32 v4, v6, s6, v4
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v6, s4, v4
; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
; GFX900-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX900-SDAG-NEXT: s_endpgm
@@ -996,37 +996,35 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s4, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s4
-; GFX1100-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s4, 32, 0
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, s5
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s5, 0
; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s3, s4
-; GFX1100-SDAG-NEXT: s_and_b32 s5, s5, exec_lo
-; GFX1100-SDAG-NEXT: s_cselect_b32 s5, 32, 0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s5
+; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, s5
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s3
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v6, 0x3e9a209a, v1, -v4
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v6, 0x3284fbcf, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v5, 0x3e9a209a, v3 :: v_dual_add_f32 v4, v4, v6
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_fma_f32 v7, 0x3e9a209a, v3, -v5
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v7, 0x3284fbcf, v3 :: v_dual_mov_b32 v4, 0
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v1, v1, v0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_add_f32_e32 v5, v5, v7
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v3, v2
; GFX1100-SDAG-NEXT: global_store_b64 v4, v[0:1], s[0:1]
; GFX1100-SDAG-NEXT: s_endpgm
@@ -1340,37 +1338,37 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
; VI-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; VI-SDAG-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v5
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
-; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; VI-SDAG-NEXT: s_cselect_b32 s5, 32, 0
; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, s5
; VI-SDAG-NEXT: v_ldexp_f32 v6, s1, v6
; VI-SDAG-NEXT: v_log_f32_e32 v6, v6
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-SDAG-NEXT: s_mov_b32 s6, 0x7f800000
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s6
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
; VI-SDAG-NEXT: v_and_b32_e32 v3, 0xfffff000, v6
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; VI-SDAG-NEXT: v_sub_f32_e32 v4, v6, v3
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v3
@@ -1383,7 +1381,7 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
; VI-SDAG-NEXT: v_log_f32_e32 v4, v1
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s6
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v5
; VI-SDAG-NEXT: v_and_b32_e32 v3, 0xfffff000, v4
@@ -1395,7 +1393,7 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s6
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
@@ -1503,50 +1501,50 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-SDAG-NEXT: s_mov_b32 s8, 0x7f800000
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s3
; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-SDAG-NEXT: s_cselect_b32 s5, 32, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x3e9a209a
; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v3
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s2
-; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3284fbcf
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s4, -v5
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s5
+; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s2, -v5
; GFX900-SDAG-NEXT: v_ldexp_f32 v7, s1, v7
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s5, v6
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s3, v6
; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v7
; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v7
; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
-; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s4, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s2, -v3
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s5, v5
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s3, v5
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
; GFX900-SDAG-NEXT: v_log_f32_e32 v5, v1
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc
; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v6
; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v5
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s4, -v3
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s5, v6
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s2, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s3, v6
; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v6
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s8
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
@@ -1636,23 +1634,22 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s3
-; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_cselect_b32 s7, 32, 0
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s6, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s6
-; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x411a209b, s7
; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s3
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s7
; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; GFX1100-SDAG-NEXT: v_ldexp_f32 v4, s1, s6
; GFX1100-SDAG-NEXT: v_ldexp_f32 v5, s0, s2
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x411a209b, s3
; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
@@ -2092,33 +2089,33 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-SDAG-NEXT: s_mov_b32 s8, 0x7f800000
; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s6
; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v5
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
-; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; VI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-SDAG-NEXT: v_mov_b32_e32 v6, s3
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, s6
; VI-SDAG-NEXT: v_ldexp_f32 v6, s2, v6
; VI-SDAG-NEXT: v_log_f32_e32 v6, v6
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: s_mov_b32 s3, 0x7f800000
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v6
@@ -2127,7 +2124,7 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v4
; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v2
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_add_f32_e32 v4, v8, v4
; VI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; VI-SDAG-NEXT: v_add_f32_e32 v4, v7, v4
@@ -2137,13 +2134,13 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v5
; VI-SDAG-NEXT: v_and_b32_e32 v5, 0xfffff000, v7
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; VI-SDAG-NEXT: v_sub_f32_e32 v6, v7, v5
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3e9a2000, v6
; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v6
; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v5
@@ -2156,7 +2153,7 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; VI-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
; VI-SDAG-NEXT: v_log_f32_e32 v6, v1
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v4
; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v6
@@ -2168,7 +2165,7 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s3
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
@@ -2301,64 +2298,64 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-SDAG-NEXT: s_mov_b32 s8, 0x3e9a209a
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x7f800000
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s4
; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3e9a209a
; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v3
-; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
-; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3284fbcf
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s8, -v5
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s3
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s9, v6
-; GFX900-SDAG-NEXT: s_mov_b32 s10, 0x7f800000
+; GFX900-SDAG-NEXT: s_cselect_b32 s8, 32, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s3, -v5
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s8
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s4, v6
; GFX900-SDAG-NEXT: v_ldexp_f32 v7, s2, v7
; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v7
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s10
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v7
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s2
-; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s8, -v2
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s3, -v2
; GFX900-SDAG-NEXT: v_ldexp_f32 v8, s1, v8
-; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s9, v5
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s4, v5
; GFX900-SDAG-NEXT: v_log_f32_e32 v8, v8
; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v6
; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v8
; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
-; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s8, -v6
+; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s3, -v6
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s9, v7
+; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s4, v7
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v6, v6, v7
; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v1
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s10
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v5
; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v7
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s8, -v5
-; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s9, v6
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s3, -v5
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s4, v6
; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s5
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v5, v0
@@ -2470,59 +2467,65 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s6, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s6
-; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s7
-; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s3, s6
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s8
-; GFX1100-SDAG-NEXT: s_cselect_b32 s7, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s9, 32, 0
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s3, s9
; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s6, s9, exec_lo
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s7
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s8, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s3
; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v6, s1, s3
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v7, s0, s2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v6, s1, s2
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s7
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s8
; GFX1100-SDAG-NEXT: v_log_f32_e32 v6, v6
-; GFX1100-SDAG-NEXT: v_log_f32_e32 v7, v7
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 0x411a209b, s9
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-SDAG-NEXT: v_dual_mul_f32 v8, 0x3e9a209a, v2 :: v_dual_mul_f32 v9, 0x3e9a209a, v3
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 0x411a209b, s6
+; GFX1100-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v2
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v7, s0, s1
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-NEXT: v_dual_mul_f32 v10, 0x3e9a209a, v6 :: v_dual_mul_f32 v11, 0x3e9a209a, v7
-; GFX1100-SDAG-NEXT: v_fma_f32 v12, 0x3e9a209a, v2, -v8
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v9, 0x3e9a209a, v3
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: v_fma_f32 v11, 0x3e9a209a, v2, -v8
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v7, v7
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_fma_f32 v13, 0x3e9a209a, v3, -v9
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v11, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v13, 0x3284fbcf, v3
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v10, 0x3e9a209a, v6
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v8, v8, v11
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v9, v9, v13
; GFX1100-SDAG-NEXT: v_fma_f32 v14, 0x3e9a209a, v6, -v10
-; GFX1100-SDAG-NEXT: v_fma_f32 v15, 0x3e9a209a, v7, -v11
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v12, 0x3284fbcf, v2 :: v_dual_fmac_f32 v13, 0x3284fbcf, v3
-; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v14, 0x3284fbcf, v6 :: v_dual_fmac_f32 v15, 0x3284fbcf, v7
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-NEXT: v_dual_add_f32 v8, v8, v12 :: v_dual_add_f32 v9, v9, v13
-; GFX1100-SDAG-NEXT: v_dual_add_f32 v10, v10, v14 :: v_dual_add_f32 v11, v11, v15
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
-; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v8, v3, v9 :: v_dual_mov_b32 v9, 0
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v14, 0x3284fbcf, v6 :: v_dual_cndmask_b32 v9, v3, v9
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v3, v2, v0
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v10, v10, v14
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v9, v1
; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v7|
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
-; GFX1100-SDAG-NEXT: v_sub_f32_e32 v3, v2, v0
-; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v8, v1
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v12, 0x3e9a209a, v7
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v15, 0x3e9a209a, v7, -v12
+; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v15, 0x3284fbcf, v7
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v8, v12, v15
+; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v7, v7, v8 :: v_dual_mov_b32 v8, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-SDAG-NEXT: global_store_b128 v9, v[0:3], s[0:1]
+; GFX1100-SDAG-NEXT: global_store_b128 v8, v[0:3], s[0:1]
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log10_v4f32:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index e08185b64bb94..b2103fa7b349a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -58,17 +58,17 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
;
; VI-SDAG-LABEL: s_log2_f32:
; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
-; VI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s2
-; VI-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
; VI-SDAG-NEXT: v_log_f32_e32 v1, v1
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v1, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
@@ -100,18 +100,18 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
;
; GFX900-SDAG-LABEL: s_log2_f32:
; GFX900-SDAG: ; %bb.0:
-; GFX900-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX900-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s2
-; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1]
@@ -145,12 +145,12 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s0, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s0
-; GFX1100-SDAG-NEXT: s_and_b32 s0, s0, exec_lo
; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s2, s3
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
@@ -294,12 +294,12 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
-; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
@@ -354,12 +354,12 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s4
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
@@ -409,12 +409,11 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s4, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s4
-; GFX1100-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s5
; GFX1100-SDAG-NEXT: s_cselect_b32 s4, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s5, 0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s5
; GFX1100-SDAG-NEXT: s_cselect_b32 s5, 32, 0
; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s3, s4
; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s5
@@ -610,18 +609,18 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
-; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
; VI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v5, s2
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_ldexp_f32 v5, s1, v5
; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
@@ -691,18 +690,18 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, s2
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_ldexp_f32 v5, s1, v5
; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
@@ -768,26 +767,26 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s3
-; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_cselect_b32 s7, 32, 0
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s6, 0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s6
-; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s7
; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s3
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s7
; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; GFX1100-SDAG-NEXT: v_ldexp_f32 v4, s1, s6
; GFX1100-SDAG-NEXT: v_ldexp_f32 v5, s0, s2
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s3
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v6, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v2, v2, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v1, v4, v1
@@ -1030,24 +1029,24 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; VI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v3, s6
-; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
-; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; VI-SDAG-NEXT: v_mov_b32_e32 v5, s3
+; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, s3
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_ldexp_f32 v5, s2, v5
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
; VI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v7, s2
-; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-NEXT: v_ldexp_f32 v7, s1, v7
; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
@@ -1130,24 +1129,24 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s4
-; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
-; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, s3
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, s3
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_ldexp_f32 v6, s2, v6
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v7, 0, v1, vcc
; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s2
-; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cmp_lg_u64 vcc, 0
; GFX900-SDAG-NEXT: v_ldexp_f32 v8, s1, v8
; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
@@ -1226,29 +1225,29 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s6
-; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s7
-; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s8
-; GFX1100-SDAG-NEXT: s_cselect_b32 s7, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s3, s6
+; GFX1100-SDAG-NEXT: s_cselect_b32 s8, 32, 0
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_cselect_b32 s9, 32, 0
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s3, s8
; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-SDAG-NEXT: s_and_b32 s6, s9, exec_lo
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s7
+; GFX1100-SDAG-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s9
; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
; GFX1100-SDAG-NEXT: v_ldexp_f32 v6, s1, s3
; GFX1100-SDAG-NEXT: v_ldexp_f32 v7, s0, s2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v8, v3
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s9
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s6
; GFX1100-SDAG-NEXT: v_log_f32_e32 v6, v6
; GFX1100-SDAG-NEXT: v_log_f32_e32 v7, v7
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s7
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v9, 0
; GFX1100-SDAG-NEXT: v_sub_f32_e32 v3, v2, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
diff --git a/llvm/test/CodeGen/AMDGPU/max.ll b/llvm/test/CodeGen/AMDGPU/max.ll
index 38fa362d6ab95..f4ffe10e33e2f 100644
--- a/llvm/test/CodeGen/AMDGPU/max.ll
+++ b/llvm/test/CodeGen/AMDGPU/max.ll
@@ -1198,7 +1198,7 @@ define amdgpu_kernel void @test_umax_ugt_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cmp_gt_u64_e64 s4, s[2:3], s[6:7]
-; GFX1250-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1250-NEXT: s_cmp_lg_u32 s4, 0
; GFX1250-NEXT: s_cselect_b32 s2, s2, s6
; GFX1250-NEXT: s_cselect_b32 s3, s3, s7
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
@@ -1260,7 +1260,7 @@ define amdgpu_kernel void @test_umax_uge_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cmp_ge_u64_e64 s4, s[2:3], s[6:7]
-; GFX1250-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1250-NEXT: s_cmp_lg_u32 s4, 0
; GFX1250-NEXT: s_cselect_b32 s2, s2, s6
; GFX1250-NEXT: s_cselect_b32 s3, s3, s7
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
@@ -1322,7 +1322,7 @@ define amdgpu_kernel void @test_imax_sgt_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cmp_gt_i64_e64 s4, s[2:3], s[6:7]
-; GFX1250-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1250-NEXT: s_cmp_lg_u32 s4, 0
; GFX1250-NEXT: s_cselect_b32 s2, s2, s6
; GFX1250-NEXT: s_cselect_b32 s3, s3, s7
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
@@ -1384,7 +1384,7 @@ define amdgpu_kernel void @test_imax_sge_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cmp_ge_i64_e64 s4, s[2:3], s[6:7]
-; GFX1250-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1250-NEXT: s_cmp_lg_u32 s4, 0
; GFX1250-NEXT: s_cselect_b32 s2, s2, s6
; GFX1250-NEXT: s_cselect_b32 s3, s3, s7
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll
index cab1b8a45ec5a..ac4ee03db3725 100644
--- a/llvm/test/CodeGen/AMDGPU/min.ll
+++ b/llvm/test/CodeGen/AMDGPU/min.ll
@@ -4402,7 +4402,7 @@ define amdgpu_kernel void @test_umin_ult_i64(ptr addrspace(1) %out, i64 %a, i64
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[1:2]
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, s3, s5
; VI-NEXT: s_cselect_b32 s1, s2, s4
; VI-NEXT: v_mov_b32_e32 v2, s1
@@ -4419,7 +4419,7 @@ define amdgpu_kernel void @test_umin_ult_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
-; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s3, s3, s5
; GFX9-NEXT: s_cselect_b32 s2, s2, s4
; GFX9-NEXT: v_mov_b32_e32 v0, s2
@@ -4435,7 +4435,7 @@ define amdgpu_kernel void @test_umin_ult_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cmp_lt_u64_e64 s6, s[2:3], s[4:5]
-; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s6, 0
; GFX10-NEXT: s_cselect_b32 s2, s2, s4
; GFX10-NEXT: s_cselect_b32 s3, s3, s5
; GFX10-NEXT: v_mov_b32_e32 v0, s2
@@ -4451,7 +4451,7 @@ define amdgpu_kernel void @test_umin_ult_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_lt_u64_e64 s6, s[2:3], s[4:5]
-; GFX11-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s6, 0
; GFX11-NEXT: s_cselect_b32 s2, s2, s4
; GFX11-NEXT: s_cselect_b32 s3, s3, s5
; GFX11-NEXT: v_mov_b32_e32 v0, s2
@@ -4471,7 +4471,7 @@ define amdgpu_kernel void @test_umin_ult_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cmp_lt_u64_e64 s4, s[2:3], s[6:7]
-; GFX1250-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1250-NEXT: s_cmp_lg_u32 s4, 0
; GFX1250-NEXT: s_cselect_b32 s2, s2, s6
; GFX1250-NEXT: s_cselect_b32 s3, s3, s7
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
@@ -4535,7 +4535,7 @@ define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: v_cmp_le_u64_e32 vcc, s[2:3], v[1:2]
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, s3, s5
; VI-NEXT: s_cselect_b32 s1, s2, s4
; VI-NEXT: v_mov_b32_e32 v2, s1
@@ -4552,7 +4552,7 @@ define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_cmp_le_u64_e32 vcc, s[2:3], v[0:1]
-; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s3, s3, s5
; GFX9-NEXT: s_cselect_b32 s2, s2, s4
; GFX9-NEXT: v_mov_b32_e32 v0, s2
@@ -4568,7 +4568,7 @@ define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cmp_le_u64_e64 s6, s[2:3], s[4:5]
-; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s6, 0
; GFX10-NEXT: s_cselect_b32 s2, s2, s4
; GFX10-NEXT: s_cselect_b32 s3, s3, s5
; GFX10-NEXT: v_mov_b32_e32 v0, s2
@@ -4584,7 +4584,7 @@ define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_le_u64_e64 s6, s[2:3], s[4:5]
-; GFX11-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s6, 0
; GFX11-NEXT: s_cselect_b32 s2, s2, s4
; GFX11-NEXT: s_cselect_b32 s3, s3, s5
; GFX11-NEXT: v_mov_b32_e32 v0, s2
@@ -4604,7 +4604,7 @@ define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cmp_le_u64_e64 s4, s[2:3], s[6:7]
-; GFX1250-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1250-NEXT: s_cmp_lg_u32 s4, 0
; GFX1250-NEXT: s_cselect_b32 s2, s2, s6
; GFX1250-NEXT: s_cselect_b32 s3, s3, s7
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
@@ -4668,7 +4668,7 @@ define amdgpu_kernel void @test_imin_slt_i64(ptr addrspace(1) %out, i64 %a, i64
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[1:2]
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, s3, s5
; VI-NEXT: s_cselect_b32 s1, s2, s4
; VI-NEXT: v_mov_b32_e32 v2, s1
@@ -4685,7 +4685,7 @@ define amdgpu_kernel void @test_imin_slt_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
-; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s3, s3, s5
; GFX9-NEXT: s_cselect_b32 s2, s2, s4
; GFX9-NEXT: v_mov_b32_e32 v0, s2
@@ -4701,7 +4701,7 @@ define amdgpu_kernel void @test_imin_slt_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cmp_lt_i64_e64 s6, s[2:3], s[4:5]
-; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s6, 0
; GFX10-NEXT: s_cselect_b32 s2, s2, s4
; GFX10-NEXT: s_cselect_b32 s3, s3, s5
; GFX10-NEXT: v_mov_b32_e32 v0, s2
@@ -4717,7 +4717,7 @@ define amdgpu_kernel void @test_imin_slt_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_lt_i64_e64 s6, s[2:3], s[4:5]
-; GFX11-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s6, 0
; GFX11-NEXT: s_cselect_b32 s2, s2, s4
; GFX11-NEXT: s_cselect_b32 s3, s3, s5
; GFX11-NEXT: v_mov_b32_e32 v0, s2
@@ -4737,7 +4737,7 @@ define amdgpu_kernel void @test_imin_slt_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cmp_lt_i64_e64 s4, s[2:3], s[6:7]
-; GFX1250-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1250-NEXT: s_cmp_lg_u32 s4, 0
; GFX1250-NEXT: s_cselect_b32 s2, s2, s6
; GFX1250-NEXT: s_cselect_b32 s3, s3, s7
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
@@ -4801,7 +4801,7 @@ define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64
; VI-NEXT: v_mov_b32_e32 v2, s5
; VI-NEXT: v_cmp_le_i64_e32 vcc, s[2:3], v[1:2]
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-NEXT: s_cmp_lg_u64 vcc, 0
; VI-NEXT: s_cselect_b32 s0, s3, s5
; VI-NEXT: s_cselect_b32 s1, s2, s4
; VI-NEXT: v_mov_b32_e32 v2, s1
@@ -4818,7 +4818,7 @@ define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_cmp_le_i64_e32 vcc, s[2:3], v[0:1]
-; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s3, s3, s5
; GFX9-NEXT: s_cselect_b32 s2, s2, s4
; GFX9-NEXT: v_mov_b32_e32 v0, s2
@@ -4834,7 +4834,7 @@ define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cmp_le_i64_e64 s6, s[2:3], s[4:5]
-; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX10-NEXT: s_cmp_lg_u32 s6, 0
; GFX10-NEXT: s_cselect_b32 s2, s2, s4
; GFX10-NEXT: s_cselect_b32 s3, s3, s5
; GFX10-NEXT: v_mov_b32_e32 v0, s2
@@ -4850,7 +4850,7 @@ define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cmp_le_i64_e64 s6, s[2:3], s[4:5]
-; GFX11-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s6, 0
; GFX11-NEXT: s_cselect_b32 s2, s2, s4
; GFX11-NEXT: s_cselect_b32 s3, s3, s5
; GFX11-NEXT: v_mov_b32_e32 v0, s2
@@ -4870,7 +4870,7 @@ define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX1250-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cmp_le_i64_e64 s4, s[2:3], s[6:7]
-; GFX1250-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1250-NEXT: s_cmp_lg_u32 s4, 0
; GFX1250-NEXT: s_cselect_b32 s2, s2, s6
; GFX1250-NEXT: s_cselect_b32 s3, s3, s7
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll b/llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
index 15ffb3a7e7dcf..1e4fe01a75ecc 100644
--- a/llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
@@ -35,9 +35,8 @@ define amdgpu_cs void @mixed_vmem_types_sampler_reads(i32 inreg %globalTable, i3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, s0, s2
; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: buffer_store_b32 v0, off, s[24:27], 0
; GFX11-NEXT: s_endpgm
@@ -74,9 +73,8 @@ define amdgpu_cs void @mixed_vmem_types_sampler_reads(i32 inreg %globalTable, i3
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-NEXT: s_and_b32 s0, s0, s2
; GFX12-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_and_b32 s0, s0, exec_lo
; GFX12-NEXT: s_cselect_b32 s0, 1, 0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: v_mov_b32_e32 v0, s0
; GFX12-NEXT: buffer_store_b32 v0, off, s[24:27], null
; GFX12-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/or.ll b/llvm/test/CodeGen/AMDGPU/or.ll
index 23d9a57cffd05..40eff999ef801 100644
--- a/llvm/test/CodeGen/AMDGPU/or.ll
+++ b/llvm/test/CodeGen/AMDGPU/or.ll
@@ -910,7 +910,7 @@ define amdgpu_kernel void @or_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, p
; GFX8-NEXT: v_mul_f32_e32 v1, 1.0, v1
; GFX8-NEXT: v_max_f32_e32 v0, v1, v0
; GFX8-NEXT: v_cmp_le_f32_e32 vcc, 0, v0
-; GFX8-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
; GFX8-NEXT: s_cselect_b32 s4, 1, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
index 8de7a0de592c7..115c0ba485750 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
@@ -524,16 +524,15 @@ define amdgpu_cs float @v_s_sqrt_f32(float inreg %src) {
; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-SDAG-NEXT: s_xor_b32 s6, s4, 0x80000000
; GFX12-SDAG-NEXT: s_fmac_f32 s5, s6, s2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-SDAG-NEXT: v_cmp_class_f32_e64 s2, s1, 0x260
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_2)
; GFX12-SDAG-NEXT: s_cmp_gt_f32 s5, 0
-; GFX12-SDAG-NEXT: s_cselect_b32 s2, s4, s3
+; GFX12-SDAG-NEXT: s_cselect_b32 s3, s4, s3
; GFX12-SDAG-NEXT: s_cmp_lt_f32 s0, 0xf800000
-; GFX12-SDAG-NEXT: s_mul_f32 s0, s2, 0x37800000
-; GFX12-SDAG-NEXT: v_cmp_class_f32_e64 s3, s1, 0x260
+; GFX12-SDAG-NEXT: s_mul_f32 s0, s3, 0x37800000
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-SDAG-NEXT: s_cselect_b32 s0, s0, s2
-; GFX12-SDAG-NEXT: s_and_b32 s2, s3, exec_lo
+; GFX12-SDAG-NEXT: s_cselect_b32 s0, s0, s3
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_cselect_b32 s0, s1, s0
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/rsq.f64.ll b/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
index 59374d76a263f..3ff67920b9f69 100644
--- a/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/rsq.f64.ll
@@ -205,7 +205,7 @@ define amdgpu_ps <2 x i32> @s_rsq_f64(double inreg %x) {
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v0, 0
; VI-SDAG-CG-NEXT: v_bfrev_b32_e32 v1, 8
; VI-SDAG-CG-NEXT: v_cmp_lt_f64_e32 vcc, s[0:1], v[0:1]
-; VI-SDAG-CG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-CG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-CG-NEXT: s_cselect_b32 s2, 0x100, 0
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v0, s2
; VI-SDAG-CG-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
@@ -776,7 +776,7 @@ define amdgpu_ps <2 x i32> @s_neg_rsq_f64(double inreg %x) {
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v0, 0
; VI-SDAG-CG-NEXT: v_bfrev_b32_e32 v1, 8
; VI-SDAG-CG-NEXT: v_cmp_lt_f64_e32 vcc, s[0:1], v[0:1]
-; VI-SDAG-CG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-CG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-CG-NEXT: s_cselect_b32 s2, 0x100, 0
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v0, s2
; VI-SDAG-CG-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
@@ -1069,7 +1069,7 @@ define amdgpu_ps <2 x i32> @s_neg_rsq_neg_f64(double inreg %x) {
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v0, 0
; VI-SDAG-CG-NEXT: v_bfrev_b32_e32 v1, 9
; VI-SDAG-CG-NEXT: v_cmp_gt_f64_e32 vcc, s[0:1], v[0:1]
-; VI-SDAG-CG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-CG-NEXT: s_cmp_lg_u64 vcc, 0
; VI-SDAG-CG-NEXT: s_cselect_b32 s2, 0x100, 0
; VI-SDAG-CG-NEXT: v_mov_b32_e32 v0, s2
; VI-SDAG-CG-NEXT: v_ldexp_f64 v[0:1], -s[0:1], v0
diff --git a/llvm/test/CodeGen/AMDGPU/saddo.ll b/llvm/test/CodeGen/AMDGPU/saddo.ll
index 9d8869c765e29..93538a7780d83 100644
--- a/llvm/test/CodeGen/AMDGPU/saddo.ll
+++ b/llvm/test/CodeGen/AMDGPU/saddo.ll
@@ -299,7 +299,6 @@ define amdgpu_kernel void @v_saddo_i32(ptr addrspace(1) %out, ptr addrspace(1) %
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v5
; VI-NEXT: v_cmp_lt_i32_e64 s[0:1], v6, v4
; VI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; VI-NEXT: s_cselect_b32 s0, 1, 0
; VI-NEXT: flat_store_dword v[0:1], v6
; VI-NEXT: v_mov_b32_e32 v0, s0
@@ -546,7 +545,6 @@ define amdgpu_kernel void @v_saddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; VI-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v3
; VI-NEXT: s_xor_b64 s[0:1], s[0:1], vcc
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; VI-NEXT: s_cselect_b32 s0, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: flat_store_dwordx2 v[4:5], v[8:9]
@@ -566,7 +564,6 @@ define amdgpu_kernel void @v_saddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
; GFX9-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v3
; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], vcc
-; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: global_store_dwordx2 v6, v[4:5], s[8:9]
@@ -587,7 +584,6 @@ define amdgpu_kernel void @v_saddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX10-NEXT: v_cmp_gt_i32_e64 s0, 0, v3
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
; GFX10-NEXT: s_xor_b32 s0, s0, vcc_lo
-; GFX10-NEXT: s_and_b32 s0, s0, exec_lo
; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: global_store_dwordx2 v6, v[4:5], s[8:9]
@@ -609,9 +605,8 @@ define amdgpu_kernel void @v_saddo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX11-NEXT: v_cmp_gt_i32_e64 s0, 0, v3
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
; GFX11-NEXT: s_xor_b32 s0, s0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b64 v6, v[4:5], s[4:5]
@@ -677,25 +672,24 @@ define amdgpu_kernel void @v_saddo_v2i32(ptr addrspace(1) %out, ptr addrspace(1)
; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
-; VI-NEXT: v_mov_b32_e32 v4, s0
-; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v6, s2
; VI-NEXT: v_mov_b32_e32 v7, s3
+; VI-NEXT: v_mov_b32_e32 v4, s0
+; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_u32_e32 v9, vcc, v1, v3
; VI-NEXT: v_add_u32_e32 v8, vcc, v0, v2
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2
-; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v3
; VI-NEXT: v_cmp_lt_i32_e64 s[2:3], v8, v0
+; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v3
; VI-NEXT: v_cmp_lt_i32_e64 s[4:5], v9, v1
; VI-NEXT: s_xor_b64 s[2:3], vcc, s[2:3]
; VI-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; VI-NEXT: s_cselect_b32 s4, 1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[2:3], exec
; VI-NEXT: s_cselect_b32 s0, 1, 0
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-NEXT: s_cselect_b32 s1, 1, 0
+; VI-NEXT: v_mov_b32_e32 v0, s1
+; VI-NEXT: v_mov_b32_e32 v1, s0
; VI-NEXT: flat_store_dwordx2 v[4:5], v[8:9]
; VI-NEXT: flat_store_dwordx2 v[6:7], v[0:1]
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/scmp.ll b/llvm/test/CodeGen/AMDGPU/scmp.ll
index 6d567d5790caf..762fc2071c39c 100644
--- a/llvm/test/CodeGen/AMDGPU/scmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/scmp.ll
@@ -667,20 +667,20 @@ define i32 @scmp_i128_uniform(i128 inreg %a, i128 inreg %b) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s4, s[0:1], s[16:17]
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s5, s[2:3], s[18:19]
-; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s6, s[2:3], s[18:19]
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[16:17]
-; GFX12-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s4, 0
+; GFX12-SDAG-NEXT: v_cmp_lt_i64_e64 s4, s[2:3], s[18:19]
+; GFX12-SDAG-NEXT: s_cselect_b32 s6, 1, 0
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s5, 0
; GFX12-SDAG-NEXT: s_cselect_b32 s1, 1, 0
-; GFX12-SDAG-NEXT: s_and_b32 s4, s5, exec_lo
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-SDAG-NEXT: s_cselect_b32 s4, 1, 0
-; GFX12-SDAG-NEXT: s_and_b32 s5, s6, exec_lo
-; GFX12-SDAG-NEXT: s_cselect_b32 s5, 1, 0
-; GFX12-SDAG-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s0, 0
; GFX12-SDAG-NEXT: s_cselect_b32 s0, 1, 0
; GFX12-SDAG-NEXT: s_cmp_eq_u64 s[2:3], s[18:19]
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-NEXT: s_cselect_b32 s1, s1, s4
-; GFX12-SDAG-NEXT: s_cselect_b32 s0, s0, s5
+; GFX12-SDAG-NEXT: s_cselect_b32 s1, s6, s1
+; GFX12-SDAG-NEXT: s_cselect_b32 s0, s0, s4
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_and_b32 s1, s1, 1
; GFX12-SDAG-NEXT: s_bitcmp1_b32 s0, 0
@@ -770,9 +770,9 @@ define i32 @scmp_i64_uniform(i64 inreg %a, i64 inreg %b) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_i64_e64 s4, s[0:1], s[2:3]
; GFX12-SDAG-NEXT: v_cmp_ge_i64_e64 s0, s[0:1], s[2:3]
-; GFX12-SDAG-NEXT: s_and_b32 s1, s4, exec_lo
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-SDAG-NEXT: s_cselect_b32 s1, 1, 0
-; GFX12-SDAG-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s0, 0
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_cselect_b32 s0, s1, -1
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll b/llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
index 4ac33651db927..2bec8839e33a2 100644
--- a/llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
+++ b/llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
@@ -56,7 +56,7 @@ define i32 @select.hi32.sgpr.oeq.bad.zero(double inreg %x, double inreg %y, i32
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_mov_b32_e32 v1, s19
; CHECK-NEXT: v_cmp_eq_f64_e32 vcc, s[16:17], v[0:1]
-; CHECK-NEXT: s_and_b64 s[4:5], vcc, exec
+; CHECK-NEXT: s_cmp_lg_u64 vcc, 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -79,7 +79,7 @@ define i32 @select.hi32.sgpr.oeq.bad.nan(double inreg %x, double inreg %y, i32 i
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_mov_b32_e32 v1, s19
; CHECK-NEXT: v_cmp_eq_f64_e32 vcc, s[16:17], v[0:1]
-; CHECK-NEXT: s_and_b64 s[4:5], vcc, exec
+; CHECK-NEXT: s_cmp_lg_u64 vcc, 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -125,7 +125,7 @@ define i32 @select.hi32.sgpr.ueq.bad.zero(double inreg %x, double inreg %y, i32
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_mov_b32_e32 v1, s19
; CHECK-NEXT: v_cmp_eq_f64_e32 vcc, s[4:5], v[0:1]
-; CHECK-NEXT: s_and_b64 s[4:5], vcc, exec
+; CHECK-NEXT: s_cmp_lg_u64 vcc, 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -149,7 +149,7 @@ define i32 @select.hi32.sgpr.ueq.bad.nan(double inreg %x, double inreg %y, i32 i
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_mov_b32_e32 v1, s19
; CHECK-NEXT: v_cmp_nlg_f64_e32 vcc, s[4:5], v[0:1]
-; CHECK-NEXT: s_and_b64 s[4:5], vcc, exec
+; CHECK-NEXT: s_cmp_lg_u64 vcc, 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -213,7 +213,7 @@ define i32 @select.hi32.sgpr.olt.bad.neg(double inreg %x, double inreg %y, i32 i
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_mov_b32_e32 v1, s4
; CHECK-NEXT: v_cmp_lt_f64_e64 s[4:5], |s[16:17]|, v[0:1]
-; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; CHECK-NEXT: s_cmp_lg_u64 s[4:5], 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -233,7 +233,7 @@ define i32 @select.hi32.sgpr.olt.bad.nan(double inreg %x, double inreg %y, i32 i
; CHECK-NEXT: v_mov_b32_e32 v0, s18
; CHECK-NEXT: v_mov_b32_e32 v1, s19
; CHECK-NEXT: v_cmp_lt_f64_e64 s[4:5], |s[16:17]|, |v[0:1]|
-; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; CHECK-NEXT: s_cmp_lg_u64 s[4:5], 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -295,7 +295,7 @@ define i32 @select.hi32.sgpr.ult.bad.0(double inreg %x, double inreg %y, i32 inr
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_mov_b32_e32 v1, s19
; CHECK-NEXT: v_cmp_nge_f64_e64 s[4:5], |s[16:17]|, v[0:1]
-; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; CHECK-NEXT: s_cmp_lg_u64 s[4:5], 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -317,7 +317,7 @@ define i32 @select.hi32.sgpr.ult.bad.1(double inreg %x, double inreg %y, i32 inr
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_mov_b32_e32 v1, s19
; CHECK-NEXT: v_cmp_nge_f64_e32 vcc, s[16:17], v[0:1]
-; CHECK-NEXT: s_and_b64 s[4:5], vcc, exec
+; CHECK-NEXT: s_cmp_lg_u64 vcc, 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -386,7 +386,7 @@ define i32 @select.hi32.sgpr.ole.bad.0(double inreg %x, double inreg %y, i32 inr
; CHECK-NEXT: v_mov_b32_e32 v0, s18
; CHECK-NEXT: v_mov_b32_e32 v1, s19
; CHECK-NEXT: v_cmp_le_f64_e32 vcc, s[4:5], v[0:1]
-; CHECK-NEXT: s_and_b64 s[4:5], vcc, exec
+; CHECK-NEXT: s_cmp_lg_u64 vcc, 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -410,7 +410,7 @@ define i32 @select.hi32.sgpr.ole.bad.1(double inreg %x, double inreg %y, i32 inr
; CHECK-NEXT: s_and_b32 s5, s17, 0x3fffffff
; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: v_cmp_le_f64_e64 s[4:5], s[4:5], |v[0:1]|
-; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; CHECK-NEXT: s_cmp_lg_u64 s[4:5], 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -471,7 +471,7 @@ define i32 @select.hi32.sgpr.ule.bad(double inreg %x, double inreg %y, i32 inreg
; CHECK-NEXT: v_mov_b32_e32 v0, s18
; CHECK-NEXT: v_mov_b32_e32 v1, s19
; CHECK-NEXT: v_cmp_ngt_f64_e64 s[4:5], |s[16:17]|, |v[0:1]|
-; CHECK-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; CHECK-NEXT: s_cmp_lg_u64 s[4:5], 0
; CHECK-NEXT: s_cselect_b32 s4, s20, s21
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/ssubo.ll b/llvm/test/CodeGen/AMDGPU/ssubo.ll
index 7d08ac6222ecc..2bb8f84271702 100644
--- a/llvm/test/CodeGen/AMDGPU/ssubo.ll
+++ b/llvm/test/CodeGen/AMDGPU/ssubo.ll
@@ -297,7 +297,6 @@ define amdgpu_kernel void @v_ssubo_i32(ptr addrspace(1) %out, ptr addrspace(1) %
; VI-NEXT: v_cmp_lt_i32_e32 vcc, v4, v5
; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v6
; VI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; VI-NEXT: s_cselect_b32 s0, 1, 0
; VI-NEXT: flat_store_dword v[0:1], v6
; VI-NEXT: v_mov_b32_e32 v0, s0
@@ -546,7 +545,6 @@ define amdgpu_kernel void @v_ssubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; VI-NEXT: v_subb_u32_e64 v1, s[0:1], v1, v3, s[0:1]
; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v1
; VI-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
; VI-NEXT: s_cselect_b32 s0, 1, 0
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; VI-NEXT: v_mov_b32_e32 v0, s0
@@ -566,7 +564,6 @@ define amdgpu_kernel void @v_ssubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX9-NEXT: v_subb_co_u32_e64 v1, s[0:1], v1, v3, s[0:1]
; GFX9-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v1
; GFX9-NEXT: s_xor_b64 s[0:1], vcc, s[0:1]
-; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], exec
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[8:9]
; GFX9-NEXT: v_mov_b32_e32 v0, s0
@@ -587,7 +584,6 @@ define amdgpu_kernel void @v_ssubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX10-NEXT: v_cmp_gt_i32_e64 s0, 0, v5
; GFX10-NEXT: s_xor_b32 s0, vcc_lo, s0
-; GFX10-NEXT: s_and_b32 s0, s0, exec_lo
; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: global_store_dwordx2 v6, v[4:5], s[8:9]
@@ -609,9 +605,8 @@ define amdgpu_kernel void @v_ssubo_i64(ptr addrspace(1) %out, ptr addrspace(1) %
; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[0:1], v[2:3]
; GFX11-NEXT: v_cmp_gt_i32_e64 s0, 0, v5
; GFX11-NEXT: s_xor_b32 s0, vcc_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b64 v6, v[4:5], s[4:5]
@@ -683,16 +678,15 @@ define amdgpu_kernel void @v_ssubo_v2i32(ptr addrspace(1) %out, ptr addrspace(1)
; VI-NEXT: v_mov_b32_e32 v7, s3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_sub_u32_e32 v8, vcc, v0, v2
-; VI-NEXT: v_sub_u32_e32 v9, vcc, v1, v3
; VI-NEXT: v_cmp_lt_i32_e64 s[0:1], v0, v2
-; VI-NEXT: v_cmp_lt_i32_e32 vcc, v1, v3
+; VI-NEXT: v_sub_u32_e32 v9, vcc, v1, v3
; VI-NEXT: v_cmp_gt_i32_e64 s[2:3], 0, v8
+; VI-NEXT: v_cmp_lt_i32_e32 vcc, v1, v3
; VI-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v9
; VI-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
; VI-NEXT: s_xor_b64 s[2:3], vcc, s[4:5]
-; VI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; VI-NEXT: s_cselect_b32 s2, 1, 0
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
+; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
; VI-NEXT: s_cselect_b32 s0, 1, 0
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s2
diff --git a/llvm/test/CodeGen/AMDGPU/ucmp.ll b/llvm/test/CodeGen/AMDGPU/ucmp.ll
index cbe27b453883a..37c065358d059 100644
--- a/llvm/test/CodeGen/AMDGPU/ucmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/ucmp.ll
@@ -662,20 +662,20 @@ define i32 @ucmp_i128_uniform(i128 inreg %a, i128 inreg %b) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s4, s[0:1], s[16:17]
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s5, s[2:3], s[18:19]
-; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s6, s[2:3], s[18:19]
; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[16:17]
-; GFX12-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s4, 0
+; GFX12-SDAG-NEXT: v_cmp_lt_u64_e64 s4, s[2:3], s[18:19]
+; GFX12-SDAG-NEXT: s_cselect_b32 s6, 1, 0
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s5, 0
; GFX12-SDAG-NEXT: s_cselect_b32 s1, 1, 0
-; GFX12-SDAG-NEXT: s_and_b32 s4, s5, exec_lo
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-SDAG-NEXT: s_cselect_b32 s4, 1, 0
-; GFX12-SDAG-NEXT: s_and_b32 s5, s6, exec_lo
-; GFX12-SDAG-NEXT: s_cselect_b32 s5, 1, 0
-; GFX12-SDAG-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s0, 0
; GFX12-SDAG-NEXT: s_cselect_b32 s0, 1, 0
; GFX12-SDAG-NEXT: s_cmp_eq_u64 s[2:3], s[18:19]
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-NEXT: s_cselect_b32 s1, s1, s4
-; GFX12-SDAG-NEXT: s_cselect_b32 s0, s0, s5
+; GFX12-SDAG-NEXT: s_cselect_b32 s1, s6, s1
+; GFX12-SDAG-NEXT: s_cselect_b32 s0, s0, s4
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_and_b32 s1, s1, 1
; GFX12-SDAG-NEXT: s_bitcmp1_b32 s0, 0
@@ -765,9 +765,9 @@ define i32 @ucmp_i64_uniform(i64 inreg %a, i64 inreg %b) {
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: v_cmp_gt_u64_e64 s4, s[0:1], s[2:3]
; GFX12-SDAG-NEXT: v_cmp_ge_u64_e64 s0, s[0:1], s[2:3]
-; GFX12-SDAG-NEXT: s_and_b32 s1, s4, exec_lo
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-SDAG-NEXT: s_cselect_b32 s1, 1, 0
-; GFX12-SDAG-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX12-SDAG-NEXT: s_cmp_lg_u32 s0, 0
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-NEXT: s_cselect_b32 s0, s1, -1
; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll b/llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
index 81a4d41ef7388..1d6ea7d32f2ac 100644
--- a/llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
@@ -213,7 +213,7 @@ define amdgpu_ps i64 @s_underflow_compare_fold_i64(i64 inreg %a, i64 inreg %b) #
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
-; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s1, s3, s1
; GFX9-NEXT: s_cselect_b32 s0, s2, s0
; GFX9-NEXT: ; return to shader part epilog
@@ -224,7 +224,7 @@ define amdgpu_ps i64 @s_underflow_compare_fold_i64(i64 inreg %a, i64 inreg %b) #
; GFX11-NEXT: s_subb_u32 s3, s1, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_cmp_lt_u64_e64 s4, s[2:3], s[0:1]
-; GFX11-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-NEXT: s_cmp_lg_u32 s4, 0
; GFX11-NEXT: s_cselect_b32 s0, s2, s0
; GFX11-NEXT: s_cselect_b32 s1, s3, s1
; GFX11-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll
index c8a3c9622c36d..5a28e411cfab4 100644
--- a/llvm/test/CodeGen/AMDGPU/wave32.ll
+++ b/llvm/test/CodeGen/AMDGPU/wave32.ll
@@ -143,7 +143,7 @@ define amdgpu_kernel void @test_vopc_class(ptr addrspace(1) %out, float %x) #0 {
; GFX1032-NEXT: v_mov_b32_e32 v0, 0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_cmp_class_f32_e64 s2, s2, 0x204
-; GFX1032-NEXT: s_and_b32 s2, s2, exec_lo
+; GFX1032-NEXT: s_cmp_lg_u32 s2, 0
; GFX1032-NEXT: s_cselect_b32 s2, 1, 0
; GFX1032-NEXT: v_mov_b32_e32 v1, s2
; GFX1032-NEXT: global_store_dword v0, v1, s[0:1]
@@ -157,7 +157,7 @@ define amdgpu_kernel void @test_vopc_class(ptr addrspace(1) %out, float %x) #0 {
; GFX1064-NEXT: v_mov_b32_e32 v0, 0
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_cmp_class_f32_e64 s[2:3], s2, 0x204
-; GFX1064-NEXT: s_and_b64 s[2:3], s[2:3], exec
+; GFX1064-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1064-NEXT: s_cselect_b32 s2, 1, 0
; GFX1064-NEXT: v_mov_b32_e32 v1, s2
; GFX1064-NEXT: global_store_dword v0, v1, s[0:1]
More information about the llvm-commits
mailing list