[llvm] [AMDGPU] Split the true16 fcopysign pattern by uniformity (PR #226898)
Changpeng Fang via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 28 20:58:10 PDT 2026
https://github.com/changpeng updated https://github.com/llvm/llvm-project/pull/226898
>From 86f8cb66e967a191915816387abb54efcf4a6471 Mon Sep 17 00:00:00 2001
From: Changpeng Fang <changpeng.fang at amd.com>
Date: Sun, 27 Sep 2026 23:57:22 -0700
Subject: [PATCH] [AMDGPU] Split the true16 fcopysign pattern by uniformity
A uniform 16-bit value already lives in the low half of an SGPR, so it can
go straight to V_BFI_B32_e64. Only a divergent VGPR_16 operand needs the
widening REG_SEQUENCE, which was ill-formed for the uniform case (operand
wider than the lo16 slot it names) and confused DetectDeadLanes.
Fixes: ROCM-31212
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 12 +-
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll | 46 +-
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 26 +-
llvm/test/CodeGen/AMDGPU/frem.ll | 2764 ++++++++++-------
llvm/test/CodeGen/AMDGPU/llvm.round.ll | 51 +-
.../AMDGPU/true16-uniform-f16-phi-copysign.ll | 80 +
6 files changed, 1790 insertions(+), 1189 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 3cf20ffb1fcf4..5d6e92b03b92d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2464,10 +2464,16 @@ def : GCNPat <
}
let True16Predicate = UseRealTrue16Insts in {
def : GCNPat <
- (fcopysign fp16vt:$src0, fp16vt:$src1),
+ (UniformBinFrag<fcopysign> fp16vt:$src0, fp16vt:$src1),
+ (S_OR_B32 (S_AND_B32 SReg_32:$src0, (i32 0x00007fff)),
+ (S_AND_B32 SReg_32:$src1, (i32 0x00008000)))
+>;
+
+def : GCNPat <
+ (DivergentBinFrag<fcopysign> fp16vt:$src0, fp16vt:$src1),
(EXTRACT_SUBREG (V_BFI_B32_e64 (S_MOV_B32 (i32 0x00007fff)),
- (REG_SEQUENCE VGPR_32, $src0, lo16, (i16 (IMPLICIT_DEF)), hi16),
- (REG_SEQUENCE VGPR_32, $src1, lo16, (i16 (IMPLICIT_DEF)), hi16)), lo16)
+ (REG_SEQUENCE VGPR_32, VGPR_16:$src0, lo16, (i16 (IMPLICIT_DEF)), hi16),
+ (REG_SEQUENCE VGPR_32, VGPR_16:$src1, lo16, (i16 (IMPLICIT_DEF)), hi16)), lo16)
>;
// TODO: Scalar case for 0 magnitude special case
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 31b868993156d..9832f8d3bfe07 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -363,13 +363,11 @@ define amdgpu_ps i32 @s_copysign_bf16_bf16(bfloat inreg %mag, bfloat inreg %sign
;
; GFX11TRUE16-LABEL: s_copysign_bf16_bf16:
; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11TRUE16-NEXT: s_and_b32 s1, s1, 0x8000
+; GFX11TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11TRUE16-NEXT: s_or_b32 s0, s0, s1
+; GFX11TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
; GFX11FAKE16-LABEL: s_copysign_bf16_bf16:
@@ -579,13 +577,11 @@ define amdgpu_ps i32 @s_copysign_bf16_f16(bfloat inreg %mag, half inreg %sign.f1
;
; GFX11TRUE16-LABEL: s_copysign_bf16_f16:
; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11TRUE16-NEXT: s_and_b32 s1, s1, 0x8000
+; GFX11TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11TRUE16-NEXT: s_or_b32 s0, s0, s1
+; GFX11TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
; GFX11FAKE16-LABEL: s_copysign_bf16_f16:
@@ -827,13 +823,11 @@ define amdgpu_ps i32 @s_copysign_f16_bf16(half inreg %mag, bfloat inreg %sign.bf
;
; GFX11TRUE16-LABEL: s_copysign_f16_bf16:
; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11TRUE16-NEXT: s_and_b32 s1, s1, 0x8000
+; GFX11TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11TRUE16-NEXT: s_or_b32 s0, s0, s1
+; GFX11TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
; GFX11FAKE16-LABEL: s_copysign_f16_bf16:
@@ -3140,15 +3134,13 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_f32_sign_bf16(float inreg %mag, bf
; GFX11TRUE16-NEXT: s_add_i32 s2, s2, s0
; GFX11TRUE16-NEXT: s_bitset1_b32 s0, 22
; GFX11TRUE16-NEXT: s_addk_i32 s2, 0x7fff
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
; GFX11TRUE16-NEXT: s_and_b32 s3, s3, exec_lo
; GFX11TRUE16-NEXT: s_cselect_b32 s0, s0, s2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11TRUE16-NEXT: s_and_b32 s1, s1, 0x8000
; GFX11TRUE16-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
+; GFX11TRUE16-NEXT: s_or_b32 s0, s0, s1
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
; GFX11FAKE16-LABEL: s_copysign_out_bf16_mag_f32_sign_bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index f9cb5d91ff615..44caae0575664 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -41,11 +41,10 @@ define amdgpu_ps i16 @s_copysign_f16(half inreg %mag, half inreg %sign) {
;
; GFX11-TRUE16-LABEL: s_copysign_f16:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0x8000
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: s_copysign_f16:
@@ -1217,7 +1216,7 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f64_sign_f16(double inreg %mag, hal
; GFX11-TRUE16-LABEL: s_copysign_out_f16_mag_f64_sign_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_and_b32 s3, s1, 0x1ff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_or_b32 s0, s3, s0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-TRUE16-NEXT: s_bfe_u32 s3, s1, 0xb0014
@@ -1258,11 +1257,10 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f64_sign_f16(double inreg %mag, hal
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, s4, 0x7c00
; GFX11-TRUE16-NEXT: s_cmpk_eq_i32 s3, 0x40f
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, 0x8000
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: s_copysign_out_f16_mag_f64_sign_f16:
@@ -2669,9 +2667,11 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f32_sign_f16(float inreg %mag, half
; GFX11-TRUE16-LABEL: s_copysign_out_f16_mag_f32_sign_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, 0x8000
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 486d7c15150bc..91688952cd330 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -529,23 +529,24 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
-; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] offset:8
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[4:5] offset:8
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v4, |v1.l|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.l|
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.h|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v2
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v4, v2
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB0_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v2
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v4, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.l, v0.h, vcc_lo
; GFX11-TRUE16-NEXT: s_branch .LBB0_3
; GFX11-TRUE16-NEXT: .LBB0_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
@@ -555,41 +556,43 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v2
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v4
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v3, 11
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v2
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v2
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v4, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v3
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
-; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX11-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -597,29 +600,51 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_fma_f32 v1, -v4, v2, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v4, v3, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX11-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX11-TRUE16-NEXT: .LBB0_8: ; %Flow19
-; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.h
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: ; %bb.7: ; %Flow
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v5, v3, v4
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x8000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v2, v3
+; GFX11-TRUE16-NEXT: .LBB0_9: ; %Flow19
+; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v1.l|
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v3.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: frem_f16:
@@ -778,41 +803,42 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s0, s1, s0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -820,23 +846,47 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1150-TRUE16-NEXT: s_add_i32 s0, s0, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX1150-TRUE16-NEXT: ; %bb.7: ; %Flow
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, s0
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1150-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX1150-TRUE16-NEXT: v_and_b32_e32 v3, 0x8000, v0
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1150-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB0_8: ; %Flow19
+; GFX1150-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; GFX1150-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX1150-TRUE16-NEXT: .LBB0_9: ; %Flow19
; GFX1150-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1150-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
@@ -1012,41 +1062,42 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1200-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s0, s1, s0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1054,26 +1105,50 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX1200-TRUE16-NEXT: ; %bb.7: ; %Flow
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, s0
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1200-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1200-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB0_8: ; %Flow19
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX1200-TRUE16-NEXT: v_and_b32_e32 v3, 0x8000, v0
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; GFX1200-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX1200-TRUE16-NEXT: .LBB0_9: ; %Flow19
; GFX1200-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1200-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -6045,42 +6120,43 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v4
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v3
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v3
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v6, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v3
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v4, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
-; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_8
; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -6088,22 +6164,44 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v4, v3, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX11-TRUE16-NEXT: ; %bb.7: ; %Flow55
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-TRUE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: v_fma_f32 v2, -v5, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v5, v3, v4
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x8000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX11-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX11-TRUE16-NEXT: .LBB9_8:
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: .LBB9_9:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -6111,81 +6209,104 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, |v4.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v6
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_10
-; GFX11-TRUE16-NEXT: ; %bb.9: ; %frem.else
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_11
+; GFX11-TRUE16-NEXT: ; %bb.10: ; %frem.else
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB9_11
-; GFX11-TRUE16-NEXT: .LBB9_10:
+; GFX11-TRUE16-NEXT: s_branch .LBB9_12
+; GFX11-TRUE16-NEXT: .LBB9_11:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-TRUE16-NEXT: .LBB9_11: ; %Flow53
+; GFX11-TRUE16-NEXT: .LBB9_12: ; %Flow53
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
-; GFX11-TRUE16-NEXT: ; %bb.12: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.compute
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v7
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v6
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v9, v6
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v5, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v9, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v8
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, -1, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v7, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v7, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, null, v6, v6, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v7, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v10, v9
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v6, 1.0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, null, v6, v6, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v11, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v9, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v8
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v9, v10, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v10
+; GFX11-TRUE16-NEXT: v_fma_f32 v12, -v10, v11, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v7, v10
-; GFX11-TRUE16-NEXT: v_fma_f32 v12, -v9, v11, v7
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v11, v12, v11
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v12, v8, v11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v11, v12, v10
-; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v9, v11, v7
+; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v10, v12, v8
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v12, v13, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v10, v12, v8
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v7, v7, v10, v11
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v7, v7, v6, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v8, v8, v11, v12
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX11-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB9_15: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v5, v7
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v7
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v10, v8
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v7, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v7, v6, v10
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, v7, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_15
+; GFX11-TRUE16-NEXT: ; %bb.16: ; %Flow
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v10
+; GFX11-TRUE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, -10, v9
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v7, v8
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v8, v8
-; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v8, v6, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, v5, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v8, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v7, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v6, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0x8000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v5.l, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0x7fff, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
-; GFX11-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-TRUE16-NEXT: .LBB9_16: ; %Flow54
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX11-TRUE16-NEXT: .LBB9_18: ; %Flow54
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
@@ -6464,41 +6585,42 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v3, v3
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v0
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_8
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s5, s6, s5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -6506,107 +6628,156 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1150-TRUE16-NEXT: s_add_i32 s5, s5, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s5, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1150-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX1150-TRUE16-NEXT: ; %bb.7: ; %Flow55
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, s5
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-TRUE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1150-TRUE16-NEXT: s_and_b32 s5, s4, 0x8000
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX1150-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: .LBB9_8:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
+; GFX1150-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX1150-TRUE16-NEXT: v_or_b32_e32 v0, s5, v0
+; GFX1150-TRUE16-NEXT: .LBB9_9:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s6, s5, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s7, s4
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1150-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
-; GFX1150-TRUE16-NEXT: ; %bb.9: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s8, s7
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_11
+; GFX1150-TRUE16-NEXT: ; %bb.10: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s8, s7
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s6
; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
-; GFX1150-TRUE16-NEXT: s_mov_b32 s8, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB9_11
-; GFX1150-TRUE16-NEXT: .LBB9_10:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s8, -1
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s9
+; GFX1150-TRUE16-NEXT: s_mov_b32 s9, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB9_12
+; GFX1150-TRUE16-NEXT: .LBB9_11:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s9, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB9_11: ; %Flow53
+; GFX1150-TRUE16-NEXT: .LBB9_12: ; %Flow53
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s8, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
-; GFX1150-TRUE16-NEXT: ; %bb.12: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s7
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v1
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s7, s6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX1150-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s7, s8, s7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: s_add_i32 s7, s7, 11
+; GFX1150-TRUE16-NEXT: .LBB9_15: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
-; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, -11
-; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, v3
+; GFX1150-TRUE16-NEXT: s_add_i32 s7, s7, -11
+; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s7, 11
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_15
+; GFX1150-TRUE16-NEXT: ; %bb.16: ; %Flow
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, s7
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-TRUE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1150-TRUE16-NEXT: s_and_b32 s6, s6, 0x8000
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
-; GFX1150-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB9_16: ; %Flow54
+; GFX1150-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; GFX1150-TRUE16-NEXT: v_or_b32_e32 v1, s6, v1
+; GFX1150-TRUE16-NEXT: .LBB9_18: ; %Flow54
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -6911,41 +7082,42 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v3, v3
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_8
; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s5, s6, s5
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -6953,119 +7125,169 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s5, s5, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s5, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX1200-TRUE16-NEXT: ; %bb.7: ; %Flow55
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, s5
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-TRUE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-TRUE16-NEXT: s_and_b32 s5, s4, 0x8000
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX1200-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: .LBB9_8:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: v_or_b32_e32 v0, s5, v0
+; GFX1200-TRUE16-NEXT: .LBB9_9:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
-; GFX1200-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s6, s5, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s4
+; GFX1200-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
-; GFX1200-TRUE16-NEXT: ; %bb.9: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s8, s7
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_11
+; GFX1200-TRUE16-NEXT: ; %bb.10: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s8, s7
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s6
; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
-; GFX1200-TRUE16-NEXT: s_mov_b32 s8, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB9_11
-; GFX1200-TRUE16-NEXT: .LBB9_10:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s8, -1
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s9
+; GFX1200-TRUE16-NEXT: s_mov_b32 s9, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB9_12
+; GFX1200-TRUE16-NEXT: .LBB9_11:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s9, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB9_11: ; %Flow53
+; GFX1200-TRUE16-NEXT: .LBB9_12: ; %Flow53
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s8, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
-; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s7
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v4
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v1
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s7, s6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX1200-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s7, s8, s7
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s7, s7, 11
+; GFX1200-TRUE16-NEXT: .LBB9_15: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s7, s7, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s7, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_15
+; GFX1200-TRUE16-NEXT: ; %bb.16: ; %Flow
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, s7
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1200-TRUE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1200-TRUE16-NEXT: s_and_b32 s6, s6, 0x8000
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
-; GFX1200-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB9_16: ; %Flow54
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: v_or_b32_e32 v1, s6, v1
+; GFX1200-TRUE16-NEXT: .LBB9_18: ; %Flow54
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -9190,353 +9412,447 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
-; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v2, s[4:5] offset:32
+; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v0, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v0, s[4:5] offset:32
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, |v0.l|
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v5, |v2.l|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v6, v5
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v4, |v0.l|
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v5, v4
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else86
-; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v6, v5
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0x8000, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v5, v4
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v2.l, v3.l, vcc_lo
; GFX11-TRUE16-NEXT: s_branch .LBB10_3
; GFX11-TRUE16-NEXT: .LBB10_2:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, -1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: .LBB10_3: ; %Flow135
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s4, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v6
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v5
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v7
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, -1, v5
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v6, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, null, v5, v5, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v6, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v5
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v4
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v3, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v4
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v7, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v6
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v5, 1.0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v7, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v6
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v8, v9, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v9
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v6, v9
-; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v8, v10, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v8, v10, v6
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v5, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_8
; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
-; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
+; GFX11-TRUE16-NEXT: s_sub_i32 s4, s4, s5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 11
; GFX11-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v4, v6
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
-; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, -11
+; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s4, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v7, v7
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v7, v5, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, v4, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v8, v6
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v5, v4, v8
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX11-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
-; GFX11-TRUE16-NEXT: .LBB10_8:
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, |v5.l|
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, |v6.l|
+; GFX11-TRUE16-NEXT: ; %bb.7: ; %Flow133
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, s4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v8
+; GFX11-TRUE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, v5, v6
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v6, v4, v5
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0x8000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_10
-; GFX11-TRUE16-NEXT: ; %bb.9: ; %frem.else53
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: .LBB10_9:
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, |s3|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, |v4.l|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v6
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_11
+; GFX11-TRUE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s3
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_11
-; GFX11-TRUE16-NEXT: .LBB10_10:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-TRUE16-NEXT: .LBB10_11: ; %Flow131
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, s3, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB10_12
+; GFX11-TRUE16-NEXT: .LBB10_11:
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, -1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
+; GFX11-TRUE16-NEXT: .LBB10_12: ; %Flow131
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
-; GFX11-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v9
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v9, v8
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s4, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v7
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v9, v6
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v5, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v9, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, null, v6, v6, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v11, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v9, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v8
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
+; GFX11-TRUE16-NEXT: s_denorm_mode 15
+; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_fma_f32 v12, -v10, v11, 1.0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v11, v12, v11
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v12, v8, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v10, v12, v8
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v12, v13, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v10, v12, v8
+; GFX11-TRUE16-NEXT: s_denorm_mode 12
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v8, v8, v11, v12
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX11-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX11-TRUE16-NEXT: s_sub_i32 s4, s4, s5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 11
+; GFX11-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body60
+; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v7
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, -11
+; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s4, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v10, v8
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v7, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v7, v6, v10
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, v7, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v8
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v9, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v9, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v11, null, v8, v8, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v9, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX11-TRUE16-NEXT: ; %bb.16: ; %Flow129
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, s4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v10
+; GFX11-TRUE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, -10, v9
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0x8000
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v7, v8
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v8, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v8, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v7, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v6, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v5.l, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0x7fff, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, s4, v5
+; GFX11-TRUE16-NEXT: .LBB10_18:
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, |s2|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, |v1.l|
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v8, v7
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_20
+; GFX11-TRUE16-NEXT: ; %bb.19: ; %frem.else20
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, s2, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB10_21
+; GFX11-TRUE16-NEXT: .LBB10_20:
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, -1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6
+; GFX11-TRUE16-NEXT: .LBB10_21: ; %Flow127
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s4, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX11-TRUE16-NEXT: ; %bb.22: ; %frem.compute19
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v8
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v10, v7
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v9, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v6, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, v7
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v10, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v11, null, v7, v7, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v12, v11
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, vcc_lo, 1.0, v8, 1.0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v10, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v10, v9
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, vcc_lo, 1.0, v7, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v11, v12, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v12, v13, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v12, v13, v12
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v13, v9, v12
-; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v11, v13, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v11, v13, v9
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v13, v14, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v11, v13, v9
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_div_fmas_f32 v9, v9, v12, v13
; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v10
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v9, v9, v8, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
-; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v9, v9, v7, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX11-TRUE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT: s_sub_i32 s4, s4, s5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 11
+; GFX11-TRUE16-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v7, v9
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
-; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, v8
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, -11
+; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s4, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v10, v10
-; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v10, v8, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, v7, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v11, v9
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v8, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v8, v7, v11
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, v8, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX11-TRUE16-NEXT: ; %bb.25: ; %Flow125
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, v11
+; GFX11-TRUE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, -10, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s2, 0x8000
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v8, v9
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v9, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v9, v7, v8
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, v8, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v7, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v6.l, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0x7fff, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
-; GFX11-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-TRUE16-NEXT: .LBB10_16:
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v10, |v1.l|
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, |v3.l|
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, s4, v6
+; GFX11-TRUE16-NEXT: .LBB10_27:
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s2, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v10, |s4|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, |v7.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v10, v9
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_18
-; GFX11-TRUE16-NEXT: ; %bb.17: ; %frem.else20
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_29
+; GFX11-TRUE16-NEXT: ; %bb.28: ; %frem.else
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s4
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s5, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_19
-; GFX11-TRUE16-NEXT: .LBB10_18:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, s4, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB10_30
+; GFX11-TRUE16-NEXT: .LBB10_29:
+; GFX11-TRUE16-NEXT: s_mov_b32 s5, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-TRUE16-NEXT: .LBB10_19: ; %Flow127
+; GFX11-TRUE16-NEXT: .LBB10_30: ; %Flow123
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX11-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s5, 1
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX11-TRUE16-NEXT: ; %bb.31: ; %frem.compute
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v10
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v10, v9
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v11
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, -1, v9
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v10, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v10, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v12, null, v9, v9, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v10, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v13, v12
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v9, 1.0
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v12, v9
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v10, v8, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v9
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v12, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v11
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v13, null, v9, v9, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, -1, v8
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v14, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v12, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v12, v11
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v12, v13, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v13, v14, v13
+; GFX11-TRUE16-NEXT: v_fma_f32 v15, -v13, v14, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v10, v13
-; GFX11-TRUE16-NEXT: v_fma_f32 v15, -v12, v14, v10
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v14, v15, v14
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v15, v11, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v14, v15, v13
-; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v12, v14, v10
+; GFX11-TRUE16-NEXT: v_fma_f32 v16, -v13, v15, v11
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v15, v16, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v13, v15, v11
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v10, v10, v13, v14
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v10, v10, v9, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX11-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
-; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v11, v11, v14, v15
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX11-TRUE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: s_sub_i32 s5, s5, s6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, 11
+; GFX11-TRUE16-NEXT: .LBB10_33: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v8, v10
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
-; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, -11
+; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s5, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v13, v11
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v10, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v10, v9, v13
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, v10, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v10, v10, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_33
+; GFX11-TRUE16-NEXT: ; %bb.34: ; %Flow
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, s5
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v13
+; GFX11-TRUE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, -10, v12
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s4, 0x8000
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v10, v10, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v10, v11
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v11, v11
-; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v11, v9, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, v8, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
-; GFX11-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-TRUE16-NEXT: .LBB10_24:
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v13, |v9.l|
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v12, |v10.l|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v13, v12
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_26
-; GFX11-TRUE16-NEXT: ; %bb.25: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v13, v12
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_27
-; GFX11-TRUE16-NEXT: .LBB10_26:
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-TRUE16-NEXT: .LBB10_27: ; %Flow123
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
-; GFX11-TRUE16-NEXT: ; %bb.28: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v13
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v13
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v13, v12
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v12, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v14
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v12
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, -1, v12
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v12, v13, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v15, null, v12, v12, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v13, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v16, v15
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v13, vcc_lo, 1.0, v12, 1.0
-; GFX11-TRUE16-NEXT: s_denorm_mode 15
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v17, -v15, v16, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v16, v17, v16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v17, v13, v16
-; GFX11-TRUE16-NEXT: v_fma_f32 v18, -v15, v17, v13
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v11, v9, v10
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, v10, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v17, v18, v16
-; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v15, v17, v13
-; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v13, v13, v16, v17
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v14
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v13, v13, v12, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX11-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
-; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
-; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v11, v13
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
-; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v9, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v14, v14
-; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v14, v12, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, v11, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v8.l, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0x7fff, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
-; GFX11-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-TRUE16-NEXT: .LBB10_32: ; %Flow124
-; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, s5, v8
+; GFX11-TRUE16-NEXT: .LBB10_36: ; %Flow124
+; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s5, 0x7c00, |v2.l|
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s3, 0x7c00, |s3|
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |s2|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v3.l, s5
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v5.l, s3
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v5.l|
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v3.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v7.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v1.l|
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v8.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v9.l|
+; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v7.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v6.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |s4|
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v11.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v8.l, s2
; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -10017,41 +10333,42 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s8
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v2
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v3, v3
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v0
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_8
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s8, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -10059,273 +10376,372 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1150-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX1150-TRUE16-NEXT: ; %bb.7: ; %Flow133
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, s6
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-TRUE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1150-TRUE16-NEXT: s_and_b32 s6, s5, 0x8000
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX1150-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: .LBB10_8:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
+; GFX1150-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX1150-TRUE16-NEXT: v_or_b32_e32 v0, s6, v0
+; GFX1150-TRUE16-NEXT: .LBB10_9:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s8, s6, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s5
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1150-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
-; GFX1150-TRUE16-NEXT: ; %bb.9: ; %frem.else53
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_11
+; GFX1150-TRUE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
-; GFX1150-TRUE16-NEXT: s_mov_b32 s10, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_11
-; GFX1150-TRUE16-NEXT: .LBB10_10:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s10, -1
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s11
+; GFX1150-TRUE16-NEXT: s_mov_b32 s11, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_12
+; GFX1150-TRUE16-NEXT: .LBB10_11:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB10_11: ; %Flow131
+; GFX1150-TRUE16-NEXT: .LBB10_12: ; %Flow131
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s10, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s10, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
-; GFX1150-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s9
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s10
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v3
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v1
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s8, s9, s8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX1150-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_add_i32 s8, s8, 11
-; GFX1150-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
+; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, 11
+; GFX1150-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body60
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
-; GFX1150-TRUE16-NEXT: s_add_i32 s8, s8, -11
-; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s8, 11
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, v3
+; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, -11
+; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX1150-TRUE16-NEXT: ; %bb.16: ; %Flow129
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, s9
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-TRUE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1150-TRUE16-NEXT: s_and_b32 s8, s8, 0x8000
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
-; GFX1150-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB10_16:
+; GFX1150-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; GFX1150-TRUE16-NEXT: v_or_b32_e32 v1, s8, v1
+; GFX1150-TRUE16-NEXT: .LBB10_18:
; GFX1150-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1150-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s8
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
-; GFX1150-TRUE16-NEXT: ; %bb.17: ; %frem.else20
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_20
+; GFX1150-TRUE16-NEXT: ; %bb.19: ; %frem.else20
; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
; GFX1150-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_19
-; GFX1150-TRUE16-NEXT: .LBB10_18:
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_21
+; GFX1150-TRUE16-NEXT: .LBB10_20:
; GFX1150-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB10_19: ; %Flow127
+; GFX1150-TRUE16-NEXT: .LBB10_21: ; %Flow127
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1150-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX1150-TRUE16-NEXT: ; %bb.22: ; %frem.compute19
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s9
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v2
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX1150-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX1150-TRUE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1150-TRUE16-NEXT: ; %bb.25: ; %Flow125
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, s9
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1150-TRUE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1150-TRUE16-NEXT: s_and_b32 s9, s7, 0x8000
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
-; GFX1150-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB10_24:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
+; GFX1150-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; GFX1150-TRUE16-NEXT: v_or_b32_e32 v2, s9, v2
+; GFX1150-TRUE16-NEXT: .LBB10_27:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s10, s9, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s11, s7
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1150-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
-; GFX1150-TRUE16-NEXT: ; %bb.25: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s12, s11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_29
+; GFX1150-TRUE16-NEXT: ; %bb.28: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s12, s11
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
; GFX1150-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
-; GFX1150-TRUE16-NEXT: s_mov_b32 s12, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_27
-; GFX1150-TRUE16-NEXT: .LBB10_26:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s12, -1
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s13
+; GFX1150-TRUE16-NEXT: s_mov_b32 s13, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_30
+; GFX1150-TRUE16-NEXT: .LBB10_29:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s13, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-TRUE16-NEXT: .LBB10_27: ; %Flow123
+; GFX1150-TRUE16-NEXT: .LBB10_30: ; %Flow123
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
-; GFX1150-TRUE16-NEXT: ; %bb.28: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s11
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: s_and_b32 s13, s13, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s13, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s13, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX1150-TRUE16-NEXT: ; %bb.31: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s11
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s12
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s11, v5
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v4, v4, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v6, v6
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v4, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v5, v3, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s12, v6
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s11, v3
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v7, v3
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v6
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v8, v9, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v10, v6, v9
+; GFX1150-TRUE16-NEXT: v_fma_f32 v11, -v8, v10, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v9
+; GFX1150-TRUE16-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX1150-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s10, s11, s10
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX1150-TRUE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s11, s12, s11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_add_i32 s10, s10, 11
-; GFX1150-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: s_add_i32 s11, s11, 11
+; GFX1150-TRUE16-NEXT: .LBB10_33: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
-; GFX1150-TRUE16-NEXT: s_add_i32 s10, s10, -11
-; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s10, 11
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v8, v5
+; GFX1150-TRUE16-NEXT: s_add_i32 s11, s11, -11
+; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s11, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v8, v6
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT: v_fma_f32 v5, v5, v4, v8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v7, v5, v4
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_33
+; GFX1150-TRUE16-NEXT: ; %bb.34: ; %Flow
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v7, s11
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, v8
+; GFX1150-TRUE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
+; GFX1150-TRUE16-NEXT: s_and_b32 s10, s10, 0x8000
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v5, v5, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v6, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v3, v6, v4
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v6, v3, v4
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v4, v3
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
-; GFX1150-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-TRUE16-NEXT: .LBB10_32: ; %Flow124
+; GFX1150-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff, v3
+; GFX1150-TRUE16-NEXT: v_or_b32_e32 v3, s10, v3
+; GFX1150-TRUE16-NEXT: .LBB10_36: ; %Flow124
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1150-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -10878,41 +11294,42 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s8
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v2
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v3, v3
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_8
; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s8, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -10920,119 +11337,169 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX1200-TRUE16-NEXT: ; %bb.7: ; %Flow133
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, s6
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-TRUE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-TRUE16-NEXT: s_and_b32 s6, s5, 0x8000
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX1200-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: .LBB10_8:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: v_or_b32_e32 v0, s6, v0
+; GFX1200-TRUE16-NEXT: .LBB10_9:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
-; GFX1200-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s8, s6, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s5
+; GFX1200-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
-; GFX1200-TRUE16-NEXT: ; %bb.9: ; %frem.else53
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_11
+; GFX1200-TRUE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
-; GFX1200-TRUE16-NEXT: s_mov_b32 s10, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_11
-; GFX1200-TRUE16-NEXT: .LBB10_10:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s10, -1
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s11
+; GFX1200-TRUE16-NEXT: s_mov_b32 s11, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_12
+; GFX1200-TRUE16-NEXT: .LBB10_11:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB10_11: ; %Flow131
+; GFX1200-TRUE16-NEXT: .LBB10_12: ; %Flow131
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s10, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s10, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
-; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s9
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s10
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v3
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v4
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v1
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s8, s9, s8
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX1200-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s8, s8, 11
-; GFX1200-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
+; GFX1200-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body60
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s8, s8, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s8, 11
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX1200-TRUE16-NEXT: ; %bb.16: ; %Flow129
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, s9
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1200-TRUE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1200-TRUE16-NEXT: s_and_b32 s8, s8, 0x8000
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
-; GFX1200-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB10_16:
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: v_or_b32_e32 v1, s8, v1
+; GFX1200-TRUE16-NEXT: .LBB10_18:
; GFX1200-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1200-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -11041,8 +11508,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
-; GFX1200-TRUE16-NEXT: ; %bb.17: ; %frem.else20
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_20
+; GFX1200-TRUE16-NEXT: ; %bb.19: ; %frem.else20
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
@@ -11050,172 +11517,223 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
; GFX1200-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_19
-; GFX1200-TRUE16-NEXT: .LBB10_18:
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_21
+; GFX1200-TRUE16-NEXT: .LBB10_20:
; GFX1200-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB10_19: ; %Flow127
+; GFX1200-TRUE16-NEXT: .LBB10_21: ; %Flow127
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1200-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX1200-TRUE16-NEXT: ; %bb.22: ; %frem.compute19
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s9
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v2
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1200-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX1200-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX1200-TRUE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1200-TRUE16-NEXT: ; %bb.25: ; %Flow125
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, s9
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1200-TRUE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1200-TRUE16-NEXT: s_and_b32 s9, s7, 0x8000
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
-; GFX1200-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB10_24:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: v_or_b32_e32 v2, s9, v2
+; GFX1200-TRUE16-NEXT: .LBB10_27:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX1200-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s10, s9, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s7
+; GFX1200-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
-; GFX1200-TRUE16-NEXT: ; %bb.25: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s12, s11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_29
+; GFX1200-TRUE16-NEXT: ; %bb.28: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s12, s11
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
; GFX1200-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
-; GFX1200-TRUE16-NEXT: s_mov_b32 s12, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_27
-; GFX1200-TRUE16-NEXT: .LBB10_26:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s12, -1
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s13
+; GFX1200-TRUE16-NEXT: s_mov_b32 s13, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_30
+; GFX1200-TRUE16-NEXT: .LBB10_29:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s13, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-TRUE16-NEXT: .LBB10_27: ; %Flow123
+; GFX1200-TRUE16-NEXT: .LBB10_30: ; %Flow123
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s13, s13, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s13, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
-; GFX1200-TRUE16-NEXT: ; %bb.28: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s11
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s13, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX1200-TRUE16-NEXT: ; %bb.31: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s11
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s12
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s11, v5
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v4, v4, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v6, v6
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v4, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v5, v3, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s12, v6
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s11, v3
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v7, v3
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v6
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v8, v9, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v9
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v10, v6, v9
+; GFX1200-TRUE16-NEXT: v_fma_f32 v11, -v8, v10, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v9
+; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX1200-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s10, s11, s10
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX1200-TRUE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s11, s12, s11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s10, s10, 11
-; GFX1200-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s11, s11, 11
+; GFX1200-TRUE16-NEXT: .LBB10_33: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v8, v5
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s10, s10, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s11, s11, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s10, 11
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s11, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v8, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v5, v5, v4, v8
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v7, v5, v4
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_33
+; GFX1200-TRUE16-NEXT: ; %bb.34: ; %Flow
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, s11
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v8
+; GFX1200-TRUE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
+; GFX1200-TRUE16-NEXT: s_and_b32 s10, s10, 0x8000
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v5, v5, v7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v6, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v3, v6, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v3, v4
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
-; GFX1200-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-TRUE16-NEXT: .LBB10_32: ; %Flow124
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v4, v3
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff, v3
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: v_or_b32_e32 v3, s10, v3
+; GFX1200-TRUE16-NEXT: .LBB10_36: ; %Flow124
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
index 265cbcb940273..eabbeb1122d00 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
@@ -835,16 +835,17 @@ define amdgpu_kernel void @round_f16(ptr addrspace(1) %out, i32 %x.arg) #0 {
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sub_f16_e32 v0.h, s2, v0.l
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0x8000
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s3, |v0.h|, 0.5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0, 0x3c00, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, 0x3c00, s3
; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v2, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, s2, v1
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
@@ -997,27 +998,31 @@ define amdgpu_kernel void @round_v2f16(ptr addrspace(1) %out, i32 %in.arg) #0 {
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s2, 16
-; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.h, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, s3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_sub_f16_e32 v1.l, s2, v0.l
-; GFX11-TRUE16-NEXT: v_sub_f16_e32 v1.h, s3, v0.h
-; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.h, s2
+; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_sub_f16_e32 v1.h, s2, v0.h
+; GFX11-TRUE16-NEXT: v_sub_f16_e32 v1.l, s3, v0.l
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, 0x8000
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0x8000
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s6, |v1.l|, 0.5
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s7, |v1.h|, 0.5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s2
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0, 0x3c00, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0, 0x3c00, s7
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s6, |v1.l|, 0.5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v2, v1
-; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v3, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0, 0x3c00, s7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, 0x3c00, s6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.h, v0.h, v2.l
-; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, s2, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, s3, v1
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f16_e32 v1.h, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_add_f16_e32 v1.l, v0.h, v2.l
+; GFX11-TRUE16-NEXT: buffer_store_b32 v1, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: round_v2f16:
diff --git a/llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll b/llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
new file mode 100644
index 0000000000000..e8945500ee08e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck %s
+
+; An f16 value merged by a PHI across a wave-uniform branch is held in a 32-bit
+; register. The true16 fcopysign pattern used to feed it to a REG_SEQUENCE lo16
+; slot, naming a 16-bit slot for a 32-bit operand; DetectDeadLanes read that as
+; a lane-for-lane transfer and marked the value dead, so %big was emitted empty
+; and the stored result was undefined.
+;
+; The uniform case now selects a scalar and/and/or sequence, which needs no
+; REG_SEQUENCE at all, so %big keeps its computation. Where an operand happens
+; to land in a VGPR anyway, SIFixSGPRCopies sinks the sequence to VALU rather
+; than reading it back with v_readfirstlane_b32.
+
+define amdgpu_kernel void @uniform_f16_phi_copysign(half %x, ptr addrspace(1) %out) {
+; CHECK-LABEL: uniform_f16_phi_copysign:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; CHECK-NEXT: s_mov_b64 s[64:65], 0
+; CHECK-NEXT: v_nop
+; CHECK-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; CHECK-NEXT: s_load_b32 s0, s[4:5], 0x0 nv
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: s_cmp_nle_f16 s0, 0x3800
+; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
+; CHECK-NEXT: ; %bb.1: ; %small
+; CHECK-NEXT: s_mul_f16 s1, s0, s0
+; CHECK-NEXT: s_mov_b32 s2, 0
+; CHECK-NEXT: s_branch .LBB0_3
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: s_mov_b32 s2, -1
+; CHECK-NEXT: ; implicit-def: $sgpr1
+; CHECK-NEXT: .LBB0_3: ; %Flow
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; CHECK-NEXT: s_and_b32 s2, s2, exec_lo
+; CHECK-NEXT: s_cselect_b32 s2, 1, 0
+; CHECK-NEXT: s_cmp_lg_u32 s2, 1
+; CHECK-NEXT: s_cbranch_scc1 .LBB0_5
+; CHECK-NEXT: ; %bb.4: ; %big
+; CHECK-NEXT: s_cvt_f32_f16 s1, s0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0.5
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
+; CHECK-NEXT: v_s_sqrt_f32 s1, s1
+; CHECK-NEXT: v_nop
+; CHECK-NEXT: v_fma_mixlo_f16 v0, s1, s0, v0 op_sel_hi:[0,1,0]
+; CHECK-NEXT: s_branch .LBB0_6
+; CHECK-NEXT: .LBB0_5:
+; CHECK-NEXT: v_mov_b32_e32 v0, s1
+; CHECK-NEXT: .LBB0_6: ; %exit
+; CHECK-NEXT: s_load_b64 s[2:3], s[4:5], 0x8 nv
+; CHECK-NEXT: s_mov_b32 s1, 0x7fff
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_bitop2_b32 v0, s1, v0 bitop3:0x40
+; CHECK-NEXT: s_and_b32 s0, s0, 0x8000
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; CHECK-NEXT: v_or_b32_e32 v0, s0, v0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: global_store_b16 v1, v0, s[2:3]
+; CHECK-NEXT: s_endpgm
+entry:
+ %c = fcmp ugt half %x, 0xH3800
+ br i1 %c, label %big, label %small
+
+small:
+ %s = fmul half %x, %x
+ br label %exit
+
+big:
+ %e = fpext half %x to float
+ %q = call float @llvm.amdgcn.sqrt.f32(float %e)
+ %m = call float @llvm.fmuladd.f32(float %q, float %e, float 5.000000e-01)
+ %t = fptrunc float %m to half
+ br label %exit
+
+exit:
+ %p = phi half [ %s, %small ], [ %t, %big ]
+ %r = call half @llvm.copysign.f16(half %p, half %x)
+ store half %r, ptr addrspace(1) %out
+ ret void
+}
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