[llvm] [DAG] SimplifyMultipleUseDemandedBits - skip ISD::SRA nodes with already enough sign bits (PR #178916)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 28 09:59:55 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/178916
>From 2f84dc8b1d7bc0a932a231d18799c573337207bc Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 30 Jan 2026 16:45:16 +0000
Subject: [PATCH] [DAG] SimplifyMultipleUseDemandedBits - skip ISD::SRA nodes
with already enough sign bits
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 9 +
.../CodeGen/AArch64/arm64-neon-mul-div-cte.ll | 12 +-
llvm/test/CodeGen/AArch64/combine-sdiv.ll | 44 +-
llvm/test/CodeGen/AArch64/rem-by-const.ll | 86 +-
.../AArch64/sdiv-by-const-promoted-ops.ll | 40 +-
llvm/test/CodeGen/AArch64/srem-vector-lkk.ll | 81 +-
.../AMDGPU/amdgpu-codegenprepare-idiv.ll | 55 +-
llvm/test/CodeGen/AMDGPU/sdiv.ll | 99 +-
llvm/test/CodeGen/AMDGPU/sdiv64.ll | 12 +-
llvm/test/CodeGen/RISCV/div-pow2.ll | 4 +
.../RISCV/rvv/fixed-vectors-extract.ll | 38 +-
.../CodeGen/RISCV/rvv/fixed-vectors-int.ll | 51 +-
llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll | 193 ++--
llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll | 226 ++---
llvm/test/CodeGen/X86/scmp.ll | 899 +++++++++---------
llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll | 268 +++---
llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 200 ++--
llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 166 ++--
18 files changed, 1200 insertions(+), 1283 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 868171e45be86..0fd627b9a8ef5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -971,6 +971,15 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
}
break;
}
+ case ISD::SRA: {
+ // If we only want bits that already match the signbit then we don't need
+ // to shift.
+ SDValue Op0 = Op.getOperand(0);
+ unsigned HiDemandedBits = BitWidth - DemandedBits.countr_zero();
+ if (DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1) >= HiDemandedBits)
+ return Op0;
+ break;
+ }
case ISD::SETCC: {
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll b/llvm/test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll
index 7aa6b77cf3524..6c66a77e88472 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll
@@ -8,9 +8,9 @@ define <16 x i8> @div16xi8(<16 x i8> %x) {
; CHECK-SD-NEXT: movi v1.16b, #41
; CHECK-SD-NEXT: smull2 v2.8h, v0.16b, v1.16b
; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b
-; CHECK-SD-NEXT: uzp2 v0.16b, v0.16b, v2.16b
-; CHECK-SD-NEXT: sshr v0.16b, v0.16b, #2
-; CHECK-SD-NEXT: usra v0.16b, v0.16b, #7
+; CHECK-SD-NEXT: uzp2 v1.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT: sshr v0.16b, v1.16b, #2
+; CHECK-SD-NEXT: usra v0.16b, v1.16b, #7
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: div16xi8:
@@ -35,9 +35,9 @@ define <8 x i16> @div8xi16(<8 x i16> %x) {
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h
-; CHECK-SD-NEXT: sshr v0.8h, v0.8h, #12
-; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT: add v1.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: sshr v0.8h, v1.8h, #12
+; CHECK-SD-NEXT: usra v0.8h, v1.8h, #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: div8xi16:
diff --git a/llvm/test/CodeGen/AArch64/combine-sdiv.ll b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
index b160333edb487..c7cf8700f7c26 100644
--- a/llvm/test/CodeGen/AArch64/combine-sdiv.ll
+++ b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
@@ -955,10 +955,10 @@ define <8 x i16> @combine_vec_sdiv_nonuniform2(<8 x i16> %x) {
; CHECK-SD-NEXT: adrp x8, .LCPI29_1
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI29_1]
-; CHECK-SD-NEXT: uzp2 v0.8h, v0.8h, v2.8h
-; CHECK-SD-NEXT: sshl v0.8h, v0.8h, v1.8h
-; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT: uzp2 v1.8h, v0.8h, v2.8h
+; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI29_1]
+; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: usra v0.8h, v1.8h, #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform2:
@@ -987,10 +987,10 @@ define <8 x i16> @combine_vec_sdiv_nonuniform3(<8 x i16> %x) {
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
-; CHECK-SD-NEXT: sshl v0.8h, v0.8h, v1.8h
-; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT: add v1.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI30_1]
+; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: usra v0.8h, v1.8h, #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform3:
@@ -1020,10 +1020,10 @@ define <8 x i16> @combine_vec_sdiv_nonuniform4(<8 x i16> %x) {
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-SD-NEXT: sub v0.8h, v1.8h, v0.8h
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI31_1]
-; CHECK-SD-NEXT: sshl v0.8h, v0.8h, v1.8h
-; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT: sub v1.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI31_1]
+; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: usra v0.8h, v1.8h, #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform4:
@@ -1058,7 +1058,7 @@ define <8 x i16> @combine_vec_sdiv_nonuniform5(<8 x i16> %x) {
; CHECK-SD-NEXT: mla v1.8h, v0.8h, v2.8h
; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI32_2]
; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h
-; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT: usra v0.8h, v1.8h, #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform5:
@@ -1085,21 +1085,21 @@ define <8 x i16> @combine_vec_sdiv_nonuniform6(<8 x i16> %x) {
; CHECK-SD-LABEL: combine_vec_sdiv_nonuniform6:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: adrp x8, .LCPI33_0
+; CHECK-SD-NEXT: adrp x9, .LCPI33_3
; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI33_0]
; CHECK-SD-NEXT: adrp x8, .LCPI33_1
+; CHECK-SD-NEXT: ldr q3, [x9, :lo12:.LCPI33_3]
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI33_1]
; CHECK-SD-NEXT: adrp x8, .LCPI33_2
; CHECK-SD-NEXT: mla v1.8h, v0.8h, v2.8h
-; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI33_2]
-; CHECK-SD-NEXT: adrp x8, .LCPI33_3
-; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI33_3]
-; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h
-; CHECK-SD-NEXT: ushr v1.8h, v0.8h, #15
-; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-SD-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI33_2]
+; CHECK-SD-NEXT: ushr v0.8h, v1.8h, #15
+; CHECK-SD-NEXT: sshl v1.8h, v1.8h, v2.8h
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform6:
@@ -1172,14 +1172,14 @@ define <16 x i8> @pr38658(<16 x i8> %x) {
; CHECK-SD-NEXT: adrp x8, .LCPI35_0
; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI35_0]
; CHECK-SD-NEXT: adrp x8, .LCPI35_1
+; CHECK-SD-NEXT: ldr q3, [x8, :lo12:.LCPI35_1]
; CHECK-SD-NEXT: smull2 v2.8h, v0.16b, v1.16b
; CHECK-SD-NEXT: smull v1.8h, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp2 v1.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: add v0.16b, v1.16b, v0.16b
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI35_1]
-; CHECK-SD-NEXT: sshl v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
; CHECK-SD-NEXT: ushr v2.16b, v0.16b, #7
+; CHECK-SD-NEXT: sshl v0.16b, v0.16b, v3.16b
; CHECK-SD-NEXT: mov v1.b[15], v2.b[15]
; CHECK-SD-NEXT: add v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/rem-by-const.ll b/llvm/test/CodeGen/AArch64/rem-by-const.ll
index 187ab1d481a27..23b1867c438f7 100644
--- a/llvm/test/CodeGen/AArch64/rem-by-const.ll
+++ b/llvm/test/CodeGen/AArch64/rem-by-const.ll
@@ -868,14 +868,14 @@ define <4 x i8> @sv4i8_7(<4 x i8> %d, <4 x i8> %e) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8
; CHECK-SD-NEXT: mov w8, #18725 // =0x4925
-; CHECK-SD-NEXT: movi v2.4h, #7
+; CHECK-SD-NEXT: movi v3.4h, #7
; CHECK-SD-NEXT: dup v1.4h, w8
; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: shrn v1.4h, v1.4s, #16
-; CHECK-SD-NEXT: sshr v1.4h, v1.4h, #1
-; CHECK-SD-NEXT: usra v1.4h, v1.4h, #15
-; CHECK-SD-NEXT: mls v0.4h, v1.4h, v2.4h
+; CHECK-SD-NEXT: sshr v2.4h, v1.4h, #1
+; CHECK-SD-NEXT: usra v2.4h, v1.4h, #15
+; CHECK-SD-NEXT: mls v0.4h, v2.4h, v3.4h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv4i8_7:
@@ -904,14 +904,14 @@ define <4 x i8> @sv4i8_100(<4 x i8> %d, <4 x i8> %e) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8
; CHECK-SD-NEXT: mov w8, #5243 // =0x147b
-; CHECK-SD-NEXT: movi v2.4h, #100
+; CHECK-SD-NEXT: movi v3.4h, #100
; CHECK-SD-NEXT: dup v1.4h, w8
; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: shrn v1.4h, v1.4s, #16
-; CHECK-SD-NEXT: sshr v1.4h, v1.4h, #3
-; CHECK-SD-NEXT: usra v1.4h, v1.4h, #15
-; CHECK-SD-NEXT: mls v0.4h, v1.4h, v2.4h
+; CHECK-SD-NEXT: sshr v2.4h, v1.4h, #3
+; CHECK-SD-NEXT: usra v2.4h, v1.4h, #15
+; CHECK-SD-NEXT: mls v0.4h, v2.4h, v3.4h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv4i8_100:
@@ -938,13 +938,13 @@ define <8 x i8> @sv8i8_7(<8 x i8> %d, <8 x i8> %e) {
; CHECK-SD-LABEL: sv8i8_7:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: movi v1.8b, #147
-; CHECK-SD-NEXT: movi v2.8b, #7
+; CHECK-SD-NEXT: movi v3.8b, #7
; CHECK-SD-NEXT: smull v1.8h, v0.8b, v1.8b
; CHECK-SD-NEXT: shrn v1.8b, v1.8h, #8
; CHECK-SD-NEXT: add v1.8b, v1.8b, v0.8b
-; CHECK-SD-NEXT: sshr v1.8b, v1.8b, #2
-; CHECK-SD-NEXT: usra v1.8b, v1.8b, #7
-; CHECK-SD-NEXT: mls v0.8b, v1.8b, v2.8b
+; CHECK-SD-NEXT: sshr v2.8b, v1.8b, #2
+; CHECK-SD-NEXT: usra v2.8b, v1.8b, #7
+; CHECK-SD-NEXT: mls v0.8b, v2.8b, v3.8b
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv8i8_7:
@@ -968,12 +968,12 @@ define <8 x i8> @sv8i8_100(<8 x i8> %d, <8 x i8> %e) {
; CHECK-SD-LABEL: sv8i8_100:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: movi v1.8b, #41
-; CHECK-SD-NEXT: movi v2.8b, #100
+; CHECK-SD-NEXT: movi v3.8b, #100
; CHECK-SD-NEXT: smull v1.8h, v0.8b, v1.8b
; CHECK-SD-NEXT: shrn v1.8b, v1.8h, #8
-; CHECK-SD-NEXT: sshr v1.8b, v1.8b, #4
-; CHECK-SD-NEXT: usra v1.8b, v1.8b, #7
-; CHECK-SD-NEXT: mls v0.8b, v1.8b, v2.8b
+; CHECK-SD-NEXT: sshr v2.8b, v1.8b, #4
+; CHECK-SD-NEXT: usra v2.8b, v1.8b, #7
+; CHECK-SD-NEXT: mls v0.8b, v2.8b, v3.8b
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv8i8_100:
@@ -996,14 +996,14 @@ define <16 x i8> @sv16i8_7(<16 x i8> %d, <16 x i8> %e) {
; CHECK-SD-LABEL: sv16i8_7:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: movi v1.16b, #147
+; CHECK-SD-NEXT: movi v3.16b, #7
; CHECK-SD-NEXT: smull2 v2.8h, v0.16b, v1.16b
; CHECK-SD-NEXT: smull v1.8h, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp2 v1.16b, v1.16b, v2.16b
-; CHECK-SD-NEXT: movi v2.16b, #7
; CHECK-SD-NEXT: add v1.16b, v1.16b, v0.16b
-; CHECK-SD-NEXT: sshr v1.16b, v1.16b, #2
-; CHECK-SD-NEXT: usra v1.16b, v1.16b, #7
-; CHECK-SD-NEXT: mls v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: sshr v2.16b, v1.16b, #2
+; CHECK-SD-NEXT: usra v2.16b, v1.16b, #7
+; CHECK-SD-NEXT: mls v0.16b, v2.16b, v3.16b
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv16i8_7:
@@ -1028,13 +1028,13 @@ define <16 x i8> @sv16i8_100(<16 x i8> %d, <16 x i8> %e) {
; CHECK-SD-LABEL: sv16i8_100:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: movi v1.16b, #41
+; CHECK-SD-NEXT: movi v3.16b, #100
; CHECK-SD-NEXT: smull2 v2.8h, v0.16b, v1.16b
; CHECK-SD-NEXT: smull v1.8h, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp2 v1.16b, v1.16b, v2.16b
-; CHECK-SD-NEXT: movi v2.16b, #100
-; CHECK-SD-NEXT: sshr v1.16b, v1.16b, #4
-; CHECK-SD-NEXT: usra v1.16b, v1.16b, #7
-; CHECK-SD-NEXT: mls v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: sshr v2.16b, v1.16b, #4
+; CHECK-SD-NEXT: usra v2.16b, v1.16b, #7
+; CHECK-SD-NEXT: mls v0.16b, v2.16b, v3.16b
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv16i8_100:
@@ -1610,13 +1610,14 @@ define <4 x i16> @sv4i16_7(<4 x i16> %d, <4 x i16> %e) {
; CHECK-SD-LABEL: sv4i16_7:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #18725 // =0x4925
-; CHECK-SD-NEXT: movi v2.4h, #7
+; CHECK-SD-NEXT: movi v3.4h, #7
; CHECK-SD-NEXT: dup v1.4h, w8
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: sshr v1.4s, v1.4s, #17
-; CHECK-SD-NEXT: xtn v1.4h, v1.4s
-; CHECK-SD-NEXT: usra v1.4h, v1.4h, #15
-; CHECK-SD-NEXT: mls v0.4h, v1.4h, v2.4h
+; CHECK-SD-NEXT: sshr v2.4s, v1.4s, #17
+; CHECK-SD-NEXT: shrn v1.4h, v1.4s, #16
+; CHECK-SD-NEXT: xtn v2.4h, v2.4s
+; CHECK-SD-NEXT: usra v2.4h, v1.4h, #15
+; CHECK-SD-NEXT: mls v0.4h, v2.4h, v3.4h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv4i16_7:
@@ -1640,13 +1641,14 @@ define <4 x i16> @sv4i16_100(<4 x i16> %d, <4 x i16> %e) {
; CHECK-SD-LABEL: sv4i16_100:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #5243 // =0x147b
-; CHECK-SD-NEXT: movi v2.4h, #100
+; CHECK-SD-NEXT: movi v3.4h, #100
; CHECK-SD-NEXT: dup v1.4h, w8
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: sshr v1.4s, v1.4s, #19
-; CHECK-SD-NEXT: xtn v1.4h, v1.4s
-; CHECK-SD-NEXT: usra v1.4h, v1.4h, #15
-; CHECK-SD-NEXT: mls v0.4h, v1.4h, v2.4h
+; CHECK-SD-NEXT: sshr v2.4s, v1.4s, #19
+; CHECK-SD-NEXT: shrn v1.4h, v1.4s, #16
+; CHECK-SD-NEXT: xtn v2.4h, v2.4s
+; CHECK-SD-NEXT: usra v2.4h, v1.4h, #15
+; CHECK-SD-NEXT: mls v0.4h, v2.4h, v3.4h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv4i16_100:
@@ -1670,14 +1672,14 @@ define <8 x i16> @sv8i16_7(<8 x i16> %d, <8 x i16> %e) {
; CHECK-SD-LABEL: sv8i16_7:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #18725 // =0x4925
+; CHECK-SD-NEXT: movi v3.8h, #7
; CHECK-SD-NEXT: dup v1.8h, w8
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-SD-NEXT: movi v2.8h, #7
-; CHECK-SD-NEXT: sshr v1.8h, v1.8h, #1
-; CHECK-SD-NEXT: usra v1.8h, v1.8h, #15
-; CHECK-SD-NEXT: mls v0.8h, v1.8h, v2.8h
+; CHECK-SD-NEXT: sshr v2.8h, v1.8h, #1
+; CHECK-SD-NEXT: usra v2.8h, v1.8h, #15
+; CHECK-SD-NEXT: mls v0.8h, v2.8h, v3.8h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv8i16_7:
@@ -1702,14 +1704,14 @@ define <8 x i16> @sv8i16_100(<8 x i16> %d, <8 x i16> %e) {
; CHECK-SD-LABEL: sv8i16_100:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #5243 // =0x147b
+; CHECK-SD-NEXT: movi v3.8h, #100
; CHECK-SD-NEXT: dup v1.8h, w8
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-SD-NEXT: movi v2.8h, #100
-; CHECK-SD-NEXT: sshr v1.8h, v1.8h, #3
-; CHECK-SD-NEXT: usra v1.8h, v1.8h, #15
-; CHECK-SD-NEXT: mls v0.8h, v1.8h, v2.8h
+; CHECK-SD-NEXT: sshr v2.8h, v1.8h, #3
+; CHECK-SD-NEXT: usra v2.8h, v1.8h, #15
+; CHECK-SD-NEXT: mls v0.8h, v2.8h, v3.8h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv8i16_100:
diff --git a/llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll b/llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll
index 840501ec48e42..c919b8c9ed595 100644
--- a/llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll
+++ b/llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll
@@ -8,9 +8,9 @@ define <8 x i16> @sdiv_v8i16_by_7(<8 x i16> %x) {
; CHECK-NEXT: dup v1.8h, w8
; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: uzp2 v0.8h, v0.8h, v2.8h
-; CHECK-NEXT: sshr v0.8h, v0.8h, #1
-; CHECK-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-NEXT: uzp2 v1.8h, v0.8h, v2.8h
+; CHECK-NEXT: sshr v0.8h, v1.8h, #1
+; CHECK-NEXT: usra v0.8h, v1.8h, #15
; CHECK-NEXT: ret
%div = sdiv <8 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <8 x i16> %div
@@ -25,12 +25,12 @@ define <16 x i16> @sdiv_v16i16_by_7(<16 x i16> %x) {
; CHECK-NEXT: smull v0.4s, v0.4h, v2.4h
; CHECK-NEXT: smull2 v4.4s, v1.8h, v2.8h
; CHECK-NEXT: smull v1.4s, v1.4h, v2.4h
-; CHECK-NEXT: uzp2 v0.8h, v0.8h, v3.8h
-; CHECK-NEXT: uzp2 v1.8h, v1.8h, v4.8h
-; CHECK-NEXT: sshr v0.8h, v0.8h, #1
-; CHECK-NEXT: sshr v1.8h, v1.8h, #1
-; CHECK-NEXT: usra v0.8h, v0.8h, #15
-; CHECK-NEXT: usra v1.8h, v1.8h, #15
+; CHECK-NEXT: uzp2 v2.8h, v0.8h, v3.8h
+; CHECK-NEXT: uzp2 v3.8h, v1.8h, v4.8h
+; CHECK-NEXT: sshr v0.8h, v2.8h, #1
+; CHECK-NEXT: sshr v1.8h, v3.8h, #1
+; CHECK-NEXT: usra v0.8h, v2.8h, #15
+; CHECK-NEXT: usra v1.8h, v3.8h, #15
; CHECK-NEXT: ret
%div = sdiv <16 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <16 x i16> %div
@@ -40,14 +40,14 @@ define <8 x i16> @srem_v8i16_by_7(<8 x i16> %x) {
; CHECK-LABEL: srem_v8i16_by_7:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #18725 // =0x4925
+; CHECK-NEXT: movi v3.8h, #7
; CHECK-NEXT: dup v1.8h, w8
; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-NEXT: movi v2.8h, #7
-; CHECK-NEXT: sshr v1.8h, v1.8h, #1
-; CHECK-NEXT: usra v1.8h, v1.8h, #15
-; CHECK-NEXT: mls v0.8h, v1.8h, v2.8h
+; CHECK-NEXT: sshr v2.8h, v1.8h, #1
+; CHECK-NEXT: usra v2.8h, v1.8h, #15
+; CHECK-NEXT: mls v0.8h, v2.8h, v3.8h
; CHECK-NEXT: ret
%rem = srem <8 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <8 x i16> %rem
@@ -57,20 +57,20 @@ define <16 x i16> @srem_v16i16_by_7(<16 x i16> %x) {
; CHECK-LABEL: srem_v16i16_by_7:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #18725 // =0x4925
+; CHECK-NEXT: movi v6.8h, #7
; CHECK-NEXT: dup v2.8h, w8
; CHECK-NEXT: smull2 v3.4s, v0.8h, v2.8h
; CHECK-NEXT: smull v4.4s, v0.4h, v2.4h
; CHECK-NEXT: smull2 v5.4s, v1.8h, v2.8h
; CHECK-NEXT: smull v2.4s, v1.4h, v2.4h
; CHECK-NEXT: uzp2 v3.8h, v4.8h, v3.8h
-; CHECK-NEXT: movi v4.8h, #7
; CHECK-NEXT: uzp2 v2.8h, v2.8h, v5.8h
-; CHECK-NEXT: sshr v3.8h, v3.8h, #1
-; CHECK-NEXT: sshr v2.8h, v2.8h, #1
-; CHECK-NEXT: usra v3.8h, v3.8h, #15
-; CHECK-NEXT: usra v2.8h, v2.8h, #15
-; CHECK-NEXT: mls v0.8h, v3.8h, v4.8h
-; CHECK-NEXT: mls v1.8h, v2.8h, v4.8h
+; CHECK-NEXT: sshr v4.8h, v3.8h, #1
+; CHECK-NEXT: sshr v5.8h, v2.8h, #1
+; CHECK-NEXT: usra v4.8h, v3.8h, #15
+; CHECK-NEXT: usra v5.8h, v2.8h, #15
+; CHECK-NEXT: mls v0.8h, v4.8h, v6.8h
+; CHECK-NEXT: mls v1.8h, v5.8h, v6.8h
; CHECK-NEXT: ret
%rem = srem <16 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <16 x i16> %rem
diff --git a/llvm/test/CodeGen/AArch64/srem-vector-lkk.ll b/llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
index 52b09565b73a5..7ff4f9bda9947 100644
--- a/llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
@@ -14,10 +14,10 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; CHECK-NEXT: mla v1.4h, v0.4h, v2.4h
; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_1]
; CHECK-NEXT: adrp x8, .LCPI0_2
-; CHECK-NEXT: sshl v1.4h, v1.4h, v2.4h
-; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_2]
-; CHECK-NEXT: usra v1.4h, v1.4h, #15
-; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
+; CHECK-NEXT: sshl v2.4h, v1.4h, v2.4h
+; CHECK-NEXT: usra v2.4h, v1.4h, #15
+; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_2]
+; CHECK-NEXT: mls v0.4h, v2.4h, v1.4h
; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
ret <4 x i16> %1
@@ -27,14 +27,14 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; CHECK-LABEL: fold_srem_vec_2:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #44151 // =0xac77
-; CHECK-NEXT: movi v2.4h, #95
+; CHECK-NEXT: movi v3.4h, #95
; CHECK-NEXT: dup v1.4h, w8
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: shrn v1.4h, v1.4s, #16
; CHECK-NEXT: add v1.4h, v1.4h, v0.4h
-; CHECK-NEXT: sshr v1.4h, v1.4h, #6
-; CHECK-NEXT: usra v1.4h, v1.4h, #15
-; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
+; CHECK-NEXT: sshr v2.4h, v1.4h, #6
+; CHECK-NEXT: usra v2.4h, v1.4h, #15
+; CHECK-NEXT: mls v0.4h, v2.4h, v3.4h
; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
ret <4 x i16> %1
@@ -46,15 +46,15 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
; CHECK-LABEL: combine_srem_sdiv:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #44151 // =0xac77
-; CHECK-NEXT: movi v2.4h, #95
+; CHECK-NEXT: movi v3.4h, #95
; CHECK-NEXT: dup v1.4h, w8
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: shrn v1.4h, v1.4s, #16
; CHECK-NEXT: add v1.4h, v1.4h, v0.4h
-; CHECK-NEXT: sshr v1.4h, v1.4h, #6
-; CHECK-NEXT: usra v1.4h, v1.4h, #15
-; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
-; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: sshr v2.4h, v1.4h, #6
+; CHECK-NEXT: usra v2.4h, v1.4h, #15
+; CHECK-NEXT: mls v0.4h, v2.4h, v3.4h
+; CHECK-NEXT: add v0.4h, v0.4h, v2.4h
; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
@@ -75,10 +75,10 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: shrn v1.4h, v1.4s, #16
; CHECK-NEXT: add v1.4h, v1.4h, v0.4h
-; CHECK-NEXT: sshl v1.4h, v1.4h, v2.4h
-; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI3_1]
-; CHECK-NEXT: usra v1.4h, v1.4h, #15
-; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
+; CHECK-NEXT: sshl v2.4h, v1.4h, v2.4h
+; CHECK-NEXT: usra v2.4h, v1.4h, #15
+; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI3_1]
+; CHECK-NEXT: mls v0.4h, v2.4h, v1.4h
; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
ret <4 x i16> %1
@@ -92,14 +92,14 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; CHECK-NEXT: movi d2, #0x00ffff0000ffff
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_0]
; CHECK-NEXT: adrp x8, .LCPI4_1
+; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI4_1]
+; CHECK-NEXT: adrp x8, .LCPI4_2
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: and v2.8b, v0.8b, v2.8b
; CHECK-NEXT: shrn v1.4h, v1.4s, #16
; CHECK-NEXT: add v1.4h, v1.4h, v2.4h
-; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_1]
-; CHECK-NEXT: adrp x8, .LCPI4_2
-; CHECK-NEXT: sshl v1.4h, v1.4h, v2.4h
; CHECK-NEXT: ushr v2.4h, v1.4h, #15
+; CHECK-NEXT: sshl v1.4h, v1.4h, v3.4h
; CHECK-NEXT: mov v2.h[0], wzr
; CHECK-NEXT: add v1.4h, v1.4h, v2.4h
; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_2]
@@ -120,12 +120,12 @@ define <4 x i16> @dont_fold_srem_i16_smax(<4 x i16> %x) {
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: fmov d2, x8
; CHECK-NEXT: adrp x8, .LCPI5_1
+; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI5_1]
+; CHECK-NEXT: adrp x8, .LCPI5_2
; CHECK-NEXT: shrn v1.4h, v1.4s, #16
; CHECK-NEXT: mla v1.4h, v0.4h, v2.4h
-; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI5_1]
-; CHECK-NEXT: adrp x8, .LCPI5_2
-; CHECK-NEXT: sshl v1.4h, v1.4h, v2.4h
; CHECK-NEXT: ushr v2.4h, v1.4h, #15
+; CHECK-NEXT: sshl v1.4h, v1.4h, v3.4h
; CHECK-NEXT: mov v2.h[0], wzr
; CHECK-NEXT: add v1.4h, v1.4h, v2.4h
; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI5_2]
@@ -183,13 +183,13 @@ define <16 x i8> @fold_srem_v16i8(<16 x i8> %x) {
; CHECK-LABEL: fold_srem_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.16b, #103
+; CHECK-NEXT: movi v3.16b, #10
; CHECK-NEXT: smull2 v2.8h, v0.16b, v1.16b
; CHECK-NEXT: smull v1.8h, v0.8b, v1.8b
; CHECK-NEXT: uzp2 v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: movi v2.16b, #10
-; CHECK-NEXT: sshr v1.16b, v1.16b, #2
-; CHECK-NEXT: usra v1.16b, v1.16b, #7
-; CHECK-NEXT: mls v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: sshr v2.16b, v1.16b, #2
+; CHECK-NEXT: usra v2.16b, v1.16b, #7
+; CHECK-NEXT: mls v0.16b, v2.16b, v3.16b
; CHECK-NEXT: ret
%1 = srem <16 x i8> %x, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
ret <16 x i8> %1
@@ -199,12 +199,12 @@ define <8 x i8> @fold_srem_v8i8(<8 x i8> %x) {
; CHECK-LABEL: fold_srem_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.8b, #103
-; CHECK-NEXT: movi v2.8b, #10
+; CHECK-NEXT: movi v3.8b, #10
; CHECK-NEXT: smull v1.8h, v0.8b, v1.8b
; CHECK-NEXT: shrn v1.8b, v1.8h, #8
-; CHECK-NEXT: sshr v1.8b, v1.8b, #2
-; CHECK-NEXT: usra v1.8b, v1.8b, #7
-; CHECK-NEXT: mls v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: sshr v2.8b, v1.8b, #2
+; CHECK-NEXT: usra v2.8b, v1.8b, #7
+; CHECK-NEXT: mls v0.8b, v2.8b, v3.8b
; CHECK-NEXT: ret
%1 = srem <8 x i8> %x, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
ret <8 x i8> %1
@@ -214,14 +214,14 @@ define <8 x i16> @fold_srem_v8i16(<8 x i16> %x) {
; CHECK-LABEL: fold_srem_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #26215 // =0x6667
+; CHECK-NEXT: movi v3.8h, #10
; CHECK-NEXT: dup v1.8h, w8
; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-NEXT: movi v2.8h, #10
-; CHECK-NEXT: sshr v1.8h, v1.8h, #2
-; CHECK-NEXT: usra v1.8h, v1.8h, #15
-; CHECK-NEXT: mls v0.8h, v1.8h, v2.8h
+; CHECK-NEXT: sshr v2.8h, v1.8h, #2
+; CHECK-NEXT: usra v2.8h, v1.8h, #15
+; CHECK-NEXT: mls v0.8h, v2.8h, v3.8h
; CHECK-NEXT: ret
%1 = srem <8 x i16> %x, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
ret <8 x i16> %1
@@ -231,13 +231,14 @@ define <4 x i16> @fold_srem_v4i16(<4 x i16> %x) {
; CHECK-LABEL: fold_srem_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #26215 // =0x6667
-; CHECK-NEXT: movi v2.4h, #10
+; CHECK-NEXT: movi v3.4h, #10
; CHECK-NEXT: dup v1.4h, w8
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
-; CHECK-NEXT: sshr v1.4s, v1.4s, #18
-; CHECK-NEXT: xtn v1.4h, v1.4s
-; CHECK-NEXT: usra v1.4h, v1.4h, #15
-; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
+; CHECK-NEXT: sshr v2.4s, v1.4s, #18
+; CHECK-NEXT: shrn v1.4h, v1.4s, #16
+; CHECK-NEXT: xtn v2.4h, v2.4s
+; CHECK-NEXT: usra v2.4h, v1.4h, #15
+; CHECK-NEXT: mls v0.4h, v2.4h, v3.4h
; CHECK-NEXT: ret
%1 = srem <4 x i16> %x, <i16 10, i16 10, i16 10, i16 10>
ret <4 x i16> %1
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index fb78590bd110c..74bd7be0fb179 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -9471,38 +9471,41 @@ define amdgpu_kernel void @sdiv24(ptr addrspace(1) %out, i24 %x, i24 %y) {
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_bfe_i32 s4, s3, 0x180000
-; GFX6-NEXT: s_abs_i32 s5, s4
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s5
-; GFX6-NEXT: s_sub_i32 s3, 0, s5
-; GFX6-NEXT: s_bfe_i32 s6, s2, 0x180000
-; GFX6-NEXT: s_abs_i32 s7, s6
+; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
+; GFX6-NEXT: s_bfe_i32 s2, s5, 0x180000
+; GFX6-NEXT: s_abs_i32 s6, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GFX6-NEXT: s_sub_i32 s2, 0, s6
+; GFX6-NEXT: s_lshl_b32 s7, s4, 8
+; GFX6-NEXT: s_bfe_i32 s4, s4, 0x180000
; GFX6-NEXT: v_rcp_f32_e32 v0, v0
-; GFX6-NEXT: s_xor_b32 s4, s6, s4
-; GFX6-NEXT: s_ashr_i32 s4, s4, 31
-; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_abs_i32 s4, s4
+; GFX6-NEXT: s_lshl_b32 s5, s5, 8
+; GFX6-NEXT: s_xor_b32 s5, s7, s5
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX6-NEXT: s_ashr_i32 s5, s5, 31
; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_mul_lo_u32 v1, s2, v0
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
-; GFX6-NEXT: v_readfirstlane_b32 s6, v0
-; GFX6-NEXT: s_mul_i32 s6, s6, s5
-; GFX6-NEXT: s_sub_i32 s6, s7, s6
-; GFX6-NEXT: s_sub_i32 s7, s6, s5
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_readfirstlane_b32 s7, v0
+; GFX6-NEXT: s_mul_i32 s7, s7, s6
+; GFX6-NEXT: s_sub_i32 s4, s4, s7
+; GFX6-NEXT: s_sub_i32 s7, s4, s6
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s6, s5
+; GFX6-NEXT: s_cmp_ge_u32 s4, s6
; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: s_cselect_b32 s6, s7, s6
+; GFX6-NEXT: s_cselect_b32 s4, s7, s4
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s6, s5
+; GFX6-NEXT: s_cmp_ge_u32 s4, s6
; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0
-; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_xor_b32_e32 v0, s5, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s5, v0
; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
@@ -9514,17 +9517,19 @@ define amdgpu_kernel void @sdiv24(ptr addrspace(1) %out, i24 %x, i24 %y) {
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_bfe_i32 s3, s3, 0x180000
-; GFX9-NEXT: s_abs_i32 s4, s3
+; GFX9-NEXT: s_bfe_i32 s4, s3, 0x180000
+; GFX9-NEXT: s_abs_i32 s4, s4
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4
+; GFX9-NEXT: s_lshl_b32 s5, s2, 8
+; GFX9-NEXT: s_lshl_b32 s3, s3, 8
+; GFX9-NEXT: s_xor_b32 s3, s5, s3
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_sub_i32 s5, 0, s4
; GFX9-NEXT: s_bfe_i32 s2, s2, 0x180000
-; GFX9-NEXT: s_xor_b32 s3, s2, s3
-; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_abs_i32 s2, s2
-; GFX9-NEXT: s_ashr_i32 s3, s3, 31
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: s_ashr_i32 s3, s3, 31
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: s_mul_i32 s5, s5, s6
; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll
index ff0fc8972fbb3..c065aa4a6d695 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll
@@ -2060,20 +2060,22 @@ define amdgpu_kernel void @v_sdiv_i25(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_bfe_i32 v1, v1, 0, 25
-; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v1
-; GCN-NEXT: v_max_i32_e32 v2, v1, v2
+; GCN-NEXT: v_bfe_i32 v2, v1, 0, 25
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
+; GCN-NEXT: v_max_i32_e32 v2, v2, v3
; GCN-NEXT: v_cvt_f32_u32_e32 v3, v2
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v2
-; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25
+; GCN-NEXT: v_bfe_i32 v5, v0, 0, 25
; GCN-NEXT: v_rcp_f32_e32 v3, v3
-; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v0
-; GCN-NEXT: v_max_i32_e32 v5, v0, v5
+; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v5
+; GCN-NEXT: v_max_i32_e32 v5, v5, v6
; GCN-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 7, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 7, v1
; GCN-NEXT: v_xor_b32_e32 v0, v0, v1
-; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; GCN-NEXT: v_mul_lo_u32 v4, v4, v3
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; GCN-NEXT: v_mul_hi_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GCN-NEXT: v_mul_hi_u32 v3, v5, v3
@@ -2107,20 +2109,22 @@ define amdgpu_kernel void @v_sdiv_i25(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: s_mov_b32 s0, s4
; TONGA-NEXT: s_mov_b32 s1, s5
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_bfe_i32 v1, v1, 0, 25
-; TONGA-NEXT: v_sub_u32_e32 v2, vcc, 0, v1
-; TONGA-NEXT: v_max_i32_e32 v2, v1, v2
+; TONGA-NEXT: v_bfe_i32 v2, v1, 0, 25
+; TONGA-NEXT: v_sub_u32_e32 v3, vcc, 0, v2
+; TONGA-NEXT: v_max_i32_e32 v2, v2, v3
; TONGA-NEXT: v_cvt_f32_u32_e32 v3, v2
; TONGA-NEXT: v_sub_u32_e32 v4, vcc, 0, v2
-; TONGA-NEXT: v_bfe_i32 v0, v0, 0, 25
+; TONGA-NEXT: v_bfe_i32 v5, v0, 0, 25
; TONGA-NEXT: v_rcp_f32_e32 v3, v3
-; TONGA-NEXT: v_sub_u32_e32 v5, vcc, 0, v0
-; TONGA-NEXT: v_max_i32_e32 v5, v0, v5
+; TONGA-NEXT: v_sub_u32_e32 v6, vcc, 0, v5
+; TONGA-NEXT: v_max_i32_e32 v5, v5, v6
; TONGA-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; TONGA-NEXT: v_cvt_u32_f32_e32 v3, v3
+; TONGA-NEXT: v_lshlrev_b32_e32 v0, 7, v0
+; TONGA-NEXT: v_lshlrev_b32_e32 v1, 7, v1
; TONGA-NEXT: v_xor_b32_e32 v0, v0, v1
-; TONGA-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; TONGA-NEXT: v_mul_lo_u32 v4, v4, v3
+; TONGA-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; TONGA-NEXT: v_mul_hi_u32 v4, v3, v4
; TONGA-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; TONGA-NEXT: v_mul_hi_u32 v3, v5, v3
@@ -2151,41 +2155,42 @@ define amdgpu_kernel void @v_sdiv_i25(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_mov_b32 s4, s10
; GFX9-NEXT: s_mov_b32 s5, s11
; GFX9-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
-; GFX9-NEXT: s_mov_b32 s1, s9
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_readfirstlane_b32 s0, v1
-; GFX9-NEXT: s_bfe_i32 s4, s0, 0x190000
-; GFX9-NEXT: s_abs_i32 s5, s4
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: s_mov_b32 s0, s8
-; GFX9-NEXT: s_sub_i32 s7, 0, s5
-; GFX9-NEXT: v_rcp_f32_e32 v1, v1
-; GFX9-NEXT: s_bfe_i32 s6, s6, 0x190000
-; GFX9-NEXT: s_xor_b32 s4, s6, s4
-; GFX9-NEXT: s_abs_i32 s6, s6
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_ashr_i32 s4, s4, 31
-; GFX9-NEXT: v_readfirstlane_b32 s8, v0
-; GFX9-NEXT: s_mul_i32 s7, s7, s8
-; GFX9-NEXT: s_mul_hi_u32 s7, s8, s7
-; GFX9-NEXT: s_add_i32 s8, s8, s7
-; GFX9-NEXT: s_mul_hi_u32 s7, s6, s8
-; GFX9-NEXT: s_mul_i32 s8, s7, s5
-; GFX9-NEXT: s_sub_i32 s6, s6, s8
-; GFX9-NEXT: s_add_i32 s9, s7, 1
-; GFX9-NEXT: s_sub_i32 s8, s6, s5
-; GFX9-NEXT: s_cmp_ge_u32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s7, s9, s7
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: s_bfe_i32 s1, s1, 0x190000
+; GFX9-NEXT: s_abs_i32 s4, s1
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s4
+; GFX9-NEXT: v_readfirstlane_b32 s5, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 7, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 7, v1
+; GFX9-NEXT: v_rcp_f32_e32 v2, v2
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT: s_sub_i32 s6, 0, s4
+; GFX9-NEXT: s_bfe_i32 s5, s5, 0x190000
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_abs_i32 s5, s5
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX9-NEXT: s_mov_b32 s1, s9
+; GFX9-NEXT: v_readfirstlane_b32 s7, v1
+; GFX9-NEXT: s_mul_i32 s6, s6, s7
+; GFX9-NEXT: s_mul_hi_u32 s6, s7, s6
+; GFX9-NEXT: s_add_i32 s7, s7, s6
+; GFX9-NEXT: s_mul_hi_u32 s6, s5, s7
+; GFX9-NEXT: s_mul_i32 s7, s6, s4
+; GFX9-NEXT: s_sub_i32 s5, s5, s7
+; GFX9-NEXT: s_add_i32 s8, s6, 1
+; GFX9-NEXT: s_sub_i32 s7, s5, s4
+; GFX9-NEXT: s_cmp_ge_u32 s5, s4
; GFX9-NEXT: s_cselect_b32 s6, s8, s6
-; GFX9-NEXT: s_add_i32 s8, s7, 1
-; GFX9-NEXT: s_cmp_ge_u32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s5, s8, s7
-; GFX9-NEXT: s_xor_b32 s5, s5, s4
-; GFX9-NEXT: s_sub_i32 s4, s5, s4
-; GFX9-NEXT: s_bfe_i32 s4, s4, 0x190000
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: s_cselect_b32 s5, s7, s5
+; GFX9-NEXT: s_add_i32 s7, s6, 1
+; GFX9-NEXT: s_cmp_ge_u32 s5, s4
+; GFX9-NEXT: s_cselect_b32 s4, s7, s6
+; GFX9-NEXT: v_xor_b32_e32 v1, s4, v0
+; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0
+; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 25
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
index 74ee61b676f0a..d6e9092efb71b 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -2431,12 +2431,12 @@ define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; GCN-NEXT: v_ashrrev_i32_e32 v0, 8, v1
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 17, v2
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
-; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v1
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 8, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v0
+; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v2
+; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v0, vcc
+; GCN-NEXT: v_alignbit_b32 v0, v1, v2, 15
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GCN-IR-LABEL: v_test_sdiv24_pow2_k_den_i64:
diff --git a/llvm/test/CodeGen/RISCV/div-pow2.ll b/llvm/test/CodeGen/RISCV/div-pow2.ll
index e52ccba70f71f..c0c3fa703f1a1 100644
--- a/llvm/test/CodeGen/RISCV/div-pow2.ll
+++ b/llvm/test/CodeGen/RISCV/div-pow2.ll
@@ -405,6 +405,8 @@ define i64 @sdiv64_pow2_8589934592(i64 %a) {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a2, a1, 31
; RV32I-NEXT: srli a3, a1, 31
+; RV32I-NEXT: slli a2, a2, 1
+; RV32I-NEXT: or a2, a3, a2
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: sltu a0, a2, a0
@@ -430,6 +432,8 @@ define i64 @sdiv64_pow2_negative_8589934592(i64 %a) {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: srai a2, a1, 31
; RV32I-NEXT: srli a3, a1, 31
+; RV32I-NEXT: slli a2, a2, 1
+; RV32I-NEXT: or a2, a3, a2
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: sltu a0, a2, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
index 831713780d26e..2bcce64e3b081 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
@@ -935,23 +935,14 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
; RV32NOM-LABEL: extractelt_sdiv_v4i32:
; RV32NOM: # %bb.0:
-; RV32NOM-NEXT: lui a0, 1044480
-; RV32NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32NOM-NEXT: vmv.s.x v9, a0
; RV32NOM-NEXT: lui a0, %hi(.LCPI46_0)
; RV32NOM-NEXT: addi a0, a0, %lo(.LCPI46_0)
-; RV32NOM-NEXT: vle32.v v10, (a0)
-; RV32NOM-NEXT: vsext.vf4 v11, v9
-; RV32NOM-NEXT: vmulh.vv v9, v8, v10
-; RV32NOM-NEXT: lui a0, 12320
-; RV32NOM-NEXT: vand.vv v8, v8, v11
-; RV32NOM-NEXT: addi a0, a0, 257
-; RV32NOM-NEXT: vmv.s.x v10, a0
-; RV32NOM-NEXT: vadd.vv v8, v9, v8
-; RV32NOM-NEXT: vsext.vf4 v9, v10
-; RV32NOM-NEXT: vsra.vv v9, v8, v9
-; RV32NOM-NEXT: vsrl.vi v8, v8, 31
-; RV32NOM-NEXT: vadd.vv v8, v9, v8
+; RV32NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32NOM-NEXT: vle32.v v9, (a0)
+; RV32NOM-NEXT: vmulh.vv v8, v8, v9
+; RV32NOM-NEXT: vsrl.vi v9, v8, 31
+; RV32NOM-NEXT: vsra.vi v8, v8, 2
+; RV32NOM-NEXT: vadd.vv v8, v8, v9
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
; RV32NOM-NEXT: vmv.x.s a0, v8
; RV32NOM-NEXT: ret
@@ -971,22 +962,13 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
;
; RV64NOM-LABEL: extractelt_sdiv_v4i32:
; RV64NOM: # %bb.0:
-; RV64NOM-NEXT: lui a0, 1044480
-; RV64NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV64NOM-NEXT: vmv.s.x v9, a0
; RV64NOM-NEXT: lui a0, %hi(.LCPI46_0)
; RV64NOM-NEXT: addi a0, a0, %lo(.LCPI46_0)
-; RV64NOM-NEXT: vle32.v v10, (a0)
-; RV64NOM-NEXT: vsext.vf4 v11, v9
-; RV64NOM-NEXT: vmulh.vv v9, v8, v10
-; RV64NOM-NEXT: lui a0, 12320
-; RV64NOM-NEXT: vand.vv v8, v8, v11
-; RV64NOM-NEXT: addi a0, a0, 257
-; RV64NOM-NEXT: vmv.s.x v10, a0
-; RV64NOM-NEXT: vadd.vv v8, v9, v8
-; RV64NOM-NEXT: vsext.vf4 v9, v10
-; RV64NOM-NEXT: vsra.vv v8, v8, v9
+; RV64NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV64NOM-NEXT: vle32.v v9, (a0)
+; RV64NOM-NEXT: vmulh.vv v8, v8, v9
; RV64NOM-NEXT: vsrl.vi v9, v8, 31
+; RV64NOM-NEXT: vsra.vi v8, v8, 2
; RV64NOM-NEXT: vadd.vv v8, v8, v9
; RV64NOM-NEXT: vslidedown.vi v8, v8, 2
; RV64NOM-NEXT: vmv.x.s a0, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
index 5b3ef7c000bf4..72cdb663ec282 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
@@ -1279,8 +1279,8 @@ define void @mulhs_v8i16(ptr %x) {
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vmulh.vv v8, v9, v8
-; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -1304,8 +1304,8 @@ define void @mulhs_v6i16(ptr %x) {
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vmulh.vv v8, v9, v8
-; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -1343,8 +1343,8 @@ define void @mulhs_v4i32(ptr %x) {
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vle32.v v9, (a0)
; RV64-NEXT: vmulh.vv v8, v9, v8
-; RV64-NEXT: vsra.vi v8, v8, 1
; RV64-NEXT: vsrl.vi v9, v8, 31
+; RV64-NEXT: vsra.vi v8, v8, 1
; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
@@ -3407,8 +3407,8 @@ define void @mulhs_v16i16(ptr %x) {
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: vmulh.vv v8, v10, v8
-; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsrl.vi v10, v8, 15
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -3448,8 +3448,8 @@ define void @mulhs_v8i32(ptr %x) {
; RV64-NEXT: vmv.v.x v10, a1
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-NEXT: vmulh.vv v8, v8, v10
-; RV64-NEXT: vsra.vi v8, v8, 1
; RV64-NEXT: vsrl.vi v10, v8, 31
+; RV64-NEXT: vsra.vi v8, v8, 1
; RV64-NEXT: vadd.vv v8, v8, v10
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
@@ -5558,13 +5558,13 @@ define void @mulhs_vx_v16i8(ptr %x) {
define void @mulhs_vx_v8i16(ptr %x) {
; CHECK-LABEL: mulhs_vx_v8i16:
; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 5
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: lui a1, 5
; CHECK-NEXT: addi a1, a1, -1755
; CHECK-NEXT: vmulh.vx v8, v8, a1
-; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
@@ -5575,31 +5575,18 @@ define void @mulhs_vx_v8i16(ptr %x) {
}
define void @mulhs_vx_v4i32(ptr %x) {
-; RV32-LABEL: mulhs_vx_v4i32:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a1, 629146
-; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: addi a1, a1, -1639
-; RV32-NEXT: vmulh.vx v8, v8, a1
-; RV32-NEXT: vsrl.vi v9, v8, 31
-; RV32-NEXT: vsra.vi v8, v8, 1
-; RV32-NEXT: vadd.vv v8, v8, v9
-; RV32-NEXT: vse32.v v8, (a0)
-; RV32-NEXT: ret
-;
-; RV64-LABEL: mulhs_vx_v4i32:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV64-NEXT: vle32.v v8, (a0)
-; RV64-NEXT: lui a1, 629146
-; RV64-NEXT: addi a1, a1, -1639
-; RV64-NEXT: vmulh.vx v8, v8, a1
-; RV64-NEXT: vsra.vi v8, v8, 1
-; RV64-NEXT: vsrl.vi v9, v8, 31
-; RV64-NEXT: vadd.vv v8, v8, v9
-; RV64-NEXT: vse32.v v8, (a0)
-; RV64-NEXT: ret
+; CHECK-LABEL: mulhs_vx_v4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 629146
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: addi a1, a1, -1639
+; CHECK-NEXT: vmulh.vx v8, v8, a1
+; CHECK-NEXT: vsrl.vi v9, v8, 31
+; CHECK-NEXT: vsra.vi v8, v8, 1
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: vse32.v v8, (a0)
+; CHECK-NEXT: ret
%a = load <4 x i32>, ptr %x
%b = sdiv <4 x i32> %a, <i32 -5, i32 -5, i32 -5, i32 -5>
store <4 x i32> %b, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
index fc7899a9ab136..6ba109feb95c9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
@@ -33,8 +33,8 @@ define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v8, v9, v8
-; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i8> %va, splat (i8 -7)
@@ -90,8 +90,8 @@ define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v8, v9, v8
-; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i8> %va, splat (i8 -7)
@@ -127,8 +127,8 @@ define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v8, v9, v8
-; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i8> %va, splat (i8 -7)
@@ -164,8 +164,8 @@ define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v8, v9, v8
-; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vsrl.vi v9, v8, 7
+; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i8> %va, splat (i8 -7)
@@ -201,8 +201,8 @@ define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmulh.vx v10, v8, a0
; CHECK-NEXT: vsub.vv v8, v10, v8
-; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vsrl.vi v10, v8, 7
+; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = sdiv <vscale x 16 x i8> %va, splat (i8 -7)
@@ -238,8 +238,8 @@ define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vmulh.vx v12, v8, a0
; CHECK-NEXT: vsub.vv v8, v12, v8
-; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vsrl.vi v12, v8, 7
+; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = sdiv <vscale x 32 x i8> %va, splat (i8 -7)
@@ -275,8 +275,8 @@ define <vscale x 64 x i8> @vdiv_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vmulh.vx v16, v8, a0
; CHECK-NEXT: vsub.vv v8, v16, v8
-; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vsrl.vi v16, v8, 7
+; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = sdiv <vscale x 64 x i8> %va, splat (i8 -7)
@@ -312,8 +312,8 @@ define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i16> %va, splat (i16 -7)
@@ -349,8 +349,8 @@ define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i16> %va, splat (i16 -7)
@@ -386,8 +386,8 @@ define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsrl.vi v9, v8, 15
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i16> %va, splat (i16 -7)
@@ -423,8 +423,8 @@ define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsrl.vi v10, v8, 15
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vadd.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i16> %va, splat (i16 -7)
@@ -460,8 +460,8 @@ define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsrl.vi v12, v8, 15
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = sdiv <vscale x 16 x i16> %va, splat (i16 -7)
@@ -497,8 +497,8 @@ define <vscale x 32 x i16> @vdiv_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vsrl.vi v16, v8, 15
+; CHECK-NEXT: vsra.vi v8, v8, 1
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = sdiv <vscale x 32 x i16> %va, splat (i16 -7)
@@ -528,27 +528,16 @@ define <vscale x 1 x i32> @vdiv_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %
}
define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv1i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 599186
-; RV32-NEXT: addi a0, a0, 1171
-; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV32-NEXT: vmulhsu.vx v8, v8, a0
-; RV32-NEXT: vsrl.vi v9, v8, 31
-; RV32-NEXT: vsra.vi v8, v8, 2
-; RV32-NEXT: vadd.vv v8, v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vdiv_vi_nxv1i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 599186
-; RV64-NEXT: addi a0, a0, 1171
-; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV64-NEXT: vmulhsu.vx v8, v8, a0
-; RV64-NEXT: vsra.vi v8, v8, 2
-; RV64-NEXT: vsrl.vi v9, v8, 31
-; RV64-NEXT: vadd.vv v8, v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vdiv_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 599186
+; CHECK-NEXT: addi a0, a0, 1171
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vmulhsu.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v9, v8, 31
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i32> %va, splat (i32 7)
ret <vscale x 1 x i32> %vc
}
@@ -576,29 +565,17 @@ define <vscale x 2 x i32> @vdiv_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %
}
define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv2i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV32-NEXT: vmulh.vx v9, v8, a0
-; RV32-NEXT: vsub.vv v8, v9, v8
-; RV32-NEXT: vsrl.vi v9, v8, 31
-; RV32-NEXT: vsra.vi v8, v8, 2
-; RV32-NEXT: vadd.vv v8, v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vdiv_vi_nxv2i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV64-NEXT: vmulh.vx v9, v8, a0
-; RV64-NEXT: vsub.vv v8, v9, v8
-; RV64-NEXT: vsra.vi v8, v8, 2
-; RV64-NEXT: vsrl.vi v9, v8, 31
-; RV64-NEXT: vadd.vv v8, v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vdiv_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v8, v9, v8
+; CHECK-NEXT: vsrl.vi v9, v8, 31
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i32> %va, splat (i32 -7)
ret <vscale x 2 x i32> %vc
}
@@ -626,29 +603,17 @@ define <vscale x 4 x i32> @vdiv_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %
}
define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv4i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32-NEXT: vmulh.vx v10, v8, a0
-; RV32-NEXT: vsub.vv v8, v10, v8
-; RV32-NEXT: vsrl.vi v10, v8, 31
-; RV32-NEXT: vsra.vi v8, v8, 2
-; RV32-NEXT: vadd.vv v8, v8, v10
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vdiv_vi_nxv4i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV64-NEXT: vmulh.vx v10, v8, a0
-; RV64-NEXT: vsub.vv v8, v10, v8
-; RV64-NEXT: vsra.vi v8, v8, 2
-; RV64-NEXT: vsrl.vi v10, v8, 31
-; RV64-NEXT: vadd.vv v8, v8, v10
-; RV64-NEXT: ret
+; CHECK-LABEL: vdiv_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vi v10, v8, 31
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i32> %va, splat (i32 -7)
ret <vscale x 4 x i32> %vc
}
@@ -676,29 +641,17 @@ define <vscale x 8 x i32> @vdiv_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %
}
define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv8i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmulh.vx v12, v8, a0
-; RV32-NEXT: vsub.vv v8, v12, v8
-; RV32-NEXT: vsrl.vi v12, v8, 31
-; RV32-NEXT: vsra.vi v8, v8, 2
-; RV32-NEXT: vadd.vv v8, v8, v12
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vdiv_vi_nxv8i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV64-NEXT: vmulh.vx v12, v8, a0
-; RV64-NEXT: vsub.vv v8, v12, v8
-; RV64-NEXT: vsra.vi v8, v8, 2
-; RV64-NEXT: vsrl.vi v12, v8, 31
-; RV64-NEXT: vadd.vv v8, v8, v12
-; RV64-NEXT: ret
+; CHECK-LABEL: vdiv_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v8, v12, v8
+; CHECK-NEXT: vsrl.vi v12, v8, 31
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i32> %va, splat (i32 -7)
ret <vscale x 8 x i32> %vc
}
@@ -726,29 +679,17 @@ define <vscale x 16 x i32> @vdiv_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signex
}
define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv16i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmulh.vx v16, v8, a0
-; RV32-NEXT: vsub.vv v8, v16, v8
-; RV32-NEXT: vsrl.vi v16, v8, 31
-; RV32-NEXT: vsra.vi v8, v8, 2
-; RV32-NEXT: vadd.vv v8, v8, v16
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vdiv_vi_nxv16i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV64-NEXT: vmulh.vx v16, v8, a0
-; RV64-NEXT: vsub.vv v8, v16, v8
-; RV64-NEXT: vsra.vi v8, v8, 2
-; RV64-NEXT: vsrl.vi v16, v8, 31
-; RV64-NEXT: vadd.vv v8, v8, v16
-; RV64-NEXT: ret
+; CHECK-LABEL: vdiv_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmulh.vx v16, v8, a0
+; CHECK-NEXT: vsub.vv v8, v16, v8
+; CHECK-NEXT: vsrl.vi v16, v8, 31
+; CHECK-NEXT: vsra.vi v8, v8, 2
+; CHECK-NEXT: vadd.vv v8, v8, v16
+; CHECK-NEXT: ret
%vc = sdiv <vscale x 16 x i32> %va, splat (i32 -7)
ret <vscale x 16 x i32> %vc
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
index 7682359ab0788..956e65972a476 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
@@ -33,8 +33,8 @@ define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v9, v9, v8
-; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -85,8 +85,8 @@ define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v9, v9, v8
-; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -137,8 +137,8 @@ define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v9, v9, v8
-; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -189,8 +189,8 @@ define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v9, v9, v8
-; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -241,8 +241,8 @@ define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmulh.vx v10, v8, a0
; CHECK-NEXT: vsub.vv v10, v10, v8
-; CHECK-NEXT: vsra.vi v10, v10, 2
; CHECK-NEXT: vsrl.vi v12, v10, 7
+; CHECK-NEXT: vsra.vi v10, v10, 2
; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v10
@@ -293,8 +293,8 @@ define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vmulh.vx v12, v8, a0
; CHECK-NEXT: vsub.vv v12, v12, v8
-; CHECK-NEXT: vsra.vi v12, v12, 2
; CHECK-NEXT: vsrl.vi v16, v12, 7
+; CHECK-NEXT: vsra.vi v12, v12, 2
; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v12
@@ -345,8 +345,8 @@ define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vmulh.vx v16, v8, a0
; CHECK-NEXT: vsub.vv v16, v16, v8
-; CHECK-NEXT: vsra.vi v16, v16, 2
; CHECK-NEXT: vsrl.vi v24, v16, 7
+; CHECK-NEXT: vsra.vi v16, v16, 2
; CHECK-NEXT: vadd.vv v16, v16, v24
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v16
@@ -384,8 +384,8 @@ define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
-; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -436,8 +436,8 @@ define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
-; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -488,8 +488,8 @@ define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
-; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -540,8 +540,8 @@ define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vmulh.vx v10, v8, a0
-; CHECK-NEXT: vsra.vi v10, v10, 1
; CHECK-NEXT: vsrl.vi v12, v10, 15
+; CHECK-NEXT: vsra.vi v10, v10, 1
; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v10
@@ -592,8 +592,8 @@ define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-NEXT: vmulh.vx v12, v8, a0
-; CHECK-NEXT: vsra.vi v12, v12, 1
; CHECK-NEXT: vsrl.vi v16, v12, 15
+; CHECK-NEXT: vsra.vi v12, v12, 1
; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v12
@@ -644,8 +644,8 @@ define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vmulh.vx v16, v8, a0
-; CHECK-NEXT: vsra.vi v16, v16, 1
; CHECK-NEXT: vsrl.vi v24, v16, 15
+; CHECK-NEXT: vsra.vi v16, v16, 1
; CHECK-NEXT: vadd.vv v16, v16, v24
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v16
@@ -677,33 +677,19 @@ define <vscale x 1 x i32> @vrem_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %
}
define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv1i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV32-NEXT: vmulh.vx v9, v8, a0
-; RV32-NEXT: vsub.vv v9, v9, v8
-; RV32-NEXT: vsrl.vi v10, v9, 31
-; RV32-NEXT: vsra.vi v9, v9, 2
-; RV32-NEXT: vadd.vv v9, v9, v10
-; RV32-NEXT: li a0, -7
-; RV32-NEXT: vnmsac.vx v8, a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vrem_vi_nxv1i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV64-NEXT: vmulh.vx v9, v8, a0
-; RV64-NEXT: vsub.vv v9, v9, v8
-; RV64-NEXT: vsra.vi v9, v9, 2
-; RV64-NEXT: vsrl.vi v10, v9, 31
-; RV64-NEXT: vadd.vv v9, v9, v10
-; RV64-NEXT: li a0, -7
-; RV64-NEXT: vnmsac.vx v8, a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vrem_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsrl.vi v10, v9, 31
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vadd.vv v9, v9, v10
+; CHECK-NEXT: li a0, -7
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
+; CHECK-NEXT: ret
%vc = srem <vscale x 1 x i32> %va, splat (i32 -7)
ret <vscale x 1 x i32> %vc
}
@@ -731,33 +717,19 @@ define <vscale x 2 x i32> @vrem_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %
}
define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv2i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV32-NEXT: vmulh.vx v9, v8, a0
-; RV32-NEXT: vsub.vv v9, v9, v8
-; RV32-NEXT: vsrl.vi v10, v9, 31
-; RV32-NEXT: vsra.vi v9, v9, 2
-; RV32-NEXT: vadd.vv v9, v9, v10
-; RV32-NEXT: li a0, -7
-; RV32-NEXT: vnmsac.vx v8, a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vrem_vi_nxv2i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV64-NEXT: vmulh.vx v9, v8, a0
-; RV64-NEXT: vsub.vv v9, v9, v8
-; RV64-NEXT: vsra.vi v9, v9, 2
-; RV64-NEXT: vsrl.vi v10, v9, 31
-; RV64-NEXT: vadd.vv v9, v9, v10
-; RV64-NEXT: li a0, -7
-; RV64-NEXT: vnmsac.vx v8, a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vrem_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsrl.vi v10, v9, 31
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vadd.vv v9, v9, v10
+; CHECK-NEXT: li a0, -7
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
+; CHECK-NEXT: ret
%vc = srem <vscale x 2 x i32> %va, splat (i32 -7)
ret <vscale x 2 x i32> %vc
}
@@ -785,33 +757,19 @@ define <vscale x 4 x i32> @vrem_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %
}
define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv4i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32-NEXT: vmulh.vx v10, v8, a0
-; RV32-NEXT: vsub.vv v10, v10, v8
-; RV32-NEXT: vsrl.vi v12, v10, 31
-; RV32-NEXT: vsra.vi v10, v10, 2
-; RV32-NEXT: vadd.vv v10, v10, v12
-; RV32-NEXT: li a0, -7
-; RV32-NEXT: vnmsac.vx v8, a0, v10
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vrem_vi_nxv4i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV64-NEXT: vmulh.vx v10, v8, a0
-; RV64-NEXT: vsub.vv v10, v10, v8
-; RV64-NEXT: vsra.vi v10, v10, 2
-; RV64-NEXT: vsrl.vi v12, v10, 31
-; RV64-NEXT: vadd.vv v10, v10, v12
-; RV64-NEXT: li a0, -7
-; RV64-NEXT: vnmsac.vx v8, a0, v10
-; RV64-NEXT: ret
+; CHECK-LABEL: vrem_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v10, v10, v8
+; CHECK-NEXT: vsrl.vi v12, v10, 31
+; CHECK-NEXT: vsra.vi v10, v10, 2
+; CHECK-NEXT: vadd.vv v10, v10, v12
+; CHECK-NEXT: li a0, -7
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
+; CHECK-NEXT: ret
%vc = srem <vscale x 4 x i32> %va, splat (i32 -7)
ret <vscale x 4 x i32> %vc
}
@@ -839,33 +797,19 @@ define <vscale x 8 x i32> @vrem_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %
}
define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv8i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmulh.vx v12, v8, a0
-; RV32-NEXT: vsub.vv v12, v12, v8
-; RV32-NEXT: vsrl.vi v16, v12, 31
-; RV32-NEXT: vsra.vi v12, v12, 2
-; RV32-NEXT: vadd.vv v12, v12, v16
-; RV32-NEXT: li a0, -7
-; RV32-NEXT: vnmsac.vx v8, a0, v12
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vrem_vi_nxv8i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV64-NEXT: vmulh.vx v12, v8, a0
-; RV64-NEXT: vsub.vv v12, v12, v8
-; RV64-NEXT: vsra.vi v12, v12, 2
-; RV64-NEXT: vsrl.vi v16, v12, 31
-; RV64-NEXT: vadd.vv v12, v12, v16
-; RV64-NEXT: li a0, -7
-; RV64-NEXT: vnmsac.vx v8, a0, v12
-; RV64-NEXT: ret
+; CHECK-LABEL: vrem_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v12, v12, v8
+; CHECK-NEXT: vsrl.vi v16, v12, 31
+; CHECK-NEXT: vsra.vi v12, v12, 2
+; CHECK-NEXT: vadd.vv v12, v12, v16
+; CHECK-NEXT: li a0, -7
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
+; CHECK-NEXT: ret
%vc = srem <vscale x 8 x i32> %va, splat (i32 -7)
ret <vscale x 8 x i32> %vc
}
@@ -893,33 +837,19 @@ define <vscale x 16 x i32> @vrem_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signex
}
define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv16i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmulh.vx v16, v8, a0
-; RV32-NEXT: vsub.vv v16, v16, v8
-; RV32-NEXT: vsrl.vi v24, v16, 31
-; RV32-NEXT: vsra.vi v16, v16, 2
-; RV32-NEXT: vadd.vv v16, v16, v24
-; RV32-NEXT: li a0, -7
-; RV32-NEXT: vnmsac.vx v8, a0, v16
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vrem_vi_nxv16i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV64-NEXT: vmulh.vx v16, v8, a0
-; RV64-NEXT: vsub.vv v16, v16, v8
-; RV64-NEXT: vsra.vi v16, v16, 2
-; RV64-NEXT: vsrl.vi v24, v16, 31
-; RV64-NEXT: vadd.vv v16, v16, v24
-; RV64-NEXT: li a0, -7
-; RV64-NEXT: vnmsac.vx v8, a0, v16
-; RV64-NEXT: ret
+; CHECK-LABEL: vrem_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmulh.vx v16, v8, a0
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: vsrl.vi v24, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 2
+; CHECK-NEXT: vadd.vv v16, v16, v24
+; CHECK-NEXT: li a0, -7
+; CHECK-NEXT: vnmsac.vx v8, a0, v16
+; CHECK-NEXT: ret
%vc = srem <vscale x 16 x i32> %va, splat (i32 -7)
ret <vscale x 16 x i32> %vc
}
diff --git a/llvm/test/CodeGen/X86/scmp.ll b/llvm/test/CodeGen/X86/scmp.ll
index 393e05bfd0cc6..6c3fdc26e0175 100644
--- a/llvm/test/CodeGen/X86/scmp.ll
+++ b/llvm/test/CodeGen/X86/scmp.ll
@@ -2519,147 +2519,152 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; SSE2-NEXT: pushq %r12
; SSE2-NEXT: pushq %rbx
; SSE2-NEXT: movq %rdi, %rax
-; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
-; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %ebx
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %ebp
-; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %r14d
+; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %r12d
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %r15d
-; SSE2-NEXT: addb %r15b, %r15b
-; SSE2-NEXT: sarb %r15b
+; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
+; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
+; SSE2-NEXT: addb %dil, %dil
+; SSE2-NEXT: sarb %dil
; SSE2-NEXT: addb %sil, %sil
; SSE2-NEXT: sarb %sil
-; SSE2-NEXT: cmpb %r15b, %sil
+; SSE2-NEXT: cmpb %dil, %sil
; SSE2-NEXT: setl %sil
-; SSE2-NEXT: setg %r15b
-; SSE2-NEXT: subb %sil, %r15b
-; SSE2-NEXT: movsbq %r15b, %rsi
-; SSE2-NEXT: movq %rsi, (%rax)
-; SSE2-NEXT: movq %rsi, %xmm0
-; SSE2-NEXT: sarq $63, %rsi
-; SSE2-NEXT: addb %r14b, %r14b
-; SSE2-NEXT: sarb %r14b
-; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %r15d
+; SSE2-NEXT: setg %dil
+; SSE2-NEXT: subb %sil, %dil
+; SSE2-NEXT: movsbq %dil, %rdi
+; SSE2-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; SSE2-NEXT: movq %rdi, (%rax)
+; SSE2-NEXT: sarq $63, %rdi
+; SSE2-NEXT: addb %r11b, %r11b
+; SSE2-NEXT: sarb %r11b
+; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %esi
+; SSE2-NEXT: addb %sil, %sil
+; SSE2-NEXT: sarb %sil
+; SSE2-NEXT: cmpb %r11b, %sil
+; SSE2-NEXT: setl %sil
+; SSE2-NEXT: setg %r11b
+; SSE2-NEXT: subb %sil, %r11b
+; SSE2-NEXT: movsbq %r11b, %r11
+; SSE2-NEXT: movq %r11, %r14
+; SSE2-NEXT: sarq $63, %r14
; SSE2-NEXT: addb %r15b, %r15b
; SSE2-NEXT: sarb %r15b
-; SSE2-NEXT: cmpb %r14b, %r15b
-; SSE2-NEXT: setl %r14b
-; SSE2-NEXT: setg %r15b
-; SSE2-NEXT: subb %r14b, %r15b
-; SSE2-NEXT: movsbq %r15b, %r14
-; SSE2-NEXT: movq %r14, %r15
-; SSE2-NEXT: sarq $63, %r15
-; SSE2-NEXT: addb %bpl, %bpl
-; SSE2-NEXT: sarb %bpl
; SSE2-NEXT: addb %dl, %dl
; SSE2-NEXT: sarb %dl
-; SSE2-NEXT: cmpb %bpl, %dl
+; SSE2-NEXT: cmpb %r15b, %dl
; SSE2-NEXT: setl %dl
-; SSE2-NEXT: setg %bpl
-; SSE2-NEXT: subb %dl, %bpl
-; SSE2-NEXT: movsbq %bpl, %rdx
-; SSE2-NEXT: movq %rdx, %r12
-; SSE2-NEXT: sarq $63, %r12
-; SSE2-NEXT: addb %bl, %bl
-; SSE2-NEXT: sarb %bl
+; SSE2-NEXT: setg %sil
+; SSE2-NEXT: subb %dl, %sil
+; SSE2-NEXT: movsbq %sil, %r15
+; SSE2-NEXT: movq %r15, %rsi
+; SSE2-NEXT: sarq $63, %rsi
+; SSE2-NEXT: addb %r12b, %r12b
+; SSE2-NEXT: sarb %r12b
; SSE2-NEXT: addb %cl, %cl
; SSE2-NEXT: sarb %cl
-; SSE2-NEXT: cmpb %bl, %cl
+; SSE2-NEXT: cmpb %r12b, %cl
; SSE2-NEXT: setl %cl
-; SSE2-NEXT: setg %bl
-; SSE2-NEXT: subb %cl, %bl
-; SSE2-NEXT: movsbq %bl, %rbx
-; SSE2-NEXT: movq %rbx, %rcx
-; SSE2-NEXT: sarq $63, %rcx
-; SSE2-NEXT: addb %r11b, %r11b
-; SSE2-NEXT: sarb %r11b
+; SSE2-NEXT: setg %dl
+; SSE2-NEXT: subb %cl, %dl
+; SSE2-NEXT: movsbq %dl, %rcx
+; SSE2-NEXT: movq %rcx, %r12
+; SSE2-NEXT: sarq $63, %r12
+; SSE2-NEXT: addb %bpl, %bpl
+; SSE2-NEXT: sarb %bpl
; SSE2-NEXT: addb %r8b, %r8b
; SSE2-NEXT: sarb %r8b
-; SSE2-NEXT: cmpb %r11b, %r8b
-; SSE2-NEXT: setl %r8b
-; SSE2-NEXT: setg %r11b
-; SSE2-NEXT: subb %r8b, %r11b
-; SSE2-NEXT: movsbq %r11b, %r8
-; SSE2-NEXT: movq %r8, %r11
-; SSE2-NEXT: sarq $63, %r11
-; SSE2-NEXT: addb %r10b, %r10b
-; SSE2-NEXT: sarb %r10b
+; SSE2-NEXT: cmpb %bpl, %r8b
+; SSE2-NEXT: setl %dl
+; SSE2-NEXT: setg %r8b
+; SSE2-NEXT: subb %dl, %r8b
+; SSE2-NEXT: movsbq %r8b, %r8
+; SSE2-NEXT: movq %r8, %r13
+; SSE2-NEXT: sarq $63, %r13
+; SSE2-NEXT: addb %bl, %bl
+; SSE2-NEXT: sarb %bl
; SSE2-NEXT: addb %r9b, %r9b
; SSE2-NEXT: sarb %r9b
-; SSE2-NEXT: cmpb %r10b, %r9b
-; SSE2-NEXT: setl %r9b
+; SSE2-NEXT: cmpb %bl, %r9b
+; SSE2-NEXT: setl %dl
+; SSE2-NEXT: setg %r9b
+; SSE2-NEXT: subb %dl, %r9b
+; SSE2-NEXT: movsbq %r9b, %r9
+; SSE2-NEXT: movq %r9, %rbx
+; SSE2-NEXT: sarq $63, %rbx
+; SSE2-NEXT: addb %r10b, %r10b
+; SSE2-NEXT: sarb %r10b
+; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
+; SSE2-NEXT: addb %dl, %dl
+; SSE2-NEXT: sarb %dl
+; SSE2-NEXT: cmpb %r10b, %dl
+; SSE2-NEXT: setl %dl
; SSE2-NEXT: setg %r10b
-; SSE2-NEXT: subb %r9b, %r10b
-; SSE2-NEXT: movsbq %r10b, %r9
-; SSE2-NEXT: movq %r9, %r10
-; SSE2-NEXT: sarq $63, %r10
-; SSE2-NEXT: addb %dil, %dil
-; SSE2-NEXT: sarb %dil
-; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %ebp
-; SSE2-NEXT: addb %bpl, %bpl
-; SSE2-NEXT: sarb %bpl
-; SSE2-NEXT: cmpb %dil, %bpl
-; SSE2-NEXT: setl %dil
-; SSE2-NEXT: setg %bpl
-; SSE2-NEXT: subb %dil, %bpl
-; SSE2-NEXT: movsbq %bpl, %rdi
-; SSE2-NEXT: movq %rdi, %r13
-; SSE2-NEXT: sarq $63, %r13
-; SSE2-NEXT: movl %r13d, 96(%rax)
+; SSE2-NEXT: subb %dl, %r10b
+; SSE2-NEXT: movsbq %r10b, %r10
+; SSE2-NEXT: movq %r10, %rdx
+; SSE2-NEXT: sarq $63, %rdx
+; SSE2-NEXT: movl %edx, 96(%rax)
; SSE2-NEXT: movabsq $2251799813685247, %rbp # imm = 0x7FFFFFFFFFFFF
-; SSE2-NEXT: andq %r13, %rbp
-; SSE2-NEXT: shldq $62, %rdi, %r13
-; SSE2-NEXT: movq %r13, 88(%rax)
-; SSE2-NEXT: movq %r9, %r13
-; SSE2-NEXT: shrdq $44, %r10, %r13
-; SSE2-NEXT: movq %r13, 64(%rax)
-; SSE2-NEXT: movq %r8, %r13
-; SSE2-NEXT: shrdq $33, %r11, %r13
+; SSE2-NEXT: andq %rdx, %rbp
+; SSE2-NEXT: shldq $62, %r10, %rdx
+; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Folded Reload
+; SSE2-NEXT: # xmm0 = mem[0],zero
+; SSE2-NEXT: movq %rdx, 88(%rax)
+; SSE2-NEXT: shldq $20, %r9, %rbx
+; SSE2-NEXT: movq %rbx, 64(%rax)
+; SSE2-NEXT: shldq $31, %r8, %r13
; SSE2-NEXT: movq %r13, 48(%rax)
-; SSE2-NEXT: movq %rbx, %r13
-; SSE2-NEXT: shrdq $22, %rcx, %r13
-; SSE2-NEXT: movq %r13, 32(%rax)
-; SSE2-NEXT: movq %rdx, %r13
-; SSE2-NEXT: shrdq $11, %r12, %r13
-; SSE2-NEXT: movq %r13, 16(%rax)
-; SSE2-NEXT: movq %rbp, %r13
-; SSE2-NEXT: shrq $48, %r13
-; SSE2-NEXT: movb %r13b, 102(%rax)
+; SSE2-NEXT: shldq $42, %rcx, %r12
+; SSE2-NEXT: movq %r12, 32(%rax)
+; SSE2-NEXT: movq %r15, %rdx
+; SSE2-NEXT: shrdq $11, %rsi, %rdx
+; SSE2-NEXT: movq %rdx, 16(%rax)
+; SSE2-NEXT: movq %rbp, %rdx
+; SSE2-NEXT: shrq $48, %rdx
+; SSE2-NEXT: movb %dl, 102(%rax)
; SSE2-NEXT: shrq $32, %rbp
; SSE2-NEXT: movw %bp, 100(%rax)
-; SSE2-NEXT: movabsq $9007199254740991, %r13 # imm = 0x1FFFFFFFFFFFFF
-; SSE2-NEXT: andq %r13, %r15
-; SSE2-NEXT: shldq $9, %r14, %r15
-; SSE2-NEXT: shlq $62, %rdi
-; SSE2-NEXT: orq %r15, %rdi
-; SSE2-NEXT: movq %rdi, 80(%rax)
-; SSE2-NEXT: movabsq $9007199254738944, %rdi # imm = 0x1FFFFFFFFFF800
-; SSE2-NEXT: andq %r12, %rdi
-; SSE2-NEXT: shlq $42, %rbx
-; SSE2-NEXT: shrq $11, %rdi
-; SSE2-NEXT: orq %rbx, %rdi
-; SSE2-NEXT: movq %rdi, 24(%rax)
-; SSE2-NEXT: shlq $9, %r14
-; SSE2-NEXT: andl $511, %r10d # imm = 0x1FF
+; SSE2-NEXT: movabsq $9007199254740991, %rdx # imm = 0x1FFFFFFFFFFFFF
+; SSE2-NEXT: andq %rdx, %r14
+; SSE2-NEXT: shldq $9, %r11, %r14
+; SSE2-NEXT: shlq $62, %r10
; SSE2-NEXT: orq %r14, %r10
-; SSE2-NEXT: movq %r10, 72(%rax)
+; SSE2-NEXT: movq %r10, 80(%rax)
+; SSE2-NEXT: movabsq $9007199254738944, %r10 # imm = 0x1FFFFFFFFFF800
+; SSE2-NEXT: andq %rsi, %r10
+; SSE2-NEXT: movq %rcx, %rsi
+; SSE2-NEXT: shlq $42, %rsi
+; SSE2-NEXT: shrq $11, %r10
+; SSE2-NEXT: orq %rsi, %r10
+; SSE2-NEXT: movq %r10, 24(%rax)
+; SSE2-NEXT: shlq $9, %r11
+; SSE2-NEXT: movq %r9, %rsi
+; SSE2-NEXT: shrq $44, %rsi
+; SSE2-NEXT: andl $511, %esi # imm = 0x1FF
+; SSE2-NEXT: orq %r11, %rsi
+; SSE2-NEXT: movq %rsi, 72(%rax)
; SSE2-NEXT: shlq $20, %r9
-; SSE2-NEXT: andl $1048575, %r11d # imm = 0xFFFFF
-; SSE2-NEXT: orq %r9, %r11
-; SSE2-NEXT: movq %r11, 56(%rax)
+; SSE2-NEXT: movq %r8, %rsi
+; SSE2-NEXT: shrq $33, %rsi
+; SSE2-NEXT: andl $1048575, %esi # imm = 0xFFFFF
+; SSE2-NEXT: orq %r9, %rsi
+; SSE2-NEXT: movq %rsi, 56(%rax)
; SSE2-NEXT: shlq $31, %r8
+; SSE2-NEXT: shrq $22, %rcx
; SSE2-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
; SSE2-NEXT: orq %r8, %rcx
; SSE2-NEXT: movq %rcx, 40(%rax)
-; SSE2-NEXT: movq %rsi, %xmm1
+; SSE2-NEXT: movq %rdi, %xmm1
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; SSE2-NEXT: movq %xmm0, %rcx
-; SSE2-NEXT: andq %r13, %rcx
-; SSE2-NEXT: shlq $53, %rdx
-; SSE2-NEXT: orq %rcx, %rdx
-; SSE2-NEXT: movq %rdx, 8(%rax)
+; SSE2-NEXT: andq %rdx, %rcx
+; SSE2-NEXT: shlq $53, %r15
+; SSE2-NEXT: orq %rcx, %r15
+; SSE2-NEXT: movq %r15, 8(%rax)
; SSE2-NEXT: popq %rbx
; SSE2-NEXT: popq %r12
; SSE2-NEXT: popq %r13
@@ -2682,30 +2687,30 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; SSE4-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
; SSE4-NEXT: movzbl {{[0-9]+}}(%rsp), %ebx
; SSE4-NEXT: movzbl {{[0-9]+}}(%rsp), %ebp
-; SSE4-NEXT: movzbl {{[0-9]+}}(%rsp), %r15d
; SSE4-NEXT: movzbl {{[0-9]+}}(%rsp), %r14d
-; SSE4-NEXT: addb %r14b, %r14b
-; SSE4-NEXT: sarb %r14b
-; SSE4-NEXT: addb %sil, %sil
-; SSE4-NEXT: sarb %sil
-; SSE4-NEXT: cmpb %r14b, %sil
-; SSE4-NEXT: setl %sil
-; SSE4-NEXT: setg %r14b
-; SSE4-NEXT: subb %sil, %r14b
-; SSE4-NEXT: movsbq %r14b, %r14
-; SSE4-NEXT: movq %r14, (%rax)
-; SSE4-NEXT: sarq $63, %r14
+; SSE4-NEXT: movzbl {{[0-9]+}}(%rsp), %r15d
; SSE4-NEXT: addb %r15b, %r15b
; SSE4-NEXT: sarb %r15b
-; SSE4-NEXT: movzbl {{[0-9]+}}(%rsp), %esi
; SSE4-NEXT: addb %sil, %sil
; SSE4-NEXT: sarb %sil
; SSE4-NEXT: cmpb %r15b, %sil
; SSE4-NEXT: setl %sil
; SSE4-NEXT: setg %r15b
; SSE4-NEXT: subb %sil, %r15b
-; SSE4-NEXT: movsbq %r15b, %rsi
-; SSE4-NEXT: movq %rsi, %r12
+; SSE4-NEXT: movsbq %r15b, %r15
+; SSE4-NEXT: movq %r15, (%rax)
+; SSE4-NEXT: sarq $63, %r15
+; SSE4-NEXT: addb %r14b, %r14b
+; SSE4-NEXT: sarb %r14b
+; SSE4-NEXT: movzbl {{[0-9]+}}(%rsp), %esi
+; SSE4-NEXT: addb %sil, %sil
+; SSE4-NEXT: sarb %sil
+; SSE4-NEXT: cmpb %r14b, %sil
+; SSE4-NEXT: setl %sil
+; SSE4-NEXT: setg %r14b
+; SSE4-NEXT: subb %sil, %r14b
+; SSE4-NEXT: movsbq %r14b, %r12
+; SSE4-NEXT: movq %r12, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE4-NEXT: sarq $63, %r12
; SSE4-NEXT: addb %bpl, %bpl
; SSE4-NEXT: sarb %bpl
@@ -2716,8 +2721,8 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; SSE4-NEXT: setg %bpl
; SSE4-NEXT: subb %dl, %bpl
; SSE4-NEXT: movsbq %bpl, %r13
-; SSE4-NEXT: movq %r13, %r15
-; SSE4-NEXT: sarq $63, %r15
+; SSE4-NEXT: movq %r13, %rsi
+; SSE4-NEXT: sarq $63, %rsi
; SSE4-NEXT: addb %bl, %bl
; SSE4-NEXT: sarb %bl
; SSE4-NEXT: addb %cl, %cl
@@ -2726,9 +2731,9 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; SSE4-NEXT: setl %cl
; SSE4-NEXT: setg %dl
; SSE4-NEXT: subb %cl, %dl
-; SSE4-NEXT: movsbq %dl, %rbx
-; SSE4-NEXT: movq %rbx, %rcx
-; SSE4-NEXT: sarq $63, %rcx
+; SSE4-NEXT: movsbq %dl, %rcx
+; SSE4-NEXT: movq %rcx, %rbx
+; SSE4-NEXT: sarq $63, %rbx
; SSE4-NEXT: addb %r11b, %r11b
; SSE4-NEXT: sarb %r11b
; SSE4-NEXT: addb %r8b, %r8b
@@ -2737,81 +2742,88 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; SSE4-NEXT: setl %dl
; SSE4-NEXT: setg %r8b
; SSE4-NEXT: subb %dl, %r8b
-; SSE4-NEXT: movsbq %r8b, %rdx
-; SSE4-NEXT: movq %rdx, %r8
-; SSE4-NEXT: sarq $63, %r8
+; SSE4-NEXT: movsbq %r8b, %r14
+; SSE4-NEXT: movq %r14, %r11
+; SSE4-NEXT: sarq $63, %r11
; SSE4-NEXT: addb %r10b, %r10b
; SSE4-NEXT: sarb %r10b
; SSE4-NEXT: addb %r9b, %r9b
; SSE4-NEXT: sarb %r9b
; SSE4-NEXT: cmpb %r10b, %r9b
-; SSE4-NEXT: setl %r9b
-; SSE4-NEXT: setg %r10b
-; SSE4-NEXT: subb %r9b, %r10b
-; SSE4-NEXT: movsbq %r10b, %r9
-; SSE4-NEXT: movq %r9, %r10
-; SSE4-NEXT: sarq $63, %r10
+; SSE4-NEXT: setl %r8b
+; SSE4-NEXT: setg %r9b
+; SSE4-NEXT: subb %r8b, %r9b
+; SSE4-NEXT: movsbq %r9b, %r8
+; SSE4-NEXT: movq %r8, %r9
+; SSE4-NEXT: sarq $63, %r9
; SSE4-NEXT: addb %dil, %dil
; SSE4-NEXT: sarb %dil
-; SSE4-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
-; SSE4-NEXT: addb %r11b, %r11b
-; SSE4-NEXT: sarb %r11b
-; SSE4-NEXT: cmpb %dil, %r11b
+; SSE4-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
+; SSE4-NEXT: addb %r10b, %r10b
+; SSE4-NEXT: sarb %r10b
+; SSE4-NEXT: cmpb %dil, %r10b
; SSE4-NEXT: setl %dil
-; SSE4-NEXT: setg %r11b
-; SSE4-NEXT: subb %dil, %r11b
-; SSE4-NEXT: movsbq %r11b, %rdi
-; SSE4-NEXT: movq %rdi, %r11
-; SSE4-NEXT: sarq $63, %r11
-; SSE4-NEXT: movl %r11d, 96(%rax)
-; SSE4-NEXT: movabsq $2251799813685247, %rbp # imm = 0x7FFFFFFFFFFFF
-; SSE4-NEXT: andq %r11, %rbp
-; SSE4-NEXT: shldq $62, %rdi, %r11
-; SSE4-NEXT: movq %r11, 88(%rax)
-; SSE4-NEXT: movq %r9, %r11
-; SSE4-NEXT: shrdq $44, %r10, %r11
-; SSE4-NEXT: movq %r11, 64(%rax)
-; SSE4-NEXT: movq %rdx, %r11
-; SSE4-NEXT: shrdq $33, %r8, %r11
-; SSE4-NEXT: movq %r11, 48(%rax)
-; SSE4-NEXT: movq %rbx, %r11
-; SSE4-NEXT: shrdq $22, %rcx, %r11
-; SSE4-NEXT: movq %r11, 32(%rax)
-; SSE4-NEXT: movq %r13, %r11
-; SSE4-NEXT: shrdq $11, %r15, %r11
-; SSE4-NEXT: movq %r11, 16(%rax)
-; SSE4-NEXT: movq %rbp, %r11
-; SSE4-NEXT: shrq $48, %r11
-; SSE4-NEXT: movb %r11b, 102(%rax)
-; SSE4-NEXT: shrq $32, %rbp
-; SSE4-NEXT: movw %bp, 100(%rax)
-; SSE4-NEXT: movabsq $9007199254740991, %r11 # imm = 0x1FFFFFFFFFFFFF
-; SSE4-NEXT: andq %r11, %r12
-; SSE4-NEXT: shldq $9, %rsi, %r12
+; SSE4-NEXT: setg %r10b
+; SSE4-NEXT: subb %dil, %r10b
+; SSE4-NEXT: movsbq %r10b, %rdi
+; SSE4-NEXT: movq %rdi, %r10
+; SSE4-NEXT: sarq $63, %r10
+; SSE4-NEXT: movq %rax, %rdx
+; SSE4-NEXT: movl %r10d, 96(%rax)
+; SSE4-NEXT: movq %r10, %rbp
+; SSE4-NEXT: shldq $62, %rdi, %rbp
+; SSE4-NEXT: movabsq $2251799813685247, %rax # imm = 0x7FFFFFFFFFFFF
+; SSE4-NEXT: andq %r10, %rax
+; SSE4-NEXT: movq %rbp, 88(%rdx)
+; SSE4-NEXT: shldq $20, %r8, %r9
+; SSE4-NEXT: movq %r9, 64(%rdx)
+; SSE4-NEXT: shldq $31, %r14, %r11
+; SSE4-NEXT: movq %r11, 48(%rdx)
+; SSE4-NEXT: shldq $42, %rcx, %rbx
+; SSE4-NEXT: movq %rbx, 32(%rdx)
+; SSE4-NEXT: movq %r13, %r9
+; SSE4-NEXT: shrdq $11, %rsi, %r9
+; SSE4-NEXT: movq %r9, 16(%rdx)
+; SSE4-NEXT: movq %rax, %r9
+; SSE4-NEXT: shrq $48, %r9
+; SSE4-NEXT: movb %r9b, 102(%rdx)
+; SSE4-NEXT: shrq $32, %rax
+; SSE4-NEXT: movw %ax, 100(%rdx)
+; SSE4-NEXT: movq %rdx, %rax
+; SSE4-NEXT: movabsq $9007199254740991, %r9 # imm = 0x1FFFFFFFFFFFFF
+; SSE4-NEXT: andq %r9, %r12
+; SSE4-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
+; SSE4-NEXT: shldq $9, %rdx, %r12
; SSE4-NEXT: shlq $62, %rdi
; SSE4-NEXT: orq %r12, %rdi
; SSE4-NEXT: movq %rdi, 80(%rax)
-; SSE4-NEXT: andq %r11, %r14
+; SSE4-NEXT: andq %r9, %r15
; SSE4-NEXT: shlq $53, %r13
-; SSE4-NEXT: orq %r14, %r13
+; SSE4-NEXT: orq %r15, %r13
; SSE4-NEXT: movq %r13, 8(%rax)
-; SSE4-NEXT: shlq $42, %rbx
+; SSE4-NEXT: movq %rcx, %r9
+; SSE4-NEXT: shlq $42, %r9
; SSE4-NEXT: movabsq $9007199254738944, %rdi # imm = 0x1FFFFFFFFFF800
-; SSE4-NEXT: andq %r15, %rdi
+; SSE4-NEXT: andq %rsi, %rdi
; SSE4-NEXT: shrq $11, %rdi
-; SSE4-NEXT: orq %rbx, %rdi
+; SSE4-NEXT: orq %r9, %rdi
; SSE4-NEXT: movq %rdi, 24(%rax)
-; SSE4-NEXT: shlq $9, %rsi
-; SSE4-NEXT: andl $511, %r10d # imm = 0x1FF
-; SSE4-NEXT: orq %rsi, %r10
-; SSE4-NEXT: movq %r10, 72(%rax)
-; SSE4-NEXT: shlq $20, %r9
-; SSE4-NEXT: andl $1048575, %r8d # imm = 0xFFFFF
-; SSE4-NEXT: orq %r9, %r8
-; SSE4-NEXT: movq %r8, 56(%rax)
-; SSE4-NEXT: shlq $31, %rdx
+; SSE4-NEXT: shlq $9, %rdx
+; SSE4-NEXT: movq %r8, %rdi
+; SSE4-NEXT: shrq $44, %rdi
+; SSE4-NEXT: andl $511, %edi # imm = 0x1FF
+; SSE4-NEXT: orq %rdx, %rdi
+; SSE4-NEXT: movq %rdi, 72(%rax)
+; SSE4-NEXT: shlq $20, %r8
+; SSE4-NEXT: movq %r14, %rsi
+; SSE4-NEXT: shrq $33, %rsi
+; SSE4-NEXT: andl $1048575, %esi # imm = 0xFFFFF
+; SSE4-NEXT: orq %r8, %rsi
+; SSE4-NEXT: movq %rsi, 56(%rax)
+; SSE4-NEXT: shlq $31, %r14
+; SSE4-NEXT: shrq $22, %rcx
; SSE4-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; SSE4-NEXT: orq %rdx, %rcx
+; SSE4-NEXT: orq %r14, %rcx
; SSE4-NEXT: movq %rcx, 40(%rax)
; SSE4-NEXT: popq %rbx
; SSE4-NEXT: popq %r12
@@ -2879,9 +2891,9 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; AVX-NEXT: setl %cl
; AVX-NEXT: setg %dl
; AVX-NEXT: subb %cl, %dl
-; AVX-NEXT: movsbq %dl, %rbx
-; AVX-NEXT: movq %rbx, %rcx
-; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: movsbq %dl, %rcx
+; AVX-NEXT: movq %rcx, %rbx
+; AVX-NEXT: sarq $63, %rbx
; AVX-NEXT: addb %r11b, %r11b
; AVX-NEXT: sarb %r11b
; AVX-NEXT: addb %r8b, %r8b
@@ -2891,77 +2903,80 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; AVX-NEXT: setg %r8b
; AVX-NEXT: subb %dl, %r8b
; AVX-NEXT: movsbq %r8b, %rdx
-; AVX-NEXT: movq %rdx, %r8
-; AVX-NEXT: sarq $63, %r8
+; AVX-NEXT: movq %rdx, %r11
+; AVX-NEXT: sarq $63, %r11
; AVX-NEXT: addb %r10b, %r10b
; AVX-NEXT: sarb %r10b
; AVX-NEXT: addb %r9b, %r9b
; AVX-NEXT: sarb %r9b
; AVX-NEXT: cmpb %r10b, %r9b
-; AVX-NEXT: setl %r9b
-; AVX-NEXT: setg %r10b
-; AVX-NEXT: subb %r9b, %r10b
-; AVX-NEXT: movsbq %r10b, %r9
-; AVX-NEXT: movq %r9, %r10
-; AVX-NEXT: sarq $63, %r10
+; AVX-NEXT: setl %r8b
+; AVX-NEXT: setg %r9b
+; AVX-NEXT: subb %r8b, %r9b
+; AVX-NEXT: movsbq %r9b, %r8
+; AVX-NEXT: movq %r8, %r9
+; AVX-NEXT: sarq $63, %r9
; AVX-NEXT: addb %dil, %dil
; AVX-NEXT: sarb %dil
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
-; AVX-NEXT: addb %r11b, %r11b
-; AVX-NEXT: sarb %r11b
-; AVX-NEXT: cmpb %dil, %r11b
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
+; AVX-NEXT: addb %r10b, %r10b
+; AVX-NEXT: sarb %r10b
+; AVX-NEXT: cmpb %dil, %r10b
; AVX-NEXT: setl %dil
-; AVX-NEXT: setg %r11b
-; AVX-NEXT: subb %dil, %r11b
-; AVX-NEXT: movsbq %r11b, %rdi
-; AVX-NEXT: movq %rdi, %r11
-; AVX-NEXT: sarq $63, %r11
-; AVX-NEXT: movl %r11d, 96(%rax)
+; AVX-NEXT: setg %r10b
+; AVX-NEXT: subb %dil, %r10b
+; AVX-NEXT: movsbq %r10b, %rdi
+; AVX-NEXT: movq %rdi, %r10
+; AVX-NEXT: sarq $63, %r10
+; AVX-NEXT: movl %r10d, 96(%rax)
; AVX-NEXT: movb $51, %bpl
-; AVX-NEXT: bzhiq %rbp, %r11, %rbp
-; AVX-NEXT: shldq $62, %rdi, %r11
-; AVX-NEXT: movq %r11, 88(%rax)
-; AVX-NEXT: movq %r9, %r11
-; AVX-NEXT: shrdq $44, %r10, %r11
-; AVX-NEXT: movq %r11, 64(%rax)
-; AVX-NEXT: movq %rdx, %r11
-; AVX-NEXT: shrdq $33, %r8, %r11
+; AVX-NEXT: bzhiq %rbp, %r10, %rbp
+; AVX-NEXT: shldq $62, %rdi, %r10
+; AVX-NEXT: movq %r10, 88(%rax)
+; AVX-NEXT: shldq $20, %r8, %r9
+; AVX-NEXT: movq %r9, 64(%rax)
+; AVX-NEXT: shldq $31, %rdx, %r11
; AVX-NEXT: movq %r11, 48(%rax)
-; AVX-NEXT: movq %rbx, %r11
-; AVX-NEXT: shrdq $22, %rcx, %r11
-; AVX-NEXT: movq %r11, 32(%rax)
-; AVX-NEXT: movq %r15, %r11
-; AVX-NEXT: shrdq $11, %r13, %r11
-; AVX-NEXT: movq %r11, 16(%rax)
-; AVX-NEXT: movq %rbp, %r11
-; AVX-NEXT: shrq $48, %r11
-; AVX-NEXT: movb %r11b, 102(%rax)
+; AVX-NEXT: shldq $42, %rcx, %rbx
+; AVX-NEXT: movq %rbx, 32(%rax)
+; AVX-NEXT: shldq $53, %r15, %r13
+; AVX-NEXT: movq %r13, 16(%rax)
+; AVX-NEXT: movq %rbp, %r9
+; AVX-NEXT: shrq $48, %r9
+; AVX-NEXT: movb %r9b, 102(%rax)
; AVX-NEXT: shrq $32, %rbp
; AVX-NEXT: movw %bp, 100(%rax)
-; AVX-NEXT: movb $53, %r11b
-; AVX-NEXT: bzhiq %r11, %r12, %r12
-; AVX-NEXT: shldq $9, %rsi, %r12
+; AVX-NEXT: movb $53, %r9b
+; AVX-NEXT: bzhiq %r9, %r12, %r10
+; AVX-NEXT: shldq $9, %rsi, %r10
; AVX-NEXT: shlq $62, %rdi
-; AVX-NEXT: orq %r12, %rdi
+; AVX-NEXT: orq %r10, %rdi
; AVX-NEXT: movq %rdi, 80(%rax)
-; AVX-NEXT: movb $42, %dil
-; AVX-NEXT: bzhiq %rdi, %r13, %rdi
-; AVX-NEXT: shlq $42, %rbx
-; AVX-NEXT: orq %rdi, %rbx
-; AVX-NEXT: movq %rbx, 24(%rax)
-; AVX-NEXT: bzhiq %r11, %r14, %rdi
+; AVX-NEXT: movq %rcx, %rdi
+; AVX-NEXT: shlq $42, %rdi
+; AVX-NEXT: movabsq $9007199254738944, %r10 # imm = 0x1FFFFFFFFFF800
+; AVX-NEXT: andq %r15, %r10
+; AVX-NEXT: shrq $11, %r10
+; AVX-NEXT: orq %rdi, %r10
+; AVX-NEXT: movq %r10, 24(%rax)
+; AVX-NEXT: bzhiq %r9, %r14, %rdi
; AVX-NEXT: shlq $53, %r15
; AVX-NEXT: orq %rdi, %r15
; AVX-NEXT: movq %r15, 8(%rax)
; AVX-NEXT: shlq $9, %rsi
-; AVX-NEXT: andl $511, %r10d # imm = 0x1FF
-; AVX-NEXT: orq %rsi, %r10
-; AVX-NEXT: movq %r10, 72(%rax)
-; AVX-NEXT: shlq $20, %r9
-; AVX-NEXT: andl $1048575, %r8d # imm = 0xFFFFF
-; AVX-NEXT: orq %r9, %r8
-; AVX-NEXT: movq %r8, 56(%rax)
+; AVX-NEXT: movq %r8, %rdi
+; AVX-NEXT: shrq $44, %rdi
+; AVX-NEXT: andl $511, %edi # imm = 0x1FF
+; AVX-NEXT: orq %rsi, %rdi
+; AVX-NEXT: movq %rdi, 72(%rax)
+; AVX-NEXT: shlq $20, %r8
+; AVX-NEXT: movq %rdx, %rsi
+; AVX-NEXT: shrq $33, %rsi
+; AVX-NEXT: andl $1048575, %esi # imm = 0xFFFFF
+; AVX-NEXT: orq %r8, %rsi
+; AVX-NEXT: movq %rsi, 56(%rax)
; AVX-NEXT: shlq $31, %rdx
+; AVX-NEXT: shrq $22, %rcx
; AVX-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
; AVX-NEXT: orq %rdx, %rcx
; AVX-NEXT: movq %rcx, 40(%rax)
@@ -2979,7 +2994,7 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
-; X86-NEXT: subl $52, %esp
+; X86-NEXT: subl $56, %esp
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-NEXT: addb %al, %al
; X86-NEXT: sarb %al
@@ -3000,22 +3015,22 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; X86-NEXT: addb %al, %al
; X86-NEXT: sarb %al
; X86-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movb {{[0-9]+}}(%esp), %ah
+; X86-NEXT: addb %ah, %ah
+; X86-NEXT: sarb %ah
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: addb %al, %al
; X86-NEXT: sarb %al
; X86-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: addb %al, %al
+; X86-NEXT: sarb %al
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: addb %dl, %dl
+; X86-NEXT: sarb %dl
; X86-NEXT: movb {{[0-9]+}}(%esp), %dh
; X86-NEXT: addb %dh, %dh
; X86-NEXT: sarb %dh
-; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
-; X86-NEXT: addb %dl, %dl
-; X86-NEXT: sarb %dl
-; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: addb %al, %al
-; X86-NEXT: sarb %al
-; X86-NEXT: movb {{[0-9]+}}(%esp), %ah
-; X86-NEXT: addb %ah, %ah
-; X86-NEXT: sarb %ah
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: addb %cl, %cl
; X86-NEXT: sarb %cl
@@ -3046,133 +3061,137 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: sarl $31, %esi
; X86-NEXT: movl %esi, %ecx
-; X86-NEXT: movl %esi, %ebx
+; X86-NEXT: movl %esi, %edi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: andl $2097151, %ecx # imm = 0x1FFFFF
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: cmpb %al, %ah
+; X86-NEXT: cmpb %dl, %dh
+; X86-NEXT: setl %cl
+; X86-NEXT: setg %dl
+; X86-NEXT: subb %cl, %dl
+; X86-NEXT: movsbl %dl, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %ecx, (%edx)
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: sarl $31, %edx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: andl $2097151, %ecx # imm = 0x1FFFFF
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: cmpb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Folded Reload
; X86-NEXT: setl %al
; X86-NEXT: setg %cl
; X86-NEXT: subb %al, %cl
-; X86-NEXT: movsbl %cl, %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: movl %ecx, (%eax)
-; X86-NEXT: sarl $31, %ecx
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: andl $2097151, %eax # imm = 0x1FFFFF
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: cmpb %dh, %dl
-; X86-NEXT: setl %al
-; X86-NEXT: setg %dl
-; X86-NEXT: subb %al, %dl
-; X86-NEXT: movsbl %dl, %ebp
+; X86-NEXT: movsbl %cl, %ebp
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sarl $31, %ebp
-; X86-NEXT: movzbl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 1-byte Folded Reload
-; X86-NEXT: cmpb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Folded Reload
+; X86-NEXT: movl %ebp, %ecx
+; X86-NEXT: andl $2095104, %ecx # imm = 0x1FF800
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: cmpb {{[-0-9]+}}(%e{{[sb]}}p), %ah # 1-byte Folded Reload
; X86-NEXT: setl %al
-; X86-NEXT: setg %dl
-; X86-NEXT: subb %al, %dl
-; X86-NEXT: movsbl %dl, %edi
-; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sarl $31, %edi
+; X86-NEXT: setg %cl
+; X86-NEXT: subb %al, %cl
+; X86-NEXT: movsbl %cl, %eax
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: movl %eax, %esi
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: andl $2093056, %ecx # imm = 0x1FF000
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sarl $31, %ebp
; X86-NEXT: movzbl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 1-byte Folded Reload
; X86-NEXT: cmpb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Folded Reload
; X86-NEXT: setl %al
-; X86-NEXT: setg %dl
-; X86-NEXT: subb %al, %dl
-; X86-NEXT: movsbl %dl, %eax
-; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: setg %cl
+; X86-NEXT: subb %al, %cl
+; X86-NEXT: movsbl %cl, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sarl $31, %ecx
+; X86-NEXT: movl %esi, %eax
; X86-NEXT: sarl $31, %eax
-; X86-NEXT: movzbl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 1-byte Folded Reload
-; X86-NEXT: cmpb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Folded Reload
-; X86-NEXT: setl %dl
-; X86-NEXT: setg %dh
-; X86-NEXT: subb %dl, %dh
-; X86-NEXT: movsbl %dh, %edx
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: sarl $31, %edx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT: movl %edx, 96(%esi)
-; X86-NEXT: movl %edx, 92(%esi)
-; X86-NEXT: movl %ebx, 80(%esi)
-; X86-NEXT: movl %eax, 68(%esi)
-; X86-NEXT: movl %eax, 64(%esi)
-; X86-NEXT: movl %edi, 52(%esi)
-; X86-NEXT: movl %edi, 48(%esi)
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X86-NEXT: movl %ebx, 36(%esi)
-; X86-NEXT: movl %ebp, 24(%esi)
-; X86-NEXT: movl %ebp, 20(%esi)
-; X86-NEXT: movl %ecx, 8(%esi)
-; X86-NEXT: movl %ecx, 4(%esi)
-; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NEXT: movw %dx, 100(%esi)
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shrdl $2, %edx, %ecx
-; X86-NEXT: movl %ecx, 88(%esi)
-; X86-NEXT: movl %esi, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shldl $9, %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: shldl $9, %esi, %ecx
-; X86-NEXT: movl %edx, %esi
-; X86-NEXT: movl %ecx, 76(%edx)
-; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: movzbl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 1-byte Folded Reload
+; X86-NEXT: cmpb {{[-0-9]+}}(%e{{[sb]}}p), %bl # 1-byte Folded Reload
+; X86-NEXT: setl %bl
+; X86-NEXT: setg %bh
+; X86-NEXT: subb %bl, %bh
+; X86-NEXT: movsbl %bh, %esi
+; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: sarl $31, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl %esi, 96(%ebx)
+; X86-NEXT: movl %edi, 80(%ebx)
+; X86-NEXT: movl %eax, 64(%ebx)
+; X86-NEXT: movl %ecx, 52(%ebx)
+; X86-NEXT: movl %ecx, 48(%ebx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl %edi, 36(%ebx)
+; X86-NEXT: movl %ebp, 20(%ebx)
+; X86-NEXT: movl %edx, 8(%ebx)
+; X86-NEXT: movl %edx, 4(%ebx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl %edi, %edx
+; X86-NEXT: shrl $2, %edx
+; X86-NEXT: movw %dx, 100(%ebx)
+; X86-NEXT: shldl $30, %edi, %esi
+; X86-NEXT: movl %esi, 92(%ebx)
+; X86-NEXT: movl %esi, 88(%ebx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: shldl $20, %edx, %ecx
-; X86-NEXT: movl %ecx, 60(%esi)
-; X86-NEXT: movl %esi, %ebx
-; X86-NEXT: movl %edi, %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: shldl $31, %esi, %ecx
-; X86-NEXT: movl %ecx, 44(%ebx)
-; X86-NEXT: movl %ebx, %edx
+; X86-NEXT: shldl $9, %edx, %esi
+; X86-NEXT: movl %esi, 76(%ebx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $20, %edx, %eax
+; X86-NEXT: movl %eax, 68(%ebx)
+; X86-NEXT: movl %eax, 60(%ebx)
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $31, %edx, %eax
+; X86-NEXT: movl %eax, 44(%ebx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; X86-NEXT: shldl $10, %eax, %edx
+; X86-NEXT: movl %edx, 32(%ebx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: shldl $21, %eax, %ebp
+; X86-NEXT: movl %ebp, 24(%ebx)
+; X86-NEXT: movl %ebp, 16(%ebx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X86-NEXT: movl %esi, %ecx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X86-NEXT: shrdl $22, %ebx, %ecx
-; X86-NEXT: movl %ecx, 32(%edx)
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X86-NEXT: movl %ebx, %ecx
-; X86-NEXT: shrdl $11, %ebp, %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: movl %ecx, 16(%edx)
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shll $9, %ecx
-; X86-NEXT: andl $511, %eax # imm = 0x1FF
-; X86-NEXT: orl %ecx, %eax
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl %eax, 72(%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: shldl $9, %eax, %esi
+; X86-NEXT: shll $9, %eax
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: shrl $12, %edi
+; X86-NEXT: orl %eax, %edi
+; X86-NEXT: movl %edi, 72(%ebx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: shll $20, %eax
-; X86-NEXT: andl $1048575, %edi # imm = 0xFFFFF
+; X86-NEXT: andl $1048575, %ecx # imm = 0xFFFFF
+; X86-NEXT: orl %eax, %ecx
+; X86-NEXT: movl %ecx, 56(%ebx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: shldl $10, %eax, %ecx
+; X86-NEXT: shll $10, %eax
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: shrl $11, %edi
; X86-NEXT: orl %eax, %edi
-; X86-NEXT: movl %edi, 56(%ecx)
-; X86-NEXT: shll $10, %esi
-; X86-NEXT: andl $1023, %ebp # imm = 0x3FF
-; X86-NEXT: orl %esi, %ebp
-; X86-NEXT: movl %ebp, 28(%ecx)
-; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: movl %edi, 28(%ebx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: shll $21, %eax
; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
-; X86-NEXT: movl %eax, 12(%ecx)
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, 12(%ebx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: shrl $16, %eax
; X86-NEXT: andl $7, %eax
-; X86-NEXT: movb %al, 102(%ecx)
+; X86-NEXT: movb %al, 102(%ebx)
+; X86-NEXT: shll $30, %edi
+; X86-NEXT: orl %esi, %edi
+; X86-NEXT: movl %edi, 84(%ebx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X86-NEXT: shll $30, %eax
-; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
-; X86-NEXT: movl %eax, 84(%ecx)
-; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shldl $10, %ecx, %edx
-; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; X86-NEXT: shll $31, %ecx
-; X86-NEXT: orl %edx, %ecx
-; X86-NEXT: movl %ecx, 40(%eax)
-; X86-NEXT: addl $52, %esp
+; X86-NEXT: shll $31, %eax
+; X86-NEXT: orl %ecx, %eax
+; X86-NEXT: movl %eax, 40(%ebx)
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: addl $56, %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx
@@ -3238,9 +3257,9 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; SETZUCC-NEXT: setzul %cl
; SETZUCC-NEXT: setzug %bl
; SETZUCC-NEXT: subb %cl, %bl
-; SETZUCC-NEXT: movsbq %bl, %rbx
-; SETZUCC-NEXT: movq %rbx, %rcx
-; SETZUCC-NEXT: sarq $63, %rcx
+; SETZUCC-NEXT: movsbq %bl, %rcx
+; SETZUCC-NEXT: movq %rcx, %rbx
+; SETZUCC-NEXT: sarq $63, %rbx
; SETZUCC-NEXT: addb %r11b, %r11b
; SETZUCC-NEXT: sarb %r11b
; SETZUCC-NEXT: addb %r8b, %r8b
@@ -3272,52 +3291,55 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; SETZUCC-NEXT: setzul %dil
; SETZUCC-NEXT: setzug %bpl
; SETZUCC-NEXT: subb %dil, %bpl
-; SETZUCC-NEXT: movsbq %bpl, %rdi
-; SETZUCC-NEXT: movq %rdi, %r13
-; SETZUCC-NEXT: sarq $63, %r13
-; SETZUCC-NEXT: movl %r13d, 96(%rax)
+; SETZUCC-NEXT: movsbq %bpl, %r13
+; SETZUCC-NEXT: movq %r13, %rdi
+; SETZUCC-NEXT: sarq $63, %rdi
+; SETZUCC-NEXT: movl %edi, 96(%rax)
; SETZUCC-NEXT: movabsq $2251799813685247, %rbp # imm = 0x7FFFFFFFFFFFF
-; SETZUCC-NEXT: andq %r13, %rbp
-; SETZUCC-NEXT: shldq $62, %rdi, %r13
-; SETZUCC-NEXT: movq %r13, 88(%rax)
-; SETZUCC-NEXT: movq %r9, %r13
-; SETZUCC-NEXT: shrdq $44, %r10, %r13
-; SETZUCC-NEXT: movq %r13, 64(%rax)
-; SETZUCC-NEXT: movq %r8, %r13
-; SETZUCC-NEXT: shrdq $33, %r11, %r13
-; SETZUCC-NEXT: movq %r13, 48(%rax)
-; SETZUCC-NEXT: movq %rbx, %r13
-; SETZUCC-NEXT: shrdq $22, %rcx, %r13
-; SETZUCC-NEXT: movq %r13, 32(%rax)
-; SETZUCC-NEXT: movq %rdx, %r13
-; SETZUCC-NEXT: shrdq $11, %r12, %r13
-; SETZUCC-NEXT: movq %r13, 16(%rax)
-; SETZUCC-NEXT: movq %rbp, %r13
-; SETZUCC-NEXT: shrq $48, %r13
-; SETZUCC-NEXT: movb %r13b, 102(%rax)
+; SETZUCC-NEXT: andq %rdi, %rbp
+; SETZUCC-NEXT: shldq $62, %r13, %rdi
+; SETZUCC-NEXT: movq %rdi, 88(%rax)
+; SETZUCC-NEXT: shldq $20, %r9, %r10
+; SETZUCC-NEXT: movq %r10, 64(%rax)
+; SETZUCC-NEXT: shldq $31, %r8, %r11
+; SETZUCC-NEXT: movq %r11, 48(%rax)
+; SETZUCC-NEXT: shldq $42, %rcx, %rbx
+; SETZUCC-NEXT: movq %rbx, 32(%rax)
+; SETZUCC-NEXT: movq %rdx, %rdi
+; SETZUCC-NEXT: shrdq $11, %r12, %rdi
+; SETZUCC-NEXT: movq %rdi, 16(%rax)
+; SETZUCC-NEXT: movq %rbp, %rdi
+; SETZUCC-NEXT: shrq $48, %rdi
+; SETZUCC-NEXT: movb %dil, 102(%rax)
; SETZUCC-NEXT: shrq $32, %rbp
; SETZUCC-NEXT: movw %bp, 100(%rax)
-; SETZUCC-NEXT: movabsq $9007199254740991, %r13 # imm = 0x1FFFFFFFFFFFFF
-; SETZUCC-NEXT: andq %r13, %r15
+; SETZUCC-NEXT: movabsq $9007199254740991, %rdi # imm = 0x1FFFFFFFFFFFFF
+; SETZUCC-NEXT: andq %rdi, %r15
; SETZUCC-NEXT: shldq $9, %r14, %r15
-; SETZUCC-NEXT: shlq $62, %rdi
-; SETZUCC-NEXT: orq %r15, %rdi
-; SETZUCC-NEXT: movq %rdi, 80(%rax)
-; SETZUCC-NEXT: movabsq $9007199254738944, %rdi # imm = 0x1FFFFFFFFFF800
-; SETZUCC-NEXT: andq %r12, %rdi
-; SETZUCC-NEXT: shlq $42, %rbx
-; SETZUCC-NEXT: shrq $11, %rdi
-; SETZUCC-NEXT: orq %rbx, %rdi
-; SETZUCC-NEXT: movq %rdi, 24(%rax)
+; SETZUCC-NEXT: shlq $62, %r13
+; SETZUCC-NEXT: orq %r15, %r13
+; SETZUCC-NEXT: movq %r13, 80(%rax)
+; SETZUCC-NEXT: movabsq $9007199254738944, %r10 # imm = 0x1FFFFFFFFFF800
+; SETZUCC-NEXT: andq %r12, %r10
+; SETZUCC-NEXT: movq %rcx, %r11
+; SETZUCC-NEXT: shlq $42, %r11
+; SETZUCC-NEXT: shrq $11, %r10
+; SETZUCC-NEXT: orq %r11, %r10
+; SETZUCC-NEXT: movq %r10, 24(%rax)
; SETZUCC-NEXT: shlq $9, %r14
+; SETZUCC-NEXT: movq %r9, %r10
+; SETZUCC-NEXT: shrq $44, %r10
; SETZUCC-NEXT: andl $511, %r10d # imm = 0x1FF
; SETZUCC-NEXT: orq %r14, %r10
; SETZUCC-NEXT: movq %r10, 72(%rax)
; SETZUCC-NEXT: shlq $20, %r9
-; SETZUCC-NEXT: andl $1048575, %r11d # imm = 0xFFFFF
-; SETZUCC-NEXT: orq %r9, %r11
-; SETZUCC-NEXT: movq %r11, 56(%rax)
+; SETZUCC-NEXT: movq %r8, %r10
+; SETZUCC-NEXT: shrq $33, %r10
+; SETZUCC-NEXT: andl $1048575, %r10d # imm = 0xFFFFF
+; SETZUCC-NEXT: orq %r9, %r10
+; SETZUCC-NEXT: movq %r10, 56(%rax)
; SETZUCC-NEXT: shlq $31, %r8
+; SETZUCC-NEXT: shrq $22, %rcx
; SETZUCC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
; SETZUCC-NEXT: orq %r8, %rcx
; SETZUCC-NEXT: movq %rcx, 40(%rax)
@@ -3325,7 +3347,7 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; SETZUCC-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SETZUCC-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; SETZUCC-NEXT: movq %xmm0, %rcx
-; SETZUCC-NEXT: andq %r13, %rcx
+; SETZUCC-NEXT: andq %rdi, %rcx
; SETZUCC-NEXT: shlq $53, %rdx
; SETZUCC-NEXT: orq %rcx, %rdx
; SETZUCC-NEXT: movq %rdx, 8(%rax)
@@ -3396,9 +3418,9 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; NO-SETZUCC-NEXT: setl %cl
; NO-SETZUCC-NEXT: setg %bl
; NO-SETZUCC-NEXT: subb %cl, %bl
-; NO-SETZUCC-NEXT: movsbq %bl, %rbx
-; NO-SETZUCC-NEXT: movq %rbx, %rcx
-; NO-SETZUCC-NEXT: sarq $63, %rcx
+; NO-SETZUCC-NEXT: movsbq %bl, %rcx
+; NO-SETZUCC-NEXT: movq %rcx, %rbx
+; NO-SETZUCC-NEXT: sarq $63, %rbx
; NO-SETZUCC-NEXT: addb %r11b, %r11b
; NO-SETZUCC-NEXT: sarb %r11b
; NO-SETZUCC-NEXT: addb %r8b, %r8b
@@ -3430,52 +3452,55 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; NO-SETZUCC-NEXT: setl %dil
; NO-SETZUCC-NEXT: setg %bpl
; NO-SETZUCC-NEXT: subb %dil, %bpl
-; NO-SETZUCC-NEXT: movsbq %bpl, %rdi
-; NO-SETZUCC-NEXT: movq %rdi, %r13
-; NO-SETZUCC-NEXT: sarq $63, %r13
-; NO-SETZUCC-NEXT: movl %r13d, 96(%rax)
+; NO-SETZUCC-NEXT: movsbq %bpl, %r13
+; NO-SETZUCC-NEXT: movq %r13, %rdi
+; NO-SETZUCC-NEXT: sarq $63, %rdi
+; NO-SETZUCC-NEXT: movl %edi, 96(%rax)
; NO-SETZUCC-NEXT: movabsq $2251799813685247, %rbp # imm = 0x7FFFFFFFFFFFF
-; NO-SETZUCC-NEXT: andq %r13, %rbp
-; NO-SETZUCC-NEXT: shldq $62, %rdi, %r13
-; NO-SETZUCC-NEXT: movq %r13, 88(%rax)
-; NO-SETZUCC-NEXT: movq %r9, %r13
-; NO-SETZUCC-NEXT: shrdq $44, %r10, %r13
-; NO-SETZUCC-NEXT: movq %r13, 64(%rax)
-; NO-SETZUCC-NEXT: movq %r8, %r13
-; NO-SETZUCC-NEXT: shrdq $33, %r11, %r13
-; NO-SETZUCC-NEXT: movq %r13, 48(%rax)
-; NO-SETZUCC-NEXT: movq %rbx, %r13
-; NO-SETZUCC-NEXT: shrdq $22, %rcx, %r13
-; NO-SETZUCC-NEXT: movq %r13, 32(%rax)
-; NO-SETZUCC-NEXT: movq %rdx, %r13
-; NO-SETZUCC-NEXT: shrdq $11, %r12, %r13
-; NO-SETZUCC-NEXT: movq %r13, 16(%rax)
-; NO-SETZUCC-NEXT: movq %rbp, %r13
-; NO-SETZUCC-NEXT: shrq $48, %r13
-; NO-SETZUCC-NEXT: movb %r13b, 102(%rax)
+; NO-SETZUCC-NEXT: andq %rdi, %rbp
+; NO-SETZUCC-NEXT: shldq $62, %r13, %rdi
+; NO-SETZUCC-NEXT: movq %rdi, 88(%rax)
+; NO-SETZUCC-NEXT: shldq $20, %r9, %r10
+; NO-SETZUCC-NEXT: movq %r10, 64(%rax)
+; NO-SETZUCC-NEXT: shldq $31, %r8, %r11
+; NO-SETZUCC-NEXT: movq %r11, 48(%rax)
+; NO-SETZUCC-NEXT: shldq $42, %rcx, %rbx
+; NO-SETZUCC-NEXT: movq %rbx, 32(%rax)
+; NO-SETZUCC-NEXT: movq %rdx, %rdi
+; NO-SETZUCC-NEXT: shrdq $11, %r12, %rdi
+; NO-SETZUCC-NEXT: movq %rdi, 16(%rax)
+; NO-SETZUCC-NEXT: movq %rbp, %rdi
+; NO-SETZUCC-NEXT: shrq $48, %rdi
+; NO-SETZUCC-NEXT: movb %dil, 102(%rax)
; NO-SETZUCC-NEXT: shrq $32, %rbp
; NO-SETZUCC-NEXT: movw %bp, 100(%rax)
-; NO-SETZUCC-NEXT: movabsq $9007199254740991, %r13 # imm = 0x1FFFFFFFFFFFFF
-; NO-SETZUCC-NEXT: andq %r13, %r15
+; NO-SETZUCC-NEXT: movabsq $9007199254740991, %rdi # imm = 0x1FFFFFFFFFFFFF
+; NO-SETZUCC-NEXT: andq %rdi, %r15
; NO-SETZUCC-NEXT: shldq $9, %r14, %r15
-; NO-SETZUCC-NEXT: shlq $62, %rdi
-; NO-SETZUCC-NEXT: orq %r15, %rdi
-; NO-SETZUCC-NEXT: movq %rdi, 80(%rax)
-; NO-SETZUCC-NEXT: movabsq $9007199254738944, %rdi # imm = 0x1FFFFFFFFFF800
-; NO-SETZUCC-NEXT: andq %r12, %rdi
-; NO-SETZUCC-NEXT: shlq $42, %rbx
-; NO-SETZUCC-NEXT: shrq $11, %rdi
-; NO-SETZUCC-NEXT: orq %rbx, %rdi
-; NO-SETZUCC-NEXT: movq %rdi, 24(%rax)
+; NO-SETZUCC-NEXT: shlq $62, %r13
+; NO-SETZUCC-NEXT: orq %r15, %r13
+; NO-SETZUCC-NEXT: movq %r13, 80(%rax)
+; NO-SETZUCC-NEXT: movabsq $9007199254738944, %r10 # imm = 0x1FFFFFFFFFF800
+; NO-SETZUCC-NEXT: andq %r12, %r10
+; NO-SETZUCC-NEXT: movq %rcx, %r11
+; NO-SETZUCC-NEXT: shlq $42, %r11
+; NO-SETZUCC-NEXT: shrq $11, %r10
+; NO-SETZUCC-NEXT: orq %r11, %r10
+; NO-SETZUCC-NEXT: movq %r10, 24(%rax)
; NO-SETZUCC-NEXT: shlq $9, %r14
+; NO-SETZUCC-NEXT: movq %r9, %r10
+; NO-SETZUCC-NEXT: shrq $44, %r10
; NO-SETZUCC-NEXT: andl $511, %r10d # imm = 0x1FF
; NO-SETZUCC-NEXT: orq %r14, %r10
; NO-SETZUCC-NEXT: movq %r10, 72(%rax)
; NO-SETZUCC-NEXT: shlq $20, %r9
-; NO-SETZUCC-NEXT: andl $1048575, %r11d # imm = 0xFFFFF
-; NO-SETZUCC-NEXT: orq %r9, %r11
-; NO-SETZUCC-NEXT: movq %r11, 56(%rax)
+; NO-SETZUCC-NEXT: movq %r8, %r10
+; NO-SETZUCC-NEXT: shrq $33, %r10
+; NO-SETZUCC-NEXT: andl $1048575, %r10d # imm = 0xFFFFF
+; NO-SETZUCC-NEXT: orq %r9, %r10
+; NO-SETZUCC-NEXT: movq %r10, 56(%rax)
; NO-SETZUCC-NEXT: shlq $31, %r8
+; NO-SETZUCC-NEXT: shrq $22, %rcx
; NO-SETZUCC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
; NO-SETZUCC-NEXT: orq %r8, %rcx
; NO-SETZUCC-NEXT: movq %rcx, 40(%rax)
@@ -3483,7 +3508,7 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; NO-SETZUCC-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; NO-SETZUCC-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; NO-SETZUCC-NEXT: movq %xmm0, %rcx
-; NO-SETZUCC-NEXT: andq %r13, %rcx
+; NO-SETZUCC-NEXT: andq %rdi, %rcx
; NO-SETZUCC-NEXT: shlq $53, %rdx
; NO-SETZUCC-NEXT: orq %rcx, %rdx
; NO-SETZUCC-NEXT: movq %rdx, 8(%rax)
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
index 92615c859ea72..6d860d9bda569 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
@@ -180,13 +180,13 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; SSE-NEXT: psrlw $8, %xmm4
; SSE-NEXT: packuswb %xmm2, %xmm4
; SSE-NEXT: paddb %xmm4, %xmm0
+; SSE-NEXT: pcmpgtb %xmm0, %xmm1
; SSE-NEXT: psrlw $2, %xmm0
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; SSE-NEXT: pxor %xmm2, %xmm0
-; SSE-NEXT: psubb %xmm2, %xmm0
-; SSE-NEXT: pcmpgtb %xmm0, %xmm1
; SSE-NEXT: psubb %xmm1, %xmm0
+; SSE-NEXT: psubb %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: test_div7_16i8:
@@ -201,13 +201,13 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpaddb %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm0
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2NOBW-LABEL: test_div7_16i8:
@@ -218,14 +218,14 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
-; AVX2NOBW-NEXT: vpsrlw $2, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} xmm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX2NOBW-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX2NOBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpsrlw $2, %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX2NOBW-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX2NOBW-NEXT: vzeroupper
; AVX2NOBW-NEXT: retq
;
@@ -236,14 +236,14 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vpsrlw $2, %xmm0, %xmm0
-; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} xmm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT: vpsrlw $2, %xmm0, %xmm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX512BW-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%res = sdiv <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
@@ -274,12 +274,12 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; SSE-NEXT: psraw $8, %xmm2
; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [32,64,128,32,64,128,128,64]
; SSE-NEXT: psrlw $8, %xmm2
+; SSE-NEXT: pcmpgtb %xmm0, %xmm1
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: psraw $8, %xmm0
; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [64,64,128,64,32,128,64,32]
; SSE-NEXT: psrlw $8, %xmm0
; SSE-NEXT: packuswb %xmm2, %xmm0
-; SSE-NEXT: pcmpgtb %xmm0, %xmm1
; SSE-NEXT: psubb %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -299,13 +299,13 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [32,64,128,32,64,128,128,64]
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [64,64,128,64,32,128,64,32]
-; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [64,64,128,64,32,128,64,32]
+; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
+; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm0
; AVX1-NEXT: retq
;
; AVX2NOBW-LABEL: test_divconstant_16i8:
@@ -317,14 +317,14 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
-; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm0
-; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [64,64,128,64,32,128,64,32,32,64,128,32,64,128,128,64]
-; AVX2NOBW-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2NOBW-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [64,64,128,64,32,128,64,32,32,64,128,32,64,128,128,64]
+; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
+; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
+; AVX2NOBW-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; AVX2NOBW-NEXT: vzeroupper
; AVX2NOBW-NEXT: retq
;
@@ -337,12 +337,12 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vpaddb %xmm0, %xmm2, %xmm0
-; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm0
-; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
-; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX512BW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm2
+; AVX512BW-NEXT: vpsravw %zmm1, %zmm2, %zmm1
+; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
+; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512BW-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
+; AVX512BW-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%res = sdiv <16 x i8> %a, <i8 7, i8 8, i8 9, i8 10,i8 11, i8 12, i8 13, i8 14, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9,i8 9, i8 7>
@@ -570,13 +570,13 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; SSE-NEXT: psrlw $8, %xmm4
; SSE-NEXT: packuswb %xmm2, %xmm4
; SSE-NEXT: paddb %xmm0, %xmm4
+; SSE-NEXT: pcmpgtb %xmm4, %xmm1
; SSE-NEXT: psrlw $2, %xmm4
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; SSE-NEXT: pxor %xmm2, %xmm4
-; SSE-NEXT: psubb %xmm2, %xmm4
-; SSE-NEXT: pcmpgtb %xmm4, %xmm1
; SSE-NEXT: psubb %xmm1, %xmm4
+; SSE-NEXT: psubb %xmm2, %xmm4
; SSE-NEXT: movdqa %xmm4, %xmm1
; SSE-NEXT: psllw $3, %xmm1
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
@@ -596,13 +596,13 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpaddb %xmm0, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $2, %xmm2, %xmm2
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2
-; AVX1-NEXT: vpsubb %xmm3, %xmm2, %xmm2
-; AVX1-NEXT: vpcmpgtb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpsllw $3, %xmm1, %xmm2
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsubb %xmm2, %xmm1, %xmm1
@@ -617,14 +617,14 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpsrlw $2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX2NOBW-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2NOBW-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpsrlw $2, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX2NOBW-NEXT: vpxor %xmm3, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsllw $3, %xmm1, %xmm2
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
@@ -639,14 +639,14 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %xmm0, %xmm1, %xmm1
-; AVX512BW-NEXT: vpsrlw $2, %xmm1, %xmm1
-; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX512BW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512BW-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm2
+; AVX512BW-NEXT: vpsrlw $2, %xmm1, %xmm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpxor %xmm3, %xmm1, %xmm1
; AVX512BW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
+; AVX512BW-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX512BW-NEXT: vpsllw $3, %xmm1, %xmm2
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512BW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
@@ -682,12 +682,12 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE2-NEXT: psraw $8, %xmm3
; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [32,64,128,32,64,128,128,64]
; SSE2-NEXT: psrlw $8, %xmm3
+; SSE2-NEXT: pcmpgtb %xmm1, %xmm2
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: psraw $8, %xmm1
; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [64,64,128,64,32,128,64,32]
; SSE2-NEXT: psrlw $8, %xmm1
; SSE2-NEXT: packuswb %xmm3, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm1, %xmm2
; SSE2-NEXT: psubb %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
@@ -721,12 +721,12 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE41-NEXT: psraw $8, %xmm3
; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [32,64,128,32,64,128,128,64]
; SSE41-NEXT: psrlw $8, %xmm3
+; SSE41-NEXT: pcmpgtb %xmm2, %xmm1
; SSE41-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE41-NEXT: psraw $8, %xmm2
; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [64,64,128,64,32,128,64,32]
; SSE41-NEXT: psrlw $8, %xmm2
; SSE41-NEXT: packuswb %xmm3, %xmm2
-; SSE41-NEXT: pcmpgtb %xmm2, %xmm1
; SSE41-NEXT: psubb %xmm1, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm1
; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,8,0,10,0,12,0,14,0,13,0,11,0,9,0,7]
@@ -753,13 +753,13 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [32,64,128,32,64,128,128,64]
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [64,64,128,64,32,128,64,32]
-; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [64,64,128,64,32,128,64,32]
+; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
+; AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpcmpgtb %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpsubb %xmm1, %xmm3, %xmm1
; AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2 # [0,8,0,10,0,12,0,14,0,13,0,11,0,9,0,7]
; AVX1-NEXT: vpsllw $8, %xmm2, %xmm2
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [7,8,9,10,11,12,13,14,14,13,12,11,10,9,9,7]
@@ -777,14 +777,14 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX2NOBW-NEXT: vpaddb %xmm2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpmovsxbw %xmm1, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [64,64,128,64,32,128,64,32,32,64,128,32,64,128,128,64]
-; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX2NOBW-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm2
-; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpmovsxbw %xmm1, %ymm2
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [64,64,128,64,32,128,64,32,32,64,128,32,64,128,128,64]
+; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
+; AVX2NOBW-NEXT: vextracti128 $1, %ymm2, %xmm3
+; AVX2NOBW-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX2NOBW-NEXT: vpcmpgtb %xmm1, %xmm3, %xmm1
+; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm2, %xmm1
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [7,8,9,10,11,12,13,14,14,13,12,11,10,9,9,7]
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
@@ -803,11 +803,11 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; AVX512BW-NEXT: vpaddb %xmm3, %xmm2, %xmm2
-; AVX512BW-NEXT: vpmovsxbw %xmm2, %ymm2
-; AVX512BW-NEXT: vpsravw %zmm1, %zmm2, %zmm1
+; AVX512BW-NEXT: vpmovsxbw %xmm2, %ymm3
+; AVX512BW-NEXT: vpsravw %zmm1, %zmm3, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
-; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX512BW-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm2
+; AVX512BW-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX512BW-NEXT: vpcmpgtb %xmm2, %xmm3, %xmm2
; AVX512BW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [7,8,9,10,11,12,13,14,14,13,12,11,10,9,9,7]
@@ -1014,34 +1014,62 @@ define <16 x i8> @test_rem_variable_16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
}
define <16 x i8> @PR143238(<16 x i8> %a0) {
-; SSE-LABEL: PR143238:
-; SSE: # %bb.0:
-; SSE-NEXT: pxor %xmm1, %xmm1
-; SSE-NEXT: pxor %xmm2, %xmm2
-; SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
-; SSE-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [0,103,0,187,0,43,0,79,0,147,0,137,0,129,0,121]
-; SSE-NEXT: psrlw $8, %xmm2
-; SSE-NEXT: pxor %xmm3, %xmm3
-; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
-; SSE-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [0,129,0,86,0,129,0,103,0,43,0,147,0,129,0,57]
-; SSE-NEXT: psrlw $8, %xmm3
-; SSE-NEXT: packuswb %xmm2, %xmm3
-; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: paddb %xmm3, %xmm0
-; SSE-NEXT: movdqa %xmm0, %xmm2
-; SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
-; SSE-NEXT: psraw $8, %xmm2
-; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [64,32,128,64,32,32,32,32]
-; SSE-NEXT: psrlw $8, %xmm2
-; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSE-NEXT: psraw $8, %xmm0
-; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [256,256,128,128,256,64,64,128]
-; SSE-NEXT: psrlw $8, %xmm0
-; SSE-NEXT: packuswb %xmm2, %xmm0
-; SSE-NEXT: pcmpgtb %xmm0, %xmm1
-; SSE-NEXT: psubb %xmm1, %xmm0
-; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: retq
+; SSE2-LABEL: PR143238:
+; SSE2: # %bb.0:
+; SSE2-NEXT: pxor %xmm2, %xmm2
+; SSE2-NEXT: pxor %xmm1, %xmm1
+; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
+; SSE2-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,103,0,187,0,43,0,79,0,147,0,137,0,129,0,121]
+; SSE2-NEXT: psrlw $8, %xmm1
+; SSE2-NEXT: pxor %xmm3, %xmm3
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [0,129,0,86,0,129,0,103,0,43,0,147,0,129,0,57]
+; SSE2-NEXT: psrlw $8, %xmm3
+; SSE2-NEXT: packuswb %xmm1, %xmm3
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: paddb %xmm3, %xmm0
+; SSE2-NEXT: movdqa %xmm0, %xmm3
+; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [64,32,128,64,32,32,32,32]
+; SSE2-NEXT: psrlw $8, %xmm3
+; SSE2-NEXT: movdqa %xmm0, %xmm1
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [256,256,128,128,256,64,64,128]
+; SSE2-NEXT: psrlw $8, %xmm1
+; SSE2-NEXT: packuswb %xmm3, %xmm1
+; SSE2-NEXT: pcmpgtb %xmm0, %xmm2
+; SSE2-NEXT: psubb %xmm2, %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: movdqa %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: PR143238:
+; SSE41: # %bb.0:
+; SSE41-NEXT: pxor %xmm2, %xmm2
+; SSE41-NEXT: pxor %xmm1, %xmm1
+; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
+; SSE41-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,103,0,187,0,43,0,79,0,147,0,137,0,129,0,121]
+; SSE41-NEXT: psrlw $8, %xmm1
+; SSE41-NEXT: pxor %xmm3, %xmm3
+; SSE41-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE41-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [0,129,0,86,0,129,0,103,0,43,0,147,0,129,0,57]
+; SSE41-NEXT: psrlw $8, %xmm3
+; SSE41-NEXT: packuswb %xmm1, %xmm3
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: paddb %xmm3, %xmm0
+; SSE41-NEXT: movdqa %xmm0, %xmm3
+; SSE41-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [64,32,128,64,32,32,32,32]
+; SSE41-NEXT: psrlw $8, %xmm3
+; SSE41-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [256,256,128,128,256,64,64,128]
+; SSE41-NEXT: psrlw $8, %xmm1
+; SSE41-NEXT: packuswb %xmm3, %xmm1
+; SSE41-NEXT: pcmpgtb %xmm0, %xmm2
+; SSE41-NEXT: psubb %xmm2, %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: movdqa %xmm1, %xmm0
+; SSE41-NEXT: retq
;
; AVX1-LABEL: PR143238:
; AVX1: # %bb.0:
@@ -1055,17 +1083,15 @@ define <16 x i8> @PR143238(<16 x i8> %a0) {
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm0, %xmm2, %xmm0
-; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
+; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [64,32,128,64,32,32,32,32]
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [256,256,128,128,256,64,64,128]
-; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [256,256,128,128,256,64,64,128]
+; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
+; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -1078,14 +1104,14 @@ define <16 x i8> @PR143238(<16 x i8> %a0) {
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
-; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm0
-; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [256,256,128,128,256,64,64,128,64,32,128,64,32,32,32,32]
-; AVX2NOBW-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2NOBW-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [256,256,128,128,256,64,64,128,64,32,128,64,32,32,32,32]
+; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
+; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
+; AVX2NOBW-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vzeroupper
; AVX2NOBW-NEXT: retq
@@ -1099,12 +1125,12 @@ define <16 x i8> @PR143238(<16 x i8> %a0) {
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vpaddb %xmm0, %xmm2, %xmm0
-; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm0
-; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
-; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX512BW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm2, %zmm1
+; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
+; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512BW-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
+; AVX512BW-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
index e42a3febbf041..1309f2719e67a 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
@@ -182,28 +182,28 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpackuswb %xmm3, %xmm5, %xmm3
; AVX1-NEXT: vpaddb %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm3
; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm1
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX1-NEXT: vpxor %xmm5, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm5, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm6
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; AVX1-NEXT: vpand %xmm5, %xmm1, %xmm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX1-NEXT: vpxor %xmm6, %xmm1, %xmm1
+; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpsubb %xmm6, %xmm1, %xmm1
-; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
-; AVX1-NEXT: vpmulhw %xmm4, %xmm6, %xmm6
-; AVX1-NEXT: vpsrlw $8, %xmm6, %xmm6
+; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
+; AVX1-NEXT: vpmulhw %xmm4, %xmm3, %xmm3
+; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
; AVX1-NEXT: vpmulhw %xmm4, %xmm7, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpackuswb %xmm6, %xmm4, %xmm4
-; AVX1-NEXT: vpaddb %xmm0, %xmm4, %xmm0
-; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm0
-; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; AVX1-NEXT: vpxor %xmm5, %xmm0, %xmm0
-; AVX1-NEXT: vpsubb %xmm5, %xmm0, %xmm0
+; AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vpaddb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm2
+; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0
+; AVX1-NEXT: vpxor %xmm6, %xmm0, %xmm0
; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpsubb %xmm6, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
@@ -219,13 +219,13 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm3, %ymm2
; AVX2NOBW-NEXT: vpaddb %ymm0, %ymm2, %ymm0
+; AVX2NOBW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $2, %ymm0, %ymm0
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} ymm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX2NOBW-NEXT: vpxor %ymm2, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm0, %ymm0
; AVX2NOBW-NEXT: retq
;
; AVX512BW-LABEL: test_div7_32i8:
@@ -235,14 +235,14 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %ymm0, %ymm1, %ymm0
-; AVX512BW-NEXT: vpsrlw $2, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} ymm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpxor %ymm1, %ymm0, %ymm0
-; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
+; AVX512BW-NEXT: vpsrlw $2, %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} ymm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpxor %ymm2, %ymm0, %ymm0
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: vpsubb %ymm2, %ymm0, %ymm0
; AVX512BW-NEXT: retq
%res = sdiv <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
ret <32 x i8> %res
@@ -271,13 +271,13 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm4, %xmm4
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [32,64,128,32,64,128,64,64]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [16,64,32,128,64,32,32,32]
-; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
-; AVX1-NEXT: vpcmpgtb %xmm2, %xmm1, %xmm4
-; AVX1-NEXT: vpsubb %xmm4, %xmm2, %xmm2
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5 # [16,64,32,128,64,32,32,32]
+; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
+; AVX1-NEXT: vpackuswb %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpcmpgtb %xmm2, %xmm1, %xmm2
+; AVX1-NEXT: vpsubb %xmm2, %xmm4, %xmm2
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [0,137,0,129,0,121,0,57,0,27,0,103,0,49,0,187]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
@@ -290,13 +290,13 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [32,32,32,64,128,32,64,16]
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [64,64,128,64,32,128,64,32]
-; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [64,64,128,64,32,128,64,32]
+; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
+; AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpsubb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq
;
@@ -316,13 +316,13 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpsraw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [32,32,32,64,128,32,64,16,32,64,128,32,64,128,64,64]
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX2NOBW-NEXT: vpsraw $8, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [64,64,128,64,32,128,64,32,16,64,32,128,64,32,32,32]
-; AVX2NOBW-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm3 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX2NOBW-NEXT: vpsraw $8, %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [64,64,128,64,32,128,64,32,16,64,32,128,64,32,32,32]
+; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm3, %ymm2
+; AVX2NOBW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
+; AVX2NOBW-NEXT: vpsubb %ymm0, %ymm2, %ymm0
; AVX2NOBW-NEXT: retq
;
; AVX512BW-LABEL: test_divconstant_32i8:
@@ -333,11 +333,11 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; AVX512BW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm0
; AVX512BW-NEXT: vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
-; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX512BW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: retq
%res = sdiv <32 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
@@ -552,49 +552,49 @@ define <16 x i16> @test_rem7_16i16(<16 x i16> %a) nounwind {
define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
; AVX1-LABEL: test_rem7_32i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8],xmm2[8],xmm1[9],xmm2[9],xmm1[10],xmm2[10],xmm1[11],xmm2[11],xmm1[12],xmm2[12],xmm1[13],xmm2[13],xmm1[14],xmm2[14],xmm1[15],xmm2[15]
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147]
; AVX1-NEXT: vpmulhw %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; AVX1-NEXT: vpmulhw %xmm4, %xmm5, %xmm5
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpackuswb %xmm3, %xmm5, %xmm3
-; AVX1-NEXT: vpaddb %xmm2, %xmm3, %xmm3
+; AVX1-NEXT: vpaddb %xmm1, %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtb %xmm3, %xmm2, %xmm5
; AVX1-NEXT: vpsrlw $2, %xmm3, %xmm3
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX1-NEXT: vpxor %xmm6, %xmm3, %xmm3
-; AVX1-NEXT: vpsubb %xmm6, %xmm3, %xmm3
-; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm7
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm7 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX1-NEXT: vpxor %xmm7, %xmm3, %xmm3
+; AVX1-NEXT: vpsubb %xmm5, %xmm3, %xmm3
; AVX1-NEXT: vpsubb %xmm7, %xmm3, %xmm3
-; AVX1-NEXT: vpsllw $3, %xmm3, %xmm7
+; AVX1-NEXT: vpsllw $3, %xmm3, %xmm5
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm8 = [248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248]
-; AVX1-NEXT: vpand %xmm7, %xmm8, %xmm7
-; AVX1-NEXT: vpsubb %xmm7, %xmm3, %xmm3
-; AVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm2
-; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
+; AVX1-NEXT: vpand %xmm5, %xmm8, %xmm5
+; AVX1-NEXT: vpsubb %xmm5, %xmm3, %xmm3
+; AVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
; AVX1-NEXT: vpmulhw %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; AVX1-NEXT: vpmulhw %xmm4, %xmm7, %xmm4
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; AVX1-NEXT: vpmulhw %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpaddb %xmm0, %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $2, %xmm3, %xmm3
-; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
-; AVX1-NEXT: vpxor %xmm6, %xmm3, %xmm3
-; AVX1-NEXT: vpsubb %xmm6, %xmm3, %xmm3
-; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm3, %xmm1
-; AVX1-NEXT: vpsllw $3, %xmm1, %xmm3
+; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
+; AVX1-NEXT: vpxor %xmm7, %xmm3, %xmm3
+; AVX1-NEXT: vpsubb %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpsubb %xmm7, %xmm2, %xmm2
+; AVX1-NEXT: vpsllw $3, %xmm2, %xmm3
; AVX1-NEXT: vpand %xmm3, %xmm8, %xmm3
-; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: vpsubb %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2NOBW-LABEL: test_rem7_32i8:
@@ -609,13 +609,13 @@ define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm3, %ymm2
; AVX2NOBW-NEXT: vpaddb %ymm0, %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpcmpgtb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $2, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} ymm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX2NOBW-NEXT: vpxor %ymm3, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpsubb %ymm3, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpcmpgtb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm2, %ymm1
+; AVX2NOBW-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsllw $3, %ymm1, %ymm2
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
@@ -629,14 +629,14 @@ define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %ymm0, %ymm1, %ymm1
-; AVX512BW-NEXT: vpsrlw $2, %ymm1, %ymm1
-; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} ymm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpxor %ymm2, %ymm1, %ymm1
-; AVX512BW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512BW-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm2
+; AVX512BW-NEXT: vpsrlw $2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} ymm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpxor %ymm3, %ymm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512BW-NEXT: vpsllw $3, %ymm1, %ymm2
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512BW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
@@ -669,13 +669,13 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm5, %xmm5
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5 # [32,64,128,32,64,128,64,64]
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [16,64,32,128,64,32,32,32]
-; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpackuswb %xmm5, %xmm3, %xmm3
-; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm5
-; AVX1-NEXT: vpsubb %xmm5, %xmm3, %xmm3
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm6 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm6, %xmm6
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6, %xmm6 # [16,64,32,128,64,32,32,32]
+; AVX1-NEXT: vpsrlw $8, %xmm6, %xmm6
+; AVX1-NEXT: vpackuswb %xmm5, %xmm6, %xmm5
+; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm3
+; AVX1-NEXT: vpsubb %xmm3, %xmm5, %xmm3
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm5 # [22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpand %xmm6, %xmm5, %xmm5
@@ -695,13 +695,13 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm4, %xmm4
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [32,32,32,64,128,32,64,16]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [64,64,128,64,32,128,64,32]
-; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpackuswb %xmm4, %xmm3, %xmm3
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5 # [64,64,128,64,32,128,64,32]
+; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
+; AVX1-NEXT: vpackuswb %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpsubb %xmm1, %xmm4, %xmm1
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm3 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22]
; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
; AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [0,8,0,10,0,12,0,14,0,16,0,18,0,20,0,22]
@@ -727,13 +727,13 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpsraw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [32,32,32,64,128,32,64,16,32,64,128,32,64,128,64,64]
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm2 = ymm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX2NOBW-NEXT: vpsraw $8, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [64,64,128,64,32,128,64,32,16,64,32,128,64,32,32,32]
-; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpackuswb %ymm3, %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX2NOBW-NEXT: vpsraw $8, %ymm4, %ymm4
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [64,64,128,64,32,128,64,32,16,64,32,128,64,32,32,32]
+; AVX2NOBW-NEXT: vpsrlw $8, %ymm4, %ymm4
+; AVX2NOBW-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
; AVX2NOBW-NEXT: vpcmpgtb %ymm2, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm2, %ymm1
+; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm3, %ymm1
; AVX2NOBW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2 # [0,8,0,10,0,12,0,14,0,16,0,18,0,20,0,22,0,21,0,19,0,17,0,15,0,13,0,11,0,9,0,7]
; AVX2NOBW-NEXT: vpsllw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
@@ -750,11 +750,11 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpaddb %ymm1, %ymm2, %ymm1
+; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512BW-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm2
; AVX512BW-NEXT: vpmovsxbw %ymm1, %zmm1
; AVX512BW-NEXT: vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
-; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX512BW-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm2
; AVX512BW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
index 3fad53ef87838..a2607c2d4d211 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
@@ -134,28 +134,28 @@ define <64 x i8> @test_div7_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpackuswb %ymm3, %ymm5, %ymm3
; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm3
; AVX512F-NEXT: vpsrlw $2, %ymm1, %ymm1
-; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm3 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; AVX512F-NEXT: vpand %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512F-NEXT: vpxor %ymm5, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1
-; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm6
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm6 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512F-NEXT: vpxor %ymm6, %ymm1, %ymm1
+; AVX512F-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpsubb %ymm6, %ymm1, %ymm1
-; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm6 = ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15],ymm2[24],ymm0[24],ymm2[25],ymm0[25],ymm2[26],ymm0[26],ymm2[27],ymm0[27],ymm2[28],ymm0[28],ymm2[29],ymm0[29],ymm2[30],ymm0[30],ymm2[31],ymm0[31]
-; AVX512F-NEXT: vpmulhw %ymm4, %ymm6, %ymm6
-; AVX512F-NEXT: vpsrlw $8, %ymm6, %ymm6
+; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15],ymm2[24],ymm0[24],ymm2[25],ymm0[25],ymm2[26],ymm0[26],ymm2[27],ymm0[27],ymm2[28],ymm0[28],ymm2[29],ymm0[29],ymm2[30],ymm0[30],ymm2[31],ymm0[31]
+; AVX512F-NEXT: vpmulhw %ymm4, %ymm3, %ymm3
+; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm7 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[16],ymm0[16],ymm2[17],ymm0[17],ymm2[18],ymm0[18],ymm2[19],ymm0[19],ymm2[20],ymm0[20],ymm2[21],ymm0[21],ymm2[22],ymm0[22],ymm2[23],ymm0[23]
; AVX512F-NEXT: vpmulhw %ymm4, %ymm7, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpackuswb %ymm6, %ymm4, %ymm4
-; AVX512F-NEXT: vpaddb %ymm0, %ymm4, %ymm0
-; AVX512F-NEXT: vpsrlw $2, %ymm0, %ymm0
-; AVX512F-NEXT: vpand %ymm3, %ymm0, %ymm0
-; AVX512F-NEXT: vpxor %ymm5, %ymm0, %ymm0
-; AVX512F-NEXT: vpsubb %ymm5, %ymm0, %ymm0
+; AVX512F-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
+; AVX512F-NEXT: vpaddb %ymm0, %ymm3, %ymm0
; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm2
+; AVX512F-NEXT: vpsrlw $2, %ymm0, %ymm0
+; AVX512F-NEXT: vpand %ymm5, %ymm0, %ymm0
+; AVX512F-NEXT: vpxor %ymm6, %ymm0, %ymm0
; AVX512F-NEXT: vpsubb %ymm2, %ymm0, %ymm0
+; AVX512F-NEXT: vpsubb %ymm6, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512F-NEXT: retq
;
@@ -171,13 +171,13 @@ define <64 x i8> @test_div7_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
-; AVX512BW-NEXT: vpsrlw $2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm0 = zmm1 ^ (zmm0 & m32bcst)
-; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpsrlw $2, %zmm0, %zmm1
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm1 = zmm2 ^ (zmm1 & m32bcst)
; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
-; AVX512BW-NEXT: vpmovm2b %k0, %zmm1
-; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
+; AVX512BW-NEXT: vpsubb %zmm0, %zmm1, %zmm0
+; AVX512BW-NEXT: vpsubb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: retq
%res = sdiv <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
ret <64 x i8> %res
@@ -206,13 +206,13 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsraw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [16,32,16,128,32,64,64,16,32,64,128,32,64,128,64,64]
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm2 = ymm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX512F-NEXT: vpsraw $8, %ymm2, %ymm2
-; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [64,16,32,32,16,16,16,16,16,64,32,128,64,32,32,32]
-; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
-; AVX512F-NEXT: vpackuswb %ymm4, %ymm2, %ymm2
-; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm1, %ymm4
-; AVX512F-NEXT: vpsubb %ymm4, %ymm2, %ymm2
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX512F-NEXT: vpsraw $8, %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5 # [64,16,32,32,16,16,16,16,16,64,32,128,64,32,32,32]
+; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
+; AVX512F-NEXT: vpackuswb %ymm4, %ymm5, %ymm4
+; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm1, %ymm2
+; AVX512F-NEXT: vpsubb %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [0,137,0,129,0,121,0,57,0,27,0,103,0,49,0,187,0,133,0,129,0,125,0,121,0,59,0,57,0,111,0,27]
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
@@ -225,13 +225,13 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsraw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [32,32,32,64,128,32,64,16,16,16,16,16,32,32,16,64]
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX512F-NEXT: vpsraw $8, %ymm0, %ymm0
-; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [64,64,128,64,32,128,64,32,16,64,64,32,128,16,32,16]
-; AVX512F-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX512F-NEXT: vpackuswb %ymm3, %ymm0, %ymm0
-; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX512F-NEXT: vpsraw $8, %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [64,64,128,64,32,128,64,32,16,64,64,32,128,16,32,16]
+; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
+; AVX512F-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
+; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
+; AVX512F-NEXT: vpsubb %ymm0, %ymm3, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512F-NEXT: retq
;
@@ -251,14 +251,14 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsraw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
-; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
-; AVX512BW-NEXT: vpsraw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
-; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpackuswb %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm2 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
+; AVX512BW-NEXT: vpsraw $8, %zmm2, %zmm2
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
+; AVX512BW-NEXT: vpackuswb %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
-; AVX512BW-NEXT: vpmovm2b %k0, %zmm1
-; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
+; AVX512BW-NEXT: vpsubb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: retq
%res = sdiv <64 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
ret <64 x i8> %res
@@ -413,33 +413,33 @@ define <64 x i8> @test_rem7_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpackuswb %ymm3, %ymm5, %ymm3
; AVX512F-NEXT: vpaddb %ymm2, %ymm3, %ymm3
+; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm5
; AVX512F-NEXT: vpsrlw $2, %ymm3, %ymm3
-; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; AVX512F-NEXT: vpand %ymm5, %ymm3, %ymm3
-; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm6 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512F-NEXT: vpxor %ymm6, %ymm3, %ymm3
-; AVX512F-NEXT: vpsubb %ymm6, %ymm3, %ymm3
-; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm7
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm7 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512F-NEXT: vpxor %ymm7, %ymm3, %ymm3
+; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512F-NEXT: vpsubb %ymm7, %ymm3, %ymm3
-; AVX512F-NEXT: vpsllw $3, %ymm3, %ymm7
+; AVX512F-NEXT: vpsllw $3, %ymm3, %ymm5
; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm8 = [248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248]
-; AVX512F-NEXT: vpand %ymm7, %ymm8, %ymm7
-; AVX512F-NEXT: vpsubb %ymm7, %ymm3, %ymm3
+; AVX512F-NEXT: vpand %ymm5, %ymm8, %ymm5
+; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512F-NEXT: vpaddb %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
; AVX512F-NEXT: vpmulhw %ymm4, %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm7 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23]
-; AVX512F-NEXT: vpmulhw %ymm4, %ymm7, %ymm4
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23]
+; AVX512F-NEXT: vpmulhw %ymm4, %ymm5, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
; AVX512F-NEXT: vpaddb %ymm0, %ymm3, %ymm3
-; AVX512F-NEXT: vpsrlw $2, %ymm3, %ymm3
-; AVX512F-NEXT: vpand %ymm5, %ymm3, %ymm3
-; AVX512F-NEXT: vpxor %ymm6, %ymm3, %ymm3
-; AVX512F-NEXT: vpsubb %ymm6, %ymm3, %ymm3
; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm1
+; AVX512F-NEXT: vpsrlw $2, %ymm3, %ymm3
+; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3
+; AVX512F-NEXT: vpxor %ymm7, %ymm3, %ymm3
; AVX512F-NEXT: vpsubb %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT: vpsubb %ymm7, %ymm1, %ymm1
; AVX512F-NEXT: vpsllw $3, %ymm1, %ymm3
; AVX512F-NEXT: vpand %ymm3, %ymm8, %ymm3
; AVX512F-NEXT: vpsubb %ymm3, %ymm1, %ymm1
@@ -459,13 +459,13 @@ define <64 x i8> @test_rem7_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm1
-; AVX512BW-NEXT: vpsrlw $2, %zmm1, %zmm1
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm1 = zmm2 ^ (zmm1 & m32bcst)
-; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
+; AVX512BW-NEXT: vpsrlw $2, %zmm1, %zmm2
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm2 = zmm3 ^ (zmm2 & m32bcst)
; AVX512BW-NEXT: vpmovb2m %zmm1, %k0
-; AVX512BW-NEXT: vpmovm2b %k0, %zmm2
-; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
+; AVX512BW-NEXT: vpmovm2b %k0, %zmm1
+; AVX512BW-NEXT: vpsubb %zmm1, %zmm2, %zmm1
+; AVX512BW-NEXT: vpsubb %zmm3, %zmm1, %zmm1
; AVX512BW-NEXT: vpsllw $3, %zmm1, %zmm2
; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
@@ -498,13 +498,13 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsraw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5 # [16,32,16,128,32,64,64,16,32,64,128,32,64,128,64,64]
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm3 = ymm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX512F-NEXT: vpsraw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [64,16,32,32,16,16,16,16,16,64,32,128,64,32,32,32]
-; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpackuswb %ymm5, %ymm3, %ymm3
-; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm5
-; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm6 = ymm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX512F-NEXT: vpsraw $8, %ymm6, %ymm6
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm6 # [64,16,32,32,16,16,16,16,16,64,32,128,64,32,32,32]
+; AVX512F-NEXT: vpsrlw $8, %ymm6, %ymm6
+; AVX512F-NEXT: vpackuswb %ymm5, %ymm6, %ymm5
+; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm3
+; AVX512F-NEXT: vpsubb %ymm3, %ymm5, %ymm3
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm5 # [38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
; AVX512F-NEXT: vpbroadcastw {{.*#+}} ymm6 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-NEXT: vpand %ymm6, %ymm5, %ymm5
@@ -524,13 +524,13 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsraw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [32,32,32,64,128,32,64,16,16,16,16,16,32,32,16,64]
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm3 = ymm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX512F-NEXT: vpsraw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [64,64,128,64,32,128,64,32,16,64,64,32,128,16,32,16]
-; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpackuswb %ymm4, %ymm3, %ymm3
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX512F-NEXT: vpsraw $8, %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5 # [64,64,128,64,32,128,64,32,16,64,64,32,128,16,32,16]
+; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
+; AVX512F-NEXT: vpackuswb %ymm4, %ymm5, %ymm4
; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT: vpsubb %ymm1, %ymm4, %ymm1
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm3 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38]
; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3
; AVX512F-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,8,0,10,0,12,0,14,0,16,0,18,0,20,0,22,0,24,0,26,0,28,0,30,0,32,0,34,0,36,0,38]
@@ -556,14 +556,14 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsraw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
-; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm1 = zmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
-; AVX512BW-NEXT: vpsraw $8, %zmm1, %zmm1
-; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
-; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
-; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
+; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm3 = zmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
+; AVX512BW-NEXT: vpsraw $8, %zmm3, %zmm3
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
+; AVX512BW-NEXT: vpackuswb %zmm2, %zmm3, %zmm2
; AVX512BW-NEXT: vpmovb2m %zmm1, %k0
-; AVX512BW-NEXT: vpmovm2b %k0, %zmm2
-; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
+; AVX512BW-NEXT: vpmovm2b %k0, %zmm1
+; AVX512BW-NEXT: vpsubb %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm2 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
; AVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,8,0,10,0,12,0,14,0,16,0,18,0,20,0,22,0,24,0,26,0,28,0,30,0,32,0,34,0,36,0,38,0,37,0,35,0,33,0,31,0,29,0,27,0,25,0,23,0,21,0,19,0,17,0,15,0,13,0,11,0,9,0,7]
; AVX512BW-NEXT: vpsllw $8, %zmm1, %zmm1
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