[llvm] [DAG] SimplifyMultipleUseDemandedBits - skip ISD::SRA nodes with already enough sign bits (PR #178916)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 28 09:52:50 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/178916
>From db8a61060e51f7c553ce0dce16922ca9292098c9 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 30 Jan 2026 16:45:16 +0000
Subject: [PATCH] [DAG] SimplifyMultipleUseDemandedBits - skip ISD::SRA nodes
with already enough sign bits
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 9 +
.../CodeGen/AArch64/arm64-neon-mul-div-cte.ll | 12 +-
llvm/test/CodeGen/AArch64/combine-sdiv.ll | 44 +--
.../AArch64/sdiv-by-const-promoted-ops.ll | 40 +--
llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll | 226 +++++----------
llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll | 268 ++++++++++--------
llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 200 ++++++-------
llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 190 ++++++-------
8 files changed, 477 insertions(+), 512 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 868171e45be86..0fd627b9a8ef5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -971,6 +971,15 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
}
break;
}
+ case ISD::SRA: {
+ // If we only want bits that already match the signbit then we don't need
+ // to shift.
+ SDValue Op0 = Op.getOperand(0);
+ unsigned HiDemandedBits = BitWidth - DemandedBits.countr_zero();
+ if (DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1) >= HiDemandedBits)
+ return Op0;
+ break;
+ }
case ISD::SETCC: {
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll b/llvm/test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll
index 7aa6b77cf3524..6c66a77e88472 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll
@@ -8,9 +8,9 @@ define <16 x i8> @div16xi8(<16 x i8> %x) {
; CHECK-SD-NEXT: movi v1.16b, #41
; CHECK-SD-NEXT: smull2 v2.8h, v0.16b, v1.16b
; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b
-; CHECK-SD-NEXT: uzp2 v0.16b, v0.16b, v2.16b
-; CHECK-SD-NEXT: sshr v0.16b, v0.16b, #2
-; CHECK-SD-NEXT: usra v0.16b, v0.16b, #7
+; CHECK-SD-NEXT: uzp2 v1.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT: sshr v0.16b, v1.16b, #2
+; CHECK-SD-NEXT: usra v0.16b, v1.16b, #7
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: div16xi8:
@@ -35,9 +35,9 @@ define <8 x i16> @div8xi16(<8 x i16> %x) {
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h
-; CHECK-SD-NEXT: sshr v0.8h, v0.8h, #12
-; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT: add v1.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: sshr v0.8h, v1.8h, #12
+; CHECK-SD-NEXT: usra v0.8h, v1.8h, #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: div8xi16:
diff --git a/llvm/test/CodeGen/AArch64/combine-sdiv.ll b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
index b160333edb487..c7cf8700f7c26 100644
--- a/llvm/test/CodeGen/AArch64/combine-sdiv.ll
+++ b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
@@ -955,10 +955,10 @@ define <8 x i16> @combine_vec_sdiv_nonuniform2(<8 x i16> %x) {
; CHECK-SD-NEXT: adrp x8, .LCPI29_1
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI29_1]
-; CHECK-SD-NEXT: uzp2 v0.8h, v0.8h, v2.8h
-; CHECK-SD-NEXT: sshl v0.8h, v0.8h, v1.8h
-; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT: uzp2 v1.8h, v0.8h, v2.8h
+; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI29_1]
+; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: usra v0.8h, v1.8h, #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform2:
@@ -987,10 +987,10 @@ define <8 x i16> @combine_vec_sdiv_nonuniform3(<8 x i16> %x) {
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
-; CHECK-SD-NEXT: sshl v0.8h, v0.8h, v1.8h
-; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT: add v1.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI30_1]
+; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: usra v0.8h, v1.8h, #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform3:
@@ -1020,10 +1020,10 @@ define <8 x i16> @combine_vec_sdiv_nonuniform4(<8 x i16> %x) {
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-SD-NEXT: sub v0.8h, v1.8h, v0.8h
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI31_1]
-; CHECK-SD-NEXT: sshl v0.8h, v0.8h, v1.8h
-; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT: sub v1.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI31_1]
+; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: usra v0.8h, v1.8h, #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform4:
@@ -1058,7 +1058,7 @@ define <8 x i16> @combine_vec_sdiv_nonuniform5(<8 x i16> %x) {
; CHECK-SD-NEXT: mla v1.8h, v0.8h, v2.8h
; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI32_2]
; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h
-; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-SD-NEXT: usra v0.8h, v1.8h, #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform5:
@@ -1085,21 +1085,21 @@ define <8 x i16> @combine_vec_sdiv_nonuniform6(<8 x i16> %x) {
; CHECK-SD-LABEL: combine_vec_sdiv_nonuniform6:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: adrp x8, .LCPI33_0
+; CHECK-SD-NEXT: adrp x9, .LCPI33_3
; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI33_0]
; CHECK-SD-NEXT: adrp x8, .LCPI33_1
+; CHECK-SD-NEXT: ldr q3, [x9, :lo12:.LCPI33_3]
; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI33_1]
; CHECK-SD-NEXT: adrp x8, .LCPI33_2
; CHECK-SD-NEXT: mla v1.8h, v0.8h, v2.8h
-; CHECK-SD-NEXT: ldr q0, [x8, :lo12:.LCPI33_2]
-; CHECK-SD-NEXT: adrp x8, .LCPI33_3
-; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI33_3]
-; CHECK-SD-NEXT: sshl v0.8h, v1.8h, v0.8h
-; CHECK-SD-NEXT: ushr v1.8h, v0.8h, #15
-; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-SD-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI33_2]
+; CHECK-SD-NEXT: ushr v0.8h, v1.8h, #15
+; CHECK-SD-NEXT: sshl v1.8h, v1.8h, v2.8h
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_vec_sdiv_nonuniform6:
@@ -1172,14 +1172,14 @@ define <16 x i8> @pr38658(<16 x i8> %x) {
; CHECK-SD-NEXT: adrp x8, .LCPI35_0
; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI35_0]
; CHECK-SD-NEXT: adrp x8, .LCPI35_1
+; CHECK-SD-NEXT: ldr q3, [x8, :lo12:.LCPI35_1]
; CHECK-SD-NEXT: smull2 v2.8h, v0.16b, v1.16b
; CHECK-SD-NEXT: smull v1.8h, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp2 v1.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: add v0.16b, v1.16b, v0.16b
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI35_1]
-; CHECK-SD-NEXT: sshl v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
; CHECK-SD-NEXT: ushr v2.16b, v0.16b, #7
+; CHECK-SD-NEXT: sshl v0.16b, v0.16b, v3.16b
; CHECK-SD-NEXT: mov v1.b[15], v2.b[15]
; CHECK-SD-NEXT: add v0.16b, v0.16b, v1.16b
; CHECK-SD-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll b/llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll
index 840501ec48e42..c919b8c9ed595 100644
--- a/llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll
+++ b/llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll
@@ -8,9 +8,9 @@ define <8 x i16> @sdiv_v8i16_by_7(<8 x i16> %x) {
; CHECK-NEXT: dup v1.8h, w8
; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-NEXT: uzp2 v0.8h, v0.8h, v2.8h
-; CHECK-NEXT: sshr v0.8h, v0.8h, #1
-; CHECK-NEXT: usra v0.8h, v0.8h, #15
+; CHECK-NEXT: uzp2 v1.8h, v0.8h, v2.8h
+; CHECK-NEXT: sshr v0.8h, v1.8h, #1
+; CHECK-NEXT: usra v0.8h, v1.8h, #15
; CHECK-NEXT: ret
%div = sdiv <8 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <8 x i16> %div
@@ -25,12 +25,12 @@ define <16 x i16> @sdiv_v16i16_by_7(<16 x i16> %x) {
; CHECK-NEXT: smull v0.4s, v0.4h, v2.4h
; CHECK-NEXT: smull2 v4.4s, v1.8h, v2.8h
; CHECK-NEXT: smull v1.4s, v1.4h, v2.4h
-; CHECK-NEXT: uzp2 v0.8h, v0.8h, v3.8h
-; CHECK-NEXT: uzp2 v1.8h, v1.8h, v4.8h
-; CHECK-NEXT: sshr v0.8h, v0.8h, #1
-; CHECK-NEXT: sshr v1.8h, v1.8h, #1
-; CHECK-NEXT: usra v0.8h, v0.8h, #15
-; CHECK-NEXT: usra v1.8h, v1.8h, #15
+; CHECK-NEXT: uzp2 v2.8h, v0.8h, v3.8h
+; CHECK-NEXT: uzp2 v3.8h, v1.8h, v4.8h
+; CHECK-NEXT: sshr v0.8h, v2.8h, #1
+; CHECK-NEXT: sshr v1.8h, v3.8h, #1
+; CHECK-NEXT: usra v0.8h, v2.8h, #15
+; CHECK-NEXT: usra v1.8h, v3.8h, #15
; CHECK-NEXT: ret
%div = sdiv <16 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <16 x i16> %div
@@ -40,14 +40,14 @@ define <8 x i16> @srem_v8i16_by_7(<8 x i16> %x) {
; CHECK-LABEL: srem_v8i16_by_7:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #18725 // =0x4925
+; CHECK-NEXT: movi v3.8h, #7
; CHECK-NEXT: dup v1.8h, w8
; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-NEXT: uzp2 v1.8h, v1.8h, v2.8h
-; CHECK-NEXT: movi v2.8h, #7
-; CHECK-NEXT: sshr v1.8h, v1.8h, #1
-; CHECK-NEXT: usra v1.8h, v1.8h, #15
-; CHECK-NEXT: mls v0.8h, v1.8h, v2.8h
+; CHECK-NEXT: sshr v2.8h, v1.8h, #1
+; CHECK-NEXT: usra v2.8h, v1.8h, #15
+; CHECK-NEXT: mls v0.8h, v2.8h, v3.8h
; CHECK-NEXT: ret
%rem = srem <8 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <8 x i16> %rem
@@ -57,20 +57,20 @@ define <16 x i16> @srem_v16i16_by_7(<16 x i16> %x) {
; CHECK-LABEL: srem_v16i16_by_7:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #18725 // =0x4925
+; CHECK-NEXT: movi v6.8h, #7
; CHECK-NEXT: dup v2.8h, w8
; CHECK-NEXT: smull2 v3.4s, v0.8h, v2.8h
; CHECK-NEXT: smull v4.4s, v0.4h, v2.4h
; CHECK-NEXT: smull2 v5.4s, v1.8h, v2.8h
; CHECK-NEXT: smull v2.4s, v1.4h, v2.4h
; CHECK-NEXT: uzp2 v3.8h, v4.8h, v3.8h
-; CHECK-NEXT: movi v4.8h, #7
; CHECK-NEXT: uzp2 v2.8h, v2.8h, v5.8h
-; CHECK-NEXT: sshr v3.8h, v3.8h, #1
-; CHECK-NEXT: sshr v2.8h, v2.8h, #1
-; CHECK-NEXT: usra v3.8h, v3.8h, #15
-; CHECK-NEXT: usra v2.8h, v2.8h, #15
-; CHECK-NEXT: mls v0.8h, v3.8h, v4.8h
-; CHECK-NEXT: mls v1.8h, v2.8h, v4.8h
+; CHECK-NEXT: sshr v4.8h, v3.8h, #1
+; CHECK-NEXT: sshr v5.8h, v2.8h, #1
+; CHECK-NEXT: usra v4.8h, v3.8h, #15
+; CHECK-NEXT: usra v5.8h, v2.8h, #15
+; CHECK-NEXT: mls v0.8h, v4.8h, v6.8h
+; CHECK-NEXT: mls v1.8h, v5.8h, v6.8h
; CHECK-NEXT: ret
%rem = srem <16 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <16 x i16> %rem
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
index 7682359ab0788..956e65972a476 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
@@ -33,8 +33,8 @@ define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v9, v9, v8
-; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -85,8 +85,8 @@ define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v9, v9, v8
-; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -137,8 +137,8 @@ define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v9, v9, v8
-; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -189,8 +189,8 @@ define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
; CHECK-NEXT: vsub.vv v9, v9, v8
-; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vsrl.vi v10, v9, 7
+; CHECK-NEXT: vsra.vi v9, v9, 2
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -241,8 +241,8 @@ define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmulh.vx v10, v8, a0
; CHECK-NEXT: vsub.vv v10, v10, v8
-; CHECK-NEXT: vsra.vi v10, v10, 2
; CHECK-NEXT: vsrl.vi v12, v10, 7
+; CHECK-NEXT: vsra.vi v10, v10, 2
; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v10
@@ -293,8 +293,8 @@ define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; CHECK-NEXT: vmulh.vx v12, v8, a0
; CHECK-NEXT: vsub.vv v12, v12, v8
-; CHECK-NEXT: vsra.vi v12, v12, 2
; CHECK-NEXT: vsrl.vi v16, v12, 7
+; CHECK-NEXT: vsra.vi v12, v12, 2
; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v12
@@ -345,8 +345,8 @@ define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vmulh.vx v16, v8, a0
; CHECK-NEXT: vsub.vv v16, v16, v8
-; CHECK-NEXT: vsra.vi v16, v16, 2
; CHECK-NEXT: vsrl.vi v24, v16, 7
+; CHECK-NEXT: vsra.vi v16, v16, 2
; CHECK-NEXT: vadd.vv v16, v16, v24
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v16
@@ -384,8 +384,8 @@ define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
-; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -436,8 +436,8 @@ define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
-; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -488,8 +488,8 @@ define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmulh.vx v9, v8, a0
-; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vsrl.vi v10, v9, 15
+; CHECK-NEXT: vsra.vi v9, v9, 1
; CHECK-NEXT: vadd.vv v9, v9, v10
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v9
@@ -540,8 +540,8 @@ define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vmulh.vx v10, v8, a0
-; CHECK-NEXT: vsra.vi v10, v10, 1
; CHECK-NEXT: vsrl.vi v12, v10, 15
+; CHECK-NEXT: vsra.vi v10, v10, 1
; CHECK-NEXT: vadd.vv v10, v10, v12
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v10
@@ -592,8 +592,8 @@ define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-NEXT: vmulh.vx v12, v8, a0
-; CHECK-NEXT: vsra.vi v12, v12, 1
; CHECK-NEXT: vsrl.vi v16, v12, 15
+; CHECK-NEXT: vsra.vi v12, v12, 1
; CHECK-NEXT: vadd.vv v12, v12, v16
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v12
@@ -644,8 +644,8 @@ define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-NEXT: addi a0, a0, 1755
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vmulh.vx v16, v8, a0
-; CHECK-NEXT: vsra.vi v16, v16, 1
; CHECK-NEXT: vsrl.vi v24, v16, 15
+; CHECK-NEXT: vsra.vi v16, v16, 1
; CHECK-NEXT: vadd.vv v16, v16, v24
; CHECK-NEXT: li a0, -7
; CHECK-NEXT: vnmsac.vx v8, a0, v16
@@ -677,33 +677,19 @@ define <vscale x 1 x i32> @vrem_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %
}
define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv1i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV32-NEXT: vmulh.vx v9, v8, a0
-; RV32-NEXT: vsub.vv v9, v9, v8
-; RV32-NEXT: vsrl.vi v10, v9, 31
-; RV32-NEXT: vsra.vi v9, v9, 2
-; RV32-NEXT: vadd.vv v9, v9, v10
-; RV32-NEXT: li a0, -7
-; RV32-NEXT: vnmsac.vx v8, a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vrem_vi_nxv1i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV64-NEXT: vmulh.vx v9, v8, a0
-; RV64-NEXT: vsub.vv v9, v9, v8
-; RV64-NEXT: vsra.vi v9, v9, 2
-; RV64-NEXT: vsrl.vi v10, v9, 31
-; RV64-NEXT: vadd.vv v9, v9, v10
-; RV64-NEXT: li a0, -7
-; RV64-NEXT: vnmsac.vx v8, a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vrem_vi_nxv1i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsrl.vi v10, v9, 31
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vadd.vv v9, v9, v10
+; CHECK-NEXT: li a0, -7
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
+; CHECK-NEXT: ret
%vc = srem <vscale x 1 x i32> %va, splat (i32 -7)
ret <vscale x 1 x i32> %vc
}
@@ -731,33 +717,19 @@ define <vscale x 2 x i32> @vrem_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %
}
define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv2i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV32-NEXT: vmulh.vx v9, v8, a0
-; RV32-NEXT: vsub.vv v9, v9, v8
-; RV32-NEXT: vsrl.vi v10, v9, 31
-; RV32-NEXT: vsra.vi v9, v9, 2
-; RV32-NEXT: vadd.vv v9, v9, v10
-; RV32-NEXT: li a0, -7
-; RV32-NEXT: vnmsac.vx v8, a0, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vrem_vi_nxv2i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV64-NEXT: vmulh.vx v9, v8, a0
-; RV64-NEXT: vsub.vv v9, v9, v8
-; RV64-NEXT: vsra.vi v9, v9, 2
-; RV64-NEXT: vsrl.vi v10, v9, 31
-; RV64-NEXT: vadd.vv v9, v9, v10
-; RV64-NEXT: li a0, -7
-; RV64-NEXT: vnmsac.vx v8, a0, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vrem_vi_nxv2i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmulh.vx v9, v8, a0
+; CHECK-NEXT: vsub.vv v9, v9, v8
+; CHECK-NEXT: vsrl.vi v10, v9, 31
+; CHECK-NEXT: vsra.vi v9, v9, 2
+; CHECK-NEXT: vadd.vv v9, v9, v10
+; CHECK-NEXT: li a0, -7
+; CHECK-NEXT: vnmsac.vx v8, a0, v9
+; CHECK-NEXT: ret
%vc = srem <vscale x 2 x i32> %va, splat (i32 -7)
ret <vscale x 2 x i32> %vc
}
@@ -785,33 +757,19 @@ define <vscale x 4 x i32> @vrem_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %
}
define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv4i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32-NEXT: vmulh.vx v10, v8, a0
-; RV32-NEXT: vsub.vv v10, v10, v8
-; RV32-NEXT: vsrl.vi v12, v10, 31
-; RV32-NEXT: vsra.vi v10, v10, 2
-; RV32-NEXT: vadd.vv v10, v10, v12
-; RV32-NEXT: li a0, -7
-; RV32-NEXT: vnmsac.vx v8, a0, v10
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vrem_vi_nxv4i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV64-NEXT: vmulh.vx v10, v8, a0
-; RV64-NEXT: vsub.vv v10, v10, v8
-; RV64-NEXT: vsra.vi v10, v10, 2
-; RV64-NEXT: vsrl.vi v12, v10, 31
-; RV64-NEXT: vadd.vv v10, v10, v12
-; RV64-NEXT: li a0, -7
-; RV64-NEXT: vnmsac.vx v8, a0, v10
-; RV64-NEXT: ret
+; CHECK-LABEL: vrem_vi_nxv4i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vmulh.vx v10, v8, a0
+; CHECK-NEXT: vsub.vv v10, v10, v8
+; CHECK-NEXT: vsrl.vi v12, v10, 31
+; CHECK-NEXT: vsra.vi v10, v10, 2
+; CHECK-NEXT: vadd.vv v10, v10, v12
+; CHECK-NEXT: li a0, -7
+; CHECK-NEXT: vnmsac.vx v8, a0, v10
+; CHECK-NEXT: ret
%vc = srem <vscale x 4 x i32> %va, splat (i32 -7)
ret <vscale x 4 x i32> %vc
}
@@ -839,33 +797,19 @@ define <vscale x 8 x i32> @vrem_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %
}
define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv8i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmulh.vx v12, v8, a0
-; RV32-NEXT: vsub.vv v12, v12, v8
-; RV32-NEXT: vsrl.vi v16, v12, 31
-; RV32-NEXT: vsra.vi v12, v12, 2
-; RV32-NEXT: vadd.vv v12, v12, v16
-; RV32-NEXT: li a0, -7
-; RV32-NEXT: vnmsac.vx v8, a0, v12
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vrem_vi_nxv8i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV64-NEXT: vmulh.vx v12, v8, a0
-; RV64-NEXT: vsub.vv v12, v12, v8
-; RV64-NEXT: vsra.vi v12, v12, 2
-; RV64-NEXT: vsrl.vi v16, v12, 31
-; RV64-NEXT: vadd.vv v12, v12, v16
-; RV64-NEXT: li a0, -7
-; RV64-NEXT: vnmsac.vx v8, a0, v12
-; RV64-NEXT: ret
+; CHECK-LABEL: vrem_vi_nxv8i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmulh.vx v12, v8, a0
+; CHECK-NEXT: vsub.vv v12, v12, v8
+; CHECK-NEXT: vsrl.vi v16, v12, 31
+; CHECK-NEXT: vsra.vi v12, v12, 2
+; CHECK-NEXT: vadd.vv v12, v12, v16
+; CHECK-NEXT: li a0, -7
+; CHECK-NEXT: vnmsac.vx v8, a0, v12
+; CHECK-NEXT: ret
%vc = srem <vscale x 8 x i32> %va, splat (i32 -7)
ret <vscale x 8 x i32> %vc
}
@@ -893,33 +837,19 @@ define <vscale x 16 x i32> @vrem_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signex
}
define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv16i32_0:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, 449390
-; RV32-NEXT: addi a0, a0, -1171
-; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmulh.vx v16, v8, a0
-; RV32-NEXT: vsub.vv v16, v16, v8
-; RV32-NEXT: vsrl.vi v24, v16, 31
-; RV32-NEXT: vsra.vi v16, v16, 2
-; RV32-NEXT: vadd.vv v16, v16, v24
-; RV32-NEXT: li a0, -7
-; RV32-NEXT: vnmsac.vx v8, a0, v16
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vrem_vi_nxv16i32_0:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, 449390
-; RV64-NEXT: addi a0, a0, -1171
-; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV64-NEXT: vmulh.vx v16, v8, a0
-; RV64-NEXT: vsub.vv v16, v16, v8
-; RV64-NEXT: vsra.vi v16, v16, 2
-; RV64-NEXT: vsrl.vi v24, v16, 31
-; RV64-NEXT: vadd.vv v16, v16, v24
-; RV64-NEXT: li a0, -7
-; RV64-NEXT: vnmsac.vx v8, a0, v16
-; RV64-NEXT: ret
+; CHECK-LABEL: vrem_vi_nxv16i32_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 449390
+; CHECK-NEXT: addi a0, a0, -1171
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmulh.vx v16, v8, a0
+; CHECK-NEXT: vsub.vv v16, v16, v8
+; CHECK-NEXT: vsrl.vi v24, v16, 31
+; CHECK-NEXT: vsra.vi v16, v16, 2
+; CHECK-NEXT: vadd.vv v16, v16, v24
+; CHECK-NEXT: li a0, -7
+; CHECK-NEXT: vnmsac.vx v8, a0, v16
+; CHECK-NEXT: ret
%vc = srem <vscale x 16 x i32> %va, splat (i32 -7)
ret <vscale x 16 x i32> %vc
}
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
index 92615c859ea72..6d860d9bda569 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
@@ -180,13 +180,13 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; SSE-NEXT: psrlw $8, %xmm4
; SSE-NEXT: packuswb %xmm2, %xmm4
; SSE-NEXT: paddb %xmm4, %xmm0
+; SSE-NEXT: pcmpgtb %xmm0, %xmm1
; SSE-NEXT: psrlw $2, %xmm0
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; SSE-NEXT: pxor %xmm2, %xmm0
-; SSE-NEXT: psubb %xmm2, %xmm0
-; SSE-NEXT: pcmpgtb %xmm0, %xmm1
; SSE-NEXT: psubb %xmm1, %xmm0
+; SSE-NEXT: psubb %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: test_div7_16i8:
@@ -201,13 +201,13 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpaddb %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm0
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2NOBW-LABEL: test_div7_16i8:
@@ -218,14 +218,14 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
-; AVX2NOBW-NEXT: vpsrlw $2, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} xmm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX2NOBW-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX2NOBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpsrlw $2, %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX2NOBW-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX2NOBW-NEXT: vzeroupper
; AVX2NOBW-NEXT: retq
;
@@ -236,14 +236,14 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
-; AVX512BW-NEXT: vpsrlw $2, %xmm0, %xmm0
-; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} xmm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpxor %xmm1, %xmm0, %xmm0
-; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
+; AVX512BW-NEXT: vpsrlw $2, %xmm0, %xmm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX512BW-NEXT: vpsubb %xmm2, %xmm0, %xmm0
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%res = sdiv <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
@@ -274,12 +274,12 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; SSE-NEXT: psraw $8, %xmm2
; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [32,64,128,32,64,128,128,64]
; SSE-NEXT: psrlw $8, %xmm2
+; SSE-NEXT: pcmpgtb %xmm0, %xmm1
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: psraw $8, %xmm0
; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [64,64,128,64,32,128,64,32]
; SSE-NEXT: psrlw $8, %xmm0
; SSE-NEXT: packuswb %xmm2, %xmm0
-; SSE-NEXT: pcmpgtb %xmm0, %xmm1
; SSE-NEXT: psubb %xmm1, %xmm0
; SSE-NEXT: retq
;
@@ -299,13 +299,13 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [32,64,128,32,64,128,128,64]
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [64,64,128,64,32,128,64,32]
-; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [64,64,128,64,32,128,64,32]
+; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
+; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm0
; AVX1-NEXT: retq
;
; AVX2NOBW-LABEL: test_divconstant_16i8:
@@ -317,14 +317,14 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
-; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm0
-; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [64,64,128,64,32,128,64,32,32,64,128,32,64,128,128,64]
-; AVX2NOBW-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2NOBW-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm1
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [64,64,128,64,32,128,64,32,32,64,128,32,64,128,128,64]
+; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
+; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
+; AVX2NOBW-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; AVX2NOBW-NEXT: vzeroupper
; AVX2NOBW-NEXT: retq
;
@@ -337,12 +337,12 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vpaddb %xmm0, %xmm2, %xmm0
-; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm0
-; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
-; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX512BW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm2
+; AVX512BW-NEXT: vpsravw %zmm1, %zmm2, %zmm1
+; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
+; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512BW-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
+; AVX512BW-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
%res = sdiv <16 x i8> %a, <i8 7, i8 8, i8 9, i8 10,i8 11, i8 12, i8 13, i8 14, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9,i8 9, i8 7>
@@ -570,13 +570,13 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; SSE-NEXT: psrlw $8, %xmm4
; SSE-NEXT: packuswb %xmm2, %xmm4
; SSE-NEXT: paddb %xmm0, %xmm4
+; SSE-NEXT: pcmpgtb %xmm4, %xmm1
; SSE-NEXT: psrlw $2, %xmm4
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; SSE-NEXT: pxor %xmm2, %xmm4
-; SSE-NEXT: psubb %xmm2, %xmm4
-; SSE-NEXT: pcmpgtb %xmm4, %xmm1
; SSE-NEXT: psubb %xmm1, %xmm4
+; SSE-NEXT: psubb %xmm2, %xmm4
; SSE-NEXT: movdqa %xmm4, %xmm1
; SSE-NEXT: psllw $3, %xmm1
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
@@ -596,13 +596,13 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpaddb %xmm0, %xmm2, %xmm2
+; AVX1-NEXT: vpcmpgtb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $2, %xmm2, %xmm2
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2
-; AVX1-NEXT: vpsubb %xmm3, %xmm2, %xmm2
-; AVX1-NEXT: vpcmpgtb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpsllw $3, %xmm1, %xmm2
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsubb %xmm2, %xmm1, %xmm1
@@ -617,14 +617,14 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpsrlw $2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX2NOBW-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2NOBW-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpsrlw $2, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX2NOBW-NEXT: vpxor %xmm3, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpsllw $3, %xmm1, %xmm2
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
@@ -639,14 +639,14 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %xmm0, %xmm1, %xmm1
-; AVX512BW-NEXT: vpsrlw $2, %xmm1, %xmm1
-; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX512BW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512BW-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm2
+; AVX512BW-NEXT: vpsrlw $2, %xmm1, %xmm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpxor %xmm3, %xmm1, %xmm1
; AVX512BW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
+; AVX512BW-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX512BW-NEXT: vpsllw $3, %xmm1, %xmm2
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512BW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
@@ -682,12 +682,12 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE2-NEXT: psraw $8, %xmm3
; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [32,64,128,32,64,128,128,64]
; SSE2-NEXT: psrlw $8, %xmm3
+; SSE2-NEXT: pcmpgtb %xmm1, %xmm2
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: psraw $8, %xmm1
; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [64,64,128,64,32,128,64,32]
; SSE2-NEXT: psrlw $8, %xmm1
; SSE2-NEXT: packuswb %xmm3, %xmm1
-; SSE2-NEXT: pcmpgtb %xmm1, %xmm2
; SSE2-NEXT: psubb %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
@@ -721,12 +721,12 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; SSE41-NEXT: psraw $8, %xmm3
; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [32,64,128,32,64,128,128,64]
; SSE41-NEXT: psrlw $8, %xmm3
+; SSE41-NEXT: pcmpgtb %xmm2, %xmm1
; SSE41-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE41-NEXT: psraw $8, %xmm2
; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [64,64,128,64,32,128,64,32]
; SSE41-NEXT: psrlw $8, %xmm2
; SSE41-NEXT: packuswb %xmm3, %xmm2
-; SSE41-NEXT: pcmpgtb %xmm2, %xmm1
; SSE41-NEXT: psubb %xmm1, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm1
; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,8,0,10,0,12,0,14,0,13,0,11,0,9,0,7]
@@ -753,13 +753,13 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [32,64,128,32,64,128,128,64]
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [64,64,128,64,32,128,64,32]
-; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [64,64,128,64,32,128,64,32]
+; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
+; AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpcmpgtb %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1
+; AVX1-NEXT: vpsubb %xmm1, %xmm3, %xmm1
; AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2 # [0,8,0,10,0,12,0,14,0,13,0,11,0,9,0,7]
; AVX1-NEXT: vpsllw $8, %xmm2, %xmm2
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [7,8,9,10,11,12,13,14,14,13,12,11,10,9,9,7]
@@ -777,14 +777,14 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX2NOBW-NEXT: vpaddb %xmm2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpmovsxbw %xmm1, %ymm1
-; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [64,64,128,64,32,128,64,32,32,64,128,32,64,128,128,64]
-; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
-; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX2NOBW-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm2
-; AVX2NOBW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpmovsxbw %xmm1, %ymm2
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [64,64,128,64,32,128,64,32,32,64,128,32,64,128,128,64]
+; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
+; AVX2NOBW-NEXT: vextracti128 $1, %ymm2, %xmm3
+; AVX2NOBW-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX2NOBW-NEXT: vpcmpgtb %xmm1, %xmm3, %xmm1
+; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm2, %xmm1
; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [7,8,9,10,11,12,13,14,14,13,12,11,10,9,9,7]
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
@@ -803,11 +803,11 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; AVX512BW-NEXT: vpaddb %xmm3, %xmm2, %xmm2
-; AVX512BW-NEXT: vpmovsxbw %xmm2, %ymm2
-; AVX512BW-NEXT: vpsravw %zmm1, %zmm2, %zmm1
+; AVX512BW-NEXT: vpmovsxbw %xmm2, %ymm3
+; AVX512BW-NEXT: vpsravw %zmm1, %zmm3, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
-; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX512BW-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm2
+; AVX512BW-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX512BW-NEXT: vpcmpgtb %xmm2, %xmm3, %xmm2
; AVX512BW-NEXT: vpsubb %xmm2, %xmm1, %xmm1
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [7,8,9,10,11,12,13,14,14,13,12,11,10,9,9,7]
@@ -1014,34 +1014,62 @@ define <16 x i8> @test_rem_variable_16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
}
define <16 x i8> @PR143238(<16 x i8> %a0) {
-; SSE-LABEL: PR143238:
-; SSE: # %bb.0:
-; SSE-NEXT: pxor %xmm1, %xmm1
-; SSE-NEXT: pxor %xmm2, %xmm2
-; SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
-; SSE-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [0,103,0,187,0,43,0,79,0,147,0,137,0,129,0,121]
-; SSE-NEXT: psrlw $8, %xmm2
-; SSE-NEXT: pxor %xmm3, %xmm3
-; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
-; SSE-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [0,129,0,86,0,129,0,103,0,43,0,147,0,129,0,57]
-; SSE-NEXT: psrlw $8, %xmm3
-; SSE-NEXT: packuswb %xmm2, %xmm3
-; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: paddb %xmm3, %xmm0
-; SSE-NEXT: movdqa %xmm0, %xmm2
-; SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
-; SSE-NEXT: psraw $8, %xmm2
-; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [64,32,128,64,32,32,32,32]
-; SSE-NEXT: psrlw $8, %xmm2
-; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; SSE-NEXT: psraw $8, %xmm0
-; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [256,256,128,128,256,64,64,128]
-; SSE-NEXT: psrlw $8, %xmm0
-; SSE-NEXT: packuswb %xmm2, %xmm0
-; SSE-NEXT: pcmpgtb %xmm0, %xmm1
-; SSE-NEXT: psubb %xmm1, %xmm0
-; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: retq
+; SSE2-LABEL: PR143238:
+; SSE2: # %bb.0:
+; SSE2-NEXT: pxor %xmm2, %xmm2
+; SSE2-NEXT: pxor %xmm1, %xmm1
+; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
+; SSE2-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,103,0,187,0,43,0,79,0,147,0,137,0,129,0,121]
+; SSE2-NEXT: psrlw $8, %xmm1
+; SSE2-NEXT: pxor %xmm3, %xmm3
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [0,129,0,86,0,129,0,103,0,43,0,147,0,129,0,57]
+; SSE2-NEXT: psrlw $8, %xmm3
+; SSE2-NEXT: packuswb %xmm1, %xmm3
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: paddb %xmm3, %xmm0
+; SSE2-NEXT: movdqa %xmm0, %xmm3
+; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [64,32,128,64,32,32,32,32]
+; SSE2-NEXT: psrlw $8, %xmm3
+; SSE2-NEXT: movdqa %xmm0, %xmm1
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [256,256,128,128,256,64,64,128]
+; SSE2-NEXT: psrlw $8, %xmm1
+; SSE2-NEXT: packuswb %xmm3, %xmm1
+; SSE2-NEXT: pcmpgtb %xmm0, %xmm2
+; SSE2-NEXT: psubb %xmm2, %xmm1
+; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: movdqa %xmm1, %xmm0
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: PR143238:
+; SSE41: # %bb.0:
+; SSE41-NEXT: pxor %xmm2, %xmm2
+; SSE41-NEXT: pxor %xmm1, %xmm1
+; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
+; SSE41-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,103,0,187,0,43,0,79,0,147,0,137,0,129,0,121]
+; SSE41-NEXT: psrlw $8, %xmm1
+; SSE41-NEXT: pxor %xmm3, %xmm3
+; SSE41-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE41-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [0,129,0,86,0,129,0,103,0,43,0,147,0,129,0,57]
+; SSE41-NEXT: psrlw $8, %xmm3
+; SSE41-NEXT: packuswb %xmm1, %xmm3
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: paddb %xmm3, %xmm0
+; SSE41-NEXT: movdqa %xmm0, %xmm3
+; SSE41-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [64,32,128,64,32,32,32,32]
+; SSE41-NEXT: psrlw $8, %xmm3
+; SSE41-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; SSE41-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [256,256,128,128,256,64,64,128]
+; SSE41-NEXT: psrlw $8, %xmm1
+; SSE41-NEXT: packuswb %xmm3, %xmm1
+; SSE41-NEXT: pcmpgtb %xmm0, %xmm2
+; SSE41-NEXT: psubb %xmm2, %xmm1
+; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE41-NEXT: movdqa %xmm1, %xmm0
+; SSE41-NEXT: retq
;
; AVX1-LABEL: PR143238:
; AVX1: # %bb.0:
@@ -1055,17 +1083,15 @@ define <16 x i8> @PR143238(<16 x i8> %a0) {
; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm0, %xmm2, %xmm0
-; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
-; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
+; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [64,32,128,64,32,32,32,32]
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [256,256,128,128,256,64,64,128]
-; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [256,256,128,128,256,64,64,128]
+; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
+; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: retq
;
@@ -1078,14 +1104,14 @@ define <16 x i8> @PR143238(<16 x i8> %a0) {
; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vpaddb %xmm0, %xmm1, %xmm0
-; AVX2NOBW-NEXT: vpmovsxbw %xmm0, %ymm0
-; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [256,256,128,128,256,64,64,128,64,32,128,64,32,32,32,32]
-; AVX2NOBW-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2NOBW-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
-; AVX2NOBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX2NOBW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [256,256,128,128,256,64,64,128,64,32,128,64,32,32,32,32]
+; AVX2NOBW-NEXT: vpsrlw $8, %ymm1, %ymm1
+; AVX2NOBW-NEXT: vextracti128 $1, %ymm1, %xmm2
+; AVX2NOBW-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
+; AVX2NOBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2NOBW-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
+; AVX2NOBW-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2NOBW-NEXT: vzeroupper
; AVX2NOBW-NEXT: retq
@@ -1099,12 +1125,12 @@ define <16 x i8> @PR143238(<16 x i8> %a0) {
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vpaddb %xmm0, %xmm2, %xmm0
-; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm0
-; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
-; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX512BW-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX512BW-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm2, %zmm1
+; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
+; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512BW-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
+; AVX512BW-NEXT: vpsubb %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
index e42a3febbf041..1309f2719e67a 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
@@ -182,28 +182,28 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpackuswb %xmm3, %xmm5, %xmm3
; AVX1-NEXT: vpaddb %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm3
; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm1
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX1-NEXT: vpxor %xmm5, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm5, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm6
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; AVX1-NEXT: vpand %xmm5, %xmm1, %xmm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX1-NEXT: vpxor %xmm6, %xmm1, %xmm1
+; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpsubb %xmm6, %xmm1, %xmm1
-; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
-; AVX1-NEXT: vpmulhw %xmm4, %xmm6, %xmm6
-; AVX1-NEXT: vpsrlw $8, %xmm6, %xmm6
+; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
+; AVX1-NEXT: vpmulhw %xmm4, %xmm3, %xmm3
+; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
; AVX1-NEXT: vpmulhw %xmm4, %xmm7, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpackuswb %xmm6, %xmm4, %xmm4
-; AVX1-NEXT: vpaddb %xmm0, %xmm4, %xmm0
-; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm0
-; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; AVX1-NEXT: vpxor %xmm5, %xmm0, %xmm0
-; AVX1-NEXT: vpsubb %xmm5, %xmm0, %xmm0
+; AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vpaddb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm2
+; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0
+; AVX1-NEXT: vpxor %xmm6, %xmm0, %xmm0
; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vpsubb %xmm6, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
@@ -219,13 +219,13 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm3, %ymm2
; AVX2NOBW-NEXT: vpaddb %ymm0, %ymm2, %ymm0
+; AVX2NOBW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $2, %ymm0, %ymm0
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} ymm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX2NOBW-NEXT: vpxor %ymm2, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm0, %ymm0
; AVX2NOBW-NEXT: retq
;
; AVX512BW-LABEL: test_div7_32i8:
@@ -235,14 +235,14 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %ymm0, %ymm1, %ymm0
-; AVX512BW-NEXT: vpsrlw $2, %ymm0, %ymm0
-; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} ymm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpxor %ymm1, %ymm0, %ymm0
-; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
+; AVX512BW-NEXT: vpsrlw $2, %ymm0, %ymm0
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} ymm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpxor %ymm2, %ymm0, %ymm0
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: vpsubb %ymm2, %ymm0, %ymm0
; AVX512BW-NEXT: retq
%res = sdiv <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
ret <32 x i8> %res
@@ -271,13 +271,13 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm4, %xmm4
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [32,64,128,32,64,128,64,64]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [16,64,32,128,64,32,32,32]
-; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
-; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
-; AVX1-NEXT: vpcmpgtb %xmm2, %xmm1, %xmm4
-; AVX1-NEXT: vpsubb %xmm4, %xmm2, %xmm2
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5 # [16,64,32,128,64,32,32,32]
+; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
+; AVX1-NEXT: vpackuswb %xmm4, %xmm5, %xmm4
+; AVX1-NEXT: vpcmpgtb %xmm2, %xmm1, %xmm2
+; AVX1-NEXT: vpsubb %xmm2, %xmm4, %xmm2
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [0,137,0,129,0,121,0,57,0,27,0,103,0,49,0,187]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
@@ -290,13 +290,13 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [32,32,32,64,128,32,64,16]
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [64,64,128,64,32,128,64,32]
-; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
-; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm4, %xmm4
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [64,64,128,64,32,128,64,32]
+; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
+; AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm3
+; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpsubb %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq
;
@@ -316,13 +316,13 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpsraw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [32,32,32,64,128,32,64,16,32,64,128,32,64,128,64,64]
; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX2NOBW-NEXT: vpsraw $8, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [64,64,128,64,32,128,64,32,16,64,32,128,64,32,32,32]
-; AVX2NOBW-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
-; AVX2NOBW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm3 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX2NOBW-NEXT: vpsraw $8, %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [64,64,128,64,32,128,64,32,16,64,32,128,64,32,32,32]
+; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
+; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm3, %ymm2
+; AVX2NOBW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
+; AVX2NOBW-NEXT: vpsubb %ymm0, %ymm2, %ymm0
; AVX2NOBW-NEXT: retq
;
; AVX512BW-LABEL: test_divconstant_32i8:
@@ -333,11 +333,11 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
; AVX512BW-NEXT: vpaddb %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; AVX512BW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovsxbw %ymm0, %zmm0
; AVX512BW-NEXT: vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
-; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX512BW-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: retq
%res = sdiv <32 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
@@ -552,49 +552,49 @@ define <16 x i16> @test_rem7_16i16(<16 x i16> %a) nounwind {
define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
; AVX1-LABEL: test_rem7_32i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8],xmm2[8],xmm1[9],xmm2[9],xmm1[10],xmm2[10],xmm1[11],xmm2[11],xmm1[12],xmm2[12],xmm1[13],xmm2[13],xmm1[14],xmm2[14],xmm1[15],xmm2[15]
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147]
; AVX1-NEXT: vpmulhw %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; AVX1-NEXT: vpmulhw %xmm4, %xmm5, %xmm5
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
; AVX1-NEXT: vpackuswb %xmm3, %xmm5, %xmm3
-; AVX1-NEXT: vpaddb %xmm2, %xmm3, %xmm3
+; AVX1-NEXT: vpaddb %xmm1, %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtb %xmm3, %xmm2, %xmm5
; AVX1-NEXT: vpsrlw $2, %xmm3, %xmm3
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX1-NEXT: vpxor %xmm6, %xmm3, %xmm3
-; AVX1-NEXT: vpsubb %xmm6, %xmm3, %xmm3
-; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm7
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm7 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX1-NEXT: vpxor %xmm7, %xmm3, %xmm3
+; AVX1-NEXT: vpsubb %xmm5, %xmm3, %xmm3
; AVX1-NEXT: vpsubb %xmm7, %xmm3, %xmm3
-; AVX1-NEXT: vpsllw $3, %xmm3, %xmm7
+; AVX1-NEXT: vpsllw $3, %xmm3, %xmm5
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm8 = [248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248]
-; AVX1-NEXT: vpand %xmm7, %xmm8, %xmm7
-; AVX1-NEXT: vpsubb %xmm7, %xmm3, %xmm3
-; AVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm2
-; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
+; AVX1-NEXT: vpand %xmm5, %xmm8, %xmm5
+; AVX1-NEXT: vpsubb %xmm5, %xmm3, %xmm3
+; AVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
; AVX1-NEXT: vpmulhw %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; AVX1-NEXT: vpmulhw %xmm4, %xmm7, %xmm4
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; AVX1-NEXT: vpmulhw %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vpaddb %xmm0, %xmm3, %xmm3
+; AVX1-NEXT: vpcmpgtb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $2, %xmm3, %xmm3
-; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
-; AVX1-NEXT: vpxor %xmm6, %xmm3, %xmm3
-; AVX1-NEXT: vpsubb %xmm6, %xmm3, %xmm3
-; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm3, %xmm1
-; AVX1-NEXT: vpsllw $3, %xmm1, %xmm3
+; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
+; AVX1-NEXT: vpxor %xmm7, %xmm3, %xmm3
+; AVX1-NEXT: vpsubb %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpsubb %xmm7, %xmm2, %xmm2
+; AVX1-NEXT: vpsllw $3, %xmm2, %xmm3
; AVX1-NEXT: vpand %xmm3, %xmm8, %xmm3
-; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: vpsubb %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2NOBW-LABEL: test_rem7_32i8:
@@ -609,13 +609,13 @@ define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpackuswb %ymm2, %ymm3, %ymm2
; AVX2NOBW-NEXT: vpaddb %ymm0, %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpcmpgtb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsrlw $2, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpbroadcastb {{.*#+}} ymm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; AVX2NOBW-NEXT: vpxor %ymm3, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpsubb %ymm3, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpcmpgtb %ymm2, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm2, %ymm1
+; AVX2NOBW-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX2NOBW-NEXT: vpsllw $3, %ymm1, %ymm2
; AVX2NOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX2NOBW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
@@ -629,14 +629,14 @@ define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
; AVX512BW-NEXT: vpaddb %ymm0, %ymm1, %ymm1
-; AVX512BW-NEXT: vpsrlw $2, %ymm1, %ymm1
-; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} ymm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpxor %ymm2, %ymm1, %ymm1
-; AVX512BW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512BW-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm2
+; AVX512BW-NEXT: vpsrlw $2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} ymm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpxor %ymm3, %ymm1, %ymm1
; AVX512BW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
+; AVX512BW-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512BW-NEXT: vpsllw $3, %ymm1, %ymm2
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
; AVX512BW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
@@ -669,13 +669,13 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm5, %xmm5
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5 # [32,64,128,32,64,128,64,64]
; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [16,64,32,128,64,32,32,32]
-; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpackuswb %xmm5, %xmm3, %xmm3
-; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm5
-; AVX1-NEXT: vpsubb %xmm5, %xmm3, %xmm3
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm6 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm6, %xmm6
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6, %xmm6 # [16,64,32,128,64,32,32,32]
+; AVX1-NEXT: vpsrlw $8, %xmm6, %xmm6
+; AVX1-NEXT: vpackuswb %xmm5, %xmm6, %xmm5
+; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm3
+; AVX1-NEXT: vpsubb %xmm3, %xmm5, %xmm3
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm5 # [22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [255,255,255,255,255,255,255,255]
; AVX1-NEXT: vpand %xmm6, %xmm5, %xmm5
@@ -695,13 +695,13 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX1-NEXT: vpsraw $8, %xmm4, %xmm4
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [32,32,32,64,128,32,64,16]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
-; AVX1-NEXT: vpsraw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3 # [64,64,128,64,32,128,64,32]
-; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
-; AVX1-NEXT: vpackuswb %xmm4, %xmm3, %xmm3
+; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; AVX1-NEXT: vpsraw $8, %xmm5, %xmm5
+; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5 # [64,64,128,64,32,128,64,32]
+; AVX1-NEXT: vpsrlw $8, %xmm5, %xmm5
+; AVX1-NEXT: vpackuswb %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpcmpgtb %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpsubb %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpsubb %xmm1, %xmm4, %xmm1
; AVX1-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm3 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22]
; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
; AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [0,8,0,10,0,12,0,14,0,16,0,18,0,20,0,22]
@@ -727,13 +727,13 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX2NOBW-NEXT: vpsraw $8, %ymm3, %ymm3
; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [32,32,32,64,128,32,64,16,32,64,128,32,64,128,64,64]
; AVX2NOBW-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm2 = ymm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX2NOBW-NEXT: vpsraw $8, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [64,64,128,64,32,128,64,32,16,64,32,128,64,32,32,32]
-; AVX2NOBW-NEXT: vpsrlw $8, %ymm2, %ymm2
-; AVX2NOBW-NEXT: vpackuswb %ymm3, %ymm2, %ymm2
+; AVX2NOBW-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX2NOBW-NEXT: vpsraw $8, %ymm4, %ymm4
+; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [64,64,128,64,32,128,64,32,16,64,32,128,64,32,32,32]
+; AVX2NOBW-NEXT: vpsrlw $8, %ymm4, %ymm4
+; AVX2NOBW-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
; AVX2NOBW-NEXT: vpcmpgtb %ymm2, %ymm1, %ymm1
-; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm2, %ymm1
+; AVX2NOBW-NEXT: vpsubb %ymm1, %ymm3, %ymm1
; AVX2NOBW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2 # [0,8,0,10,0,12,0,14,0,16,0,18,0,20,0,22,0,21,0,19,0,17,0,15,0,13,0,11,0,9,0,7]
; AVX2NOBW-NEXT: vpsllw $8, %ymm2, %ymm2
; AVX2NOBW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
@@ -750,11 +750,11 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpmovwb %zmm2, %ymm2
; AVX512BW-NEXT: vpaddb %ymm1, %ymm2, %ymm1
+; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512BW-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm2
; AVX512BW-NEXT: vpmovsxbw %ymm1, %zmm1
; AVX512BW-NEXT: vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpmovwb %zmm1, %ymm1
-; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX512BW-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm2
; AVX512BW-NEXT: vpsubb %ymm2, %ymm1, %ymm1
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
index 3fad53ef87838..2db57f4762428 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
@@ -134,28 +134,28 @@ define <64 x i8> @test_div7_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpackuswb %ymm3, %ymm5, %ymm3
; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm3
; AVX512F-NEXT: vpsrlw $2, %ymm1, %ymm1
-; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm3 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; AVX512F-NEXT: vpand %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512F-NEXT: vpxor %ymm5, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1
-; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm6
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm6 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512F-NEXT: vpxor %ymm6, %ymm1, %ymm1
+; AVX512F-NEXT: vpsubb %ymm3, %ymm1, %ymm1
; AVX512F-NEXT: vpsubb %ymm6, %ymm1, %ymm1
-; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm6 = ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15],ymm2[24],ymm0[24],ymm2[25],ymm0[25],ymm2[26],ymm0[26],ymm2[27],ymm0[27],ymm2[28],ymm0[28],ymm2[29],ymm0[29],ymm2[30],ymm0[30],ymm2[31],ymm0[31]
-; AVX512F-NEXT: vpmulhw %ymm4, %ymm6, %ymm6
-; AVX512F-NEXT: vpsrlw $8, %ymm6, %ymm6
+; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15],ymm2[24],ymm0[24],ymm2[25],ymm0[25],ymm2[26],ymm0[26],ymm2[27],ymm0[27],ymm2[28],ymm0[28],ymm2[29],ymm0[29],ymm2[30],ymm0[30],ymm2[31],ymm0[31]
+; AVX512F-NEXT: vpmulhw %ymm4, %ymm3, %ymm3
+; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm7 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[16],ymm0[16],ymm2[17],ymm0[17],ymm2[18],ymm0[18],ymm2[19],ymm0[19],ymm2[20],ymm0[20],ymm2[21],ymm0[21],ymm2[22],ymm0[22],ymm2[23],ymm0[23]
; AVX512F-NEXT: vpmulhw %ymm4, %ymm7, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpackuswb %ymm6, %ymm4, %ymm4
-; AVX512F-NEXT: vpaddb %ymm0, %ymm4, %ymm0
-; AVX512F-NEXT: vpsrlw $2, %ymm0, %ymm0
-; AVX512F-NEXT: vpand %ymm3, %ymm0, %ymm0
-; AVX512F-NEXT: vpxor %ymm5, %ymm0, %ymm0
-; AVX512F-NEXT: vpsubb %ymm5, %ymm0, %ymm0
+; AVX512F-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
+; AVX512F-NEXT: vpaddb %ymm0, %ymm3, %ymm0
; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm2
+; AVX512F-NEXT: vpsrlw $2, %ymm0, %ymm0
+; AVX512F-NEXT: vpand %ymm5, %ymm0, %ymm0
+; AVX512F-NEXT: vpxor %ymm6, %ymm0, %ymm0
; AVX512F-NEXT: vpsubb %ymm2, %ymm0, %ymm0
+; AVX512F-NEXT: vpsubb %ymm6, %ymm0, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512F-NEXT: retq
;
@@ -171,13 +171,13 @@ define <64 x i8> @test_div7_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0
-; AVX512BW-NEXT: vpsrlw $2, %zmm0, %zmm0
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm0 = zmm1 ^ (zmm0 & m32bcst)
-; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpsrlw $2, %zmm0, %zmm1
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm1 = zmm2 ^ (zmm1 & m32bcst)
; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
-; AVX512BW-NEXT: vpmovm2b %k0, %zmm1
-; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
+; AVX512BW-NEXT: vpsubb %zmm0, %zmm1, %zmm0
+; AVX512BW-NEXT: vpsubb %zmm2, %zmm0, %zmm0
; AVX512BW-NEXT: retq
%res = sdiv <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
ret <64 x i8> %res
@@ -206,13 +206,13 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsraw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [16,32,16,128,32,64,64,16,32,64,128,32,64,128,64,64]
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm2 = ymm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX512F-NEXT: vpsraw $8, %ymm2, %ymm2
-; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [64,16,32,32,16,16,16,16,16,64,32,128,64,32,32,32]
-; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
-; AVX512F-NEXT: vpackuswb %ymm4, %ymm2, %ymm2
-; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm1, %ymm4
-; AVX512F-NEXT: vpsubb %ymm4, %ymm2, %ymm2
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX512F-NEXT: vpsraw $8, %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5 # [64,16,32,32,16,16,16,16,16,64,32,128,64,32,32,32]
+; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
+; AVX512F-NEXT: vpackuswb %ymm4, %ymm5, %ymm4
+; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm1, %ymm2
+; AVX512F-NEXT: vpsubb %ymm2, %ymm4, %ymm2
; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
; AVX512F-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [0,137,0,129,0,121,0,57,0,27,0,103,0,49,0,187,0,133,0,129,0,125,0,121,0,59,0,57,0,111,0,27]
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
@@ -225,13 +225,13 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsraw $8, %ymm3, %ymm3
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [32,32,32,64,128,32,64,16,16,16,16,16,32,32,16,64]
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX512F-NEXT: vpsraw $8, %ymm0, %ymm0
-; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [64,64,128,64,32,128,64,32,16,64,64,32,128,16,32,16]
-; AVX512F-NEXT: vpsrlw $8, %ymm0, %ymm0
-; AVX512F-NEXT: vpackuswb %ymm3, %ymm0, %ymm0
-; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm1, %ymm0, %ymm0
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX512F-NEXT: vpsraw $8, %ymm4, %ymm4
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [64,64,128,64,32,128,64,32,16,64,64,32,128,16,32,16]
+; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
+; AVX512F-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
+; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm1, %ymm0
+; AVX512F-NEXT: vpsubb %ymm0, %ymm3, %ymm0
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512F-NEXT: retq
;
@@ -251,14 +251,14 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsraw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
-; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
-; AVX512BW-NEXT: vpsraw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
-; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
-; AVX512BW-NEXT: vpackuswb %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm2 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
+; AVX512BW-NEXT: vpsraw $8, %zmm2, %zmm2
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
+; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
+; AVX512BW-NEXT: vpackuswb %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
-; AVX512BW-NEXT: vpmovm2b %k0, %zmm1
-; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
+; AVX512BW-NEXT: vpsubb %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: retq
%res = sdiv <64 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
ret <64 x i8> %res
@@ -402,49 +402,49 @@ define <32 x i16> @test_rem7_32i16(<32 x i16> %a) nounwind {
define <64 x i8> @test_rem7_64i8(<64 x i8> %a) nounwind {
; AVX512F-LABEL: test_rem7_64i8:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm2
-; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15],ymm1[24],ymm2[24],ymm1[25],ymm2[25],ymm1[26],ymm2[26],ymm1[27],ymm2[27],ymm1[28],ymm2[28],ymm1[29],ymm2[29],ymm1[30],ymm2[30],ymm1[31],ymm2[31]
+; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15],ymm2[24],ymm1[24],ymm2[25],ymm1[25],ymm2[26],ymm1[26],ymm2[27],ymm1[27],ymm2[28],ymm1[28],ymm2[29],ymm1[29],ymm2[30],ymm1[30],ymm2[31],ymm1[31]
; AVX512F-NEXT: vpbroadcastw {{.*#+}} ymm4 = [0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147]
; AVX512F-NEXT: vpmulhw %ymm4, %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[16],ymm2[16],ymm1[17],ymm2[17],ymm1[18],ymm2[18],ymm1[19],ymm2[19],ymm1[20],ymm2[20],ymm1[21],ymm2[21],ymm1[22],ymm2[22],ymm1[23],ymm2[23]
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[16],ymm1[16],ymm2[17],ymm1[17],ymm2[18],ymm1[18],ymm2[19],ymm1[19],ymm2[20],ymm1[20],ymm2[21],ymm1[21],ymm2[22],ymm1[22],ymm2[23],ymm1[23]
; AVX512F-NEXT: vpmulhw %ymm4, %ymm5, %ymm5
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpackuswb %ymm3, %ymm5, %ymm3
-; AVX512F-NEXT: vpaddb %ymm2, %ymm3, %ymm3
+; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm3
+; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm2, %ymm5
; AVX512F-NEXT: vpsrlw $2, %ymm3, %ymm3
-; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; AVX512F-NEXT: vpand %ymm5, %ymm3, %ymm3
-; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm6 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512F-NEXT: vpxor %ymm6, %ymm3, %ymm3
-; AVX512F-NEXT: vpsubb %ymm6, %ymm3, %ymm3
-; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm7
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
+; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3
+; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm7 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512F-NEXT: vpxor %ymm7, %ymm3, %ymm3
+; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3
; AVX512F-NEXT: vpsubb %ymm7, %ymm3, %ymm3
-; AVX512F-NEXT: vpsllw $3, %ymm3, %ymm7
+; AVX512F-NEXT: vpsllw $3, %ymm3, %ymm5
; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm8 = [248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248]
-; AVX512F-NEXT: vpand %ymm7, %ymm8, %ymm7
-; AVX512F-NEXT: vpsubb %ymm7, %ymm3, %ymm3
-; AVX512F-NEXT: vpaddb %ymm3, %ymm2, %ymm2
-; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
+; AVX512F-NEXT: vpand %ymm5, %ymm8, %ymm5
+; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3
+; AVX512F-NEXT: vpaddb %ymm3, %ymm1, %ymm1
+; AVX512F-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15],ymm2[24],ymm0[24],ymm2[25],ymm0[25],ymm2[26],ymm0[26],ymm2[27],ymm0[27],ymm2[28],ymm0[28],ymm2[29],ymm0[29],ymm2[30],ymm0[30],ymm2[31],ymm0[31]
; AVX512F-NEXT: vpmulhw %ymm4, %ymm3, %ymm3
; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm7 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23]
-; AVX512F-NEXT: vpmulhw %ymm4, %ymm7, %ymm4
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[16],ymm0[16],ymm2[17],ymm0[17],ymm2[18],ymm0[18],ymm2[19],ymm0[19],ymm2[20],ymm0[20],ymm2[21],ymm0[21],ymm2[22],ymm0[22],ymm2[23],ymm0[23]
+; AVX512F-NEXT: vpmulhw %ymm4, %ymm5, %ymm4
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
; AVX512F-NEXT: vpaddb %ymm0, %ymm3, %ymm3
+; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm2, %ymm2
; AVX512F-NEXT: vpsrlw $2, %ymm3, %ymm3
-; AVX512F-NEXT: vpand %ymm5, %ymm3, %ymm3
-; AVX512F-NEXT: vpxor %ymm6, %ymm3, %ymm3
-; AVX512F-NEXT: vpsubb %ymm6, %ymm3, %ymm3
-; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm1, %ymm3, %ymm1
-; AVX512F-NEXT: vpsllw $3, %ymm1, %ymm3
+; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3
+; AVX512F-NEXT: vpxor %ymm7, %ymm3, %ymm3
+; AVX512F-NEXT: vpsubb %ymm2, %ymm3, %ymm2
+; AVX512F-NEXT: vpsubb %ymm7, %ymm2, %ymm2
+; AVX512F-NEXT: vpsllw $3, %ymm2, %ymm3
; AVX512F-NEXT: vpand %ymm3, %ymm8, %ymm3
-; AVX512F-NEXT: vpsubb %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm0
-; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX512F-NEXT: vpsubb %ymm3, %ymm2, %ymm2
+; AVX512F-NEXT: vpaddb %ymm2, %ymm0, %ymm0
+; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512F-NEXT: retq
;
; AVX512BW-LABEL: test_rem7_64i8:
@@ -459,13 +459,13 @@ define <64 x i8> @test_rem7_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm1
-; AVX512BW-NEXT: vpsrlw $2, %zmm1, %zmm1
-; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
-; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm1 = zmm2 ^ (zmm1 & m32bcst)
-; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
+; AVX512BW-NEXT: vpsrlw $2, %zmm1, %zmm2
+; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm2 = zmm3 ^ (zmm2 & m32bcst)
; AVX512BW-NEXT: vpmovb2m %zmm1, %k0
-; AVX512BW-NEXT: vpmovm2b %k0, %zmm2
-; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
+; AVX512BW-NEXT: vpmovm2b %k0, %zmm1
+; AVX512BW-NEXT: vpsubb %zmm1, %zmm2, %zmm1
+; AVX512BW-NEXT: vpsubb %zmm3, %zmm1, %zmm1
; AVX512BW-NEXT: vpsllw $3, %zmm1, %zmm2
; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
@@ -498,13 +498,13 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsraw $8, %ymm5, %ymm5
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5 # [16,32,16,128,32,64,64,16,32,64,128,32,64,128,64,64]
; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm3 = ymm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX512F-NEXT: vpsraw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [64,16,32,32,16,16,16,16,16,64,32,128,64,32,32,32]
-; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpackuswb %ymm5, %ymm3, %ymm3
-; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm5
-; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm6 = ymm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX512F-NEXT: vpsraw $8, %ymm6, %ymm6
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm6, %ymm6 # [64,16,32,32,16,16,16,16,16,64,32,128,64,32,32,32]
+; AVX512F-NEXT: vpsrlw $8, %ymm6, %ymm6
+; AVX512F-NEXT: vpackuswb %ymm5, %ymm6, %ymm5
+; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm3
+; AVX512F-NEXT: vpsubb %ymm3, %ymm5, %ymm3
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm5 # [38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
; AVX512F-NEXT: vpbroadcastw {{.*#+}} ymm6 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; AVX512F-NEXT: vpand %ymm6, %ymm5, %ymm5
@@ -524,13 +524,13 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512F-NEXT: vpsraw $8, %ymm4, %ymm4
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [32,32,32,64,128,32,64,16,16,16,16,16,32,32,16,64]
; AVX512F-NEXT: vpsrlw $8, %ymm4, %ymm4
-; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm3 = ymm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; AVX512F-NEXT: vpsraw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [64,64,128,64,32,128,64,32,16,64,64,32,128,16,32,16]
-; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm3
-; AVX512F-NEXT: vpackuswb %ymm4, %ymm3, %ymm3
+; AVX512F-NEXT: vpunpcklbw {{.*#+}} ymm5 = ymm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; AVX512F-NEXT: vpsraw $8, %ymm5, %ymm5
+; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm5, %ymm5 # [64,64,128,64,32,128,64,32,16,64,64,32,128,16,32,16]
+; AVX512F-NEXT: vpsrlw $8, %ymm5, %ymm5
+; AVX512F-NEXT: vpackuswb %ymm4, %ymm5, %ymm4
; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm1
-; AVX512F-NEXT: vpsubb %ymm1, %ymm3, %ymm1
+; AVX512F-NEXT: vpsubb %ymm1, %ymm4, %ymm1
; AVX512F-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm3 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38]
; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3
; AVX512F-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [0,8,0,10,0,12,0,14,0,16,0,18,0,20,0,22,0,24,0,26,0,28,0,30,0,32,0,34,0,36,0,38]
@@ -556,14 +556,14 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
; AVX512BW-NEXT: vpsraw $8, %zmm2, %zmm2
; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
-; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm1 = zmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
-; AVX512BW-NEXT: vpsraw $8, %zmm1, %zmm1
-; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
-; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
-; AVX512BW-NEXT: vpackuswb %zmm2, %zmm1, %zmm1
+; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm3 = zmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
+; AVX512BW-NEXT: vpsraw $8, %zmm3, %zmm3
+; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
+; AVX512BW-NEXT: vpsrlw $8, %zmm3, %zmm3
+; AVX512BW-NEXT: vpackuswb %zmm2, %zmm3, %zmm2
; AVX512BW-NEXT: vpmovb2m %zmm1, %k0
-; AVX512BW-NEXT: vpmovm2b %k0, %zmm2
-; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1
+; AVX512BW-NEXT: vpmovm2b %k0, %zmm1
+; AVX512BW-NEXT: vpsubb %zmm1, %zmm2, %zmm1
; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm2 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
; AVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,8,0,10,0,12,0,14,0,16,0,18,0,20,0,22,0,24,0,26,0,28,0,30,0,32,0,34,0,36,0,38,0,37,0,35,0,33,0,31,0,29,0,27,0,25,0,23,0,21,0,19,0,17,0,15,0,13,0,11,0,9,0,7]
; AVX512BW-NEXT: vpsllw $8, %zmm1, %zmm1
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