[llvm] [CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (PR #226556)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgpu12.50 -run-pass detect-dead-lanes -o - %s | FileCheck %s
+
+---
+name: reg_sequence_wide_source_in_narrow_slot
+tracksRegLiveness: true
+registers:
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arsenm wrote:

Should not have registers section 

https://github.com/llvm/llvm-project/pull/226556