[llvm] [CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (PR #226556)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgpu12.50 -run-pass detect-dead-lanes -o - %s | FileCheck %s
+
+---
+name: reg_sequence_wide_source_in_narrow_slot
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_16 }
+  - { id: 1, class: vgpr_32 }
+  - { id: 2, class: vgpr_32 }
+  - { id: 3, class: vgpr_32 }
+  - { id: 4, class: vgpr_32 }
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: reg_sequence_wide_source_in_narrow_slot
+    ; CHECK: S_NOP 0, implicit-def %0
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE %0, %subreg.lo16, undef %2:vgpr_32, %subreg.hi16
+    ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.lo16, undef %4:vgpr_32, %subreg.hi16
+    ; CHECK-NEXT: S_NOP 0, implicit [[REG_SEQUENCE1]]
+    S_NOP 0, implicit-def %0
+    %1 = REG_SEQUENCE %0, %subreg.lo16, undef %2, %subreg.hi16
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arsenm wrote:

This is malformed and should fail the verifier 

https://github.com/llvm/llvm-project/pull/226556