[llvm] [CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (PR #226556)

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@llvm/pr-subscribers-backend-amdgpu

Author: Changpeng Fang (changpeng)

<details>
<summary>Changes</summary>

isCrossCopy() returned early whenever source and destination shared a register class, treating the transfer as lane-for-lane. That is wrong when a REG_SEQUENCE names a subregister slot narrower than the source operand, e.g. a 32-bit vreg used as the lo16 piece of another 32-bit vreg. Only take the early exit when the two widths match; otherwise fall through to findCommonRegClass().

Fixes: ROCM-31212

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Full diff: https://github.com/llvm/llvm-project/pull/226556.diff


3 Files Affected:

- (modified) llvm/lib/CodeGen/DetectDeadLanes.cpp (+13-2) 
- (added) llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir (+24) 
- (added) llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll (+72) 


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</details>


https://github.com/llvm/llvm-project/pull/226556