[llvm] [CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (PR #226556)
Changpeng Fang via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 11:08:10 PDT 2026
https://github.com/changpeng created https://github.com/llvm/llvm-project/pull/226556
isCrossCopy() returned early whenever source and destination shared a register class, treating the transfer as lane-for-lane. That is wrong when a REG_SEQUENCE names a subregister slot narrower than the source operand, e.g. a 32-bit vreg used as the lo16 piece of another 32-bit vreg. Only take the early exit when the two widths match; otherwise fall through to findCommonRegClass().
Fixes: ROCM-31212
>From f3671c432e2bb3ac1df845be47d4ebcf907be3bd Mon Sep 17 00:00:00 2001
From: Changpeng Fang <changpeng.fang at amd.com>
Date: Fri, 25 Sep 2026 10:49:11 -0700
Subject: [PATCH] [CodeGen] Fix DetectDeadLanes for same-class copies with
mismatched widths
isCrossCopy() returned early whenever source and destination shared a
register class, treating the transfer as lane-for-lane. That is wrong
when a REG_SEQUENCE names a subregister slot narrower than the source
operand, e.g. a 32-bit vreg used as the lo16 piece of another 32-bit
vreg. Only take the early exit when the two widths match; otherwise fall
through to findCommonRegClass().
Fixes: ROCM-31212
---
llvm/lib/CodeGen/DetectDeadLanes.cpp | 15 +++-
...ct-dead-lanes-reg-sequence-narrow-slot.mir | 24 +++++++
.../AMDGPU/true16-uniform-f16-phi-copysign.ll | 72 +++++++++++++++++++
3 files changed, 109 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp
index 79104760b7b75..7a2fc38c1aa58 100644
--- a/llvm/lib/CodeGen/DetectDeadLanes.cpp
+++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp
@@ -72,8 +72,6 @@ static bool isCrossCopy(const MachineRegisterInfo &MRI,
assert(lowersToCopies(MI));
Register SrcReg = MO.getReg();
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
- if (DstRC == SrcRC)
- return false;
unsigned SrcSubIdx = MO.getSubReg();
@@ -95,6 +93,19 @@ static bool isCrossCopy(const MachineRegisterInfo &MRI,
}
}
+ if (DstRC == SrcRC) {
+ // Identical register classes only give a lane-for-lane transfer if the
+ // source operand and the destination subregister slot are the same width.
+ TypeSize SrcSize = SrcSubIdx
+ ? TypeSize::getFixed(TRI.getSubRegIdxSize(SrcSubIdx))
+ : TRI.getRegSizeInBits(*SrcRC);
+ TypeSize DstSize = DstSubIdx
+ ? TypeSize::getFixed(TRI.getSubRegIdxSize(DstSubIdx))
+ : TRI.getRegSizeInBits(*DstRC);
+ if (SrcSize == DstSize)
+ return false;
+ }
+
return !TRI.findCommonRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx);
}
diff --git a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
new file mode 100644
index 0000000000000..d474bcb70ea39
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgpu12.50 -run-pass detect-dead-lanes -o - %s | FileCheck %s
+
+---
+name: reg_sequence_wide_source_in_narrow_slot
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vgpr_16 }
+ - { id: 1, class: vgpr_32 }
+ - { id: 2, class: vgpr_32 }
+ - { id: 3, class: vgpr_32 }
+ - { id: 4, class: vgpr_32 }
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: reg_sequence_wide_source_in_narrow_slot
+ ; CHECK: S_NOP 0, implicit-def %0
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE %0, %subreg.lo16, undef %2:vgpr_32, %subreg.hi16
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.lo16, undef %4:vgpr_32, %subreg.hi16
+ ; CHECK-NEXT: S_NOP 0, implicit [[REG_SEQUENCE1]]
+ S_NOP 0, implicit-def %0
+ %1 = REG_SEQUENCE %0, %subreg.lo16, undef %2, %subreg.hi16
+ %3 = REG_SEQUENCE %1, %subreg.lo16, undef %4, %subreg.hi16
+ S_NOP 0, implicit %3
+...
diff --git a/llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll b/llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
new file mode 100644
index 0000000000000..b056d718fff87
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
@@ -0,0 +1,72 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -mattr=+real-true16 < %s | FileCheck %s
+
+; An f16 value merged by a PHI across a wave-uniform branch is held in a 32-bit
+; register, and the true16 fcopysign pattern feeds it to a REG_SEQUENCE lo16
+; slot. DetectDeadLanes used to treat that as a lane-for-lane transfer and mark
+; the value produced in %big dead, deleting the whole block.
+
+define amdgpu_kernel void @uniform_f16_phi_copysign(half %x, ptr addrspace(1) %out) {
+; CHECK-LABEL: uniform_f16_phi_copysign:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; CHECK-NEXT: s_mov_b64 s[64:65], 0
+; CHECK-NEXT: v_nop
+; CHECK-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; CHECK-NEXT: s_load_b32 s0, s[4:5], 0x0 nv
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: s_cmp_nle_f16 s0, 0x3800
+; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
+; CHECK-NEXT: ; %bb.1: ; %small
+; CHECK-NEXT: s_mul_f16 s1, s0, s0
+; CHECK-NEXT: s_mov_b32 s2, 0
+; CHECK-NEXT: s_branch .LBB0_3
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: s_mov_b32 s2, -1
+; CHECK-NEXT: ; implicit-def: $sgpr1
+; CHECK-NEXT: .LBB0_3: ; %Flow
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; CHECK-NEXT: s_and_b32 s2, s2, exec_lo
+; CHECK-NEXT: s_cselect_b32 s2, 1, 0
+; CHECK-NEXT: s_cmp_lg_u32 s2, 1
+; CHECK-NEXT: s_cbranch_scc1 .LBB0_5
+; CHECK-NEXT: ; %bb.4: ; %big
+; CHECK-NEXT: s_cvt_f32_f16 s1, s0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0.5
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
+; CHECK-NEXT: v_s_sqrt_f32 s1, s1
+; CHECK-NEXT: v_nop
+; CHECK-NEXT: v_fma_mixlo_f16 v0, s1, s0, v0 op_sel_hi:[0,1,0]
+; CHECK-NEXT: s_branch .LBB0_6
+; CHECK-NEXT: .LBB0_5:
+; CHECK-NEXT: v_mov_b32_e32 v0, s1
+; CHECK-NEXT: .LBB0_6: ; %exit
+; CHECK-NEXT: s_load_b64 s[2:3], s[4:5], 0x8 nv
+; CHECK-NEXT: v_mov_b16_e32 v1.l, s0
+; CHECK-NEXT: v_mov_b32_e32 v2, 0
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; CHECK-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: global_store_b16 v2, v0, s[2:3]
+; CHECK-NEXT: s_endpgm
+entry:
+ %c = fcmp ugt half %x, 0xH3800
+ br i1 %c, label %big, label %small
+
+small:
+ %s = fmul half %x, %x
+ br label %exit
+
+big:
+ %e = fpext half %x to float
+ %q = call float @llvm.amdgcn.sqrt.f32(float %e)
+ %m = call float @llvm.fmuladd.f32(float %q, float %e, float 5.000000e-01)
+ %t = fptrunc float %m to half
+ br label %exit
+
+exit:
+ %p = phi half [ %s, %small ], [ %t, %big ]
+ %r = call half @llvm.copysign.f16(half %p, half %x)
+ store half %r, ptr addrspace(1) %out
+ ret void
+}
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