[llvm] [MachineCSE] Enhance MachineCSE simple PRE to find common subexpressi… (PR #129860)

[via llvm-commits]

Jinlock9 wrote:

@arsenm @emelliu I’ve opened draft PR #226510 implementing eager CSE during PRE, with end-to-end RISC-V tests that survive the O2 IR pipeline.

RISC-V CodeGen tests pass with assertions enabled; broader validation is pending. Physical-register operands remain excluded, so the original AMDGPU $exec case is not yet addressed.

Could you review the approach, especially correctness and PREMap updates? Thanks!

https://github.com/llvm/llvm-project/pull/129860