[llvm] [AArch64] Remove variable only used in assert (PR #226433)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Gaëtan Bossu (gbossu)

<details>
<summary>Changes</summary>

This caused a buildbot failure after the variable was introduced in https://github.com/llvm/llvm-project/pull/208212

---
Full diff: https://github.com/llvm/llvm-project/pull/226433.diff


1 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+1-2) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 395d586bd89eb6..101a3961779fe9 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17854,8 +17854,7 @@ SDValue AArch64TargetLowering::LowerVECTOR_REPEAT(SDValue Op,
   SDLoc DL(Op);
   SDValue Src = Op.getOperand(0);
   EVT VT = Op.getValueType();
-  EVT SrcVT = Src.getValueType();
-  assert(SrcVT.is64BitVector() && "Expected 64bit source!");
+  assert(Src.getValueType().is64BitVector() && "Expected 64bit source!");
 
   // Repeat into a packed container before extracting the low lanes, which
   // places the result elements at the spacing required by the unpacked type.

``````````

</details>


https://github.com/llvm/llvm-project/pull/226433