[llvm] [DAGCombiner] fold `(sext_inreg (freeze (extload x)))` -> `(freeze (sextload x))` (PR #226208)

[via llvm-commits]

https://github.com/VachanVY updated https://github.com/llvm/llvm-project/pull/226208

>From fcf0e91c3f07d15bdce0175b80f833f477d8ebc8 Mon Sep 17 00:00:00 2001
From: Vachan V Y <vachanvy05 at gmail.com>
Date: Thu, 24 Sep 2026 21:02:21 +0530
Subject: [PATCH] [DAGCombiner] fold `(sext_inreg (freeze (extload x)))` ->
 `(freeze (sextload x))`

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 28a8cb9409648..d51872d854078 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17371,21 +17371,26 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
       }
   }
 
+  bool Frozen = N0.getOpcode() == ISD::FREEZE && N0.hasOneUse();
+
   // fold (sext_inreg (extload x)) -> (sextload x)
+  // fold (sext_inreg (freeze (extload x))) -> (freeze (sextload x))
   // If sextload is not supported by target, we can only do the combine when
   // load has one use. Doing otherwise can block folding the extload with other
   // extends that the target does support.
-  if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
-    auto *LN0 = cast<LoadSDNode>(N0);
+  SDValue LoadOp = Frozen ? N0.getOperand(0) : N0;
+  if (ISD::isEXTLoad(LoadOp.getNode()) &&
+      ISD::isUNINDEXEDLoad(LoadOp.getNode())) {
+    auto *LN0 = cast<LoadSDNode>(LoadOp);
     if (ExtVT == LN0->getMemoryVT() &&
-        ((!LegalOperations && LN0->isSimple() && N0.hasOneUse()) ||
+        ((!LegalOperations && LN0->isSimple() && LoadOp.hasOneUse()) ||
          TLI.isLoadLegal(VT, ExtVT, LN0->getAlign(), LN0->getAddressSpace(),
                          ISD::SEXTLOAD, false))) {
       SDValue ExtLoad =
           DAG.getExtLoad(ISD::SEXTLOAD, DL, VT, LN0->getChain(),
                          LN0->getBasePtr(), ExtVT, LN0->getMemOperand());
-      CombineTo(N, ExtLoad);
-      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
+      CombineTo(N, Frozen ? N0 : ExtLoad);
+      CombineTo(LN0, ExtLoad, ExtLoad.getValue(1));
       AddToWorklist(ExtLoad.getNode());
       return SDValue(N, 0); // Return N so it doesn't get rechecked!
     }
@@ -17410,7 +17415,6 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
 
   // fold (sext_inreg (masked_load x)) -> (sext_masked_load x)
   // ignore it if the masked load is already sign extended
-  bool Frozen = N0.getOpcode() == ISD::FREEZE && N0.hasOneUse();
   if (auto *Ld = dyn_cast<MaskedLoadSDNode>(Frozen ? N0.getOperand(0) : N0)) {
     if (ExtVT == Ld->getMemoryVT() && Ld->hasNUsesOfValue(1, 0) &&
         Ld->getExtensionType() != ISD::LoadExtType::NON_EXTLOAD &&