[llvm] [DAGCombiner] fold `(sext_inreg (freeze (extload x)))` -> `(freeze (sextload x))` (PR #226208)
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Thu Sep 24 08:45:54 PDT 2026
VachanVY wrote:
<details>
After implementing the fold in https://github.com/llvm/llvm-project/pull/218454
```llvm
Legalized selection DAG: %bb.0 'test:'
SelectionDAG has 13 nodes:
t0: ch,glue = EntryToken
t17: i16 = xor t14, t16
t18: i16 = sub t17, t16
t12: ch,glue = CopyToReg t0, Register:i16 $ax, t18
t3: i16,ch = load<(load (s16) from %fixed-stack.0, align 4)> t0, FrameIndex:i32<-1>, poison:i32
t14: i16 = freeze t3
t16: i16 = sra t14, Constant:i8<15>
t13: ch = X86ISD::RET_GLUE t12, TargetConstant:i32<0>, Register:i16 $ax, t12:1
Optimized legalized selection DAG: %bb.0 'test:'
SelectionDAG has 16 nodes:
t0: ch,glue = EntryToken
t24: i32 = xor t27, t31
t21: i32 = sub t24, t31
t22: i16 = truncate t21
t12: ch,glue = CopyToReg t0, Register:i16 $ax, t22
///// ====> This Patch folds : (sext_inreg (freeze (extload x))) -> (freeze (sextload x)) //////////////
t26: i32,ch = load<(load (s16) from %fixed-stack.0, align 4), anyext from i16> t0, FrameIndex:i32<-1>, poison:i32
t27: i32 = freeze t26
t30: i32 = sign_extend_inreg t27, ValueType:ch:i16
t31: i32 = sra t30, Constant:i8<15>
t13: ch = X86ISD::RET_GLUE t12, TargetConstant:i32<0>, Register:i16 $ax, t12:1
...
===== Instruction selection begins: %bb.0 ''
...
ISEL: Starting selection on root node: t30: i32 = sign_extend_inreg t27, ValueType:ch:i16
ISEL: Starting pattern match
Initial Opcode index to 130443
TypeSwitch[i32] from 130450 to 130453
Created node: t36: i16 = EXTRACT_SUBREG t27, TargetConstant:i32<4>
Morphed node: t30: i32 = MOVSX32rr16 t36
ISEL: Match complete!
ISEL: Starting selection on root node: t27: i32 = freeze t26
ISEL: Starting selection on root node: t26: i32,ch = load<(load (s16) from %fixed-stack.0, align 4), anyext from i16> t0, FrameIndex:i32<-1>, poison:i32
ISEL: Starting pattern match
Initial Opcode index to 116728
Match failed at index 116736
Continuing at 116749
Match failed at index 116752
Continuing at 116765
Morphed node: t26: i32,ch = MOV32rm<Mem:(load (s16) from %fixed-stack.0, align 4)> TargetFrameIndex:i32<-1>, TargetConstant:i8<1>, Register:i32 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
ISEL: Match complete!
...
```
</details>
https://github.com/llvm/llvm-project/pull/226208
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