[llvm] [DAG] SimplifyMultipleUseDemandedBits - simplify ISD::SCALAR_TO_VECTOR to ISD::POISON if we don't demand 0th element (PR #225530)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon auto_merge_enabled https://github.com/llvm/llvm-project/pull/225530