[llvm] [TableGen] Assign LaneBitmask bits in a less surprising order (PR #225809)

[Guo Chen via llvm-commits]

================
@@ -529,97 +529,122 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX11-TRUE16-NEXT:    s_clause 0x1
----------------
broxigarchen wrote:

I see Thanks

https://github.com/llvm/llvm-project/pull/225809