[llvm] [TableGen] Assign LaneBitmask bits in a less surprising order (PR #225809)

[Jay Foad via llvm-commits]

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@@ -86,7 +86,7 @@ BT::BitMask HexagonEvaluator::mask(Register Reg, unsigned Sub) const {
   bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
   switch (ID) {
     case Hexagon::DoubleRegsRegClassID:
-    case Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID:
+    case Hexagon::DoubleRegs_with_isub_lo_in_IntRegsLow8RegClassID:
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jayfoad wrote:

#226110 would avoid the need for any changes in this file.

https://github.com/llvm/llvm-project/pull/225809