[llvm] [TableGen] Assign LaneBitmask bits in a less surprising order (PR #225809)

[Sander de Smalen via llvm-commits]

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@@ -1457,6 +1472,15 @@ bool AArch64RegisterInfo::shouldCoalesce(
   MachineFunction &MF = *MI->getMF();
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
+  // The SVE Z register tuples overlap the NEON Q and D tuples, so both ZPR2 and
+  // QQ (for example) are valid answers when the coalescer asks for a register
+  // class covering a pair of D registers. If it picks an SVE class on a
+  // subtarget without SVE then the register allocator has no way to spill or
+  // reload the result, so reject the coalesce and leave the copy alone.
+  if (NewRC && isSVERegClass(NewRC) &&
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sdesmalen-arm wrote:

Does this need an additional check that `!isSVERegClass(SrcRC)`?

https://github.com/llvm/llvm-project/pull/225809