[llvm] [TableGen] Assign LaneBitmask bits in a less surprising order (PR #225809)

[Sander de Smalen via llvm-commits]

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@@ -1449,6 +1449,21 @@ unsigned AArch64RegisterInfo::getLocalAddressRegister(
   return getFrameRegister(MF);
 }
 
+/// Return true if \p RC is one of the SVE register classes that can only be
+/// spilled and reloaded using SVE instructions. This must be kept in sync with
+/// the classes handled by AArch64InstrInfo::storeRegToStackSlot() and
+/// loadRegFromStackSlot().
+static bool isSVERegClass(const TargetRegisterClass *RC) {
+  return AArch64::ZPRRegClass.hasSubClassEq(RC) ||
+         AArch64::ZPR2RegClass.hasSubClassEq(RC) ||
+         AArch64::ZPR3RegClass.hasSubClassEq(RC) ||
+         AArch64::ZPR4RegClass.hasSubClassEq(RC) ||
+         AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC) ||
+         AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC) ||
+         AArch64::PPRRegClass.hasSubClassEq(RC) ||
+         AArch64::PPR2RegClass.hasSubClassEq(RC);
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sdesmalen-arm wrote:

This list is missing the `AArch64::PNRRegClass`.

Having a static list like this is a bit brittle when adding new regclasses in the future, specifically the tuples. For tuples, can we get the register class for the zsub/psub subreg index and test if that register class is either one of PPR/ZPR/PNR ?

https://github.com/llvm/llvm-project/pull/225809