[llvm] [TableGen] Assign LaneBitmask bits in a less surprising order (PR #225809)

[Jay Foad via llvm-commits]

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@@ -529,97 +529,122 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX11-TRUE16-NEXT:    s_clause 0x1
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jayfoad wrote:

See the description: I believe these codegen changes are due to the way DetectDeadLanes handles illegal REG_SEQUENCE instructions whose operand widths do not match the width of the corresponding subreg.

https://github.com/llvm/llvm-project/pull/225809