[llvm] fbe07e2 - [AMDGPU] Remove unneeded code from EmitInstrWithCustomInserter. NFC. (#225919)

via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 23 22:24:15 PDT 2026


Author: Jay Foad
Date: 2026-09-24T06:24:08+01:00
New Revision: fbe07e2e386265a5ee77f57ade0410e96736b487

URL: https://github.com/llvm/llvm-project/commit/fbe07e2e386265a5ee77f57ade0410e96736b487
DIFF: https://github.com/llvm/llvm-project/commit/fbe07e2e386265a5ee77f57ade0410e96736b487.diff

LOG: [AMDGPU] Remove unneeded code from EmitInstrWithCustomInserter. NFC. (#225919)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 28b1016d9141c..e47dd0e788796 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -7324,35 +7324,9 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   }
   case AMDGPU::V_ADD_CO_U32_e32:
   case AMDGPU::V_SUB_CO_U32_e32:
-  case AMDGPU::V_SUBREV_CO_U32_e32: {
-    // TODO: Define distinct V_*_I32_Pseudo instructions instead.
-    unsigned Opc = MI.getOpcode();
-
-    bool NeedClampOperand = false;
-    if (TII->pseudoToMCOpcode(Opc) == -1) {
-      Opc = AMDGPU::getVOPe64(Opc);
-      NeedClampOperand = true;
-    }
-
-    bool VCCDead = MI.getOperand(3).isDead();
-
-    auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
-    bool IsVOP3 = TII->isVOP3(*I);
-    if (IsVOP3)
-      I.addReg(TRI->getVCC(), RegState::Define | getDeadRegState(VCCDead));
-
-    I.add(MI.getOperand(1)).add(MI.getOperand(2));
-    if (NeedClampOperand)
-      I.addImm(0); // clamp bit for e64 encoding
-
-    if (!IsVOP3 && VCCDead)
-      I.setOperandDead(3);
-
-    TII->legalizeOperands(*I);
-
-    MI.eraseFromParent();
+  case AMDGPU::V_SUBREV_CO_U32_e32:
+    // TODO: Remove usesCustomInserter from these instructions.
     return BB;
-  }
   case AMDGPU::V_ADDC_U32_e32:
   case AMDGPU::V_SUBB_U32_e32:
   case AMDGPU::V_SUBBREV_U32_e32:


        


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