[llvm] [DAGCombiner] Fix commutativity in the (X + Y) + X --> Y + (X + X) fold. (PR #226021)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 22:09:08 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-llvm-selectiondag
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
The check didn't support the commuted form of the inner add, Y + X.
The "m_Add(m_Value(X), m_Value(Y)" match would never check the commuted form since it always matches 2 values.
We need to match the outer X first then use m_Deferred for inner add match.
This affects a lot more tests than the original patch and I'm not sure they are improvements. I just happened to notice the incorrect pattern match usage and wanted to share.
---
Patch is 44.73 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/226021.diff
17 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+6-4)
- (modified) llvm/test/CodeGen/AArch64/pr72777.ll (+3-2)
- (modified) llvm/test/CodeGen/AArch64/reassocmls.ll (+3-3)
- (modified) llvm/test/CodeGen/AArch64/u128-square.ll (+3-2)
- (modified) llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll (+25-65)
- (modified) llvm/test/CodeGen/AMDGPU/idot4u.ll (+3-3)
- (modified) llvm/test/CodeGen/ARM/demanded-bits-and.ll (+5-4)
- (modified) llvm/test/CodeGen/RISCV/rvp-mul-parts-acc-fold.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll (+74-74)
- (modified) llvm/test/CodeGen/X86/lea-opt-cse4.ll (+24-26)
- (modified) llvm/test/CodeGen/X86/masked_gather.ll (+12-12)
- (modified) llvm/test/CodeGen/X86/mul-constant-i16.ll (+11-11)
- (modified) llvm/test/CodeGen/X86/mul-constant-i32.ll (+14-14)
- (modified) llvm/test/CodeGen/X86/mul-constant-i64.ll (+7-12)
- (modified) llvm/test/CodeGen/X86/mul-constant-i8.ll (+3-3)
- (modified) llvm/test/CodeGen/X86/mul-constant-result.ll (+74-72)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e86514aed9410..a2fc215def9e8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3024,10 +3024,12 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) {
// (X + Y) + X --> Y + (X + X)
SDValue X, Y, InnerAdd;
- if (sd_match(
- N, m_Add(m_OneUse(m_Value(InnerAdd, m_Add(m_Value(X), m_Value(Y)))),
- m_Deferred(X)))) {
- if (X != Y) {
+ if (sd_match(N, m_Add(m_Value(X),
+ m_OneUse(m_Value(
+ InnerAdd, m_Add(m_Deferred(X), m_Value(Y))))))) {
+ // X may be an opaque constant that will get reassociated back outside
+ // which will cause an infinite loop.
+ if (X != Y && !isa<ConstantSDNode>(X)) {
// Redistribute shared NUW flag.
// TODO: If NSW+NUW occurs on both adds, that can be redistributed too.
SDNodeFlags NewFlags =
diff --git a/llvm/test/CodeGen/AArch64/pr72777.ll b/llvm/test/CodeGen/AArch64/pr72777.ll
index 27ba1302ffd0c..fa9f82f8c93c2 100644
--- a/llvm/test/CodeGen/AArch64/pr72777.ll
+++ b/llvm/test/CodeGen/AArch64/pr72777.ll
@@ -5,10 +5,11 @@ define i64 @f(i64 %0, i64 %1) {
; CHECK-LABEL: f:
; CHECK: // %bb.0:
; CHECK-NEXT: orr x8, x1, #0x1
+; CHECK-NEXT: add x9, x0, x0
; CHECK-NEXT: mov x10, #-9223372036854775808 // =0x8000000000000000
-; CHECK-NEXT: adds x8, x8, x0, lsl #1
-; CHECK-NEXT: cinv x10, x10, pl
+; CHECK-NEXT: adds x8, x8, x9
; CHECK-NEXT: lsl x9, x8, #1
+; CHECK-NEXT: cinv x10, x10, pl
; CHECK-NEXT: cmp x8, x9, asr #1
; CHECK-NEXT: csel x0, x10, x9, ne
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/reassocmls.ll b/llvm/test/CodeGen/AArch64/reassocmls.ll
index ca4393b0b8387..e815fa7caca82 100644
--- a/llvm/test/CodeGen/AArch64/reassocmls.ll
+++ b/llvm/test/CodeGen/AArch64/reassocmls.ll
@@ -176,9 +176,9 @@ define i64 @mla_i64_uses(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {
define i64 @mla_i64_mul(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {
; CHECK-SD-LABEL: mla_i64_mul:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: mul x8, x4, x3
-; CHECK-SD-NEXT: mul x9, x2, x1
-; CHECK-SD-NEXT: add x0, x8, x9, lsl #1
+; CHECK-SD-NEXT: mul x8, x2, x1
+; CHECK-SD-NEXT: add x8, x8, x8
+; CHECK-SD-NEXT: madd x0, x4, x3, x8
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: mla_i64_mul:
diff --git a/llvm/test/CodeGen/AArch64/u128-square.ll b/llvm/test/CodeGen/AArch64/u128-square.ll
index 9e8504c49ad48..d0fa64070b2f7 100644
--- a/llvm/test/CodeGen/AArch64/u128-square.ll
+++ b/llvm/test/CodeGen/AArch64/u128-square.ll
@@ -7,9 +7,10 @@ define i128 @square(i128 %x) {
; CHECK-NEXT: mul x8, x0, x1
; CHECK-NEXT: umulh x9, x0, x0
; CHECK-NEXT: mul x0, x0, x0
-; CHECK-NEXT: add x1, x9, x8, lsl #1
+; CHECK-NEXT: add x8, x8, x8
+; CHECK-NEXT: add x1, x9, x8
; CHECK-NEXT: ret
entry:
%mul = mul i128 %x, %x
ret i128 %mul
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll b/llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll
index 3758a5cace7ff..c356e8b2b1b6b 100644
--- a/llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll
+++ b/llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll
@@ -27,77 +27,37 @@ define amdgpu_kernel void @fence_barrier_latency_test(ptr addrspace(1) %global_p
; CHECK-NEXT: ds_load_b128 v[20:23], v28 offset:160
; CHECK-NEXT: ds_load_b128 v[24:27], v28 offset:192
; CHECK-NEXT: ds_load_b128 v[28:31], v28 offset:224
-; CHECK-NEXT: s_wait_dscnt 0x7
-; CHECK-NEXT: v_readfirstlane_b32 s4, v3
; CHECK-NEXT: s_wait_dscnt 0x6
-; CHECK-NEXT: v_readfirstlane_b32 s5, v7
-; CHECK-NEXT: v_readfirstlane_b32 s6, v6
-; CHECK-NEXT: v_readfirstlane_b32 s7, v2
-; CHECK-NEXT: v_readfirstlane_b32 s18, v5
-; CHECK-NEXT: v_readfirstlane_b32 s19, v1
-; CHECK-NEXT: v_readfirstlane_b32 s20, v4
-; CHECK-NEXT: v_readfirstlane_b32 s21, v0
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
+; CHECK-NEXT: v_dual_add_nc_u32 v3, v3, v7 :: v_dual_add_nc_u32 v2, v2, v6
+; CHECK-NEXT: v_dual_add_nc_u32 v1, v1, v5 :: v_dual_add_nc_u32 v0, v0, v4
+; CHECK-NEXT: v_dual_add_nc_u32 v4, v4, v4 :: v_dual_add_nc_u32 v5, v5, v5
+; CHECK-NEXT: v_dual_add_nc_u32 v6, v6, v6 :: v_dual_add_nc_u32 v7, v7, v7
+; CHECK-NEXT: s_wait_dscnt 0x4
+; CHECK-NEXT: v_dual_add_nc_u32 v11, v11, v15 :: v_dual_add_nc_u32 v0, v4, v0
+; CHECK-NEXT: v_dual_add_nc_u32 v1, v5, v1 :: v_dual_add_nc_u32 v2, v6, v2
+; CHECK-NEXT: v_dual_add_nc_u32 v3, v7, v3 :: v_dual_add_nc_u32 v6, v6, v6
; CHECK-NEXT: s_wait_dscnt 0x0
; CHECK-NEXT: s_barrier_signal -1
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
+; CHECK-NEXT: v_dual_add_nc_u32 v7, v7, v7 :: v_dual_add_nc_u32 v5, v5, v5
+; CHECK-NEXT: v_dual_add_nc_u32 v4, v4, v4 :: v_dual_add_nc_u32 v10, v10, v14
+; CHECK-NEXT: v_dual_add_nc_u32 v6, v6, v6 :: v_dual_add_nc_u32 v7, v7, v7
+; CHECK-NEXT: v_dual_add_nc_u32 v5, v5, v5 :: v_dual_add_nc_u32 v4, v4, v4
+; CHECK-NEXT: v_dual_add_nc_u32 v9, v9, v13 :: v_dual_add_nc_u32 v2, v2, v6
+; CHECK-NEXT: v_dual_add_nc_u32 v3, v3, v7 :: v_dual_add_nc_u32 v1, v1, v5
+; CHECK-NEXT: v_dual_add_nc_u32 v0, v0, v4 :: v_dual_add_nc_u32 v5, v19, v23
+; CHECK-NEXT: v_dual_add_nc_u32 v4, v8, v12 :: v_dual_add_nc_u32 v6, v18, v22
; CHECK-NEXT: s_barrier_wait -1
; CHECK-NEXT: s_wait_tensorcnt 0xa
; CHECK-NEXT: tensor_load_to_lds s[0:3], s[8:15]
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: v_dual_add_nc_u32 v0, v11, v15 :: v_dual_add_nc_u32 v1, v10, v14
-; CHECK-NEXT: v_dual_add_nc_u32 v2, v9, v13 :: v_dual_add_nc_u32 v3, v8, v12
-; CHECK-NEXT: v_dual_add_nc_u32 v4, v19, v23 :: v_dual_add_nc_u32 v5, v18, v22
-; CHECK-NEXT: v_dual_add_nc_u32 v6, v17, v21 :: v_dual_add_nc_u32 v7, v16, v20
-; CHECK-NEXT: v_dual_add_nc_u32 v8, v27, v31 :: v_dual_add_nc_u32 v9, v26, v30
-; CHECK-NEXT: v_dual_add_nc_u32 v10, v25, v29 :: v_dual_add_nc_u32 v11, v24, v28
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s7, s7, s6
-; CHECK-NEXT: s_add_co_i32 s4, s4, s5
-; CHECK-NEXT: s_add_co_i32 s19, s19, s18
-; CHECK-NEXT: s_add_co_i32 s21, s21, s20
-; CHECK-NEXT: v_dual_add_nc_u32 v2, s19, v2 :: v_dual_add_nc_u32 v3, s21, v3
-; CHECK-NEXT: v_dual_add_nc_u32 v12, s7, v1 :: v_dual_add_nc_u32 v13, s4, v0
-; CHECK-NEXT: v_dual_add_nc_u32 v0, v7, v11 :: v_dual_add_nc_u32 v1, v6, v10
-; CHECK-NEXT: v_dual_add_nc_u32 v5, v5, v9 :: v_dual_add_nc_u32 v4, v4, v8
-; CHECK-NEXT: v_dual_add_nc_u32 v0, v3, v0 :: v_dual_add_nc_u32 v1, v2, v1
-; CHECK-NEXT: v_dual_add_nc_u32 v2, v12, v5 :: v_dual_add_nc_u32 v3, v13, v4
+; CHECK-NEXT: v_dual_add_nc_u32 v7, v17, v21 :: v_dual_add_nc_u32 v8, v16, v20
+; CHECK-NEXT: v_dual_add_nc_u32 v12, v27, v31 :: v_dual_add_nc_u32 v13, v26, v30
+; CHECK-NEXT: v_dual_add_nc_u32 v14, v25, v29 :: v_dual_add_nc_u32 v15, v24, v28
+; CHECK-NEXT: v_dual_add_nc_u32 v0, v0, v4 :: v_dual_add_nc_u32 v1, v1, v9
+; CHECK-NEXT: v_dual_add_nc_u32 v2, v2, v10 :: v_dual_add_nc_u32 v3, v3, v11
+; CHECK-NEXT: v_dual_add_nc_u32 v4, v8, v15 :: v_dual_add_nc_u32 v7, v7, v14
+; CHECK-NEXT: v_dual_add_nc_u32 v6, v6, v13 :: v_dual_add_nc_u32 v5, v5, v12
+; CHECK-NEXT: v_dual_add_nc_u32 v0, v0, v4 :: v_dual_add_nc_u32 v1, v1, v7
+; CHECK-NEXT: v_dual_add_nc_u32 v2, v2, v6 :: v_dual_add_nc_u32 v3, v3, v5
; CHECK-NEXT: global_store_b128 v32, v[0:3], s[16:17]
; CHECK-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll
index 3f2c70790fd56..434cce09d357a 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll
@@ -1383,7 +1383,7 @@ define amdgpu_kernel void @udot4_multiuse_add1(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_mul_u32_u24_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, s0
-; GFX9-DL-NEXT: v_add3_u32 v1, s1, v3, v1
+; GFX9-DL-NEXT: v_add3_u32 v1, v3, s1, v1
; GFX9-DL-NEXT: global_store_dword v0, v1, s[6:7]
; GFX9-DL-NEXT: s_endpgm
;
@@ -1405,7 +1405,7 @@ define amdgpu_kernel void @udot4_multiuse_add1(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, s0
; GFX10-DL-NEXT: s_add_i32 s0, s0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-DL-NEXT: v_add3_u32 v0, s0, v0, v1
+; GFX10-DL-NEXT: v_add3_u32 v0, v0, s0, v1
; GFX10-DL-NEXT: global_store_dword v2, v0, s[6:7]
; GFX10-DL-NEXT: s_endpgm
;
@@ -1431,7 +1431,7 @@ define amdgpu_kernel void @udot4_multiuse_add1(ptr addrspace(1) %src1,
; GFX11-DL-NEXT: v_mov_b32_e32 v1, 0
; GFX11-DL-NEXT: v_mul_u32_u24_e32 v2, v2, v3
; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-NEXT: v_add3_u32 v0, s0, v2, v0
+; GFX11-DL-NEXT: v_add3_u32 v0, v2, s0, v0
; GFX11-DL-NEXT: global_store_b32 v1, v0, s[4:5]
; GFX11-DL-NEXT: s_endpgm
ptr addrspace(1) %src2,
diff --git a/llvm/test/CodeGen/ARM/demanded-bits-and.ll b/llvm/test/CodeGen/ARM/demanded-bits-and.ll
index ddfff681f30f6..16706d6b794a7 100644
--- a/llvm/test/CodeGen/ARM/demanded-bits-and.ll
+++ b/llvm/test/CodeGen/ARM/demanded-bits-and.ll
@@ -10,10 +10,11 @@ define dso_local void @f(ptr %p) {
; CHECK-NEXT: .LBB0_1: @ %bb
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrh r1, [r0]
-; CHECK-NEXT: and r2, r1, #255
-; CHECK-NEXT: add r3, r2, r1, lsr #8
-; CHECK-NEXT: add r2, r3, r2
-; CHECK-NEXT: add r1, r2, r1, lsr #8
+; CHECK-NEXT: lsr r2, r1, #8
+; CHECK-NEXT: add r2, r2, r1, lsr #8
+; CHECK-NEXT: and r1, r1, #255
+; CHECK-NEXT: add r1, r1, r1
+; CHECK-NEXT: add r1, r1, r2
; CHECK-NEXT: add r1, r1, #2
; CHECK-NEXT: lsr r1, r1, #2
; CHECK-NEXT: strh r1, [r0]
diff --git a/llvm/test/CodeGen/RISCV/rvp-mul-parts-acc-fold.ll b/llvm/test/CodeGen/RISCV/rvp-mul-parts-acc-fold.ll
index fa660331631d0..f27319aacef12 100644
--- a/llvm/test/CodeGen/RISCV/rvp-mul-parts-acc-fold.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-mul-parts-acc-fold.ll
@@ -377,14 +377,14 @@ define i32 @multi_use(i32 %rd, <2 x i16> %a, <2 x i16> %b) {
; RV32-LABEL: multi_use:
; RV32: # %bb.0:
; RV32-NEXT: mul.h00 a1, a1, a2
-; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: add a1, a1, a1
; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: ret
;
; RV64-LABEL: multi_use:
; RV64: # %bb.0:
; RV64-NEXT: pmul.w.h00 a1, a1, a2
-; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: add a1, a1, a1
; RV64-NEXT: addw a0, a0, a1
; RV64-NEXT: ret
%m = call i32 @llvm.riscv.mul.00.i32.v2i16(<2 x i16> %a, <2 x i16> %b)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
index f7e79834ce25a..d9f7627345e59 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
@@ -857,7 +857,7 @@ define <vscale x 8 x i32> @vadd_vv_mask_negative1_nxv8i32(<vscale x 8 x i32> %va
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vadd.vv v8, v8, v12
+; CHECK-NEXT: vadd.vv v12, v12, v12
; CHECK-NEXT: vadd.vv v8, v8, v12
; CHECK-NEXT: ret
%vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll b/llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
index 5c78092e9f2c4..895a59535f730 100644
--- a/llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
+++ b/llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
@@ -41,164 +41,164 @@ define fastcc i64 @foo() nounwind {
; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: addq %rax, %rax
; CHECK-NEXT: addq %r10, %rax
-; CHECK-NEXT: addq %r11, %r8
; CHECK-NEXT: addq %r10, %rax
+; CHECK-NEXT: movq X(%rip), %rbx
+; CHECK-NEXT: addq %r11, %r8
; CHECK-NEXT: addq %r11, %rax
-; CHECK-NEXT: movq X(%rip), %r11
-; CHECK-NEXT: bswapq %r11
-; CHECK-NEXT: addq %rdx, %r11
-; CHECK-NEXT: leaq (%rdi,%rsi), %rdx
-; CHECK-NEXT: addq %r8, %rdx
+; CHECK-NEXT: bswapq %rbx
+; CHECK-NEXT: leaq (%rdi,%rsi), %r11
; CHECK-NEXT: addq %r8, %r11
-; CHECK-NEXT: addq %rdx, %r11
+; CHECK-NEXT: addq %rdx, %rbx
+; CHECK-NEXT: addq %r8, %rbx
+; CHECK-NEXT: addq %r11, %rbx
; CHECK-NEXT: leaq (%r10,%rcx), %rdx
; CHECK-NEXT: addq %rdx, %rdx
; CHECK-NEXT: addq %rax, %rdx
-; CHECK-NEXT: addq %r11, %r9
; CHECK-NEXT: addq %rax, %rdx
-; CHECK-NEXT: addq %r11, %rdx
; CHECK-NEXT: movq X(%rip), %r11
+; CHECK-NEXT: addq %rbx, %r9
+; CHECK-NEXT: addq %rbx, %rdx
; CHECK-NEXT: bswapq %r11
+; CHECK-NEXT: leaq (%r8,%rdi), %rbx
+; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rsi, %r11
-; CHECK-NEXT: leaq (%r8,%rdi), %rsi
-; CHECK-NEXT: addq %r9, %rsi
; CHECK-NEXT: addq %r9, %r11
-; CHECK-NEXT: addq %rsi, %r11
+; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: leaq (%rax,%r10), %rsi
; CHECK-NEXT: addq %rsi, %rsi
; CHECK-NEXT: addq %rdx, %rsi
-; CHECK-NEXT: addq %r11, %rcx
; CHECK-NEXT: addq %rdx, %rsi
+; CHECK-NEXT: movq X(%rip), %rbx
+; CHECK-NEXT: addq %r11, %rcx
; CHECK-NEXT: addq %r11, %rsi
-; CHECK-NEXT: movq X(%rip), %r11
-; CHECK-NEXT: bswapq %r11
-; CHECK-NEXT: addq %rdi, %r11
-; CHECK-NEXT: leaq (%r9,%r8), %rdi
-; CHECK-NEXT: addq %rcx, %rdi
+; CHECK-NEXT: bswapq %rbx
+; CHECK-NEXT: leaq (%r9,%r8), %r11
; CHECK-NEXT: addq %rcx, %r11
-; CHECK-NEXT: addq %rdi, %r11
+; CHECK-NEXT: addq %rdi, %rbx
+; CHECK-NEXT: addq %rcx, %rbx
+; CHECK-NEXT: addq %r11, %rbx
; CHECK-NEXT: leaq (%rdx,%rax), %rdi
; CHECK-NEXT: addq %rdi, %rdi
; CHECK-NEXT: addq %rsi, %rdi
-; CHECK-NEXT: addq %r11, %r10
; CHECK-NEXT: addq %rsi, %rdi
-; CHECK-NEXT: addq %r11, %rdi
; CHECK-NEXT: movq X(%rip), %r11
+; CHECK-NEXT: addq %rbx, %r10
+; CHECK-NEXT: addq %rbx, %rdi
; CHECK-NEXT: bswapq %r11
+; CHECK-NEXT: leaq (%rcx,%r9), %rbx
+; CHECK-NEXT: addq %r10, %rbx
; CHECK-NEXT: addq %r8, %r11
-; CHECK-NEXT: leaq (%rcx,%r9), %r8
-; CHECK-NEXT: addq %r10, %r8
; CHECK-NEXT: addq %r10, %r11
-; CHECK-NEXT: addq %r8, %r11
+; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: leaq (%rsi,%rdx), %r8
; CHECK-NEXT: addq %r8, %r8
; CHECK-NEXT: addq %rdi, %r8
-; CHECK-NEXT: addq %r11, %rax
; CHECK-NEXT: addq %rdi, %r8
+; CHECK-NEXT: movq X(%rip), %rbx
+; CHECK-NEXT: addq %r11, %rax
; CHECK-NEXT: addq %r11, %r8
-; CHECK-NEXT: movq X(%rip), %r11
-; CHECK-NEXT: bswapq %r11
-; CHECK-NEXT: addq %r9, %r11
-; CHECK-NEXT: leaq (%r10,%rcx), %r9
-; CHECK-NEXT: addq %rax, %r9
+; CHECK-NEXT: bswapq %rbx
+; CHECK-NEXT: leaq (%r10,%rcx), %r11
; CHECK-NEXT: addq %rax, %r11
-; CHECK-NEXT: addq %r9, %r11
+; CHECK-NEXT: addq %r9, %rbx
+; CHECK-NEXT: addq %rax, %rbx
+; CHECK-NEXT: addq %r11, %rbx
; CHECK-NEXT: leaq (%rdi,%rsi), %r9
; CHECK-NEXT: addq %r9, %r9
; CHECK-NEXT: addq %r8, %r9
-; CHECK-NEXT: addq %r11, %rdx
; CHECK-NEXT: addq %r8, %r9
-; CHECK-NEXT: addq %r11, %r9
; CHECK-NEXT: movq X(%rip), %r11
+; CHECK-NEXT: addq %rbx, %rdx
+; CHECK-NEXT: addq %rbx, %r9
; CHECK-NEXT: bswapq %r11
+; CHECK-NEXT: leaq (%rax,%r10), %rbx
+; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: addq %rcx, %r11
-; CHECK-NEXT: leaq (%rax,%r10), %rcx
-; CHECK-NEXT: addq %rdx, %rcx
; CHECK-NEXT: addq %rdx, %r11
-; CHECK-NEXT: addq %rcx, %r11
+; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: leaq (%r8,%rdi), %rcx
; CHECK-NEXT: addq %rcx, %rcx
; CHECK-NEXT: addq %r9, %rcx
-; CHECK-NEXT: addq %r11, %rsi
; CHECK-NEXT: addq %r9, %rcx
+; CHECK-NEXT: movq X(%rip), %rbx
+; CHECK-NEXT: addq %r11, %rsi
; CHECK-NEXT: addq %r11, %rcx
-; CHECK-NEXT: movq X(%rip), %r11
-; CHECK-NEXT: bswapq %r11
-; CHECK-NEXT: addq %r10, %r11
-; CHECK-NEXT: leaq (%rdx,%rax), %r10
-; CHECK-NEXT: addq %rsi, %r10
+; CHECK-NEXT: bswapq %rbx
+; CHECK-NEXT: leaq (%rdx,%rax), %r11
; CHECK-NEXT: addq %rsi, %r11
-; CHECK-NEXT: addq %r10, %r11
+; CHECK-NEXT: addq %r10, %rbx
+; CHECK-NEXT: addq %rsi, %rbx
+; CHECK-NEXT: addq %r11, %rbx
; CHECK-NEXT: leaq (%r9,%r8), %r10
; CHECK-NEXT: addq %r10, %r10
; CHECK-NEXT: addq %rcx, %r10
-; CHECK-NEXT: addq %r11, %rdi
; CHECK-NEXT: addq %rcx, %r10
-; CHECK-NEXT: addq %r11, %r10
-; CHECK-NEXT: movq X(%rip), %rbx
-; CHECK-NEXT: bswapq %rbx
-; CHECK-NEXT: addq %rax, %rbx
-; CHECK-NEXT: leaq (%rsi,%rdx), %rax
-; CHECK-NEXT: addq %rdi, %rax
-; CHECK-NEXT: addq %rdi, %rbx
-; CHECK-NEXT: addq %rax, %rbx
+; CHECK-NEXT: movq X(%rip), %r14
+; CHECK-NEXT: addq %rbx, %rdi
+; CHECK-NEXT: addq %rbx, %r10
+; CHECK-NEXT: bswapq %r14
+; CHECK-NEXT: leaq (%rsi,%rdx), %r11
+; CHECK-NEXT: addq %rdi, %r11
+; CHECK-NEXT: addq %rax, %r14
+; CHECK-NEXT: addq %rdi, %r14
+; CHECK-NEXT: addq %r11, %r14
; CHECK-NEXT: leaq (%rcx,%r9), %r11
; CHECK-NEXT: addq %r11, %r11
; CHECK-NEXT: addq %r10, %r11
-; CHECK-NEXT: addq %rbx, %r8
; CHECK-NEXT: addq %r10, %r11
-; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: movq X(%rip), %rax
+; CHECK-NEXT: addq %r14, %r8
+; CHECK-NEXT: addq %r14, %r11
; CHECK-NEXT: bswapq %rax
+; CHECK-NEXT: leaq (%rdi,%rsi), %rbx
+; CHECK-NEXT: addq %r8, %rbx
; CHECK-NEXT: addq %rdx, %rax
-; CHECK-NEXT: leaq (%rdi,%rsi), %rdx
-; CHECK-NEXT: addq %r8, %rdx
; CHECK-NEXT: addq %r8, %rax
-; CHECK-NEXT: addq %rdx, %rax
+; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: leaq (%r10,%rcx), %rdx
; CHECK-NEXT: addq %rdx, %rdx
; CHECK-NEXT: addq %r11, %rdx
-; CHECK-NEXT: addq %rax, %r9
; CHECK-NEXT: addq %r11, %rdx
-; CHECK-NEXT: addq %rax, %rdx
; CHECK-NEXT: movq X(%rip), %rbx
+; CHECK-NEXT: addq %rax, %r9
+; CHECK-NEXT: addq %rax, %rdx
; CHECK-NEXT: bswapq %rbx
-; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: leaq (%r8,%rdi), %rax
; CHECK-NEXT: addq %r9, %rax
+; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rax, %rbx
; CHECK-NEXT: leaq (%r11,%r10), %rax
; CHECK-NEXT: addq %rax, %rax
; CHECK-NEXT: addq %rdx, %rax
-; CHECK-NEXT: addq %rbx, %rcx
; CHECK-NEXT: addq %rdx, %rax
+; CHECK-NEXT: movq X(%rip), %r14
+; CHECK-NEXT: addq %rbx, %rcx
; CHECK-NEXT: addq %rbx, %rax
-; CHECK-NEXT: movq X(%rip), %rbx
-; CHECK-NEXT: bswapq %rbx
-; CHECK-NEXT: addq %...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/226021
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